tmp39CE TMP

ECS Transactions, 77 (5) 59-79 (2017)
10.1149/07705.0059ecst The Electrochemical Society
Contacts in Advanced CMOS: History and Emerging Challenges
Christian Lavoiea,b, Praneet Adusumillib, Adra V. Carrb, Jean S. Jordan Sweeta,

Ahmet S. Ozcand, Elisabeth Levraua, Nicolas Breilc,e, Emre Alptekinb, c
a
IBM T. J. Watson Research Center, Yorktown Heights NY 10598 USA;
b
IBM Research, Albany NY 12203 USA;
c
IBM SRDC, Hopewell Junction NY 12533 USA;
d
IBM Almaden Research Center, San Jose CA 95120 USA;
e
Now at Applied Materials, Santa Clara, CA 95054 USA;
Silicide materials used as contacts in CMOS devices have evolved

over many technology nodes. This article traces the often forgotten
defectivity related reasons that were the primary drivers for a
change in materials or process flow evolving from Ti to Co and
Ni silicides, and the more recent return to Ti-based liner silicides.
The criteria used for the selection of these metal silicides have
undergone a dramatic change with the advent of 3-D transistors
and trench silicide contacts, and is now primarily guided by the
value of interfacial contact resistivity (c). Furthermore, using
results from synchrotron X-ray diffraction and pole-figure analysis,
we present how phase formation and microstructure of contacts
vary with Ti thickness, alternative annealing treatments, and
substrate composition and orientation. We show that
microstructure in very thin films can change from amorphous to
epitaxial, a factor likely to become important for the contacts in
upcoming generations of devices.
Introduction
Processes and materials for fabricating contacts to microelectronic devices have evolved
continually through the past three or four decades. In the past few years, the evolution has
been such that the current criteria for building a successful device connection have little
in common with what were good metrics only a few years ago. Until about a decade ago,
as dimensional scaling enabled subsequent technology nodes, the challenges associated
with forming contacts to microelectronic devices were primarily related to defects and
yield issues. In contrast to current trends, the size of devices and their contacts were
such that the interface resistance of the contact itself was not a concern, at least not a
significant one, roughly until the 32 nm technology node. Because performance gains
simply came for free with dimensional scaling, there was no need at first to look for
additional elements to boost device properties. Starting with the simple Al/Si contact
used in early Si technologies modifications to the material set or the process flow were
largely driven by defects that impacted yield. As we often heard: what is not broken does
not need fixing. An important consequence, however, was that extensive modifications to
a process occurred almost exclusively at a crisis point, often when an unexpected
catastrophe spectacularly collided with program schedules and business priorities. In
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these crunch situations, the resources available to solving the problem as well as the
insights and understanding generated are simply extraordinary.
Over the past 20 years, our materials research team has been closely linked with
the development and manufacturing of these contact materials, with responsibilities
encompassing the understanding of current and alternative material sets, their properties,
formation mechanisms, process windows and dependencies. This awareness and
preparation can only take one so far. The unexpected always comes along and there will
be a need for rapid analyses to determine the root cause of a specific deficiency. It is in
this spirit that we have developed fast turnaround techniques that take advantage of
intense synchrotron x-ray beams to characterize materials(14). Rapid access to these
facilities often can provide answers to critical scientific questions in a matter of a few
days. These powerful techniques were exploited over the past several decades to study
the critical defects which lead to important changes in technologies as the contact
materials evolved first from C54-TiSi2 to CoSi2 and then to Ni-Pt monosilicide contacts.
More recently, the advent of 3-D devices and continuous dimensional scaling has led to a
significant change in the contact module as intrinsic contact resistivity between the metal
and semiconductor increasingly affects device performance. As a result, criteria for the
selection of metals for source-drain contacts have changed dramatically with the industry
witnessing a return to a titanium-based contact.
This article traces the pivotal moments in the evolution of these contacts as we
witnessed them in technology and offers a perspective on possible future directions. For a
more extensive description of the early evolution, we refer the reader to earlier and more
detailed book chapters(46). Challenges and transitions associated with early C54-TiSi2,
CoSi2 and Ni(Pt) monosilicides are here reviewed briefly. Additionally, the significant
change in approach necessitated by the move to 3-D transistors is discussed. Finally, we
return to Ti contacts and discuss the impact of Ti thickness scaling, substrate composition,
orientation and different thermal budgets on the phase formation and microstructure in
advanced contacts.
History
Silicided contacts were first introduced to prevent diffusion at the

semiconductor/metal interface and avoid the spiking of Al metal through the p-n
junction(7). While this spiking had been mitigated by the use of Si containing Al (Al
solution saturated in Si), the introduction of a silicide compound at the interface
dramatically reduced these interactions at the interface. The presence of this conducting
layer above the source, drain and gate regions of transistors, also helped to alleviate any
misalignment of the metal wires. Indeed, while the dimensions at the time were very
large compared to what we are accustomed to now, we must remember each of these
technologies as being at the forefront of what could be achieved at the time yet with
difficulties similar to what we are facing today with advanced tools. With a silicided
contact formed in a self-aligned manner (no need for lithography), even if the metal
above did not fully cover the contact areas, the conducting silicide would redistribute the
current where it was expected and make the process more stable and reliable(810).
Thus, the silicided contact eliminated or drastically reduced two critical problems:
device shorting and significant variations in external resistance, which were controlled,
respectively, by stopping the Al spiking through the junction and by reducing the effects
of contact misalignment.
60
Early silicide: C54 TiSi2 Contacts
Prior to the 14 nm technology (and earlier for some manufacturers), contact formation
was achieve through a self-aligned silicidation process in which a blanket metal is first
deposited after the silicon areas have been cleaned of remaining oxide and contaminants.
The silicide formation over the gate, source and drain regions is then typically done using
two annealing steps. The first one, a low temperature anneal, is sufficient to react the
metal with some available silicon and form a new crystalline phase which will be
resistant to the removal of the metal using a selective etch. The temperature of this first
anneal must be low enough to either prevent the Si from the source or drain from
diffusing into the metal over the sidewall spacers to the gate and causing shorts, or
prevent a diffusing metal from reaching deep into Si either to the bottom of the gate or
down through the junctions. Once the unreacted metal is removed, a second anneal at
higher temperature transforms the silicide into the desired low resistance contact. Thus,
selective etch of the unreacted metal and low resistivity of the contact were the twin
criteria guiding silicide selection. While some early experiments included Pt and Pd (8,
1113), once the shorting problem between the gate and drain (or source) was understood
and controlled for the Ti reaction, the industry quickly converged to using the C54
structure of TiSi2. As can be seen in Fig. 1, this silicide forms at a relatively high
temperature (>700 C), a temperature at which Si is sufficiently mobile and becomes the
dominant diffusing species during the formation. As a result, original attempts to form a
self-aligned contact were plagued by the Si quickly diffusing at the Ti grain boundaries
and severely shorting most, if not all, contacts. The solution was to anneal in a nitrogen
ambient. This allowed simultaneous silicide and TiN formation. TiN first formed in the
grain boundaries of Ti and blocked the diffusion pathways of Si over the sidewall spacers,
enabling a sufficiently wide process window. This allowed the formation of TiSi2 over
the source, drain and gate of transistors while preventing any significant silicidation
above sidewall spacers. During the first anneal, the first phase to form is the C49-TiSi2,
an orthorhombic structure (IBM Res. Report - unpublished, a=3.562 , b=13.531 ,
c=3.55 ). This crystal structure is the high resistivity form of TiSi2 with a bulk
resistivity of about 75 -cm. With the second anneal in the process-flow, the crystal
structure transforms into the C54-TiSi2 (JCPDS card 35-0785, a=8.2687 , b=8.5534 ,
c=4.7983 ) and the resistivity drops roughly by a factor of 4 leading to the formation of
acceptable first-level interconnections. Because the difference in enthalpy of formation
between the two crystal structures is very small, the nucleation barrier is important and
this leads to a low nucleation density for the phase transformation in thin films. As a
result, when the line width decreased to m, C54 formation became more difficult and
a bimodal distribution of resistances appeared(14, 15). Indeed, because a fraction of the
interconnections remained in the C49 phase, some connections were 4 times more
resistive, negatively affecting the timing between elements of the electrical circuit. The
addition of a small percentage of Ta or Nb to the titanium allowed us to enhance the
nucleation of the low resistivity C54 and maintain this process for an additional node
(1619).
61
Figure 1. Evolution of silicide contacts from 250 nm to 10 nm technology

shown as a function of (a) contact formation temperature and (b) metal
diffusion coefficient in the silicide at 500 C. Dominant Diffusing Species
(DDS) is also indicated for each silicide. Diffusion data from(20)
Elimination of the C54 nucleation issue: CoSi2 contacts
Further size reduction rendered the problem too difficult and forced a change in
the contact material to the cubic CoSi2, which also has a low resistivity without the
complication of presenting two possible crystal structures. However, the CoSi2 process
was found to be much more sensitive to oxygen that remained at the interface or in the
annealing ambient. Cleaning contact areas before metal deposition thus became crucial,
typically requiring reduced queue times before metal deposition. The process also
required a capping layer (TiN) for the Co film in order to prevent the preferential
formation of silicates during silicide formation anneals. The overall replacement of Ti by
Co silicide contacts led to multiple new defects that had to be kept in check. Such defects
included the sword like silicide penetration through junctions caused by the fast diffusion
of Co and CoSi2 formation along dislocations in the substrate (21)(22). Also important
was the leakage caused by the faceting detected when the CoSi2 would form large grains
epitaxially aligned with the substrate (both CoSi2 and Si are cubic with very similar
dimensions). As the critical dimensions were further reduced, a new defect appeared in
gate structures in which damaging voids were detected at the interface between the
62
silicide and the silicon. These voids originated from the diffusion of Si during the
monosilicide formation which caused a very high concentration of vacancies within the
Si gates. These vacancies typically reach top surfaces as the overall volume shrinks
during silicide reactions but in this case, because the volume was constrained by the TiN
cap, in the smaller gates, the vacancies collapsed into voids to limit the mechanical strain
in the system. In some cases, the voids were sufficiently large to raise the resistance of
gate interconnections by two to three orders of magnitudes over the expected value(4).
These difficulties in narrow gates combined with the introduction of SiGe stressors for
the upcoming technology, closed the process window for CoSi2 since the presence of
germanium delays the formation of CoSi2 to much higher temperature(21, 2325).
A compatible process with SiGe: Ni(Pt) Si contacts
As a result, starting at our 65 nm technology node, the contact material was

changed to NiSi(26), as the limiting voids do not form with this silicide and the low
resistivity phase can form at low temperature on SiGe substrates. From Fig. 1, it is clear
that this silicide is formed at very low temperature and it cannot withstand the high
temperatures used for the formation of the Ti and Co silicide contacts. As a result, when
NiSi was implemented, it became necessary to limit the anneal temperatures used during
back-end-of-line (BEOL) processing to below 500 C at the time and closer to 400 C
later on. An immediate advantage of this was to limit dopant deactivation in the devices,
producing a significant boost in performance on first attempts. Another early advantage
found was that since Ni is the dominant diffusing species, the formation of NiSi generates
a new interface below the original Si interface which renders the process much less
sensitive to interfacial cleaning and the presence of oxygen. For example, the process
was found to be much less sensitive to queue time between the cleaning and metal
deposition steps compared to a Co process. It was also determined that, with NiSi
contacts, some interstitial dopants in the Si near the interface could be activated at much
lower temperature (<600 C)(27, 28). Because of this low temperature activation, it was
found that both junction leakage and contact resistivity could be reduced using
implantation and diffusion of dopants through the silicide (5, 28).
To control the low temperature agglomeration of the nickel monosilicide on
single crystal silicon substrates, the Ni was alloyed with a few atomic percent of
platinum(2931). While there are multiple advantages to this Pt addition, first and
foremost, because of miscibility of the monosilicides (NiSi and PtSi), the alloying caused
a slight increase in lattice constant and consequently a drastic modification in grain
orientation within the polycrystalline silicide film; eliminating the axiotaxial texture
component(32) and as a result, this early agglomeration. The Pt was also useful to
control NiSi encroachment and to increase the formation temperature of the NiSi2(31),
the thermodynamically stable phase in contact with Si. It is important to retain the
monosilicide phase in order to control the resistivity and Si consumption because the Si
available is increasingly limited as the size of devices is further decreased. The amount
of Pt typically varied from a few atomic % up to about 10 at. %. Increasing Pt
concentration well above these numbers is not necessarily beneficial because it leads to
increases in resistivity (about 5% increase in resistivity per atomic % Pt), increased Si
diffusion in the silicide and possibly unacceptable radiation levels from the contacts
themselves. Pt is a beta emitter, producing radiation that can cause soft errors in circuits
(33, 34).
63
Main limitation for the NiSi process: encroachment
Even though multiple difficulties associated with the NiSi process have been
described in the past(29), little has been mentioned about encroachment. It has been a
very difficult problem to solve(35), primarily because similar defects can have different
or multiple origins(36). Indeed, while the low temperature formation has definite
advantages, the very high coefficient of diffusion of Ni in Si can often be problematic.
Ni atoms diffuse extremely fast through the Si lattice, and even faster along defects in the
Si, often decorating them(37). The diffusion coefficient of Ni in Si is similar to that of
Cu, which is a metal recognized as damaging and feared in the front end of line (FEOL).
Here, we use a metal very similar to Cu, at least as far as diffusion properties are
concerned, and we put it directly in contact with the transistor while, concurrently, a
stunning effort goes into ensuring that the Cu will never be in contact with the device.
Comparing the metals used over the last decades, one can think of the temperature
presented in Fig. 1(a) as the condition for which the diffusion coefficient is sufficient to
form a silicide of roughly 20 nm in a few seconds. For each of the metal-Si systems,
formation rates and diffusion coefficients at the processing temperatures are thus of the
same order of magnitude. Fig. 1(b) shows an alternative view of the diffusion
coefficients considering diffusion properties at 500 C. On the left axis, the approximate
diffusion coefficient (evaluated using growth constants in thin films) is given, while on
the right axis, the diffusion length of species (metal or Si) in the silicide is given for an
anneal of 100 seconds at 500 C ( = ). Interestingly, for this 500 C/100s anneal,
diffusion of Si in a TiSi2 film would reach a few nanometers at most while the distance a
Ni atom could diffuse in NiSi would be of the order of 1 um, many times larger than the
size of a state-of-the-art device. As a result, the optimization of Ni contacts included
much work on the control of various Ni silicide encroachments where the conducting
silicide extends locally in non-desired areas such as through the junction or into the
channel.
Various encroachment defects had different origins but were consistently related
to a difference in the rate of silicide formation in different regions of a source or drain
and depended on substrate quality, crystallographic orientation and composition. For
crystalline substrates, the monosilicide formation will be fastest for undoped substrates
and delayed by high concentrations of dopants or the presence of Ge. As diffusion on
defects or at grain boundaries is typically much faster, defective Si will be the first and
the fastest to react. Diffusion coefficients are typically about 2 orders of magnitude larger
at grain boundaries, so that silicide penetration can easily be 10 times that of the planned
silicide thickness. Early encroachment resulted from two mechanisms. One was related
to the formation of NiSi2 along preexisting dislocations in the substrate, which generated
a sword like defect. The other consisted of the formation of non uniform NiSi on end-of-
range defects originating from the dopant implantation, which caused a non-uniform
interface near the spacer and channel of the device. Both resulted in enhanced device
leakage.
64
Figure 2. (a) cross sectional TEM and (b) elemental map of a typical Ni
contact on S/D SiGe showing the NiSi defect with Ge (blue), Ni (green),
and Oxygen (red) highlighted.
Other encroachment types also appeared later in the process, such as the
unexpected FANG defect which we described in earlier work(36). This defect, shown in
Fig. 2, was impressive at first just by its sheer size since the source of Ni for its formation
was unclear at the time of identification. It was also surprising that such a penetrating
encroachment was in the form of NiSi and not NiSi2. These encroachment defects were
not detected at the silicide contact module but only after reliability stress tests in the back
end of line (BEOL) The formation was caused by an enrichment of Ni in the contact
during RIE processing and a preferential reaction with undoped Si over the SiGe that
formed the source and drain regions. The defect was controlled using an additional short
time-scale high temperature anneal to force the complete reaction with the SiGe at the
adequate point in the process flow(36).
Transition to New Criteria for Contact Formation: intrinsic contact resistivity c
While these defects were controlled for the planar device geometries and the use
of self-aligned silicide formation, the advent of devices which are more 3 dimensional in
nature and the change in contact geometry to a trench contact dramatically changed the
conditions and criteria for the metal selection. As mentioned above, the two most
important criteria for the silicide formation were the low resistivity of the silicide and the
ability to perform a selective etch that would remove the unreacted metal and leave the
silicide untouched, allowing for a self-aligned contact formation which does not require
lithography. In this planar case, the silicide is formed fully over the source and drain area
and the contact via or trench contacts the silicide later in the flow as can be observed in
Fig. 3a. With the change in device geometry and the change to replacement gate, the
contacts to source and drain regions of transistors are now completed at the bottom of a
trench using what we refer to as a liner silicide contact, Fig. 3(b).
65
Figure 3. transition in contact formation from, in planer devices, (a)

silicide fully formed over S/D region to (b) silicide only formed at the
bottom of contact trenches. Liner contacts in finFET technologies, with
typical cross sectional TEMs, are shown in (c). xGate TEM adapted
from(38), xFIN TEM adapted from(39)
First and foremost, the change in contact flow (processing steps) to a liner silicide
drastically affects the criteria for metal selection. In such a geometry, the silicide is fully
covered with a conducting metal (typically W but now Co is also being considered) so
that its resistivity is not critical. Also, because the gate is now being replaced earlier in
the process by a conducting metal, the formation of a low-resistivity silicide over gates is
not necessary. The need for self-alignment through a selective etch is also not critical any
longer since the chemical mechanical polishing that follows will remove unreacted metal
over field areas. Thus, for state-of-the-art device architectures and current contact sizes,
the main criteria for liner silicide selection are a low intrinsic contact resistivity (c)
between the metal contact and the Si substrate and a sufficient morphological stability
mainly driven by size constraints. In a trench contact flow, the contact length becomes
considerably smaller as one can observe going from Fig. 3a to 3b. When we first
introduced this type of contact, the reduction in contact length was roughly a factor of 3.
Additionally, the change in device geometry from planar to 3-D finFETs, causes the
channel width of a device to become larger than the contact width as shown in Fig.3c.
For tall fin heights and narrow fin pitches, this increase in the ratio of channel width to
contact width can easily reach a factor of 3 (i.e. if the fin is ~50% taller than the fin pitch)
leading to additional constraints on the contacts. The change from planar devices and
66
self-aligned silicide contacts to the 3-D devices and trench contacts can therefore be
dramatic and roughly equivalent to reducing the contact length by an order of magnitude.
With such a decrease in real and effective contact length, the contacts are now primarily
limited by c at the Si-contact interface. An example of this is presented in Fig. 4 where
the resistance of a trench contact is given as a function of average resistivity of the
material in the trench for different intrinsic contact resistivity for the interface with the
semiconductor surface below. The selected trench is 20 nm wide and 50 nm in height
and we consider a flat contact (20 nm also) at the bottom of the trench.
Figure 4. resistance of a contact trench as a function of material resistivity.

Resistivity ranges of commonly employed metals are shown in the shaded
regions.
The first conclusion from this simple calculation is that as long as the average
resistivity of the material filling the trench is below about 100 -cm, its effect is
negligible on the overall resistance of the trench and the total resistance is dominated by
the interface below the trench. The resistance values here are normalized to a 1 m long
trench. In a device, the contact resistance is measured with respect to the width of the
channel not the width of the contact. While for planar devices these numbers are similar,
as mentioned above for finFET devices, this may increase the contribution of Rc roughly
by a factor 3 when the fin is 50% taller than the measured fin pitch. For a very good c
of 1 e-9 -cm2, the 5 calculated for a 20 nm contact first needs to be increased two
fold because two contacts are present and then three fold because of the ratio of the
channel width to the trench length. As a result, even at such good c values, the
contribution of the contact resistance to the external resistance of the device would reach
30 m, normalized to channel width as is commonly reported. In todays devices,
these types of numbers will roughly represent about a quarter of the external resistance
budget for a technology(40) Clearly, as the contacts further shrink in upcoming
technologies and engineers find ingenious structures which further increase the channel
width for a given contact width, this contribution will increase further, stressing the need
to further reduce intrinsic contact resistivity of the interface.
67
Interestingly, one can realize how dramatic the problem would be if contact
resistivity could not be reduced below 1e-7 as was originally predicted by the ITRS
(using early predictions from 1997 to 2007). For a decade, the intrinsic contact resistivity
issue was considered a show stopper for technology scaling. Using our understanding of
thermionic emission at a metal semiconductor, one can determine that for a Si substrate
doped at the solubility limit, the use of a midgap silicide leads to a best scenario of c of
1 e-7 -cm2 which would here contribute 3 Km in our simple calculation above
instead of the current 30 m. This suggested that contacts based on Ni, Co or Ti
would certainly become impractical by the 32 nm node. As a result and for a few years,
much research was done on dual silicide flows where band edge contacts using rare
earth silicides for the n-FET device and either Pt or Ir silicides for the pFET device were
used to reduce the resistivity of the interface by lowering the Schottky barrier height at
each of the contacts. While this was partly successful, it was quickly realized that
increasing doping concentration above the solubility limit continues to be beneficial for
contact resistance reduction. After witnessing many years of evolution, the classic
solution for contact resistance reduction seems to remain in effect: increase dopant
concentration at the interface, anneal at higher temperature to activate as many dopant
atoms as possible and reduce anneal duration to prevent diffusion away from the interface
and changes to the junction in the device. With dopant concentrations now reaching into
the 1021 atoms/cm3 range, the contact resistivity of the metal/SC interface is reaching the
low range of 10-9 -cm2(40, 41), in some case with a single metal treatment for both
types of devices(42).
A return to Ti contacts
As contact sizes continue to decrease, this very low c is key to device

optimization. Any metal selection must first meet this criterion. Because of increasingly
limited space in the contact trench and since sheet resistance is not a significant concern
any longer, the films used for contacts now can and must become very thin. While any
metal could in principle become a candidate for contact, the small thickness of the film
pushes the choice first towards metals which form silicides at higher temperature and
show higher morphological stability. Since a straightforward Ti/TiN bilayer has been
used to contact the silicide at the bottom of the trench (before W fill) for many
generations, it seems logical at first to simply remove the self-aligned NiSi contact below
and attempt optimization of the thin Ti/Si interface. Since the Ti is not mobile at
standard BEOL processing temperatures, standard encroachment issues, so recurrent for
the NiSi process, simply vanish with clear advantages for yield in any technology. Its
ability to withstand higher temperatures also allows for flexibility in the thermal budget
used at or near the contact level. Importantly, because sheet resistance of the Ti-Si
mixture does not affect resistance significantly, the composition and crystallinity of the
phase is not a major factor either. As a result, the adequate anneal temperature necessary
to form a contact only depends on the value of the intrinsic resistivity reached.
Importantly, depending on the requirement of a technology and incoming substrate
conditions, the necessary temperature could vary widely. With the very short-time anneal
tools now available (~ 100 ns), one can imagine temperatures could reach close to (or
above) the melting point of some materials. On the other end, it is also possible that with
no additional anneals, the simple thermal budget of the back end (~400 C for a few
hours), provides sufficient rearrangement at the interface (dissolution of some interface
68
impurity and some Si and Ge) to provide an acceptable c for the technology at stake.
This is why, in Fig. 1(a), we have expanded the practical temperature range for the Ti
contacts, from the small high temperature region defined by the nucleation of the C54
phase in planar architectures to a very wide temperature window for the new Ti liner
process which has been considerably studied and now widely adopted(39, 41, 4356).
Figure 5. Reduction in pFET contact resistance over progressive learning

cycles. Adapted from(40).
Because device optimization was for many years performed with a nickel contact,
a change in both the device architecture and the metal requires a new series of
optimizations. Fig.5 (adapted from(40)) shows the evolution of contact resistance on p-
FETs through this contact resistance optimization. The removal of NiSi first caused a
dramatic increase of more than order of magnitude in contact resistance. Sequential
optimization of the contact area, surface cleaning and metal thickness/deposition
conditions and finally the interface doping and Ge concentration ultimately allowed Ti to
outperform the original Ni silicide contact. One important difference in this optimization
relates to the substrate orientation that is being contacted. Variations in Schottky barrier
heights have been measured with substrate orientation and this should significantly affect
the intrinsic contact resistivity(57, 58). Fig. 2c shows a TEM cross section of the source
/ drain region to be contacted in the direction perpendicular to the fin. The RIE of the
trench contact will first land on a (111) surface as presented and any serious gouging will
lead to the appearance of all other types of facets. Therefore, it is important to
understand what occurs at the Ti/substrate interface as a function of crystal orientation.
Upcoming sections describe the impact of substrate orientation, composition, annealing
treatment and Ti film thickness on silicide phase formation and the microstructure of
these contacts.
69
Characterization of Ti/Si and Ti/SiGe Reaction
We have used in situ x-ray diffraction to monitor formation of crystalline phases

during annealing. The experiments were performed either at the X20C beamline of the
National Synchrotron Light Source (NSLS) in Brookhaven National Laboratory, or more
recently at the IDEAS beamline of the Canadian Light Source in Saskatoon, Canada. In
both systems, samples can be annealed at various temperature ramp rates during which
the diffraction spectra are acquired using a linear detector which is read out multiple
times per second during the ramp. At the NSLS, the detector covered 14 degrees in 2 at
a wavelength 1.80 while the one at the CLS covers 40 degrees at 1.54 . The new
system at the CLS is also automated and remotely operated. While we do not take
advantage of the capability here, these systems are also instrumented to measure sheet
resistance through 4-point probe measurement and surface morphology through light
scattering.
Effect of substrate orientation and composition
In Fig.6, starting with Ti films of 15 nm in thickness we focus on substrate

composition and orientation. For the (001) orientation, we show the reaction of the Ti
film with Si, Si0.75Ge0.25 and SiC (1.4 at.%). For the (111) orientation, the reaction is
shown for Si and SiGe. Following first the reaction with Si(001) in Fig.6a, we detect the
Ti peak at ~47 degrees up to a temperature of roughly 550 C. A zone follows over
which little diffraction is observed up to approximately 700 C where the appearing peak
likely corresponds to TiSi2 C49 (131) and remains up to about 950 C after which
nucleation of C54-TiSi2 occurs as shown by a very intense (040) peak and a much less
intense (311) peak. Compared to the reaction with thicker Ti films (>30nm) measured
previously(18), the phase transformation is pushed to higher temperature by more than
100 C as would be expected for thinner films for which the number of nucleation sites is
clearly reduced. Comparing the other compositions and orientation, we note that:
1. On a (001) substrate the presence of Ge delays the C54 formation at least to
1050 C, the highest temperature reached during the anneal.
2. On a (001) substrate, the presence of carbon seems to negate the effect of
thinning the Ti film and the nucleation temperature for the C54 is very similar
to that observed for much thicker films. Formation of C49-TiSi2 is also
occurring at lower temperatures.
3. On a Si (111) substrate, the signals detected are very weak and the appearance
of a weak C54 (040) peak seems to roughly coincide with the case of the Si
(001) substrate. The lack of diffraction signal may indicate a strong texturing
of the film with diffraction intensity appearing at other sample orientations
than the ones measured during the anneal.
4. Surprisingly, while it appears that the compound formed with Ti remains in
the C49 phase when the reaction occurs on a SiGe (001) substrate, for the
(111) orientation, the reaction appears quite similar to that of Si(001) with the
C54 phase nucleating at lower temperature than on SiGe (001).
70
Figure 6: temperature-dependent XRD spectra for 15nm PVD Ti films

deposited on (a) Si (b) Si0.75Ge0.25 and (c) SiC(1.4 at.%) (001) substrates.
Identical films were deposited on (d) Si and (e) Si0.75Ge0.25 (111) substrates.
The large variations observed in phase sequence when changing orientation from
a (001) to (111), are a strong indication of the importance of the interface in the energy
balance and are expected for nucleation controlled formation. While the scenario is
relatively clear for many of samples, the sequence on Si (111) suggests a strongly
textured film which is not well detected by the in situ detection geometry. To confirm
these in situ observations, and investigate film texture fully, we have performed XRD
pole figure analysis on samples quenched at 800 C and post annealed at 1050 C. The
pole figures were acquired either at the X20A beamline of National Synchrotron Light
Source at Brookhaven National Laboratory or at the A1 beamline of the Cornell High
Energy Synchrotron Source in Ithaca, NY. At Brookhaven, pole figures were acquired
using a linear detector and the x-ray energy is set at 8 keV (1.54 ). At Cornell, we
raised the energy to 20keV and used a state-of-the-art photon counting area detector
(Dectris Eiger 1M), which has 75 micron x 75 micron pixels and a dynamic range
reaching above 6 orders of magnitude. This last setup has allowed us to take relevant
texture information much more efficiently. The use of multiple pixels to reach a range of
d-spacings, allows for measurements that fully cover k-space. In this geometry, by
collecting data at just a few tilt angles, diffraction peaks from the film, cannot be missed.
71
Diffraction is measured in every possible angular direction where the detector subtends
the Debye sphere (with ~ 0.5 degree resolution), and multiple pole figures are measured
simultaneously for a range of d-spacings that are also nearly continuous. The large
acquired data sets allow not only for a clear identification of the phase present but also
for the determination of the crystal orientation through fitting of diffraction peaks both in
angular position and d spacings. Overall procedure and software for visualization and
fitting were presented and are available(59).
As presented in Fig. 7, each pole figure at a given d-spacing gives information on
the orientational distribution of grains by displaying a map of the diffracted intensity over
azimuthal and polar angles, typically from a strong-diffracting low-index plane of the
phase we are interested in.
Figure 7. Example pole figure distributions depending on film texture,

with respective type of grain orientations shown below.
At the center of a pole figure, we are sensitive to grains for which the diffracting
atomic planes are parallel to the surface of the substrate. As one proceeds from the center
of the pole figure towards its edge, we measure grains for which the detected planes are
increasingly tilted with respect to the sample surface, up until the planes are vertical at
the edge of the pole figure. Diffraction is basically measured in every direction of space
and a pole figure gives us information on how the grains are distributed within the film.
If the grains are randomly oriented, as in Fig.7a, the diffracted intensity from the film
simply adds a uniform intensity to the substrates signature. If the grains in the film are
textured along a fiber (Fig. 7b), concentric rings are observed. Axiotaxy, shown in Fig.
7c, is a texture where film and substrate planes of similar d-spacings are matched across
the interface, which leads to very sharp arcs of circles not centered on the pole figure
itself. The 4 very sharp and intense peaks in this figure originate from the Si (220) planes.
Finally, if the sample is epitaxial (Fig.7d), sharp spots from the film are detected at very
clear positions.
72
Figure 8: XRD intensity vs. d-spacing for identical 15nm PVD Ti films as
studied in Fig. 7, extracted from pole figures. Shown for (a) (001) and (b)
(111) substrates with Si epi composition in blue and SiGe in red. Reference
TiSi2 C49 (gray) and C54 (black) d-spacings are denoted with vertical lines.
In each of the large datasets, one can pick a region of a pole figure set that is not
affected by the substrate peaks and plot the XRD intensity vs. d-spacing as one would
similarly see in a normal 2 plot typically done on powder-textured thin films. The
result is shown in Fig. 8 for 3 annealing conditions (3 C/s to 800 C, 3C/s to 1050 C,
1100 C/0.5msec laser anneal), two substrate orientations ((001) and (111)), and two
substrate compositions (Si and SiGe). The selected subset of d-spacings ranges from
1.75 to 2.75 which covers multiple C49 and C54-TiSi2 diffraction peaks. While some
d-spacings are common to the two phases in this range, we have indicated the strongest
lines of both the C49 (dotted lines) and C54 (full lines). Since all Ti films were capped
with a thin TiN film to avoid any oxidation, one can detect small and wide diffraction
peaks at 2.12 and 2.45 for the (200) and (111) planes respectively. Clearly from this
data, a 3 C/s anneal to 800 C brings all four samples into the C49 phase while the 3C/s
anneal to 1050 C brings a mix of C49 and C54 depending on substrate composition and
orientation. As observed in the in situ measurement, the film on SiGe(001) remains in
the C49 phase while the film on Si(001) fully transforms to the C54 phase. For the (111)
orientation, the film on SiGe is confirmed to be in the C54 phase while the film on Si
seems to contain components of both crystal structures. Interestingly, a very short laser
anneal to higher temperature generates diffraction signals that are much less defined,
suggesting both a mixture of phases and much smaller grains.
73
Figure 9: Pole figures for (a) C49 (131) texture in TiSi2 and (b) C54 (311)
texture, as seen for 15nm PVD Ti films deposited on Si and SiGe substrates
with (001) and (111) orientation.
Knowing which phases are present, we can now observe film texture by selecting
appropriate pole figures from the large datasets. For the 800 C anneal in Fig. 9a, we
extract the pole figure at the d-spacing corresponding to the C49 (131) plane which does
not coincide with any C54 peaks. For the films on (001) substrates, ignoring intensity
from the Si substrate, the texture is mostly random (general intensity rise from the blue
background) with a component that shows a slightly favored in-plane orientation. In
comparison, the C49 structure is nearly epitaxial on the Si (111) substrate and shows both
a strong random component and multiple fiber textures for the SiGe (111) substrates that
are linked with different planes being parallel to the substrate surface. The very strong
nearly epitaxial texture of the C49 phase on the Si (111) substrate is consistent and
explains the lack of diffraction intensity during the in situ measurement. For the 1050 C
anneals, we have selected the C54-311 d-spacing to illustrate the texture. This d-spacing
also corresponds to the 060 plane of the C49 phase which allows for a confirmation of the
presence of C49 for films on both Si (111) and SiGe (001). The signature of the C54-
TiSi2 on Si(001) is a series of axiotaxy patterns. Many of these patterns are described in
the recent thesis of F. Geenen(60). Interestingly, the dotted nature of the intensity along
the axiotaxy lines is typical of a film that either exhibits very large grains or is
agglomerated. Since the resistance of the film remained low through the annealing
process, it is likely here that nucleation density for the C54 was low and the grains rather
large without the film becoming agglomerated. In comparison, the film on SiGe(111)
does not show such a sharp texture and we have verified that the peaks observed
correspond well to the (060) planes of the C49 structure and their positions respect the
angles necessary to match the higher intensity locations on the (131) pole figure. The
C54 texture on (111) substrate is a very sharp fiber centered around the [110] axis of the
C54-TiSi2 and shows abrupt intensity variations along the fiber itself which could also be
74
a sign of a microstructure with large grains. As expected, this pole figure also shows
peaks near the edge of the figure that are related to the C49 (060) plane (with in-plane
orientation). It is interesting that the intensity variation along the rings observed on the
SiGe substrates are here much less sharp, possibly pointing towards a more stable film.
One also notices the extra fiber ring appearing on the edge of the pole figure for the SiGe
(111) substrate. This position would match that of the (102) or (012) planes for the
suggested fiber texture. It is likely that the addition of Ge to the C54-TiSi2 modifies the
structure factor enough to make these planes more efficient at diffracting the x-rays.
The results above show that interfacial characteristics between the Ti silicide and
the substrate are highly dependent on substrate orientation, substrate composition, and
thermal budget given to the system. Because it is expected that bonding affects the
electrical properties of the interface, contacting substrate planes with different
orientations in 3-D devices becomes rather complex, particularly when c must remain
on the order of 1e-9 -cm2.
Effect of Ti thickness
As mentioned above, in a liner silicide process, the metal must be very thin
because of the limited volume available in the contact trench. From the 15 nm Ti film
shown in Figs. 6 to 9, we now shift our attention to thinner Ti films. As we reduce the
thickness to 10 and 5 nm Ti for films on Si(001) substrates we observe a strong reduction
in diffraction intensity. While the volume of the silicide is in principle only reduced by a
factor of 2 or 3, the diffracted intensity becomes almost that of a bare Si substrate.
Figure 10: Pole figures for 10nm and 5nm PVD Ti films on Si (001)
substrates, shown for d-spacing corresponding to the C54 (311) texture. Si
(001) is shown as a reference.
In Fig.10 we show the (311) pole figures of the annealed Ti films, using the same
(311) d-spacing as in Fig. 9b. In order to study their effect, these films received many
anneal combinations and we picked here the samples that received the largest thermal
budget. The samples presented here, were first subjected to a 550 C anneal for 30s, a
75
temperature sufficient to start the movement of the Si in the Ti film (and the absorption of
interfacial impurities). Then, the samples were annealed for 1000 C for 0.5 ms and
finally ramped at 10 C/s to 1000 C and held for 10s. It is clear that while the sharp
axiotaxial signature is still observed for the 10 nm film, for a 5 nm film on Si(001) that
was exposed to a large thermal budget, no extra diffraction intensity is present, as
compared to a pole figure obtained in the same conditions from a pristine Si(001)
substrate. Through the range of d-spacings measured, the only diffracted intensity
detected was from the TiN (111) and 200 planes at 2.45 and 2.12 . This result suggests
that, when the Ti thickness is sufficiently thin, the layer at the interface may remain
amorphous even if subjected to very high thermal budgets. A possible advantage of this
for 3-D devices could be that the nature of the interface remains similar, independent of
the substrate orientation, and could limit variation in interfacial resistivity from device to
device.
Generating in-plane alignment for thin films
While an amorphous film may have multiple advantages for uniformity and
diffusion barrier properties, the modeling of interface resistance performed with ab initio
calculations shows that quantum reflection at interfaces are lower when bonding is
satisfied through an epitaxial relationship at the interface. Even if the calculated
differences are considerably smaller than actual measurements of c, they may become
relevant as the requirements for the interface become more stringent with new devices
and ever-reducing dimensions. It is thus important to identify possible paths to generate
interfaces that are more oriented.
Figure 11: Pole figures from (a) 5nm thick Ti film on SiGe(001)
(Ge~30%), and (b) & (c) from a 2nm Ni / 4nm Ti bilayer film on Ge(001),
all subjected to a 800 C msec laser anneal.
Fig. 11 presents pole figure data from two samples for which strong texture was
developed in very thin films. In Fig. 11a, pole figures were acquired from a 5 nm Ti film
sputtered on a Si0.7Ge0.3 epilayer and annealed at 800 C for 0.5 ms using a laser
annealing process. The 4 most intense peaks stem from the Si(022) planes and the sharp
streaks observed are originating from the Ti-Si-Ge film. These very intense short lines
show strong texturing, suggesting that for the Ti thickness and deposition technique used,
increasing Ge in the substrate here leads to films that exhibit more in-plane texture.
76
Because the melting temperature of Ge is considerably lower than that of Si, it is

expected that diffusion would be more prevalent for a similar annealing temperature and
allow the nucleation to occur at the beginning of growth to define lower energy interfaces.
For our second example, we have increased the Ge concentration in the epilayer to reach
that of pure Ge and to facilitate the Ge diffusion we have used a bilayer stack: a thin 2
nm Ni interlayer at the interface with the Ge, capped with a 4 nm Ti layer. Ni and Ge are
expected to react first and allow for the subsequent reaction with Ti to occur at lower
temperature. This stack was also laser annealed to 800 C for 0.5 ms. Pole figures at d-
spacings of 2.24 and 2.05 are shown in Fig. 11 (b) and (c). Clearly, the contribution
from a total of 6 nm of metal is strongly oriented as this represents one of the sharpest
texture we have observed over the years. For these thin films, the texture and bonding at
the interface can be controlled with substrate composition and preparation, metal choices,
and thermal budget. While an amorphous film may have obvious uniformity advantages
when the orientation of the contacted surface varies, it is likely that the continued size
reduction and increases in device complexity will require further reduction in intrinsic
contact resistivity. Ability to control bonding at the metal/Si (or metal-Si/Si) interface
should help in achieving this goal.
Conclusions
Silicide contacts have evolved significantly over the years: starting with Al and
subsequently transitioning to Ti, Co and Ni silicides; and more recently, back to Ti based
liner contacts. Up until a few years ago, changes in contact materials or processing were
primarily driven by yield-limiting defects. Early TiSi2 contacts suffered from phase
transformation challenges to forming the low resistivity C54 phase as line widths were
scaled below 0.25 um, prompting a switch to cubic CoSi2 contacts. CoSi2, in turn,
suffered from voiding issues in scaled gate lines and its incompatibility with the
introduction of SiGe stressors gave way to NiSi contacts at the 65nm node. Throughout
this time, the choice of silicide material was guided by two factors: availability of a
selective etch chemistry to remove unreacted metal relative to the silicide, and low
resistivity of the contact phase. However, with the move towards 3-D transistors and the
change to trench silicide contacts, the criteria changed dramatically and the selection
process is now primarily driven by performance considerations. Continued gate pitch
scaling and fin pitch scaling in finFET devices have put a premium on low interfacial
contact resistivity as contact area decreases significantly from node to node. In addition
to lower c, higher morphological stability led us to return fo Ti in the form of Ti-based
liner contacts.
These Ti liner films have been scaled down progressively to accommodate more
volume for interconnect metallization. As the thickness of the PVD Ti films decreases to
10 nm, the axiotaxial signature of the C54 phase is still retained on Si (001) substrates.
However, a further reduction to 5 nm produces a film that stays amorphous even after
very high thermal treatments. Furthermore, substrate composition is found to have a
significant influence on phase formation sequence. The 15 nm films on SiGe (001) when
annealed at 3 C/s anneal to 1050 C, remain in the C49 phase while the film on Si (001)
fully transform to the C54 phase. Substrate orientation also determines the texture of
these films. The same 15 nm Ti films annealed at 3 C/s to 800 C show a C49 texture
that is mostly random on Si (001) substrates but nearly epitaxial on Si (111) substrates.
On SiGe (111) substrates, multiple fiber textures are detected after the 800 C anneal for
77
the C49 phase. Short high temperature anneals, increases in Ge concentration in the
substrate layer or introduction of a thin Ni film at the interface are all found to produce a
contact that is more epitaxial in nature. Microstructure thus varies widely with substrate
orientation and composition, anneal budget or metal film thickness, as it is shown to vary
from amorphous to nearly epitaxial. While an amorphous contact may be beneficial to
ensure uniform c, it is likely that a crystalline contact which is epitaxial with the
substrate reduces c further. As a result, it is likely that microstructure will become a key
factor for the performance of contacts in upcoming generations of devices.
Acknowledgments
The authors would like to thank David Muir and Beatriz Moreno of the Canadian Light
Source (CLS) as well as Jacob Ruff and Stan Stoupin of the Cornell High Energy
Synchrotron Source (CHESS) for their outstanding support during the diffraction
experiments. Earlier experiments were conducted at the X20A and X20C beamlines of
the NSLS at Brookhaven National Laboratory under DOE Contract No. DE-AC02-
76CH-00016. Some of the pole figure work was conducted at the Cornell High Energy
Synchrotron Source (CHESS) which is supported by the National Science Foundation
and the National Institutes of Health/National Institute of General Medical Sciences
under NSF award DMR-1332208. The Canadian Light Source is supported by the
Canada Foundation for Innovation, Natural Sciences and Engineering Research Council
of Canada, the University of Saskatchewan, the Government of Saskatchewan, Western
Economic Diversification Canada, the National Research Council Canada, and the
Canadian Institutes of Health Research.
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ECS Transactions, 77 (5) 59-79 (2017)

10.1149/07705.0059ecst The Electrochemical Society

Contacts in Advanced CMOS: History and Emerging Challenges

Christian Lavoiea,b, Praneet Adusumillib, Adra V. Carrb, Jean S. Jordan Sweeta,

Silicide materials used as contacts in CMOS devices have evolved

Silicided contacts were first introduced to prevent diffusion at the

Early silicide: C54 TiSi2 Contacts

Figure 1. Evolution of silicide contacts from 250 nm to 10 nm technology

Elimination of the C54 nucleation issue: CoSi2 contacts

A compatible process with SiGe: Ni(Pt) Si contacts

As a result, starting at our 65 nm technology node, the contact material was

Main limitation for the NiSi process: encroachment

Transition to New Criteria for Contact Formation: intrinsic contact resistivity c

Figure 3. transition in contact formation from, in planer devices, (a)

Figure 4. resistance of a contact trench as a function of material resistivity.

As contact sizes continue to decrease, this very low c is key to device

Figure 5. Reduction in pFET contact resistance over progressive learning

Characterization of Ti/Si and Ti/SiGe Reaction

We have used in situ x-ray diffraction to monitor formation of crystalline phases

Effect of substrate orientation and composition

In Fig.6, starting with Ti films of 15 nm in thickness we focus on substrate

Figure 6: temperature-dependent XRD spectra for 15nm PVD Ti films

Figure 7. Example pole figure distributions depending on film texture,

Generating in-plane alignment for thin films

Because the melting temperature of Ge is considerably lower than that of Si, it is

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