QUESTION BANK

VLSI Design & Technology ECE-702 Unit 1 An Overview Of Silicon Semiconductor

Technology

B.E VII Semester Examination

BE-VII/12(A)
241923
E & C ENGG.
Course No. ECE-702
(VLSI Design & Technology)

1. What are the various processes of CMOS fabrication?

Illustrate the main steps in a typical n-well process.
(20)

2. Explain the LOCOS technique. Illustrate the basic steps

of the LOCOS process with neat diagram.
(20)

3. Explain the fabrication steps involved in patterning

silicon dioxide through optical lithography.
(20)

B.E VII Semester Examination

BE-VII/12(A)
231101
ELECTRONICS & COMMUNICATION
ENGINEERING
(VLSI Design & Technology)
Course No. ECE-702

1 (a) Using schematic diagram show a thermally grown

oxide layer
and explain.

(b) Differentiate between dry and wet oxidation. How

is thermal oxidation modeled?
(10, 10)

2. a) Explain metallization process with the help of

diagrams.
(10
)

Department of E&CE M.B.S College of Engineering & Technology

Jammu.
 QUESTION BANK
VLSI Design & Technology ECE-702 Unit 1 An Overview Of Silicon Semiconductor
Technology

3. Discuss fabrication of CMOS using N-well and twin tub

processes.
(20
)

B.E VII Semester Examination

BE-VII/12(A)
230032
ELECTRONICS & COMMUNICATION
ENGINEERING
Course No. ECE-702
(VLSI Design & Technology)
(New Syllabus)

1. a) What is the role of silicon dioxide in VLSI

processing?
b) Give the flow chart of the complete NMOS
fabrication process.
c) What are main steps in wafer processing?
d) Give cross section view of an NMOS and CMOS
structure.
(5 4 = 20)
2. a) Explain the epitaxial process with a neat diagram.
b) What is doping? Compare and contrast epitaxy,
diffusion and ion-implantation as impurity doping
processes.
(10, 10)

B.E VII Semester Examination

BE-VII/12(A)
234584
ELECTRONICS & COMMUNICATION
ENGINEERING

Department of E&CE M.B.S College of Engineering & Technology

Jammu.
 QUESTION BANK
VLSI Design & Technology ECE-702 Unit 1 An Overview Of Silicon Semiconductor
Technology

Course No. ECE-702

(VLSI Design & Technology)

1. Discuss the following processes:

a) Oxidation (5)
b) Etching (5)
c) Lithography
(5)
d) Ion-Implantation
(5)
2. Discuss CMOS fabrication using:
a) N Well process
(10)
b) Twin tub process
(10)

3. Explain the following:

CMOS inverter layout
(10)

1(a) Explain the process flow of the starting material to pure silicon wafer.
Draw the necessary diagrams. Write the reactions that take place in the process
flow.

OR

Explain the Czochralski technique used for processing of silicon

wafer from the starting materials. Draw the neat schematic of the
apparatus used. (15 20
Marks)

Q. No. 2 What are the main steps in wafer processing.

(University
of Jammu) (4)

Q. No. 2(a) Define epitaxy. What are its types? How epitaxy is different from
crystal growth? List the applications and advantages of epitaxy.
(8)

Department of E&CE M.B.S College of Engineering & Technology

Jammu.
 QUESTION BANK
VLSI Design & Technology ECE-702 Unit 1 An Overview Of Silicon Semiconductor
Technology

(b) Explain the various techniques of epitaxial growth with suitable

schematics of the apparatus used.
(12)
OR
Define epitaxy. List the various salient features of epitaxy. With
the help of suitable diagrams explain CVD and MBE Processes of
epitaxy. (20)
OR
Explain the epitaxial processes with neat diagram.
(University
of Jammu) (10)

Q. No. 3(a) Using schematic diagram show a thermally grown oxide

layer and explain.

(b) Differentiate between dry and wet oxidation. How is thermal

oxidation modeled?
(University
of Jammu) (10, 10)

Q. No. 4(a) What is the role of silicon dioxide in VLSI processing?

(b) What are the main steps inn wafer processing.
(University
of Jammu) (2
5 )

Q. No 5 What are the salient features of oxidation? Explain in brief the

growth mechanism of silicon dioxide. Explain the kinetics of
thermal oxidation of silicon as proposed by Deal and Grove. List
the important deductions from this model. (15)

Q No. 6 What do you understand by dry oxidation and wet oxidation? With
the help of neat schematic explain the process of the oxide growth.
(10)
Q. No. 7 Discuss the following processes:
(a) Oxidation
(b) Etching
(c) Lithography
(d) Ion Implantation
(University
of Jammu) ( 4
5 )

Q. No. 8 Explain the CMOS inverter layout.

Department of E&CE M.B.S College of Engineering & Technology

Jammu.
 QUESTION BANK
VLSI Design & Technology ECE-702 Unit 1 An Overview Of Silicon Semiconductor
Technology

(University
of Jammu) (10)

Q. No.9 what are the various processes of CMOS fabrication? Illustrate the
main steps in a typical n well process.
(University
of Jammu) (20)

Q.No 10 Give the device structure for CMMOS inverter and explain the
same.
(University
of Jammu) (20)
Q. No.11 Explain the LOCOS technique. Illustrate the basic steps of the
LOCOS process with neat diagram.
(University
of Jammu) ( 20
)
Q. No. 12 Explain the fabrication steps involved in patterning silicon dioxide
through optical lithography.

(University
of Jammu) (10)

Q. No.13 Explain the metallization process with the help of diagrams.

(University
of Jammu) ( 20
)
Q. No 14 Give cross-section view of an NMOS, CMOS structure.
(University
of Jammu) ( 5 )
Q.No. 15 Give the flow chart of the complete NMOS fabrication process.
(University of Jammu)
(5)

Q.No 16 What is doping? Compare and contrast epitaxy, diffusion and ion-
implantation as impurity doping processes.
(University of
Jammu) ( 20 )
Q. No. 17 Discuss CMOS fabrication using:
(a) N-Well process

Department of E&CE M.B.S College of Engineering & Technology

Jammu.
 QUESTION BANK
VLSI Design & Technology ECE-702 Unit 1 An Overview Of Silicon Semiconductor
Technology

(b) Twin-Tub process

(University of Jammu) ( 10 ,10
)
Q.No. 18 Define lithography. What are the requirements of the lithography.
Explain the optical lithography with suitable diagrams.
Q. No.19 Explain the processes of diffusion and ion implantation of adding
impurities to a silicon structure.
Q. No. 20 Draw the CMOS inverter layout using the lambeda design rules .
Q. No.21 Explain the VLSI design flow with the help of diagram.

Department of E&CE M.B.S College of Engineering & Technology

Jammu.