1.

DESIGN OF ALL GATES

AIM: To Design and Implement all logic gates using verilog HDL.
TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

TRUTH TABLE:

Input Input Output Output Output Output Output Output Output Output
a b s=0 s=1 s=2 s=3 s=4 s=5 s=6 s=7
0 0 0 0 0 1 1 1 1 1
0 1 0 1 1 0 1 1 0 0
1 0 0 1 1 0 1 0 0 1
1 1 1 1 0 0 0 0 1 0

1
SOURCE CODE:
module allgates(a,b,s,c);
input a,b;
input[2:0]s;
output c;
reg c;
always @ (a,b,s,c)
begin
case(s)
3'd0:c=a&b;
3'd1:c=a|b;
3'd2:c=a^b;
3'd3:c=~(a|b);
3'd4:c=~(a&b);
3'd5:c=~a;
3'd6:c=~(a^b);
3'd7:c=~b;
endcase
end
endmodule

TEST BENCH:
module allgates_tb;
// Inputs
reg a;
reg b;
reg [2:0] s;
// Outputs

2
 wire c;
// Instantiate the Unit Under Test (UUT)
allgates uut (
.a(a),
.b(b),
.s(s),
.c(c)
);
initial begin
// Initialize Inputs
a = 1;
b = 0;
s = 100;
// Wait 100 ns for global reset to finish
#100;
end
endmodule

3
SCHEMATIC DIAGRAM:

SIMULATION WAVEFORMS:

4
SYNTHESIS REPORT:
RTL Top Level Output File Name : allgates.ngr
Top Level Output File Name : allgates
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : Yes
Target Technology : Automotive 9500XL
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs :6
Cell Usage :
# BELS : 56
# AND2 : 18
# INV : 19
# OR2 : 16
# OR3 :2
# XOR2 :1
# IO Buffers :6
# IBUF :5
# OBUF :1

CONCLUSION: Hence the all gates design is implemented using verilog HDL.

5
 2(i).DESIGN OF HALF ADDER

AIM: To Design and Implement full adder using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

6
TRUTH TABLE:
Input a Input b Output sum Output carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

SOURCE CODE:
module hadf(a,b,s,c);

output s,c;

input a,b;

wire s,c,a,b;

assign s=a^b;

assign c=a&b;

endmodule

TEST BENCH:
module HA_v;

// Inputs

reg a;

reg b;

// Outputs

wire s;

wire c;

// Instantiate the Unit Under Test (UUT)

hadf uut (

.a(a),

7
 .b(b),

.s(s),

.c(c)

);

initial begin

// Initialize Inputs

a = 0;

b = 0;

// Wait 100 ns for global reset to finish

#100;

a = 0;

b = 1;

#100;

a = 1;

b = 0;

#100;

a = 1;

b = 1;

#100

end

endmodule

8
SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

9
SYNTHESIS REPORT:
=====================================================================

* Synthesis Options Summary *

=====================================================================

---- Source Parameters

Input File Name : "hadf.prj"

Input Format : mixed

Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "hadf"

Output Format : NGC

Target Device : xc3s100e-5-vq100

---- Source Options

Top Module Name : hadf

Automatic FSM Extraction : YES

FSM Encoding Algorithm : Auto

Safe Implementation : No

FSM Style : lut

RAM Extraction : Yes

RAM Style : Auto

ROM Extraction : Yes

Mux Style : Auto

Decoder Extraction : YES

Priority Encoder Extraction : YES

Shift Register Extraction : YES

10
Logical Shifter Extraction : YES

XOR Collapsing : YES

ROM Style : Auto

Mux Extraction : YES

Resource Sharing : YES

Asynchronous To Synchronous : NO

Multiplier Style : auto

Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES

Global Maximum Fanout : 500

Add Generic Clock Buffer(BUFG) : 24

Register Duplication : YES

Slice Packing : YES

Optimize Instantiated Primitives : NO

Use Clock Enable : Yes

Use Synchronous Set : Yes

Use Synchronous Reset : Yes

Pack IO Registers into IOBs : auto

Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed

Optimization Effort :1

Library Search Order : hadf.lso

Keep Hierarchy : NO

11
RTL Output : Yes

Global Optimization : AllClockNets

Read Cores : YES

Write Timing Constraints : NO

Cross Clock Analysis : NO

Hierarchy Separator :/

Bus Delimiter : <>

Case Specifier : maintain

Slice Utilization Ratio : 100

BRAM Utilization Ratio : 100

Verilog 2001 : YES

Auto BRAM Packing : NO

Slice Utilization Ratio Delta :5

CONCLUSION: Hence the half adder has been designed and implemented using
Verilog HDL.

12
 2(ii).DESIGN OF FULL ADDER

AIM: To Design and Implement full adder using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

13
TRUTH TABLE:

Input a Input b Input c Output sum Output carry

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

SOURCE CODE:
module fulladderdirect(a,b,c,sum,carry);
output sum,carry;
input a,b,c;
wire sum,carry,a,b,c;
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule

TEST BENCH:
module fulladderdirect_tb;
// Inputs
reg a;
reg b;
reg c;
// Outputs

14
wire sum;
wire carry;
// Instantiate the Unit Under Test (UUT)
fulladderdirect uut (
.a(a),
.b(b),
.c(c),
.sum(sum),
.carry(carry)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;
// Wait 100 ns for global reset to finish
#100;
a = 0;
b = 1;
c = 0;
#100;
a = 0;
b = 1;
c = 1;
#100;
a = 1;
b = 0;

15
 c = 0;
#100;
a = 1;
b = 0;
c = 1;
#100;
a = 1;
b = 1;
c = 0;
#100;
a = 1;
b = 1;
c = 1;
#100;
end
endmodule

SCHEMATIC DIAGRAM:

16
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
RTL Top Level Output File Name : fulladderdirect.ngr
Top Level Output File Name : fulladderdirect
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : Yes
Target Technology : Automotive 9500XL
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs :5
Cell Usage :
# BELS :8
# AND2 :3
# INV :1
# OR2 :2

17
# XOR2 :2
# IO Buffers :5
# IBUF :3
# OBUF :2

CONCLUSION: Hence the full adder has been designed and implemented using
Verilog HDL.

18
 2(iii).DESIGN OF BINARY ADDER

AIM: To Design and Implement binary adder using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

19
SOURCE CODE:
module adder_4bit ( a ,b ,sum ,carry );

output [3:0] sum ;

reg [3:0] sum ;
output carry ;
reg carry ;

input [3:0] a ;
wire [3:0] a ;
input [3:0] b ;
wire [3:0] b ;

integer i;

reg [4:0]s;

always @ (a or b) begin
s[0] = 0;
for (i=0;i<=3;i=i+1) begin
sum [i] = a[i] ^ b[i] ^ s[i];
s[i+1] = (a[i] & b[i]) | (b[i] & s[i]) | (s[i] & a[i]);
end
carry = s[4];
end

endmodule

TEST BENCH:
module add_v;

// Inputs
reg [3:0] a;
reg [3:0] b;

// Outputs
wire [3:0] sum;
wire carry;

// Instantiate the Unit Under Test (UUT)

adder_4bit uut (
.a(a),
.b(b),

20
 .sum(sum),
.carry(carry)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;

// Wait 100 ns for global reset to finish

#100;
a = 4'b0010;
b = 4'b0011;
#100;
a = 4'b1100;
b = 4'b0101;
#100;

end

endmodule

SCHEMATIC DIAGRAM:

21
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
===========================================================
---- Source Parameters
Input File Name : "adder_4bit.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "adder_4bit"
Output Format : NGC
Target Device : xc3s100e-5-vq100

22
---- Source Options
Top Module Name : adder_4bit
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES

23
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort :1
Library Search Order : adder_4bit.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the binary adder has been designed and implemented
using Verilog HDL.

24
 2(iv).DESIGN OF CARRY LOOK AHEAD ADDER

AIM: To Design and Implement carry look ahead adder using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

25
SOURCE CODE:
module CLA_4bit(
output [3:0] S,
output Cout,PG,GG,
input [3:0] A,B,
input Cin
);
wire [3:0] G,P,C;

assign G = A & B; //Generate

assign P = A ^ B; //Propagate
assign C[0] = Cin;
assign C[1] = G[0] | (P[0] & C[0]);
assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);
assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);
assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) |(P[3]
& P[2] & P[1] & P[0] & C[0]);
assign S = P ^ C;

assign PG = P[3] & P[2] & P[1] & P[0];

assign GG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);
endmodule

TEST BENCH:
module clad_v;

// Inputs
reg [3:0] A;
reg [3:0] B;
reg Cin;

// Outputs
wire [3:0] S;
wire Cout;
wire PG;
wire GG;

// Instantiate the Unit Under Test (UUT)

CLA_4bit uut (
.S(S),
.Cout(Cout),
.PG(PG),
.GG(GG),
.A(A),
.B(B),

26
 .Cin(Cin)
);

initial begin
// Initialize Inputs
A = 0;
B = 0;
Cin = 0;

// Wait 100 ns for global reset to finish

#100;

A=4'b0001;B=4'b0000;Cin=1'b0;
#10 A=4'b100;B=4'b0011;Cin=1'b0;
#10 A=4'b1101;B=4'b1010;Cin=1'b1;
#10 A=4'b1110;B=4'b1001;Cin=1'b0;
#10 A=4'b1111;B=4'b1010;Cin=1'b0;

end

endmodule

SCHEMATIC DIAGRAM:

27
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
===========================================================
---- Source Parameters
Input File Name : "CLA_4bit.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "CLA_4bit"
Output Format : NGC
Target Device : xc3s100e-5-vq100

28
---- Source Options
Top Module Name : CLA_4bit
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES

29
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort :1
Library Search Order : CLA_4bit.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the carry look ahead adder has been designed and implemented
using Verilog HDL

30
 3.DESIGN OF 2 T0 4 DECODER

AIM: To Design and Implement 2 to 4 decoder using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

TRUTH TABLE:
Input E Input Input Output Output Output Output
W1 W0 Y0 Y1 Y2 Y3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

31
SOURCE CODE:
module dec2to4 (W, Y, En);
input [1:0] W;
input En;
output [0:3] Y;
reg [0:3] Y;

always @(W or En)

begin
case ({En, W})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
end
endmodule

TEST BENCH:
module dec24_v;

// Inputs
reg [1:0] W;
reg En;

// Outputs
wire [0:3] Y;

// Instantiate the Unit Under Test (UUT)

dec2to4 uut (
.W(W),
.Y(Y),

32
 .En(En)
);

initial begin
// Initialize Inputs
W = 0;
En = 0;

// Wait 100 ns for global reset to finish

#100;
W = 00;
En = 1;
#100;

W = 01;
En = 1;
#100;
W = 10;
En = 1;
#100;
W = 11;
En = 1;
#100;

end

endmodule

SCHEMATIC DIAGRAM:

33
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
=====================================================================
* Synthesis Options Summary *
=====================================================================

---- Source Parameters

Input File Name : "dec2to4.prj"
Input Format : mixed

---- Target Parameters

Output File Name : "dec2to4"
Output Format : NGC
Target Device : xc3s100e-5-vq100

---- Source Options

Top Module Name : dec2to4
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto

34
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort :1
Library Search Order : dec2to4.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

CONCLUSION: Hence the full adder has been designed and implemented using
Verilog HDL.
35
 4.DESIGN OF AN 8 TO 3ENCODER

AIM: To Design and Implement an 8X3encoder using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

36
TRUTH TABLE:

Input Input Input Input Input Input Input Input Output Output Output
i0 i1 i2 i3 i4 i5 i6 i7 y0 y1 y2
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

SOURCE CODE:
module encoder(i,y);
input [7:0]i;
output [2:0]y;
reg [2:0]y;
always @ (i)
begin
case(i)
8'b00000001:y=3'b000;
8'b00000010:y=3'b001;
8'b00000100:y=3'b010;
8'b00001000:y=3'b011;
8'b00010000:y=3'b100;
8'b00100000:y=3'b101;
8'b01000000:y=3'b110;
8'b10000000:y=3'b111;
default :y=3'b000;

37
endcase
end
endmodule

TEST BENCH:
module encoder_tb;

// Inputs
reg [7:0] i;
// Outputs
wire [2:0] y;
// Instantiate the Unit Under Test (UUT)
encoder uut (
.i(i),
.y(y)
);
initial begin
// Initialize Inputs
i = 00000000;
// Wait 100 ns for global reset to finish
#100;
i = 00000010;
#100;
i = 00000100;
#100;
i = 00001000;
#100;
i = 00010000;
#100;
i = 00100000;
#100;
i = 01000000;
#100;
i = 1000000;
#100;

end
endmodule

38
SCHEMATIC DIAGRAM:

39
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
RTL Top Level Output File Name : encoder.ngr
Top Level Output File Name : encoder
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : Yes
Target Technology : Automotive 9500XL
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO

40
Design Statistics
# IOs : 11

Cell Usage :
# BELS : 67
# AND2 : 17
# AND3 :2
# AND4 :1
# INV : 25
# OR2 : 20
# OR3 :2
# IO Buffers : 11
# IBUF :8
# OBUF :3

CONCLUSION: Hence an 8X3encoder has been designed and implemented using Verilog
HDL.

41
 5.DESIGN OF 8X1 MULTIPLEXER

AIM: To Design and Implement 8X1 multiplexer using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

42
TRUTH TABLE:

Sel S3 Sel S3 Sel S3 Output

0 0 0 A
0 0 1 B
0 1 0 C
0 1 1 D
1 0 0 E
1 0 1 F
1 1 0 G
1 1 1 H

SOURCE CODE:
module MUX8TO1(sel, A,B,C,D,E,F,G,H, MUX_OUT);
input [2:0] sel;
input A,B,C,D,E,F,G,H;
output reg MUX_OUT;
always@(A,B,C,D,E,F,G,H,sel)
begin
case(sel)
3'd0:MUX_OUT=A;
3'd1:MUX_OUT=B;
3'd2:MUX_OUT=C;
3'd3:MUX_OUT=D;
3'd4:MUX_OUT=E;
3'd5:MUX_OUT=F;
3'd6:MUX_OUT=G;
3'd7:MUX_OUT=H;
default:; // indicates null
endcase
end
endmodule

43
TEST BENCH:
module mux_v;

// Inputs
reg [2:0] sel;
reg A;
reg B;
reg C;
reg D;
reg E;
reg F;
reg G;
reg H;

// Outputs
wire MUX_OUT;

// Instantiate the Unit Under Test (UUT)

MUX8TO1 uut (
.sel(sel),
.A(A),
.B(B),
.C(C),
.D(D),
.E(E),
.F(F),
.G(G),
.H(H),
.MUX_OUT(MUX_OUT)
);

initial begin
// Initialize Inputs
sel = 000;
A = 1;
// Wait 100 ns for global reset to finish
#100;
sel = 001;
B = 0;

44
 #100;
sel = 010;
C = 1;
#100;
sel = 011;
D = 1;
#100;
sel = 100;
E = 1;
#100;
sel = 101;
F = 1;
#100;
sel = 110;
G = 1;
#100;
sel = 111;
H = 1;
#100;

end

endmodule

SCHEMATIC DIAGRAM:

45
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
===========================================================
---- Source Parameters
Input File Name : "MUX8TO1.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "MUX8TO1"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : MUX8TO1

46
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes

47
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort :1
Library Search Order : MUX8TO1.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the 8X1 multiplexer has been designed and implemented using
Verilog HDL.

48
 6.DESIGN OF 4 BIT BINARY TO GRAY CODE CONVERTER

AIM: To Design and Implement design of 4 bit binary to gray code converter
using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

49
SOURCE CODE:
module GTBmod(out,in);

input [3:0]in;

output [3:0]out;

assign out[3]=in[3];

xor(out[2],out[3],in[2]);

xor(out[1],out[2],in[1]);

xor(out[0],out[1],in[0]);

endmodule

TEST BENCH:
module btg_v;

// Inputs
reg [3:0] in;

// Outputs
wire [3:0] out;

// Instantiate the Unit Under Test (UUT)

GTBmod uut (
.out(out),
.in(in)
);

initial begin
// Initialize Inputs
in = 0000;

// Wait 100 ns for global reset to finish

#100;
in = 0010;
#100;
in = 0011;
#100;
in = 1111;
#100;

50
 end

endmodule

SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

51
SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
===========================================================
---- Source Parameters
Input File Name : "GTBmod.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "GTBmod"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : GTBmod
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES

52
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort :1
Library Search Order : GTBmod.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO

53
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the4 bit binary to gray code converter has been designed and
implemented using Verilog HDL.

54
 7.DESIGN OF 4 BIT COMPARATOR

AIM: To Design and Implement 4 bit comparator using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

55
SOURCE CODE:
module compare (A, B, AeqB, AgtB, AltB);
input [3:0] A, B;
output AeqB, AgtB, AltB;
reg AeqB, AgtB, AltB;

always @(A or B)
begin
AeqB = 0;
AgtB = 0;
AltB = 0;
if(A == B)
AeqB = 1;
else if (A > B)
AgtB = 1;
else
AltB = 1;
end

endmodule

TEST BENCH:

module comp4_v;

// Inputs
reg [3:0] A;
reg [3:0] B;

// Outputs
wire AeqB;
wire AgtB;
wire AltB;

// Instantiate the Unit Under Test (UUT)

compare uut (
.A(A),
.B(B),
.AeqB(AeqB),
.AgtB(AgtB),
.AltB(AltB)
);

initial begin

56
 // Initialize Inputs
A = 0;
B = 0;

// Wait 100 ns for global reset to finish

#100;
A = 0010;
B = 0001;
#100;
A = 0101;
B = 0101;
#100;
A = 0011;
B = 0101;
#100;
end

endmodule

SCHEMATIC DIAGRAM:

57
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
=====================================================================
* Synthesis Options Summary *
=====================================================================
---- Source Parameters
Input File Name : "compare.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "compare"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : compare

58
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes

59
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort :1
Library Search Order : compare.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the 4 bit comparator has been designed and implemented using
Verilog HDL.

60
 8(i)DESIGN OF SR FLIPFLOP

AIM: To Design and Implement SR flipflop using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

61
TRUTH TABLE:

SOURCE CODE:
module srffdf(s,r,clk,q,qb);

input s,r,clk;

inout q,qb;

wire s1,r1;

assign s1=!(s & clk);

assign r1=!(r&clk);

assign q=!(s1&qb);

assign qb=!(r1&q);

endmodule

TEST BENCH:
module srff_v;

// Inputs
reg s;
reg r;
reg clk;

62
 // Bidirs
wire q;
wire qb;

// Instantiate the Unit Under Test (UUT)

srffdf uut (
.s(s),
.r(r),
.clk(clk),
.q(q),
.qb(qb)
);

initial begin
// Initialize Inputs
s = 0;
r = 0;
clk = 1;

// Wait 100 ns for global reset to finish

#100;
s = 0;
r = 1;
clk = 1;
#100;
s = 1;
r = 0;
clk = 1;
#100;
s = 1;
r = 1;
clk = 1;
#100;
end

endmodule

63
SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

64
SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
===========================================================
---- Source Parameters
Input File Name : "srffdf.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "srffdf"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : srffdf
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES

65
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort :1
Library Search Order : srffdf.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO

66
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the SR flipflop has been designed and implemented using Verilog
HDL.

67
 8(ii)DESIGN OF D FLIPFLOP

AIM: To Design and Implement D flipflop using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

68
TRUTH TABLE:

SOURCE CODE:
module dflipflopmod(q, d, clk);

output q;

input d;

input clk;

reg q;

always @(posedge clk)

q=d;

endmodule

TEST BENCH:
module dfg_v;

// Inputs
reg d;
reg clk;

// Outputs

69
 wire q;

// Instantiate the Unit Under Test (UUT)

dflipflopmod uut (
.q(q),
.d(d),
.clk(clk)
);

initial begin
// Initialize Inputs
d = 0;
clk = 0;

// Wait 100 ns for global reset to finish

#100;
d = 1;
clk = 1;
#100;
d = 0;
clk = 1;
#100;
end

endmodule

70
SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

SYNTHESIS REPORT:
=====================================================================
* Synthesis Options Summary *
=====================================================================
---- Source Parameters
Input File Name : "dflipflopmod.prj"
Input Format : mixed

71
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "dflipflopmod"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : dflipflopmod
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No

72
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort :1
Library Search Order : dflipflopmod.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100

73
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the D flipflop has been designed and implemented using
Verilog HDL.

74
 8(iii).DESIGN OF JK FLIPFLOP

AIM: To Design and Implement JK flipflop using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

75
TRUTH TABLE:

SOURCE CODE:
module JK_flip_flop ( j ,k ,clk ,reset ,q ,qb );

output q ;
reg q ;
output qb ;
reg qb ;

input j ;
wire j ;
input k ;
wire k ;
input clk ;
wire clk ;
input reset ;
wire reset ;

always @ (posedge (clk)) begin

if (reset) begin
q <= 0;
qb <= 1;
end
else begin
if (j!=k) begin
q <= j;
qb <= k;
end
else if (j==1 && k==1) begin

76
 q <= ~q;
qb <= ~qb;
end
end
end

endmodule

TEST BENCH:
module JK_v;

// Inputs
reg j;
reg k;
reg clk;
reg reset;

// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
JK_flip_flop uut (
.j(j),
.k(k),
.clk(clk),
.reset(reset),
.q(q),
.qb(qb)
);

77
 initial begin
// Initialize Inputs
j = 0;
k = 0;
clk = 1;
reset = 1;

// Wait 100 ns for global reset to finish

#100;
j = 0;
k = 1;
clk = 1;
reset = 1;
#100;
j = 1;
k = 0;
clk = 1;
reset = 1;
#100;
j = 1;
k = 1;
clk = 1;
reset = 1;
#100;
end

endmodule

78
SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

79
SYNTHESIS REPORT:
=====================================================================
====
* Synthesis Options Summary *
=====================================================================
====
---- Source Parameters
Input File Name : "JK_flip_flop.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "JK_flip_flop"
Output Format : NGC
Target Device : xc3s100e-5-vq100

---- Source Options

Top Module Name : JK_flip_flop
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES

80
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort :1
Library Search Order : JK_flip_flop.lso

81
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the JKflipflop has been designed and implemented using
Verilog HDL.

82
 8(iv).DESIGN OF T FLIPFLOP

AIM: To Design and Implement T flipflop using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

83
TRUTH TABLE:

SOURCE CODE:
module t(t,clk,q,qb);
input t;
input clk;
output reg q,qb;
initial
begin q=0;qb=1; end

always@(posedge clk)
begin
if(clk)
begin
case(t)
1'b0:begin q=q;qb=qb; end
1'b1:begin q=~q;qb=~qb; end
endcase
end
end
endmodule
TEST BENCH:
module tfft_v;

// Inputs
reg t;
reg clk;

// Outputs

84
 wire q;
wire qb;

// Instantiate the Unit Under Test (UUT)

t uut (
.t(t),
.clk(clk),
.q(q),
.qb(qb)
);

initial begin
// Initialize Inputs
t = 0;
clk = 0;

// Wait 100 ns for global reset to finish

#100;
t = 0;
clk = 1;
#100;
t = 1;
clk = 1;
#100;
end

endmodule

85
SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
===========================================================

86
---- Source Parameters
Input File Name : "t.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "t"
Output Format : NGC
Target Device : xc3s100e-5-vq100

---- Source Options

Top Module Name :t
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES

87
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort :1
Library Search Order : t.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO

88
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the T flipflop has been designed and implemented using
Verilog HDL.

89
 9(i).DESIGN OF 4 BIT BINARY COUNTER

AIM: To Design and Implement 4 bit binary counter using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

90
SOURCE CODE:
module Counter_4Bit ( clk ,reset ,dout );

output [3:0] dout ;

reg [3:0] dout ;

input clk ;
wire clk ;
input reset ;
wire reset ;

initial dout = 0;

always @ (posedge (clk)) begin

if (reset)
dout <= 0;
else
dout <= dout + 1;
end
endmodule

TEST BENCH:
module bc4_v;

// Inputs
reg clk;
reg reset;

// Outputs
wire [3:0] dout;

// Instantiate the Unit Under Test (UUT)

Counter_4Bit uut (
.clk(clk),
.reset(reset),
.dout(dout)
);

initial begin
// Initialize Inputs
clk = 0;
reset = 0;

// Wait 100 ns for global reset to finish

#100;

91
 clk =0;
reset = 1;
#100;
clk = 1;
reset = 0;
#100;
end

endmodule

SCHEMATIC DIAGRAM:

SI
M
U
L
A
TI
O
N
W
A
V
EF
O
RM:

92
SYNTHESIS REPORT:
=====================================================================
* Synthesis Options Summary *
=====================================================================
---- Source Parameters
Input File Name : "Counter_4Bit.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "Counter_4Bit"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : Counter_4Bit
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES

93
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort :1
Library Search Order : Counter_4Bit.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO

94
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the 4 bit binary counter has been designed and implemented using
Verilog HDL.

95
 9(ii).DESIGN OF 4 BIT BCD COUNTER

AIM: To Design and Implement 4 bit BCDcounter using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

SOURCE CODE:
module BCD_Counter ( clk ,reset ,dout );

output [3:0] dout ;

reg [3:0] dout ;

96
input clk ;
wire clk ;
input reset ;
wire reset ;

initial dout = 0 ;

always @ (posedge (clk)) begin

if (reset)
dout <= 0;
else if (dout<=9) begin
dout <= dout + 1;
end else if (dout==9) begin
dout <= 0;
end
end

endmodule

TEST BENCH:
module bcdc4_v;

// Inputs
reg Clock;
reg Clear;
reg E;

// Outputs
wire [3:0] BCD1;
wire [3:0] BCD0;

// Instantiate the Unit Under Test (UUT)

BCDcountmod uut (
.Clock(Clock),
.Clear(Clear),
.E(E),
.BCD1(BCD1),
.BCD0(BCD0)
);

initial begin
// Initialize Inputs
Clock = 0;
Clear = 0;
97
 E = 0;

// Wait 100 ns for global reset to finish

#100;
Clock = 1;
Clear = 0;
E =1;
#100;
Clock = 1;
Clear = 1;
E = 1;
#100;

end

endmodule

SCHEMATIC DIAGRAM:

98
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
===========================================================
---- Source Parameters
Input File Name : "BCD_Counter.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "BCD_Counter"
Output Format : NGC
Target Device : xc3s100e-5-vq100

---- Source Options

Top Module Name : BCD_Counter
Automatic FSM Extraction : YES
99
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes

100
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort :1
Library Search Order : BCD_Counter.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the 4 bit BCD counter has been designed and implemented using
Verilog HDL.

101
 10(i)DESIGN OF SERIAL IN SERIAL OUT SHIFT REGISTER

AIM: To Design and Implement serial in serial out shift register using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

SOURCE CODE:
Serial In Serial Out Shift Register
module siso ( din ,clk ,reset ,dout );

output dout ;
102
input din ;
input clk ;
input reset ;
wire [2:0]s;

d_flip_flop u0 (.din(din),
.clk(clk),
.reset(reset),
.dout(s[0]));

d_flip_flop u1 (.din(s[0]),
.clk(clk),
.reset(reset),
.dout(s[1]));

d_flip_flop u2 (.din(s[1]),
.clk(clk),
.reset(reset),
.dout(s[2]));

d_flip_flop u3 (.din(s[2]),
.clk(clk),
.reset(reset),
.dout(dout));

endmodule

D FLIPFLOP
module d_flip_flop ( din ,clk ,reset ,dout );

output dout ;
reg dout;

input din ;
input clk ;
input reset ;

always @ (posedge clk)

begin
if (reset)
dout <= 1;

103
 else
dout <= din;
end

endmodule

TEST BENCH:
module sisof_v;

// Inputs
reg din;
reg clk;
reg reset;

// Outputs
wire dout;

// Instantiate the Unit Under Test (UUT)

siso uut (
.din(din),
.clk(clk),
.reset(reset),
.dout(dout)
);

initial begin
// Initialize Inputs
din = 0;
clk = 0;
reset = 0;

// Wait 100 ns for global reset to finish

#100;
din = 1;
clk = 0;
reset = 1;
#100;
din = 1;
clk = 1;
reset = 1;
#100;

end

endmodule
104
SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

SYNTHESIS REPORT:
=====================================================================
====
* Synthesis Options Summary *
=====================================================================
====
---- Source Parameters

105
Input File Name : "siso.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "siso"
Output Format : NGC
Target Device : xc3s100e-5-vq100

---- Source Options

Top Module Name : siso
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES

106
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort :1
Library Search Order : siso.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO

107
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the serial in serial out shift register has been designed and
implemented using Verilog HDL.

108
 10(ii)DESIGN OF SERIAL IN PARALLEL OUT SHIFT REGISTER

AIM: To Design and Implement serial in parallel out shift register using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

SOURCE CODE:
module SIPO ( din ,clk ,reset ,dout );

output [3:0] dout ;

wire [3:0] dout ;

109
input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;

reg [3:0]s;

always @ (posedge (clk)) begin

if (reset)
s <= 0;
else begin
s[3] <= din;
s[2] <= s[3];
s[1] <= s[2];
s[0] <= s[1];
end
end

assign dout = s;

endmodule

TEST BENCH:

module sipoo_v;

// Inputs
reg din;
reg clk;
reg reset;

// Outputs
wire [3:0] dout;

// Instantiate the Unit Under Test (UUT)

SIPO uut (
.din(din),
.clk(clk),
.reset(reset),
.dout(dout)
);

initial begin

110
 // Initialize Inputs
din = 0;
clk = 0;
reset = 0;

// Wait 100 ns for global reset to finish

#100;
din = 1;
clk = 0;
reset = 1;
#100;
din = 1;
clk = 1;
reset = 1;
#100;
din = 0;
clk = 1;
reset = 0;
#100;
din = 1;
clk = 1;
reset = 0;
#100;

end

endmodule
SCHEMATIC DIAGRAM:

111
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
=====================================================================
====
* Synthesis Options Summary *
=====================================================================
====
---- Source Parameters
Input File Name : "SIPO.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "SIPO"
Output Format : NGC
Target Device : xc3s100e-5-vq100

---- Source Options

Top Module Name : SIPO
Automatic FSM Extraction : YES

112
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes

113
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort :1
Library Search Order : SIPO.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the serial in parallel out shift register has been designed and
implemented using Verilog HDL.

114
 10(iii).DESIGN OF PARALLEL IN PARALLEL OUT SHIFT REGISTER

AIM: To Design and Implement parallel in parallel out shift register using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

SOURCE CODE:
module PIPO ( din ,clk ,reset ,dout );

output [3:0] dout ;

reg [3:0] dout ;

input [3:0] din ;

wire [3:0] din ;

115
input clk ;
wire clk ;
input reset ;
wire reset ;

always @ (posedge (clk)) begin

if (reset)
dout <= 0;
else
dout <= din;
end

endmodule

TEST BENCH:
module pipoo_v;

// Inputs
reg [3:0] din;
reg clk;
reg reset;

// Outputs
wire [3:0] dout;

// Instantiate the Unit Under Test (UUT)

PIPO uut (
.din(din),
.clk(clk),
.reset(reset),
.dout(dout)
);

initial begin
// Initialize Inputs
din = 0;
clk = 0;
reset = 0;

// Wait 100 ns for global reset to finish

#100;
din = 1;
clk = 1;
reset = 1;
#100;
din = 0;
116
 clk = 1;
reset = 1;
#100;

end

endmodule

SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

117
SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
===========================================================
---- Source Parameters
Input File Name : "PIPO.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "PIPO"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : PIPO
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES

118
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort :1
Library Search Order : PIPO.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO

119
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the parallel in parallel out shift register has been designed and
implemented using Verilog HDL.

120
 10(iv)DESIGN OF PARALLEL IN SERIAL OUT SHIFT REGISTER

AIM: To Design and Implement parallel in serial out shift register using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

SOURCE CODE:
module parallel_in_serial_out ( din ,clk ,reset ,load ,dout );

121
output dout ;
reg dout ;

input [3:0] din ;

wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
input load ;
wire load ;

reg [3:0]temp;

always @ (posedge (clk)) begin

if (reset)
temp <= 1;
else if (load)
temp <= din;
else begin
dout <= temp[3];
temp <= {temp[2:0],1'b0};
end
end

endmodule

TEST BENCH:
module pisoo_v;

// Inputs
reg [3:0] din;
reg clk;
reg reset;
reg load;

// Outputs
wire dout;

// Instantiate the Unit Under Test (UUT)

parallel_in_serial_out uut (
.din(din),
.clk(clk),
.reset(reset),
.load(load),
.dout(dout)
122
 );

initial begin
// Initialize Inputs
din = 0;
clk = 0;
reset = 0;
load = 0;

// Wait 100 ns for global reset to finish

#100;
din = 1;
clk = 1;
reset = 0;
load = 0;
#100;
din = 1;
clk = 1;
reset = 1;
load = 0;
#100;

end

endmodule

SCHEMATIC DIAGRAM:

123
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
=====================================================================
* Synthesis Options Summary *
=====================================================================
---- Source Parameters
Input File Name : "parallel_in_serial_out.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "parallel_in_serial_out"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : parallel_in_serial_out

124
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes

125
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort :1
Library Search Order : parallel_in_serial_out.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the parallel in serial out shift register has been designed and
implemented using Verilog HDL.

126
 11.DESIGN OF SEQUENCE DETECTOR

AIM: To Design and Implement sequence detector using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

SOURCE CODE:
module fsm (rst,in1,clk,out1);

parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101;

input rst,in1,clk;
output reg out1;

127
reg [2:0] state;

always @(posedge clk)

if (rst)
begin
state <= s0;
out1 <= 0 ;
end
else
case(state)
s0 : if (in1) begin state <= s1; out1 <= 0 ; end
else begin state <= s0; out1 <= 0 ; end
s1 : if (in1) begin state <= s0; out1 <= 0 ; end
else begin state <= s2; out1 <= 0 ; end
s2 : if (in1) begin state <= s3; out1 <= 0 ; end
else begin state <= s0; out1 <= 0 ; end
s3 : if (in1) begin state <= s4; out1 <= 0 ; end
else begin state <= s2; out1 <= 0 ; end
s4 : if (in1) begin state <= s1; out1 <= 0 ; end
else begin state <= s5; out1 <= 0 ; end
s5 : if (in1) begin state <= s1; out1 <= 1 ; end
else begin state <= s0; out1 <= 0 ; end
default: if (in1) begin state <= s0; out1 <= 0 ; end
else begin state <= s0; out1 <= 0 ; end
endcase

endmodule

TEST BENCH:
module tb_seq_detector;

reg rst;
reg x;

// Beginning of automatic regs (for this module's undeclared outputs)

// End of automatics
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire clk; // From clk0 of clk_gen.v
wire out; // From det0 of seq_detector.v
// End of automatics

clk_gen clk0(/*
// Outputs
.clk (clk));
128
 seq_detector det0(/*AUTOINST*/
// Outputs
.out (out),
// Inputs
.x (x),
.clk (clk),
.rst (rst));
initial
begin
rst = 1'b1;
#10
rst = 1'b0;
#1000
$stop;
$finish;
end
// Generate 100 random values for x, one per clock cycle
initial
repeat(1000)
begin
#10 x = {$random} / 16 % 2;
end

endmodule

SCHEMATIC DIAGRAM:

129
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
=====================================================================
====
* Synthesis Options Summary *
=====================================================================
====
---- Source Parameters
Input File Name : "fsm.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters

Output File Name : "fsm"
Output Format : NGC
Target Device : xc3s100e-5-vq100

---- Source Options

Top Module Name : fsm
Automatic FSM Extraction : YES

130
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No

---- Target Options

Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes

131
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort :1
Library Search Order : fsm.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the sequence detector has been designed and implemented using
Verilog HDL.

132
 12(i).DESIGN OF 4 BIT MULTIPLIER

AIM: To Design and Implement 4 bit multiplier using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

SOURCE CODE:
module multipliermod(a, b, out);

input [3:0] a;

input [3:0] b;

133
output [9:0] out;

assign out=(a*b);

endmodule

TEST BENCH:
module multipliert_b;
reg [3:0] a;
reg [3:0] b;
wire [9:0] out;
multipliermod uut (.a(a),.b(b),.out(out) );
initial begin
#10 a=4b1000;b=4b0010;
#10 a=4b0010;b=4b0010;
#10 a=4b0100;b=4b0100;
#10 a=4b1000;b=4b0001;
#10$stop;
end
endmodule

SCHEMATIC DIAGRAM:

134
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
=====================================================================
* Synthesis Options Summary *
=====================================================================
---- Source Parameters
Input File Name : "multipliermod.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "multipliermod"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : multipliermod
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto

135
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes

136
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort :1
Library Search Order : multipliermod.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the 4 bit multiplier has been designed and implemented using
Verilog HDL.

137
 12(ii).DESIGN OF 4 BIT DIVIDER

AIM: To Design and Implement 4 bit divider using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

SOURCE CODE:
module sequential_divider(ready, quotient,reminder,dividend,divider,sign,clk);

input clk;

138
input sign;
input [3:0] dividend, divider;
output [3:0] quotient,reminder;
output ready;
reg [3:0] quotient, quotient_temp,dqb,drb;
reg [7:0] dividend_copy, divider_copy, diff;
reg negative_output;

wire [3:0] remainder = (!negative_output) ?

dividend_copy[3:0] :
~dividend_copy[3:0] + 1'b1;
reg [2:0] bit;
wire ready = !bit;

initial bit = 0;
initial negative_output = 0;

always @( posedge clk )

if( ready ) begin
bit = 3'd4;
quotient = 0; quotient_temp = 0;
dividend_copy = (!sign || !dividend[3]) ?
{4'd0,dividend} :
{4'd0,~dividend + 1'b1};
divider_copy = (!sign || !divider[3]) ?
{1'b0,divider,3'd0} :
{1'b0,~divider + 1'b1,3'd0};
negative_output = sign &&
((divider[3] && !dividend[3])
||(!divider[3] && dividend[3]));

end
else if ( bit > 0 ) begin

diff = dividend_copy - divider_copy;

quotient_temp = quotient_temp << 1;
if( !diff[7] ) begin
dividend_copy = diff;
quotient_temp[0] = 1'd1;
end
quotient = (!negative_output) ?
quotient_temp :
~quotient_temp + 1'b1;
divider_copy = divider_copy >> 1;
bit = bit - 1'b1;
end

139
endmodule

TEST BENCH:
module did_v;

// Inputs
reg [3:0] dividend;
reg [3:0] divider;
reg sign;
reg clk;

// Outputs
wire ready;
wire [3:0] quotient;
wire [3:0] reminder;

// Instantiate the Unit Under Test (UUT)

sequential_divider uut (
.ready(ready),
.quotient(quotient),
.reminder(reminder),
.dividend(dividend),
.divider(divider),
.sign(sign),
.clk(clk)
);

initial begin
// Initialize Inputs
dividend = 1101;
divider =0100;
sign = 1;
clk = 1;

// Wait 100 ns for global reset to finish

#100;
dividend = 1010;
divider =0101;
sign = 1;
clk = 0;
#100;
dividend = 1111;
divider = 0101;
sign = 1;
clk = 1;
140
 #100;
end

endmodule

SCHEMATIC DIAGRAM:

141
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
=====================================================================
* Synthesis Options Summary *
=====================================================================
---- Source Parameters
Input File Name : "sequential_divider.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "sequential_divider"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : sequential_divider
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No

142
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto

143
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort :1
Library Search Order : sequential_divider.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the 4 bit divider has been designed and implemented using Verilog
HDL.

144
 13.DESIGN OF ALU

AIM: To Design and Implement ALU using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

145
SOURCE CODE:
module alu(s, A, B, F);
input [2:0] s;
input [3:0] A, B;
output [3:0] F;
reg [3:0] F;

always @(s or A or B)
begin
case (s)
0: F = 4'b0000;
1: F = B - A;
2: F = A - B;
3: F = A + B;
4: F = A ^ B;
5: F = A | B;
6: F = A & B;
7: F = 4'b1111;
endcase
end

endmodule

TEST BENCH:
module aluv_v;

// Inputs
reg [2:0] s;
reg [3:0] A;
reg [3:0] B;

// Outputs
wire [3:0] F;

// Instantiate the Unit Under Test (UUT)

alu uut (
.s(s),
.A(A),
.B(B),
.F(F)
);

initial begin
// Initialize Inputs

146
 s = 1;
A = 1010;
B = 0111;

// Wait 100 ns for global reset to finish

#100;
s = 0;
A = 1011;
B = 0110;
#100;
s = 1;
A = 1011;
B = 0011;
#100;

end

endmodule

SCHEMATIC DIAGRAM:

147
SIMULATION WAVEFORM:

SYNTHESIS REPORT:
=====================================================================
* Synthesis Options Summary *
=====================================================================
---- Source Parameters
Input File Name : "alu.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "alu"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : alu

148
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes

149
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES

---- General Options

Optimization Goal : Speed
Optimization Effort :1
Library Search Order : alu.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the ALU has been designed and implemented using
Verilog HDL.

150
 14.DESIGN OF FINITE STATE MACHINE

AIM: To Design and Implement finite state machine using verilog HDL.

TOOLS: XILINX ISE 9.2i Version

Family - Spartan 3
Device - XC3S400
Package - PQ208
Speed- -4
Synthesis-XST
Simulator-ISE Simulator

ARCHITECTURE:

SOURCE CODE:
module fsm( clk, rst, inp, outp);

input clk, rst, inp;

output outp;

151
 reg [1:0] state;
reg outp;

always @( posedge clk, posedge rst )

begin
if( rst )
state <= 2'b00;
else
begin
case( state )
2'b00:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end

2'b01:
begin
if( inp ) state <= 2'b11;
else state <= 2'b10;
end

2'b10:
begin
if( inp ) state <= 2'b01;
else state <= 2'b11;
end

2'b11:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
endcase
end
end

always @(posedge clk, posedge rst)

begin
if( rst )
outp <= 0;
else if( state == 2'b11 )
outp <= 1;
else outp <= 0;

152
end

endmodule

TEST BENCH:
module fsm_test;

reg clk, rst, inp;

wire outp;
reg[15:0] sequence;
integer i;

fsm dut( clk, rst, inp, outp);

initial
begin

clk = 0;
rst = 1;
sequence = 16'b0101_0111_0111_0010;
#5 rst = 0;

for( i = 0; i <= 15; i = i + 1)

begin
inp = sequence[i];
#2 clk = 1;
#2 clk = 0;
$display("State = ", dut.state, " Input = ", inp, ", Output = ", outp);

end
test2;
end
task test2;
for( i = 0; i <= 15; i = i + 1)
begin
inp = $random % 2;
#2 clk = 1;
#2 clk = 0;
$display("State = ", dut.state, " Input = ", inp, ", Output = ", outp);

end
endtask

endmodule
153
SCHEMATIC DIAGRAM:

SIMULATION WAVEFORM:

SYNTHESIS REPORT:
===========================================================
* Synthesis Options Summary *
===========================================================
---- Source Parameters

154
Input File Name : "fsm.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "fsm"
Output Format : NGC
Target Device : xc3s100e-5-vq100
---- Source Options
Top Module Name : fsm
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : lut
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : YES
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : YES
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : auto

155
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort :1
Library Search Order : fsm.lso
Keep Hierarchy : NO
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator :/
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100

156
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta :5

CONCLUSION: Hence the finite state machine has been designed and implemented using
Verilog HDL.

157