技术说明

TEC-XP+
TEC-XP+.............................................................................................................. 1
11 TEC-XP+ ................................................................................................................................. 1
111 TEC-XP+ ...................................................................................................... 1
112 TEC-XP+ ...................................................................................................................... 1
113 TEC-XP+ ........................................................................................................ 3
114 .................................................................................................................. 4
115 .................................................................................................................. 4
116 .......................................................................................................... 5
12 ..................................................................................................................................................... 6
121 .......................................................................................................................................... 6
122 .......................................................................................................................................... 7
TEC-XP+ 16 ..................................................................................... 8
21 TEC-XP+ 16 ................................................................................................................... 8
22 TEC-XP+ 16 ......................................................................................................... 12
221 ............................................................................................................ 12
222 .................................................................................................... 19
223 .................................................................................................................................... 21
224 ................................................................................................................................ 26
225 ................................................................................................................ 29
226 ........................................................................................................................ 59
227 ............................................................................................................................ 62
228 ................................................................................................................ 63
229 ........................................................................................................................ 64
2210 ......................................................................... 65
2211 ................................................................................. 66
TEC-XP+FPGA .................................................................................68
31 TEC-XP+FPGA ................................................................................................. 68
311 TEC-XP+FPGA .................................................................. 68
312 CPU ..................................................................................................................... 69
313 FPGA ......................................................................................................... 70
32 VHDL .................................................................................................................................................. 70
33 FPGA CPU ................................................................................................. 72
331 CPU ............................................................................................................... 72
FPGA_CPU .................................................................................................................................. 94
.................................................................................................................95
41 ................................................................................................................................... 95
42 ................................................................................................................................... 98
421 .................................................................................................................................... 98
422 .......................................................................................................................... 100
4 3 PC ...................................................................................................................... 120
44 ..................................................................................... 121
441 .......................................................................................... 121
442 ........................................................................................... !
45 ......................................................................................................................... 124
451 BASIC .............................................................................................. 124
452 BASIC ............................................................................................................. 125
453 .................................................................................................................. 127
1
................................................................................................................... 134
51 ............................................................................................................. 134
511 .................................................................................................. 134
512 .................................................................................................. 137
52 ................................................................................. 140
521 ....................................................................... 140
522 ....................................................................... 141
523 .......................................................................................... 146
53 ..................................................................................... 148
531 .................................................................................................. 148
532 .............................................................................................. 153
2
TEC-XP+
11 TEC-XP+
111 TEC-XP+
TEC-XP+
1994
TEC-2 TEC-2000 TEC-XP+
TEC-XP+
5 TEC-XP+ TEC-XP
TEC-XP+ TEC-XP
11
TEC-XP+

2004 TEC-XPTEC-XP+ 16
3
2005
16 FPGA TEC-XP+FPGA TEC-XP+
TEC-XP+ TEC-XP
CPU , 8TEC-XP+ TEC-XP
, CACHE
TEC-XP TEC-XP
16 8
16
16 FPGA
FPGA TEC-XP+

TEC-XP 8 TEC-2000
8 TEC-2000A
2000 2
TEC - 2000 TEC - 2000A TEC-2
16
2000
1994
TEC -2 16
11
112 TEC-XP+
TEC-XP+ TEC-XP 3 1 16
2 8 3 FPGA
CPU TEC-XP+
TEC-XP+ 16TEC-XP+ 8TEC-XP+(FPGA)
TEC-XP+ CPU 1 CPU

16 8 2 CPU
FPGA CPU
FPGA CPU
1 CPU TEC-XP+ TEC-XP MACH 5000
10000 70 130
MACH
ABEL
16 8
TEC-XP+ DC2DC1 Shift-Gal INTS-Gal
INTP-Gal MACH
TEC-XP+ 2 CPU TEC-XP VHDL FPGA

CPU EDA
TEC-XP+ 12
TEC-XP+ 1
1
TEC-XP+
VHDL
(2 ) ,
FPGA
TEC-XP+

5V 2
CPU

ALU
IR

32 ABEL
Fla gs
VHDL

36 16

12 TEC-XP+
/GAR

C
Z
V

S

D
FPGA

A B /SWTOIB
CPU

I8~I0 /YTOIB
SSH SCI
/IRLTOIB
SST /FTOIB
/MIO REQ
/WE

CPLD
13 CPU TEC-XP+
13 1 CPU 2 CPU
, CPU
TEC-XP+ EDA

6
BASIC
FPGA CPU CPU
5000 10000 CPLD FPGA EDA

EDA
TEC-XP+
2

PC
14 15
BASIC BASIC

FPGA

/

PC Windows
14 15
14
PC
2 CPU
CPU FPGA CPU CPU
15
PC
PC
PC
PC
113 TEC-XP+

16
DLX RISC

30 20
2
16
Am2901 16 4
16

16
3
8 4 4
DR SR

IO /

/ /
16
114

3
1

3
8 16
TEC-XP+ TEC-XP
CPU
FPGA CPU
VHDL
115
PC
FPGA CPU
BASIC

PC
Windows
116
TEC-XP+
PC
30
12

FPGA CPU
2 3
121

1
29
Assembler
4

6

5/

6
Intel 8255
7
3
/
8

122

1

3
4/
5 CPU
8 CPU
6GAL20V8MACH FPGA
VHDL ABEL MACHFPGA EDA
7 2 2
8 16 8
7
TEC-XP+ 16
21 TEC-XP+ 16
TEC-XP+ 16 TEC-XP+
TEC-XP+ 16
21
ALU
21 4 4 Am2901
Am2901 ALU 16
21 IB 16
AR 2 8 IB
FLAGFLAG 8 IB

MACH
MACH Am2910
IR 2 8 1 IR IB
IB 16 MACH
8 IB
2-1 32 32
CPU

ROMRAMROM 4
8 8KB RAM 2 8 2KB 2 8
16 6 3 0-1777h
ROM2000-2777h RAM
ROM

2 INTEL 8251 PC
80h/81h
40
INTEL 82558253

22
8

IB CPU DB
2 8 3
16 DB 8 DB 8
DB7-DB0 8
AR AR ALU
AB AR 3 1 -
4 1 1 -
8 8
3 1 -
CPU
CPU 8

22
ALU A B 3 5
IR
IB
AR IBALU
4 Flag ALU

IR MACH MACH
Am2910
D

ALU AR
DB IB IR DB IB
D
IB DB

IO AR
IN 8 DB
IB R0 OUT R0
IB DB
TEC-XP
9

8 8 8 Intel 8255
MAX202
74LS139 74LS138 74LS138
Next-A7~0
MIO REQ WE
CI3~0 SCC3~0 Intel 8251 Intel 8251
74LS377 Am2910
/CC FtoIB FLAG AR15~8 AR7~0

16 AB
Y7~0 /MAP CZVS
/LP
Am2901-3
MAP 58C65 58C65
SCCgal
ROM
Timing
AB DB
MACH Am2901-2
Nadr Micro-Ordre
32 6116 6116

32
Am2901-1
ALU

Shift-gal DC2 DC1 58C65 58C65
CLK 16 DB
IR Am2901-0
74LS04 IR15~8 IR7~0 IRLtoIB ALUtoIB ALUtoIB 74LS245 74LS245
74LS161
1.8432MHz ( 16 IB
307.2KHz 153.6KHz )
74LS00 32 4
5 74LS244 SWtoIB SWtoIB
5 3 12 8 8
RESET START

2.1 TEC-XP+16
10
2-1 TEC-XP+ 16
CI3~CI0 SCC MRW I2~I0 I8~I6 I5~I3 B A SST SSH SCI DC2 DC1
8 4 4 3 3 3 3 4 4 3 3 3 3

/MIOREQ/WE I8~6 I5~3 I2~0 SST C Z V S

CI3~0 MRW REG Q Y R S 000 C Z V S
00000 000 000 FQ F R+S A Q 001 CY F=0 OVR F15
00102 MAPROM 001 001 F SR A B 010
00113 010 I/O 010 FB A RS 0 Q 011 0 Z V S
111014 011 I/O 011 FB F RS 0 B 100 1 Z V S
1XX 100 F/2B Q/2Q F RS 0 A 101 RAM0 Z V S
101 F/2B F /RS D A RAM1
DC2 110 2FB 2QQ F RS D Q 110 Z V S
5
000 NC NC 111 2FB F /RS D 0 111 Q0 Z V S
001 /GIR
010 /GARL AR DC1 SSH SCI Cin / Shift
011 /GARH AR 000 /SWTOIB 000 Cin = 0
100 /INTR 001 /RTOIB ALU 001 Cin = 1
101 /INTN 010 /ETOIB 16
010 Cin = C
110 /EI INTE 1 011 /FTOIB
111 /DI INTE 0 100 /STOIB 8
101 /INTVH 100
110 /INTVL 101
111 NC NC

16 PCR5 T3~0 MIO I2~0 I8~7 I6 I5~3 B A SST SSHSCI DC2 DC1
REQ WE
SPR4
IO R0 4 3 3 2 + 1 3 4 4 3 3 3 3
36
11
22 TEC-XP+ 16
22 TEC-XP+ 16

221

TEC-XP+ MACH 130

10000 CPLD
16 SWHSWL
ABEL VHDL EDA

MACH
CPLD
12
CPLD MACH
MACH
23
32

SW SWTOIB
244 IB IRIR
MACH 16 MACH
MACH
32

IR
MACH

IB ABEL VHDL

16

2.3 MACH
EDAVHDL CPLD
FPGA
MACH
MACH

1 MACH
2 CPLD
3 CPLD
4 MACH

6 0 5-
2 ALU 3 ALU
24
16 32
1 MACH 2
3
6 4
4 ALU 4
4 K7~K4K3~K0 4 K11~K8 K11
K10 ALU K9 ALU K8 ALU K11~K8
0000 RK7~K4+K3~K01010 RR&K3~K00011 RR+K3~K0+C0
ADDANDADC

13
ABEL
ABEL
ABEL 4
MODULETITLE
DECLARATINONS
Symbol
ISTYPE COM ISTYPE REG,

KEEP
PIN IO
NODE IO

EQUATIONS
=:=
&#!

.OE=
.CLK=
//
END END
ABEL
14
ALU K11 K10

S3 S2 S1 S0

0 3-8
1 4

2
3
4 4 ALU, C4 C3 C2 C1 C0 (K8)
ALU R K7~K4 ,
R ALU 4 2 3
5
6 X3 K3 X2 K2 X1 K1 X0 K0
4 X3~X0 4 4 D3~D0 1
16 1 0 K9 SELK12
32 1 0 4 4
MACH
16
K7-K4 K7~K4 K3~K0
175 173 174 172 171 170 168 163 16 14 142 145 146 147 148 149
IR15 IR14 IR13 IR12 IR11 IR10 IR9 IR8 IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0
K15 K14 K13 K12 K11 K10 K9 K8 K7 K6 K5 K4 K3 K2 K1 K0
SEL ALU C0 K7~K4 K3~K0 Y7 ~ Y0 0
4 R3~R0 4

CLK 3_8
32 : 4 R
62 59 58 54 57 51 75 74 76 72 71 70 63 47 48 49 50
I2 I1 I0 I8 I7 I6 I5 I4 I3 B3 B2 B1 B0 A3 A2 A1 A0
D3 D2 D1 D0 C4 S3 S2 S1 S0 R3 R2 R1 R0 K15 K14 K13
ALU S3~S0
20 39 24 36 26 37 28 34 35 32 33 30 4 Q3~Q0 5
SST2 SST1 SST0 SSH SCI1 SCI0 DC2_2 DC2_1 DC2_0 DC1_2 DC1_1 DC1_0
Q3 Q2 Q1 Q0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 CLK
4
2.4 MACH
15
MODULE D
TITLE 'F'
DECLARATIONS
_MIO,CLK PIN 93,66 ISTYPE 'COM';
GIRH,GIRL, SWIBOUTEC, SWIBOUTL PIN 103,73,21,106;
I2,I1,I0,I4 PIN 62,59,58,74 ISTYPE 'com';
EQUATIONS
SWIBOUTEC = (0); "6
SWIBOUTL = (0);
GIRH = (0);
GIRL = (0);
_MIO =(0);
REQ = (0); "60
_WE = (0);
I2 = (0);
I1 = (0);
I0 = (0);
I4 = (0);
"03_8
DECLARATIONS
K15,K14,K13 PIN 175,173,174; "K15 K14 K13 3
Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0 PIN 26,37,28,34,35,32,33,30; " 8
"SCI1, DC2, DC1 8
EQUATIONS
Y0 = !K15 &!K14 &!K13;
Y1 = !K15 &!K14 & K13;
Y2 = !K15 & K14 &!K13;
Y3 = !K15 & K14 & K13;
Y4 = K15 &!K14 &!K13;
Y5 = K15 &!K14 & K13;
Y6 = K15 & K14 &!K13;
Y7 = K15 & K14 & K13;
"14
DECLARATIONS
D3,D2,D1,D0 PIN 54,57,51,75; " 4
"I8, I7~I5 4
K7,K6,K5,K4 PIN 16,14,142,145; " K7-K4
K3,K3,K1,K0 PIN 146,147,148,149; " K3-K0
SEL PIN 172; "K12
"K12K7-K4K3-K0
EQUATIONS
D3 = !SEL & K7 # SEL & K3;
D2 = !SEL & K6 # SEL & K2;
D1 = !SEL & K5 # SEL & K1;
D0 = !SEL & K4 # SEL &K0;
"2
DECLARATIONS
C0 PIN 163; "K8 K4, K0
S02,C02 NODE ISTYPE COM; "
" B0I3
EQUATIONS
16
S02 = !K4&!K0&C0 # !K4&K0&!C0 # K4&!K0&!C0 # K4&K0&C0;
C02 = !K4& K0&C0 # K4&!K0& C0 # K4& K0&!C0 # K4&K0&C0;
"3''
DECLARATIONS "2
K11,K10 PIN 171,170; " K11 K10ALU00: 10:
S03,C03 NODE ISTYPE COM; "
" I8I7
EQUATIONS
S03 = !K11&!K10&S02 # K11&!K10&K4 & K0;
C03 = !K11&!K12&C02;
"4 4 3ALU
DECLARATIONS
S3,S2,S1,S0 PIN 72,71,70,63; "4 B3-B0 4
" B0 23
K9 PIN 168; " K9
"K9 1 R0 K7~K4
" K11,K10 , K11K10 00, 10, 11
C4 PIN 76; " I3
"23
C3,C2,C1 NODE ISTYPE COM; "
R3,R2,R1,R0 PIN 47 50; "4,
" A3~A0 4
R30,R20,R10,R00 NODE ISTYPE REG,KEEP;
X3,X2,X1,X0 NODE ISTYPE COM; "ALUK7~K4R3~R0
EQUATIONS
X3 = Y4& K9&R3 # !K9&K7;
X2 = Y4& K9&R2 # !K9&K6;
X1 = Y4& K9 &R1 # !K9&K5;
X0 = Y4& K9&R0 # !K9&K4;
S0 = Y4& !K11&!K10 & !X0&!K0&C0 # !X0&K0&!C0 # X0&!K0&!C0 # X0&K0&C0
# K11&!K10 & X0 & K0
# K11& K10 & X0 # K0
# Y3&S03 "3
# Y2&S02; "2
C1 = Y4& !K11&!K10& !X0&K0&C0 # X0&!K0&C0 # X0&K0&!C0 # X0&K0&C0;
S1 = Y4& !K11&!K10 & !X1&!K1&C1 # !X1&K1&!C1 # X1&!K1&!C1 # X1&K1&C1

# K11&!K10 & X1 & K1
# K11& K10 & X1 # K1 ;
S2 = Y4& !K11&!K10& !X2&!K2&C2 # !X2&K2&!C2 # X2&!K2&!C2 # X2&K2&C2

# k11&K10 & X2 & K2
# K11& K10 & X2 # K2 ;
17
S3 = Y4& !K11&!K10& !X3&!K3&C3 # !X3&K3&!C3 # X3&!K3&!C3 # X3&K3&C3
# K11&!K10 & X3 & K3
# K11& K10 & X3 # K3 ;
# Y3&C03 "3
# Y2&C02; "2
R30 := S3;
R20 := S2;
R10 := S1 ;
R00 := S0;
R3 = R30.Q;
R2 = R20.Q;
R1 = R10.Q;
R0 = R00.Q;
R30.CLK = CLK;
R20.CLK = CLK;
R10.CLK = CLK;
R00.CLK = CLK;
"54RESET0000
DECLARATIONS
Q3.Q2,Q1,Q0 PIN 20,29,24,36 ISTYPE 'REG,KEEP'; "4
RESET PIN 162; "SSTSSH4
EQUATIONS
Q0 := Y5& RESET& !Q0.FB; "
Q1 := Y5& RESET& !Q1.FB&Q0 # Q1&!Q0;
Q2 := Y5& RESET& Q2.FB&Q1&Q0 # Q2&!Q1&Q0;
Q3 := Y5& RESET& Q3.FB&Q2&Q1&Q0 # Q2&!Q2&Q1&Q0;
Q0.CLK = CLK;
Q1.CLK = CLK;
Q2.CLK = CLK;
Q3.CLK = CLK;
END

MACH

MACH
3 29
24 MACH
16
K15~K0 16 IR15~IR0
25 D3~D0C4S3~S0R3~R0Q3~Q0
Y7~Y0 I8~I3B3~B0A3~A0SST2~DC1_0
23 S02S03 C02C03
S0C4 6 2
18
2 4 X3~X0

K15~K13
K15~K13 3 8
7
K15~K13 16
IR IR MACH
MACH
IR START
MACH
4 R+K3~K0
4 S4~S0 C4 B3~B0I3
R R3~R0 START
R R3~R0 START
S4~S0 R K3~K0
1 START MACH
2 R K3~K0 ALU S3~S0 R3~R0
START START
ABEL
222
PC
PC PC
PC
PC

19

BASIC
1
1
2
PC
PC
5
2
1
A U GTP

E D
R
U D
2
542
3 5 10 ~ 15
4
2
0 16 16

A G
20
W M
G
ASEC PC PC
ASEC
223
5
ALU ALU
TEC-XP+ 16 25 4 4
Am2901 Am2901 IB 4
4 AR AR
IB MACH ALU
GAL20V8 4 FLAG
ALU 4 4 FLAG 4
IB
21
FtoIB FLAG AR15~8 AR7~0
CZVS RAM15 Q015
Am2901-3
Am2901-2
Am2901-1
ALU
Am2901-0
ALUtoIB ALUtoIB
RAM0 Q0 Cin
IB
25

26
16 16 Cin
RAM0Q0RAM15Q15 MACH SHIFT MACH
16 D15~D0
23 2-2
22
26
2-2 16
I8~6 I5~3 I2~0 SST C Z V S

REG Q Y R S
000 FQ F R+S A Q 000 C Z V S
001 F SR A B 001 CY F=0 OVR F15
010 FB A RS 0 Q 010
011 FB F RS 0 B 011 0 Z V S
100 F/2B Q/2Q F RS 0 A 100 1 Z V S
101 F/2B F /RS D A 101 RAM0 Z V S
110 2FB 2QQ F RS D Q 110 RAM15 Z V S
111 2FB F /RS D 0 111 Q0 Z V S
SSH SCI Cin/ Shift

000 Cin = 0
001 Cin = 1
010 Cin = C
100
101

1 Am2901
2 4 4 16
3 2 GAL20V8 ALU
4
4 23
24 23

7

R0 1234 1234B 0D+0 B R0
R9 789F 789FB 9D+0 B R9
R9 R9-R0 B 9A 0 1B-A B R9
R0 R0+1 B 0 1B+0 B R0
R10 R0 B AA 0A+0 B R10

R9 R9^R9 B 9 A 9 B^A
Q R9 A 9 A+0 Q

23
2-3
2-4
2-3
I8-6 I5-3 I2-0 SST A B SCI SSH

R01234
R9789F
R9R9-R0
R0R0+1
R10R0
R9R9R0
QR9
Y
A B

Q

2-4
START START

Y15-Y0 CY F=0 OVR F15 C Z V S
R01234
R9789F
R9R9-R0
R0R0+1
R10R0

R9R9R0
QR9
R0+1 Y15-Y0 1234 1235

Q
C

QR9 Q
6 A
A 2000
2000: MVRD R0, 1234
2002: MVRD R9, 789F
2004: SUB R9, R0
2005: INC R0
2006: MVRR R10,R0
2007: SHR R9
24
2008: RET
G
R0 1235R9 3335R10 1235
T
1 R0 1234
2 R9 789F
3 R9 666B
4 R0 1235
5 R10 1235
6 R10 3335 C 1

RET
JR 2000 G
5
STEP/CONTINUE
7
23
6
6
23
24
23 23
/
T
25

224

ROM
RAMROM 4 8 8KB 58C65
RAM 2 8 2KB 6116 2 8 16
6 3 0-1777h ROM
2000-2777h RAM ROM
27
13 ROM RAM 11
3 3
CPU IB CPU
27
3 74LS138 3
8
74LS138 4 1
8
74LS139 - 3 MIOREQ
WE 3 1000
001010011
26

Intel 8255
MAX202
74LS139 74LS138 74LS138
MIO REQ WE
Intel 8251 Intel 8251
AR15~8 AR7~0
16 AB
ALU
58C65 58C65
AB DB
6116 6116
58C65 58C65
CPU
16 DB
74LS245 74LS245
IB
27
8K 2 8KB
8192 8
58C65 ROM EPROM
16
58C65 ROM /CE/OE

/WE 58C65 ROM RAM
58C65 ROM /CE
/OE/WE 58C65 ROM RAM
58C65 ROM /OE
/WE
8 DB CPU 8
8
TTL 0~4V 12V 0~12V
27 MAX202
+12V -12V

1
1 ROM RAM
EEPROM
2
27
3
4 58C65 ROM
5
2
1
28 28 58C65 ROM
8KB 24 6161 RAM2KB 8
16 2
2
2
/OE 58C65 ROM 6161 RAM
2 58C65 ROM 8K ROM
58C65 ROM E
1
58C65 ROM RAM
2 6161 RAM 2K RAM 24 RAM
/CE/OE/WE
2 ROM
8 ROM 2
ROM RAM 58C65 ROM
/CE/OE/WE 58C65 ROM
8K
28
225

28
PC R5
IR 2 8 IR
IB Am2910 130
CPLD MACH
8 8 8
Next-A7~0
CI3~0 SCC3~0
74LS377 Am2910
/CC
/MAP
Y7~0 /LP

Timing

MACH
Nadr Micro-Ordre
32

MAP
SCCgal Shift 32
ROM
DC2 DC1
IR CLK
PC15~0
IR15~8 IR7~0 IRLtoIB
IB
28
PC 1
16
29

IR IB 16 MACH
8 IB
Am2910
CPLD MACH
MACH MACH
ABEL VHDL
28 MACH
MAPROM CC SCCgal
MAPROM
Timing
32
DC2 DC1
MACH
MACH
8 8
MACH
29 MACH I/O
MACH I/O
MACH 33V 5V 5V
4 40 4 40
MACH ABEL
16
MACH ABEL
30
MACH I/O PIN
OMIOH
INT25
INT15
INT05
GIRH
-MIO
-PL
CI3
CI1
CC
Y7
D1
D3
D5
GND
GND
GND
VCC
127
125
123
121
117
115
113
111
109
107
105
103
99
97
95
93
39 1
U3
40 2
VCC
VCC
VCC
VCC
126
124
122
120
118
116
114
112
108
106
104
102
100
98
96
94
D0
D2
D4
D6
D7
-MAP
CI2
CI0
IRLTOIB
Q15
INT24
INT14
INT04
U4
GND 1 135 Y6 VCC 40 39 87 REQ

2
Y5 136 137 Y4 -WE 86 85 SCC3
Y3 138 139 Y2 SCC2 84 83 SCC1
Y1 140 141 Y0 SCC0 82 81 RAM15
IR5 142 GND GARL 80 GND
VCC 145 IR4 VCC 77 GARH
IR3 146 147 IR2 I3 76 75 I5
IR1 148 149 IR0 I4 74 73 GIRL
C-M 150 151 RESET B3 72 71 B2
T3 152 GND B1 70 68
CLK2 154 156 BIT8 CK 66 GND
T2 158 159 T4 T0 64 63 B0
T1 160 161 ALUTOIB I2 62 61 Q7
R 162 163 IR8 RAM7 60 59 I1
GINT 164 165 Cy I0 58 57 I7
VCC GND VCC GND
IR9 168 169 INTCLK I8 54 53 Cn
IR10 170 171 IR11 OMIOL 52 51 I6
IR12 172 173 IR14 A0 50 49 A1
IR13 174 39 40 175 IR15 A2 48 2 1 47 A3
U2
SWIBOUT
HANDLE
RAM0
DC11
DC20
SST1
SCI0
IB2
IB3
Ov
C0
P1
F3
V
Z
S
GND
GND
GND
VCC
11
15
17
19
21
23
25
27
29
33
35
37
39
5
7
9
2 40
U1
1 39
VCC
VCC
VCC
VCC
10
12
14
16
18
20
24
26
28
30
32
34
36
38
6
8
Q0
P0
C
GFTOIB
IR6
IR7
LINK
SST2
SST0
SCI1
DC22
DC10
DC12
DC21
SSH
GSIGN8
29 MACH
31
ABEL

DECLARATINONS PIN
NODE ISTYPE REG, KEEPNODE
ISTYPE COM

32 32
32 C_M
!C_M 32

EQUATIONS
=:=
&#!

.OE=
.CLK=
//
END END
4
1 CTRL GAL
SHIFT GAL DC1 DC2
2 2 4 32
232
0 1 1
PLD GAL20V8
237 238
1
0
!C_M
C_M
3 Am2910

3 1 1 CCSCC GAL Am2910
2
MAPROM
Am2910 MAP 1 PL 2 8
32
Am2910 D
3 48 48
ROM
48 := =
8 48
1 0
1 0 48
48 MACH
32 MACH 32
16 MACH
!C_M
Am2910
4 3
3 INT04~INT24INT05~INT25
INT0~INT4
AA1 AA0P1
P0INTE=1 INTE
EI 1 DI 0
/INT
ABEL
MODULE mach4000
TITLE 'mach4000'
DECLARATIONS
"
C_M, Link, HndIns, RESET,CK PIN 150,18,5,151,66;
GIRH,GIRL,GARH,GARL,R PIN 103,73,77,80,162; "
GFtoIb,GALUTOIB,GSING8 PIN 12,161,38; "
SWIBOUTEC,SWIBOUTL,IRLTOIB PIN 21,106,102;
OMIOH,OMIOL PIN 111,52; " 245
"
RAM15,RAM0 PIN 81,7;"RAM7 PIN 60
Q15,Q0 PIN 100,6;"Q7 PIN 61
F3,Cy,Cn,Ov,C0 PIN 27,165,53,25,29;
C,Z,S PIN 10,11,17; "V PIN 15
" 32
"
_MIO,REQ,_WE PIN 93,87,86;
I8,I7,I6,I5,I4,I3,I2,I1,I0 PIN 54,57,51,75,74,76,62,59,58;
A3,A2,A1,A0,B3,B2,B1,B0 PIN 47,48,49,50,72,71,70,63;
SST2,SST1,SST0,SSH,SCI1,SCI0 PIN 20,39,24,36,26,37;
DC2_2,DC2_1,DC2_0,DC1_2,DC1_1,DC1_0 PIN 28,34,35,32,33,30;
"168
IR7,IR6,IR5,IR4,IR3,IR2,IR1,IR0 PIN 16,14,142,145,146,147,148,149;
IR15,IR14,IR13,IR12,IR11,IR10,IR9,IR8 PIN 175,173,174,172,171,170,168,163;
"MACH 4
33
T3,T2,T1,T0 PIN 152,158,160,64 "T4 PIN 159
T30,T20,T10,T00 NODE ISTYPE 'REG,KEEP';
" 32
_MIO00,REQ00,_WE00 NODE ISTYPE 'REG,KEEP';
I200,I100,I000,I800,I700,I600,I500,I400,I300 NODE ISTYPE 'REG,KEEP';
A300,A200,A100,A000,B300,B200,B100,B000 NODE ISTYPE 'REG,KEEP';
SST200,SST100,SST000,SSH00,SCI100,SCI000 NODE ISTYPE 'REG,KEEP';
DC2_200,DC2_100,DC2_000,DC1_200,DC1_100,DC1_000 NODE ISTYPE 'REG,KEEP';
A30,A20,A10,A00,B30,B20,B10,B00,NRST,DC23IN,SWIBIN NODE ISTYPE 'COM';
"8
Bit8, GINT, INT PIN 156,164,169;
//**********************************************************
"Settings
c,z,x=.C.,.Z.,.X.;
T = [T3,T2,T1,T0]; "4
IR = [IR15,IR14,IR13,IR12,IR11,IR10,IR9,IR8]; " 8
"32
All = [_MIO,REQ,_WE,A3,A2,A1,A0,B3,B2,B1,B0,SCI1,SCI0,I8,I7,
I6,I5,I4,I3,I2,I1,I0,SST2,SST1,SST0,
DC1_2,DC1_1,DC1_0,DC2_2,DC2_1,DC2_0];
DC1 = [DC1_2,DC1_1,DC1_0];
"Instruction Macros "29

"
ADD = IR==[0,0,0,0,0,0,0,0];
SUB = IR==[0,0,0,0,0,0,0,1];
AND = IR==[0,0,0,0,0,0,1,0];
OR = IR==[0,0,0,0,0,1,1,0];
XOR_ = IR==[0,0,0,0,0,1,0,0];
CMP = IR==[0,0,0,0,0,0,1,1];
TEST = IR==[0,0,0,0,0,1,0,1];
MVRR = IR==[0,0,0,0,0,1,1,1];
INC = IR==[0,0,0,0,1,0,0,1];
DEC = IR==[0,0,0,0,1,0,0,0];
SHL = IR==[0,0,0,0,1,0,1,0];
SHR = IR==[0,0,0,0,1,0,1,1];
JR = IR==[0,1,0,0,0,0,0,1];
JRC = IR==[0,1,0,0,0,1,0,0];
JRNC = IR==[0,1,0,0,0,1,0,1];
JRZ = IR==[0,1,0,0,0,1,1,0];
JRNZ = IR==[0,1,0,0,0,1,1,1];
JMPA = IR==[1,0,0,0,0,0,0,0];
LDRR = IR==[1,0,0,0,0,0,0,1];
STRR = IR==[1,0,0,0,0,0,1,1];
IN_ = IR==[1,0,0,0,0,0,1,0];
OUT = IR==[1,0,0,0,0,1,1,0];
PUSH = IR==[1,0,0,0,0,1,0,1];
POP = IR==[1,0,0,0,0,1,1,1];
PSHF = IR==[1,0,0,0,0,1,0,0];
POPF = IR==[1,0,0,0,1,1,0,0];
MVRD = IR==[1,0,0,0,1,0,0,0];
CALA = IR==[1,1,0,0,1,1,1,0];
34
RET = IR==[1,0,0,0,1,1,1,1];
EQUATIONS
"*************************CTRL GAL**********************************
!SWIBOUTEC = HndIns&!_MIO&_WE # !Link#DC1==[1,0,1];
"
!SWIBOUTL = HndIns&!_MIO&_WE # !Link; "
OMIOH = !Link # HndIns # _MIO; " MIO
OMIOL = !Link # HndIns # _MIO;
"*************************SHIFT GAL*************************************
Cn = !SSH&!SCI1& SCI0# " SSH SCI1 SCI0 CN
!SSH& SCI1&!SCI0&C# " 0 0 1 1
!SSH& SCI1& SCI0&C0; " 0 1 0 C
" 0 1 1 C0
" C0 8
Q0 = SSH&SCI1&!SCI0&!F3; "
RAM0= SSH&!SCI1&SCI0&C# " 1 0 0
SSH&SCI1&!SCI0&Q15; " 1 0 1
RAM15 = SSH&!SCI1& SCI0&C#
SSH& SCI1&!SCI0&Cy#
SSH& SCI1& SCI0& F3
Q15 = SSH&SCI1&!SCI0&RAM0#
SSH&SCI1& SCI0&RAM0;
RAM15.OE = !I7; "/
Q15.OE = !I7; "
RAM0.OE = I7; "I7
Q0.OE = I7; "RAM15 Q15 , , RAM0 Q0
"************************* TIMING16 GAL**********************

T3 = T30.Q;T2 = T20.Q;T1 = T10.Q;T0 = T00.Q;
T30: = C_M&!R
# C_M&R&T==[1,0,1,0]
# C_M&R&T==[1,1,1,0]
# C_M&R&T==[1,1,0,0]
# C_M&R&T==[1,1,1,1]
# C_M&R&T==[1,1,0,1]
# C_M&R&T==[0,0,1,1]&!INT
# C_M&R&T==[0,1,0,0]&IR15&!IR14&!INT
# C_M&R&T==[0,1,0,1]&!INT;
T20 := C_M&R&T==[0,0,1,0]&IR15
# C_M&R&T==[0,1,1,0]
# C_M&R&T==[0,1,0,0]&IR15&IR14&IR11
# C_M&R&T==[0,1,1,1]
# C_M&R&T==[1,0,1,0]
# C_M&R&T==[1,1,0,0];
T10 := C_M&R&T==[0,0,0,0]
# C_M&R&T==[0,0,1,0]
# C_M&R&T==[0,1,1,0]&IR15&IR14&!IR11
# C_M&R&T==[0,1,0,0]&IR15&IR14&IR11
35
# C_M&R&T==[1,1,0,0]
# C_M&R&T==[1,1,0,1]
# C_M&R&T==[0,0,1,1]&!INT
# C_M&R&T==[0,1,0,0]&IR15&!IR14&!INT
# C_M&R&T==[0,1,0,1]&!INT;
T0 := C_M&R&T==[0,0,1,0]&!IR15
# C_M&R&T==[0,1,1,0]&IR15&IR14&!IR11
# C_M&R&T==[0,1,0,0]&IR15&IR14&IR11
# C_M&R&T==[0,1,1,1]
# C_M&R&T==[1,1,0,0]
# C_M&R&T==[1,1,0,1];
T30.CLK = CK;
T20.CLK = CK;
T10.CLK = CK;
T00.CLK = CK;
"************************DC1 138 ****************************

!SWIBIN = !DC1_0& !DC1_1& !DC1_2; " IB
!GSING8 = !DC1_0& !DC1_1& DC1_2;"
!IRLTOIB = !DC1_0& DC1_1& !DC1_2; " IB
!DC23IN = !DC1_0& DC1_1& DC1_2;"
!GALUTOIB = DC1_0& !DC1_1& !DC1_2; "ALU IB
!GINT = DC1_0& !DC1_1& DC1_2; " IB
!GFtoIb = DC1_0& DC1_1 & !DC1_2; " IB
"*************************DC2 138 *****************************

!GIRL = DC2_0 &!DC2_1&!DC2_2; "16 IRAR 8
!GIRH = DC2_0&!DC2_1&!DC2_2&!Bit8; "8 AR 8
!GARH = !DC2_0& DC2_1&!DC2_2& Bit8 " 2
# DC2_0& DC2_1&!DC2_2&!Bit8;
!GARL = DC2_0& DC2_1&!DC2_2;
"************* 16 32 ********
"
" 1 0 4 8
" 1 0
" I/O
" C-M#
" C-M# 1 C-M# 0!C-M#
!_MIO = C_M& T==[0,0,1,0] " C-M#

# T==[0,1,0,0]&MVRD#LDRR#POP#JMPA#RET#POPF
#STRR#PUSH#PSHF#IN_#OUT
# T==[0,1,0,0]&CALA
# T==[0,1,0,1]&CALA
# !C_M&!_MIO00; " !C-M#
REQ = C_M& T==[0,1,0,0]&IN_#OUT
# !C_M&REQ00;
_WE = C_M& T==[0,0,1,0]

# T==[0,1,0,0]&MVRD#LDRR#POP#JMPA#RET#POPF#IN_
# T==[0,1,0,0]&CALA
# !C_M&_WE00;
36
I2 = C_M&T==[0,0,1,1]&MVRR#JR#JRC#JRNC#JRZ#JRNZ
# T==[0,1,1,0]&LDRR#IN_#OUT
# T==[0,1,0,0]&MVRD#LDRR#POP#JMPA#RET#STRR#PUSH#IN_#OUT
# T==[0,1,0,0]&CALA
# !C_M&I200;
I1 = C_M&T==[0,0,0,0]
# T==[0,0,1,1]&INC#DEC#SHL#SHR
#T==[0,1,1,0]&MVRD#JMPA#STRR#POP#POPF#PUSH#PSHF#RET#IN_#OUT#CALA
# T==[0,1,0,0]&MVRD#LDRR#POP#JMPA#RET#IN_
# T==[0,1,0,0]&CALA
# T==[0,1,1,1]&CALA
# T==[0,1,0,1]&CALA

# !C_M&I100;
!I0 = C_M& T==[0,0,1,0]

# T==[0,0,1,1]&MVRR
# T==[0,1,1,0]&LDRR
# T==[0,1,0,0]&POPF#STRR#PUSH#PSHF#OUT
# T==[0,1,0,1]&CALA
# T==[0,0,0,1]
# !C_M&!I000;
I8 = C_M&T==[0,0,1,1]&SHL#SHR

# !C_M&I800;
I7 = C_M&T==[1,0,0,0]
# T==[0,0,0,0]
# T==[0,0,1,1]&ADD#SUB#AND#OR#XOR_#MVRR#INC#DEC#SHL#JR
# T==[0,0,1,1]&JRC
# T==[0,0,1,1]&JRNC
# T==[0,0,1,1]&JRZ
# T==[0,0,1,1]&JRNZ
# T==[0,1,1,0]&MVRD#JMPA#POP#POPF#PUSH#PSHF#RET#CALA
# T==[0,1,0,0]&MVRD#LDRR#POP#JMPA#RET#IN_
# T==[0,1,1,1]&CALA
# T==[0,1,0,1]&CALA
# T==[0,0,1,1]&MVRD
# T==[0,1,0,1]&CALA

# !C_M&I700;
!I6 = C_M& T==[0,0,0,0]
# T==[0,1,1,0]&MVRD#JMPA#POP#POPF#RET#CALA
# T==[0,1,0,0]&CALA
# T==[0,1,0,1]&CALA
# !C_M&!I600;
I5 = C_M&T==[0,0,1,1]&AND#XOR_#TEST

# !C_M&I500;
I4 = C_M&T==[0,0,1,1]&OR#XOR_

# !C_M&I400;
I3 = C_M&T==[1,0,0,0]
37
# T==[0,0,1,1]&SUB#OR#CMP#DEC
# T==[0,1,1,0]&PUSH#PSHF
# T==[0,1,1,1]&CALA
# !C_M&I300;
B3 = C_M& T==[0,0,1,1] &ADD#SUB#AND#OR#XOR_#CMP#TEST

#MVRR#INC#DEC#SHL#SHR&IR7
# T==[0,1,1,0] &STRR&IR7
# T==[0,1,0,0] &MVRD#LDRR#POP&IR7
# !C_M&B300;
B2 = C_M& T==[1,0,0,0]
# T==[0,0,0,0]
# T==[0,1,1,0] &MVRD#JMPA#POP#POPF#PUSH#PSHF#RET#CALA
# T==[0,1,0,0] &JMPA#RET
# T==[0,1,1,1] &CALA
# T==[0,1,0,1] &CALA
#T==[0,0,1,1] &(ADD#SUB#AND#OR#XOR_#CMP#TEST#MVRR
#INC#DEC#SHL#SHR)&IR6
# T==[0,1,1,0] &STRR&IR6
# T==[0,0,1,1] &JR#JRC#JRNC#JRZ#JRNZ
# !C_M&B200;
B1 = C_M&T==[0,0,1,1] &ADD#SUB#AND#OR#XOR_#CMP#TEST
#MVRR#INC#DEC#SHL#SHR&IR5
# T==[0,1,1,0] &STRR&IR5
# !C_M&B100;
B0 = C_M&T==[1,0,0,0]
#T==[0,0,0,0]
#T==[0,1,1,0] &MVRD#JMPA#CALA
#T==[0,1,0,0] &JMPA#RET
#T==[0,1,0,1] &CALA
#T==[0,0,1,1] &ADD#SUB#AND#OR#XOR_#CMP
#TEST#MVRR#INC#DEC#SHL#SHR&IR4
#T==[0,1,1,0] &STRR&IR4
#T==[0,1,0,0] &MVRD#LDRR#POP&IR4

#T==[0,0,1,1] &JR#JRC#JRNC#JRZ#JRNZ
# !C_M&B000;
A3 = C_M& T==[0,0,1,1]&ADD#SUB#AND#OR#XOR_#CMP
#TEST#MVRR&IR3
#T==[0,1,1,0] & LDRR&IR3
#T==[0,1,0,0] & STRR#PUSH&IR3
# !C_M&A300;
A2 = C_M&T==[1,0,0,0]
#T==[0,0,0,0]
#T==[0,1,1,0] &MVRD#JMPA#POP#POPF#RET#CALA
#T==[0,1,0,1] &CALA
#T==[0,0,1,1] &ADD#SUB#AND#OR#XOR_
#CMP#TEST#MVRR&IR2
#T==[0,1,1,0] &LDRR&IR2
38
#T==[0,1,0,0] &STRR#PUSH&IR2
# !C_M&A200;
A1 = C_M& T==[0,0,1,1] &ADD#SUB#AND#OR#XOR_
#CMP#TEST#MVRR&IR1
#T==[0,1,1,0] &LDRR&IR1
#T==[0,1,0,0] &STRR#PUSH&IR1
# !C_M&A100;
A0 = C_M&T==[1,0,0,0]
#T==[0,0,0,0]
#T==[0,1,1,0] &MVRD#JMPA#CALA
#T==[0,1,0,1] &CALA
#T==[0,0,1,1] &ADD#SUB#AND#OR#XOR_#CMP#TEST#MVRR&IR0
#T==[0,1,1,0] &LDRR&IR0
#T==[0,1,0,0] &STRR#PUSH&IR0
# !C_M&A000;
SST2 = C_M& T==[0,0,1,1]&SHL#SHR

# !C_M&SST200;
SST1 = C_M& T==[0,0,1,1]&SHL
#T==[0,1,0,0]&POPF
# !C_M&SST100;
SST0 = C_M& T==[0,0,1,1]&ADD#SUB#AND#OR#XOR_#CMP#TEST

#INC#DEC#SHR
# !C_M&SST000;
SSH = C_M&0
# !C_M&SSH00;
SCI1 = C_M&0
# !C_M&SCI100;
SCI0 = C_M& T==[1,0,0,0]
#T==[0,0,0,0]
#T==[0,0,1,1]&SUB#INC#CMP

#T==[0,1,1,0]&MVRD#JMPA#POP#POPF#RET#CALA
# !C_M&SCI000;
DC2_2 = C_M&T==[1,0,0,0]
# !C_M&DC2_200;
DC2_1 = C_M&T==[1,0,0,0]
# T==[0,0,0,0]
#T==[0,1,1,0]&MVRD#JMPA#LDRR#STRR#POP#POPF
#PUSH#PSHF#RET#IN_#OUT#CALA
#T==[0,1,1,1]&CALA
# !C_M&DC2_100;
DC2_0 = C_M&T==[1,0,0,0]
#T==[0,0,0,0]
#T==[0,0,1,0]
#T==[0,1,1,0]&MVRD#JMPA#LDRR#STRR#POP#POPF#PUSH
#PSHF#RET#IN_#OUT#CALA

#T==[0,1,1,1]&CALA
# !C_M&DC2_000;
39
DC1_2 = C_M&0
# !C_M&DC1_200;
DC1_1 = C_M&T==[0,0,0,0]
#T==[0,0,1,1]&JR#JRC#JRNC#JRZ#JRNZ
#T==[0,1,1,0]&IN_#OUT
#T==[0,1,0,0]&PSHF
# !C_M&DC1_100;
DC1_0 = C_M&T==[0,0,0,0]
#T==[0,1,0,0]&STRR#PUSH#PSHF#OUT
#T==[0,1,0,1]&CALA
# !C_M&DC1_000;
"******************************************
DECLARATIONS
"Am2910
_MAP,_PL,CC PIN 116,117,109;
CI3,CI2,CI1,CI0 PIN 115,114,113,112 ISTYPE 'REG,KEEP'; "Am2910
SCC3,SCC2,SCC1,SCC0 PIN 85,84,83,82 ISTYPE 'REG,KEEP'; " CC
D7,D6,D5,D4,D3,D2,D1,D0 PIN 118,107,108,122,123,124,125,126; "Am2910
Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0 PIN 127,135,136,137,138,139,140,141; "Am2910
NADR7,NADR6,NADR5,NADR4,
NADR3,NADR2, NADR1,NADR0 NODE ISTYPE 'REG,KEEP';
"
CCM NODE ISTYPE 'COM'; "SCC
" AM01
D = [D7,D6,D5,D4,D3,D2,D1,D0]; "8
Y = [Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0]; "8
" 16
GALSCC = [CI3,CI2,CI1,CI0,SCC3,SCC2,SCC1,SCC0]; "8
NADR = [NADR7,NADR6,NADR5,NADR4,NADR3,NADR2,NADR1,NADR0];
"8
"32
MINST1 = [_MIO00,REQ00,_WE00,I200,I100,I000,I800,I700,I600,I500];
MINST2 = [I400,I300,SST200,SST100,SST000,A300,A200,A100,A000,B300];
MINST3 = [B200,B100,B000,SCI100,SCI000,DC2_200,DC2_100,SSH00];
MINST4 = [DC2_000,DC1_200,DC1_100,DC1_000];
MINST = [MINST1,MINST2,MINST3,MINST4];
"MacroAddress Macros
"27
"
MA00 = Y==[0,0,0,0,0,0,0,0];
MA01 = Y==[0,0,0,0,0,0,0,1];
MA02 = Y==[0,0,0,0,0,0,1,0];
MA03 = Y==[0,0,0,0,0,0,1,1];
MA04 = Y==[0,0,0,0,0,1,0,0];
MA05 = Y==[0,0,0,0,0,1,0,1];
40
MA06 = Y==[0,0,0,0,0,1,1,0];
MA07 = Y==[0,0,0,0,0,1,1,1];
MA08 = Y==[0,0,0,0,1,0,0,0];
MA09 = Y==[0,0,0,0,1,0,0,1];
MA0A = Y==[0,0,0,0,1,0,1,0];
MA0B = Y==[0,0,0,0,1,0,1,1];
MA0C = Y==[0,0,0,0,1,1,0,0];
MA0D = Y==[0,0,0,0,1,1,0,1];
MA0E = Y==[0,0,0,0,1,1,1,0];
MA0F = Y==[0,0,0,0,1,1,1,1];
MA10 = Y==[0,0,0,1,0,0,0,0];
MA11 = Y==[0,0,0,1,0,0,0,1];
MA12 = Y==[0,0,0,1,0,0,1,0];
MA13 = Y==[0,0,0,1,0,0,1,1];
MA14 = Y==[0,0,0,1,0,1,0,0];
MA15 = Y==[0,0,0,1,0,1,0,1];
MA16 = Y==[0,0,0,1,0,1,1,0];
MA17 = Y==[0,0,0,1,0,1,1,1];
MA18 = Y==[0,0,0,1,1,0,0,0];
MA19 = Y==[0,0,0,1,1,0,0,1];
MA1A = Y==[0,0,0,1,1,0,1,0];
MA1B = Y==[0,0,0,1,1,0,1,1];
MA1C = Y==[0,0,0,1,1,1,0,0];
MA1D = Y==[0,0,0,1,1,1,0,1];
MA1E = Y==[0,0,0,1,1,1,1,0];
MA1F = Y==[0,0,0,1,1,1,1,1];
MA20 = Y==[0,0,1,0,0,0,0,0];
MA21 = Y==[0,0,1,0,0,0,0,1];
MA22 = Y==[0,0,1,0,0,0,1,0];
MA23 = Y==[0,0,1,0,0,0,1,1];
MA24 = Y==[0,0,1,0,0,1,0,0];
MA30 = Y==[0,0,1,1,0,0,0,0];
MA31 = Y==[0,0,1,1,0,0,0,1];
EQUATIONS
"************ SCC GAL ********************************
"CC
!CC = !SCC3&!SCC2&!SCC1&!SCC0
#!SCC3& SCC2& SCC1&!SCC0&!IR10
#!SCC3& SCC2&!SCC1&!SCC0&!IR9&!IR8&!C
#!SCC3& SCC2&!SCC1&!SCC0&!IR9& IR8& C
#!SCC3& SCC2&!SCC1&!SCC0& IR9&!IR8&!Z
#!SCC3& SCC2&!SCC1&!SCC0& IR9& IR8& Z
# CCM;
CCM = !SCC3& SCC2& SCC1& SCC0& IR8

#!SCC3& SCC2&!SCC1& SCC0&!IR9&!IR8&!S
#!SCC3& SCC2&!SCC1& SCC0&!IR9& IR8& S
#!SCC3&!SCC2& SCC1&!SCC0&!INT;
NRST=!RESET&!C_M#CK;
"************MAPROM ***********
"MACH Am2910 8 2 Am2910
41
" -PL -MAP -PL 8 NADR
"-MAP MAPROM
D0 = !C_M& !_MAP&SUB#OR#CMP#MVRR#DEC#SHR#JR
#PSHF#PUSH#POP#POPF#STRR#LDRR#MVRD#CALA#RET
# !_PL&NADR0;
D1 = !C_M& !_MAP&AND#OR#TEST#MVRR#SHL#SHR#IN_#OUT
#POP#POPF#LDRR#JMPA#CALA#RET
# !_PL&NADR1;
D2 = !C_M& !_MAP&ADD#SUB#AND#OR#INC#DEC#SHL#SHR#PSHF
#PUSH#POP#POPF#MVRD#JMPA#CALA
# !_PL&NADR2;
D3 = !C_M& !_MAP&XOR_#CMP#TEST#MVRR#INC#DEC#SHR#SHL#STRR
#LDRR#MVRD#JMPA#CALA#
# !_PL&NADR3;
D4 = !C_M& !_MAP&JRC#JRNC#JRZ#JRNZ#JR#IN_#OUT#PSHF#PUSH#POP
#POPF#STRR#LDRR#MVRD# JMPA#CALA
# !_PL&NADR4;
D5 = !C_M& !_MAP&RET
# !_PL&NADR5;
D6 = !C_M& !_MAP&0
# !_PL&NADR6;
D7 = !C_M& !_MAP&0
# !_PL&NADR7;
"*******************************************************
" 16 3 32
" 8
" 1
" :=
" = :=
"
" ROM
"******************** 16 ******************************
NADR7 := 0;
NADR6 := 0;
NADR5 := !C_M&MA04#MA05#MA06#MA07#MA08#MA09#MA0A#MA0B#MA0C
#MA0D#MA0E#MA0F#MA10# MA11#MA13#MA14#MA16#MA18
#MA1A#MA1C#MA1E#MA22#MA24#MA30;
NADR4 := !C_M&MA04#MA05#MA06#MA07#MA08#MA09#MA0A#MA0B#MA0C
#MA0D#MA0E#MA0F#MA10#MA11#MA12#MA13#MA14#MA15
#MA16#MA17#MA18#MA1A#MA1C#MA1D#MA22#MA24#MA30;
NADR3 := !C_M&MA15#MA17#MA1D#MA30;
NADR2 := !C_M&MA12#MA17#MA1D#MA1E;
NADR1 := !C_M&MA15#MA30#MA31;
42
NADR0 := !C_M&0;
NADR.CLK = CK;
CI3 := !C_M&MA00#MA01#MA02#MA19#MA1B#MA1F#MA20#MA21#MA23&NRST;
CI2 := !C_M&MA00#MA01#MA02#MA19#MA1B#MA1F#MA20#MA21#MA23&NRST;
CI1 := !C_M&1&NRST;
CI0 := !C_M&MA04#MA05#MA06#MA07#MA08#MA09#MA0A#MA0B#MA0C#MA0D
#MA0E#MA0F#MA10# MA11#MA12#MA13#MA14#MA15#MA16#MA17
#MA18#MA1A#MA1C#MA1D#MA1E#MA22#MA24#MA30#MA31&NRST;
SCC3 := !C_M&0&NRST;
SCC2 := !C_M&MA10#MA12#MA15#MA17&NRST;
SCC1 := !C_M&MA12#MA15#MA17#MA30&NRST;
SCC0 := !C_M&MA15#MA17&NRST;
GALSCC.CLK = CK;
"*************************32 ***********************
!_MIO00:=!MA00#MA01#MA03#MA04#MA05#MA06#MA07#MA08#MA09#MA0A
#MA0B#MA0C#MA0D#MA0E#MA0F#MA10#MA11#MA12#MA15#MA17
#MA19#MA1B#MA1D#MA1E#MA1F#MA21#MA23#MA30#MA31;
REQ00 := MA13#MA14;
_WE00 :=MA02#MA14#MA18#MA1C#MA20#MA24;
I200 :=MA0B#MA11#MA12#MA14#MA1A#MA1B#MA1C#MA20#MA24#MA30;
I100 := MA01#MA0C#MA0D#MA0E#MA0F#MA12#MA13#MA14#MA15#MA17#MA19
#MA1C#MA1D #MA1E#MA1F#MA20#MA21#MA22#MA23#MA24#MA30#MA31;
!I000 :=!MA00#MA01#MA04#MA05#MA06#MA07#MA08#MA09#MA0A#MA0C
#MA0D#MA0E#MA0F#MA11#MA12#MA13#MA14#MA15#MA17#MA19
#MA1C#MA1D#MA1E#MA1F#MA20#MA21#MA23#MA24#MA30#MA31;
I800 := MA0E#MA0F;
I700 :=MA00#MA01#MA04#MA05#MA06#MA07#MA08#MA0B#MA0C#MA0D
#MA0E#MA11#MA14#MA15#MA17#MA1C#MA1D#MA1E#MA1F
#MA21#MA22#MA23#MA24#MA31;
!I600 :=!MA00#MA02#MA03#MA04#MA05#MA06#MA07#MA08#MA09#MA0A#MA0B
#MA0C#MA0D#MA0E#MA0F#MA10#MA11#MA12#MA13#MA14#MA15#MA16
#MA18#MA19#MA1A#MA1B#MA1C#MA21#MA24;
I500 :=MA06#MA08#MA0A;
I400 :=MA07#MA08;
I300 :=MA00#MA05#MA07#MA09#MA0D#MA15#MA21;
B30 = MA04#MA05#MA06#MA07#MA08#MA09#MA0A#MA0B#MA0C#MA0D
#MA0E#MA0F#MA19#MA1C;
B300 := B30&IR7;
B20 = MA00#MA01#MA11#MA15#MA17#MA1D#MA1E#MA1F#MA21#MA22
#MA23#MA24#MA31;
B200 := !B30&B20 # B30&IR6;
43
B10 = 0;
B100 := !B30&B10 # B30&IR5;
B00 = MA00#MA01#MA11#MA1D#MA1E#MA1F#MA22#MA24#MA31;
B000 := !B30&B00 # B30&IR4;
A30 = MA04#MA05#MA06#MA07#MA08#MA09#MA0A#MA0B#MA1A#MA1B;
A300 := A30&IR3;
A20 = MA00#MA01#MA11#MA17#MA1D#MA1E#MA1F#MA22#MA23#MA31;
A200 := !A30&A20 # A30&IR2;
A10 = 0;
A100 := !A30&A10 # A30&IR1;
A00 = MA00#MA01#MA11#MA1D#MA1E#MA1F#MA22#MA31;
A000 := !A30&A00 # A30&IR0;
SST200:= MA0E#MA0F;
SST100:= MA0E#MA18;
SST000:= MA04#MA05#MA06#MA07#MA08#MA09#MA0A#MA0C#MA0D#MA0F;
SSH00 := 0;
SCI100:= 0;
SCI000:= MA00#MA01#MA05#MA09#MA0C#MA17#MA1D#MA1E#MA1F#MA23#MA31;
DC2_200:= MA00;
DC2_100:= MA00#MA01#MA12#MA15#MA17#MA19#MA1B#MA1D#MA1E#MA1F
#MA21#MA23#MA31;
DC2_000:= MA00#MA01#MA02#MA12#MA15#MA17#MA19#MA1B#MA1D#MA1E
#MA1F#MA21#MA23
#MA31;
DC1_200:= MA01#MA31;
DC1_100:= MA01#MA11#MA12#MA16#MA30#MA31;
DC1_000:= MA13#MA16#MA1A#MA22#MA30;
MINST.CLK = CK;
all.OE = Link;
END

44

1
2
3
4

5

DB
IO
4

16 PC SPC
ZVS
5 START
1-4
1-4
45

5
START
3~5

2 A 2 C
46

MACH
ABEL
210 2-5
210

4
ABCD
4
4
1000 0 PC
1000 RESET
R50
000
BCD
0
AR PC

PC PC+1

0110 0100 B
0010

AR
IR
D
A C
0011 0111 0101

AR
210
0000 0010
47
A 0011 1
B 0110 0100 2 1
IO
C 0110 0111 0101 3 2
2 3
CALR
3
D 0110 0100 0111 0101
4 2 2

1
0011016
A 6
A 2000 ; 16 2000 RAM
2000: MVRD R0,0036 ; 6 ASCII R0
2002: OUT 80 ; 6 80
2003: RET ; RET
2004
G T
2
5 11110

116
SW MVRD R0, 1234 1 8800MVRD B
10000000001001100100

2-5

1111016
48
SWHSWL OUT 80 1000 0110 1000 00008680H

1-4
MRW I2-0 I8-6 I5-3 B A SST SSHSCI DC2 DC1

1000 100 001 011 001 0101 0101 000 001 111 000
0000 100 011 010 000 0101 0101 000 001 011 000
0010 001 000 001 000 0000 0000 000 000 001 000
0110 10000110 100 111 001 000 0000 0000 000 000 011 010
0100 10000110 010 100 001 000 0000 0000 000 000 000 001

5
START
0011016
A
A 2000
MVRD R0,36
OUT 80
JR 2000
RET
U
U 2000
2000:8800 0036 MVRD R0,0036
2002:8680 OUT 0080
2003:41FC JR 2000
2004:8FOO RET
2000:8800 003688H MVRD 00H R0 36H
2002:8680 86H OUT 80H I/O
2003:41FC 41H JR FCH -0100 =11111100B=FCH
2004:8FOO 8FH RET
T2000 T
G2000 6
49
A 2000 U 2000
2000:MVRD R0,36 2000:8800 0036
2002:OUT 80 2002:8680
2003:J R 2000 2003:41FC
MRW I2-0 I8-6 I5-3 B A SST SSHSCI DC2 DC1

1000 100 001 011 001 0101 0101 000 001 111 000
0000 100 010 010 000 0101 0101 000 001 011 000
0010 001 000 001 000 0000 0000 000 000 001 000
0110 10001000 100 011 011 000 0101 0101 000 001 011 000
0100 10001000 001 111 011 000 DR 0000 000 000 000 000
0000 100 010 010 000 0101 0101 000 001 011 000
0010 001 000 001 000 0000 0000 000 000 001 000
0110 10000110 100 111 001 000 0000 0000 000 000 011 010
0100 10000110 010 100 001 000 0000 0000 000 000 000 001
0000 100 010 010 000 0101 0101 000 001 011 000
0010 001 000 001 000 0000 0000 000 000 001 000
0011 01000001 100 101 011 000 0101 0101 000 000 000 010

MACH
MACH

EI
DI
IRET

50
2-5 16
/M R /W I2-0 I8-6 I5-3 B A SST SSH SCI DC2 DC1

1000 100 001 011 001 0101 0101 000 001 111 000 0PCDI#=0
0000 100 011 010 000 0101 0101 000 001 011 000 PCARPC+1PC
0010 001 000 001 000 0000 0000 000 000 001 000 MEMIR
0011 ADD 00000000 100 001 011 000 DR SR 001 000 000 000 DR+SRDR
SUB 00000001 100 001 011 001 DR SR 001 001 000 000 DR-SRDR
AND 00000010 100 001 011 100 DR SR 001 000 000 000 DR or SRDR
CMP 00000011 100 001 001 001 DR SR 001 001 000 000 DR-SR
XOR 00000100 100 001 011 110 DR SR 001 000 000 000 DR xor SRDR
TEST 00000101 100 001 001 100 DR SR 001 000 000 000 DRSR
OR 00000110 100 001 011 011 DR SR 001 000 000 000 DR and SRDR
MVRR 00000111 100 100 011 000 DR SR 000 000 000 000 SRDR
DEC 00001000 100 011 011 001 DR 0000 001 000 000 000 DR-1DR
INC 00001001 100 011 011 000 DR 0000 001 001 000 000 DR+1DR
SHL 00001010 100 011 111 000 DR 0000 110 100 000 000 SHL DR
SHR 00001011 100 011 101 000 DR 0000 101 100 000 000 SHR DR
JR 01000001 100 101 011 000 0101 0101 000 000 000 010 Offset + PCPC
JRC 01000100 100 101 0C1 000 0101 0101 000 000 000 010 Offset + PCPC
JRNC 01000101 100 101 0/C1 000 0101 0101 000 000 000 010 Offset + PCPC
JRZ 01000110 100 101 0Z1 000 0101 0101 000 000 000 010 Offset + PCPC
JRNZ 01000111 100 101 0/Z1 000 0101 0101 000 000 000 010 Offset + PCPC
0110 JMPA 10000000 100 011 010 000 0101 0101 000 001 011 000 PCAR, PC+1PC
LDRR 10000001 100 100 001 000 0000 SR 000 000 011 000 SRAR
51
2-5 16
/M R /W I2-0 I8-6 I5-3 B A SST SSH SCI DC2 DC1

0110 IN 10000010 100 111 001 000 0000 0000 000 000 011 010 IRLARL
STRR 10000011 100 011 001 000 DR 0000 000 000 011 000 DRAR
PSHF 10000100 100 011 011 001 0100 0000 000 000 011 000 SP-1SPAR
PUSH 10000101 100 011 011 001 0100 0000 000 000 011 000 SP-1SPAR
OUT 10000110 100 111 001 000 0000 0000 000 000 011 010 IRLARL
POP 10000111 100 011 010 000 0100 0100 000 001 011 000 SPAR, SP+1SP
MVRD 10001000 100 011 010 000 0101 0101 000 001 011 000 PCAR, PC+1PC
POPF 10001100 100 011 010 000 0100 0100 000 001 011 000 SPAR, SP+1SP
RET 10001111 100 011 010 000 0100 0100 000 001 011 000 SPAR, SP+1SP
0110 CALA 11001110 100 011 010 000 0101 0101 000 001 011 000 PCARPC+1PC
0100 JMPA 10000000 001 111 011 000 0101 0000 000 000 000 000 MEMPC
LDRR 10000001 001 111 011 000 DR 0000 000 000 000 000 MEMDR
IN 10000010 011 111 011 000 0000 0000 000 000 000 000 PORTR0
STRR 10000011 000 100 001 000 0000 SR 000 000 000 001 SRMEM
PSHF 10000100 000 000 001 000 0000 0000 000 000 000 011 FLAGMEM
PUSH 10000101 000 100 001 000 0000 SR 000 000 000 001 SRMEM
OUT 10000110 010 100 001 000 0000 0000 000 000 000 001 R0PORT
POP 10000111 001 111 011 000 DR 0000 000 000 000 000 MEMDR
MVRD 10001000 001 111 011 000 DR 0000 000 000 000 000 MEMDR
POPF 10001100 001 000 001 000 0000 0000 010 000 000 000 MEMFLAG
RET 10001111 001 111 011 000 0101 0000 000 000 000 000 MEMPC
CALA 11001110 001 111 000 000 0000 0000 000 000 000 000 ARQ
0111 CALA 11001110 100 0011 011 0001 0100 0000 000 000 011 000 SP-1SPAR
0101 CALA 11001110 000 010 010 000 0101 0101 000 000 000 001 PCMEMQPC
52
II
Am2910
MACH
ABEL
211
2-6 2-7 2-8
2-6
SCC
CI3-CI0=0011 /CC=0
0000
0010 /INT=0
16
0100 JRCJRNCJRZJRNZ
0101 JRSJRNS
0110 IR10=0IN
0111 IR8=1/
00
0PC ,RESET
01
PCAR
PC+1PC
02
31
MEMIR 04 DR+SRDR PCARPC+1PC
05 DR-SRDR
06 DR and SRDR 3A
03 07 DR or SRDR
A 08
DR xor SRDR
/MAP 09 DR-SR
0A DR and SR 30

0B SRDR STRQ
0C DR+1DR
BD 0D DR-1DR
0E SHL DR
0F SHR DR
10
11 PC+OFFSETPC
B
12 PORTAR R0IO 13
15 SP-1SPAR IOR0 14 PCMEM
17 SPARSP+1SP FLAGMEM 16
QPC
19 DRAR MEMFLAG 18 22
1B SRAR SRMEM 1A
1D PCARPC+1PC MEMDR 1C
D
1E PCARPC+1PC MEMQ 20 21
MEMPC 24 SP-1SPAR
1F PCARPC+1PC
23 SPARSP+1SP
2 11 16
53
2-7 16

1 ADD DR, SR 0000 0000 04

2 SUB DR, SR 0000 0001 05
3 AND DR, SR 0000 0010 06

4 OR DR, SR 0000 0110 07
5 XOR DR, SR 0000 0100 08

6 CMP DR, SR 0000 0011 09
7 TEST DR, SR 0000 0101 0A

8 MVRR DR, SR 0000 0111 0B
9 INC DR 0000 1001 0C

10 DEC DR 0000 1000 0D
11 SHL DR 0000 1010 0E
12 SHR DR 0000 1011 0F
13 JRC OFFSET 0100 0100 10

14 JRNC OFFSET 0100 0101 10
15 JRZ OFFSET 0100 0110 10
16 JRNZ OFFSET 0100 0111 10

17 JR OFFSET 0100 0001 11
18 IN PORT 1000 0010 12

19 OUT PORT 1000 0110 12
20 PSHF 1000 0100 15

21 PUSH DR 1000 0101 15
22 POP DR 1000 0111 17

23 POPF 1000 1100 17
24 STRR [DR], SR 1000 0011 19
25 LORR DR, [SR] 1000 0001 1B
26 MVRD DR, DATA 1000 1000 1D
27 JMPA ADR 1000 0000 1E
28 CALA ADR 1100 1110 1F

29 RET 1000 1111 23
54
2-8 16
CI3~0 SCC30 MRW I2~0 I8~6 I5~3 B A SST SSHSCI DC2 DC1
00 ALL SRMEMCC#=0 30 0011 0000 000 100 001 000 0000 1000 000 000 000 001
01 PCARPC+1
ALL 00 1110 0000 100 011 010 000 0101 0101 000 001 011 000
PC
02 ALL MEMIR 00 1110 0000 001 000 001 000 0000 0000 000 000 001 000
03 ALL /MAP 00 0010 0000 100 000 001 000 0000 0000 000 000 000 000
04 ADD DR+SRDR 30 0011 0000 100 001 011 000 1000 1000 001 000 000 000
05 SUB DR-SRDR 30 0011 0000 100 001 011 001 1000 1000 001 001 000 000
06 AND DRSRDR 30 0011 0000 100 001 011 100 1000 1000 001 000 000 000
07 OR DRSRDR 30 0011 0000 100 001 011 011 1000 1000 001 000 000 000
08 XOR DRSRDR 30 0011 0000 100 001 011 110 1000 1000 001 000 000 000
09 CMP DR-SR 30 0011 0000 100 001 001 001 1000 1000 001 001 000 000
0A TEST DRSR 30 0011 0000 100 001 001 100 1000 1000 001 000 000 000
0B MOVRR SRDR 30 0011 0000 100 100 011 000 1000 1000 001 000 000 000
0C INC DR+1DR 30 0011 0000 100 011 011 000 1000 0000 001 001 000 000
0D DEC DR-1DR 30 0011 0000 100 011 011 001 1000 0000 001 000 000 000
0E SHL SHL DR 30 0011 0000 100 011 111 000 1000 0000 110 100 000 000
0F SHR SHR DR 30 0011 0000 100 011 101 000 1000 0000 101 100 000 000
10 JR CND JRCnd OFFSET 30 0011 0100 100 000 001 000 0000 0000 000 000 000 000
11 JR Offset+IPPC 30 0011 0000 100 101 011 000 0101 0101 000 000 000 010
12 IN/OUT PORTAR 14 0011 0110 100 111 001 000 0000 0000 000 000 011 010
13 R0IO 30 0011 0000 010 011 001 000 0000 0000 000 000 000 001
14 IOR0 30 0011 0000 011 111 011 000 0000 0000 000 000 000 000
15 PSH/F SP-1SP,AR 1A 0011 0111 100 011 011 001 0100 0000 000 000 011 000
16 FLAGMEM 30 0011 0000 000 000 001 000 0000 0000 000 000 000 011
17 POP/F SPAR,SP+1SP 1C 0011 0111 100 011 010 000 0100 0100 000 001 011 000
18 MEMFLAG 30 0011 0000 001 000 001 000 0000 0000 010 000 000 000
55
2-8 16
CI3~0 SCC30 MRW I2~0 I8~6 I5~3 B A SST SSHSCI DC2 DC1
19 ALL SRMEMCC#=0 30 0011 0000 000 100 001 000 0000 1000 000 000 000 001
1A LORR SRAR 00 1110 0000 100 100 001 000 0000 1000 000 000 011 000
1B STRR DRAR 00 1110 0000 100 011 001 000 1000 0000 000 000 011 000
1C ALL MEMDRCC#=0 30 0011 0000 001 111 011 000 1000 0000 000 000 000 000
PCARPC+1PC
1D MVRD 1C 0011 0000 100 011 010 000 0101 0101 000 001 011 000
CC#=0
1E JMPA PCARPC+1PC 24 0011 0000 100 011 010 000 0101 0101 000 001 011 000
1F CALA PCARPC+1PC 00 1110 0000 100 011 010 000 0101 0101 000 001 011 000
20 MEMQ 00 1110 0000 001 111 000 000 0000 0000 000 000 000 000
21 SP-1SPAR 00 1110 0000 100 011 011 001 0100 0000 000 000 011 000
PCMEMQPC
22 30 0011 0000 000 010 010 000 0101 0101 000 000 000 001
CC#=0
23 RET SPARSP+1SP 00 1110 0000 100 011 010 000 0100 0100 000 001 011 000
24 MEMPCCC#=0 30 0011 0000 001 111 011 000 0101 0000 000 000 000 000
30 ALL STRQCC#=INT# 3A 0011 0010 100 111 000 000 0000 0000 000 000 000 011
PCARPC+1PC
31 02 0011 0000 100 011 010 000 0101 0101 000 001 011 000
CC#=0

,
3A , 31 0011 0000 100 000 001 000 0000 0000 0000 000 000 000

.
3AH 31H 3AH

EIDIIRET 3
56

0001016
A 6
A 2000 ; 16 2000 RAM
2000: MVRD R0,0036 ; 6 ASCII R0
2002: OUT 80 ; 6 80
2003: RET ; RET
2004
G T

5 11010
SW MVRD R0, 1234 1 8800MVRD B
000102031D1C3031
1-7
1101016
SWHSWL OUT 80 1000 0110 1000 00008680H

1-7
CI3 SCC MRW I2-0 I8-6 I5-3 A B SST SSHSCI DC2 DC1
00 1110 0000 100 001 011 001 0101 0101 000 001 111 000
57
00 1110 0000 100 011 010 000 0101 0101 000 001 011 000
00 1110 0000 001 000 001 000 0000 0000 000 000 001 000
00 0010 0000 100 000 001 000 0000 0000 000 000 000 000
14 0011 0110 100 111 001 000 0000 0000 000 000 011 010
30 0011 0000 010 011 001 000 0000 0000 000 000 000 001

5
START
0011016
A
A 2000
MVRD R0,36
OUT 80
JR 2000
RET
U
U 2000
2000:8800 0036 MVRD R0,0036
2002:8680 OUT 0080
2003:41FC JR 2000
2004:8FOO RET
2000:8800 003688H MVRD 00H R0 36H
2002:8680 86H OUT 80H I/O
2003:41FC 41H JR FCH -0100 =11111100B=FCH
2004:8FOO 8FH RET
T2000 T
G2000 6
58
A 2000 U 2000
2000:M VR D R 0,36 2000:8800 0036
2002:OUT 80 2002:8680
2003:J R 2000 2003:41FC
CI 3 ~0 SCC MRW I2 -0 I 8 - 6 I 5 - 3 B A SST SSH SCI D C2 D C1
00 00 1110 0000 100 001 011 0 0 1 0 1 01 0101 000 001 111 000
01 00 1110 0000 1 00 010 010 000 0 10 1 0101 000 001 011 000
02 00 1110 0000 001 000 001 000 0 00 0 0000 000 000 001 000
03 00 0010 0000 100 000 001 0 0 0 0 0 00 0000 000 000 000 000
1D 1C 0011 0000 100 011 011 0 00 0 1 01 0101 000 001 011 000
1C 30 0011 0000 001 111 011 0 00 1 0 00 0000 000 000 000 000
12 14 0011 0110 100 111 001 0 0 0 0 00 0 0000 000 000 011 010
13 30 0011 0000 010 011 001 000 0 00 0 0000 000 000 000 001
11 30 0011 0000 100 101 011 000 0101 0101 000 000 000 010
30 3A 0011 0010 100 111 000 0 0 0 0 0 00 0000 000 001 000 011
31 02 0011 0000 100 011 010 000 0 10 1 0101 000 001 011 000

MACH
MACH

EI
DI
IRET

MACH
226

4 CPU CPU
CPU CPU
4

8 DB CPU 8
8
59
TTL 0~4V 12V 0~12V
MAX202 +12V -12V

8 IO
AR IN
8 DB IB R0 OUT
R0 IB DB
8 IO IN OUT 8
16 IN OUT
R0 IO 4 1
8 4 16
16 80/81
90/91-F0/F1 8
4 4 IN
OUT 2 2 4
4
IN 80 8 R0
OUT 80 R0 8
IN 81 8 R0
OUT 81 R0 8

PC
IN OUT
TTL

IN

542 1 3 3 MVRR
R0,R0
RESET START
RESET G
0000
60
RESET CALA 0000
2 Intel-8251
PC
2
3
2
2 9
2
1
1
1
2 90 91
212
A 2000
2000: IN 81 ; 1
2001: SHR R0
2002: SHR R0
2003: JRNC 2007 ; 2
2004: IN 80 ; R0
2005: OUT 80 ; 1
2006: OUT 90 ; 2
2007: IN 91 ; 2
2008: SHR R0
2009: SHR R0
200A: JRNC 2000 ; 1
200B: IN 90 ; R0
200C: OUT 80 ;
200D: JR 2000 ; 1
200E: RET ;
61

2
1

2
1

212 2

MAX202

227

3 MACH
62

EI
DI IRET

XXX4
4
PC
3
3 16 XXX4
XXX8
XXXC

80 160
M
3

M
2 2
2 1
2 1 3
3
2 3 80 160 3

2 2 2
M

228

40
DMA
63

Intel-8255 8
Intel-8255 8

229

T P

A U

A U
A A

T P

64
ROM
PC

2210

PC

A

A
G
G PC WORD
PC G
3 3

(1)
(2)
(3) 3
65
2211
TEC-XP+ 16 16
8

TEC-XP+ 16 16 8
8 8
10KB
16 8 8
8
16
8
2001

1 8 16
2
3
4 2 PC
5 PC
6 220V
7
8

3 TEC-XP+ 16 16
8
8
8

1 16 16
TEC-XP+ 16
16
2 8
3 8 8
8 PC
4 8
5 8
6 8
7
8 8
9 8
10
11 8
66
12
1 8
2 8
16
3 8
4 8
5 8
6 8
7 8
8 8
9 8 16

16 8

10

67
TEC-XP+FPGA

HDLHardware Description anguageHDLFPGA
EDA
TEC-XP+
FPGA ASIC
TEC-XP+ VHDL 16 CPU
31 TEC-XP+FPGA
TEC-XP+FPGA TEC-XP+ TEC-XP 16
TEC-XP+FPGA TEC-XP+ 16 CPU TEC-XP+
CPU TEC-XP+
311 TEC-XP+FPGA
TEC-XP+FPGA
1 16 8
16

18K 16 8K ROM 2K RAM

8K FPGA
4 Am2901 ALU 8
16
C Z 0V S
5
6 INTEL8251 PC
MAX202 +12V -12V
7
8
/
9
10 5V 3A 1.5~2.5A
220V
11
12

TEC-XP+FPGA 31 31 TEC-XP+FPGA
68

/

MAX202 74LS139

74S138 74LS138

16 16
16
ROM
16
74LS04
RAM
74S00 74LS161
16
FPGA
R S ROM 16
8 16 16
16
37
RESET START 5 16
37
16
36
31 TEC-XP+FPGA
312 CPU
CPU CPU
CPU
CPU TEC-XP+ 16
TEC-XP+ 16
CPU TEC-XP+ 16
CPU CPU
TEC-XP+FPGA CPU xinlinx SPARTANII

XC2S200 20 2352 CLB14 4Kb RAM
208 PQFP in-system programmable TEC-XP+
16 CPU
TEC-XP+ 16
TEC-XP+ 16
TEC-XP+ 16
VHDL
CPU
VHDL CPU
69
FPGA CPU CPU TEC-XP
16 CPU TEC-XP+FPGA
PC
ROM
313 FPGA
FPGA
GAL20V8 MACH PLD
GAL20V8 MACH
FPGA
CLBconfigurable logic block
IOBI/O blockinterconnect
resource3
FPGA
CLB 1 2
D
D CLK
1
3
CLB IOB
FPGA
EPROM
FPGA
32 VHDL
VHDL Very High Speed Integrated Circuit
Hardware Description Language
IEEE VHDL
VHDL
VHDL
bottom-up
top-down
VHDL
VHDL
VHDL
VHDL
VHDL CPU
VHDL component
entity
architecture
70

when elsewiTEC select
VHDL signal
<=
VHDL variableconstant
:=
VHDL process
VHDL
label: peocess --
; --
being --
; --
end process label--
peocess CPU
if case
<= DC-2 <= DC22 downto 0;

:=
addr_A := CONV_INTTEGER UNSIGNEDaddrA ;

if
if TECen 1; else 2; endif;
if 1 TECen 1;
elsif 2 TECen 2; else 3; endif;
if result = 0000000000000000 TECen Zero<=1 else Zero<=0; end
if;
16 ALU 0 Zero
case
case is
when 1 = 1;
when 2 = 2;
71

when oTECenrs = n;
end case;
case resultOper is
when 010 => resultOut <= operant1;
when oTECers => resultOut <= result;
end case
ALU resultOper
A ALU
delta
CPU
VHDL
librarylibrary
library ieeeieee
use
use ieee.std_logic_1164.all;
use ieee.std_logic_ariTEC.all;
use ieee.std_logic_unsigned.all; ieee
VHDL
33 FPGA CPU
CPU CPU
331 CPU
VHDL
VHDL
CPU CPU 3 Am2901controllordata_IB

CPU.vhdAm2901.vhdcontrollor.vhddata_IB.vhd
72
FLAGOUT
ALU_Y AR timingOut DC_2 MIO REQ WE
AR IR IRout
IR DC2
RESET CLK
FLAG(2)
FLAG Y
timing FLAG(3)

REQ MIO WE
WE MIO ALU FLAG IR
ALU C Z
D IB OB
B A Q
Control signals
timing
RAM generator
Q15 Q0 DC1
OB

RAM15 RAM0
Memory /
SST SSH SCI IO Port
CLK D SST SSH SCI CLK RESET
I Badd Aadd I Badd Aadd
32 TEC-XPFPGA CPU
CPUcpu.vhd
CPU CPU 3
CPU CPU entity port

CPU VHDL
in
out inout buffer
std_logic std_logic_vector15 downto 0 16
3 port
architecture CPU
3 component Am2901
Controllor
Data_IB IO
begin
3
FLAG
FLAGOUT IR_out
MIO_TREQ_TWE_T MIOREQWE
stateOut DC2DC1
DC_2 DC_1
clkprocess
DC2
IRAR 3
DC2 001 IR IB 3 DC2 011 AR
ALU AR IO
MIOREQWE3 IO

73
/
Am2901Am2901.vhd
TEC-XP+FPGA TEC-XP+ 16 Am2901

ALU Q
4
Am2901
ALU16 Q 3
5 4 TEC-XP+FPGA
Am2901
port 23
16 16 4
4 CZVS
12
ControlprocessfuncChoise,RE,S,Cin ALU
case 4
processresultOper,operant1,result ALU 16
A ALU
processresultOper,result,RAM0,RAM15
REG_Result_IN:processClk,Result_IN
Q_Result_IN:processClk Q
processresultOper,Q,Result,Q0,Q15 Q
SSHSCi:processSSHSCi,C_out,C,result0,result15,Q15
ALU Q
SST_Process:processClk
R_Data:processD,operant1,dataOrigin ALU R
10 S_DATA:processoperant1,operant2,Q,dataOrigin ALU S
11 A_Locker:processClk,A A
12 B_Locker:processClk,B B
data_IBData_ib.vhd
IB OB IB CPU OB
CPU IO
Port dc1
miowelink 3 ib ob
processDC1,MIO,WE DC1
IB OB
IB 8
processMIO,WE IB
74
OB OB
controllor controllor.vhd

CPU
TEC-XP+ 16
TEC-XP+
16
Port
RESET clk IR 16 C 0 Z
32 4
3
instruction:processIR15 downto 8 29
timeKeeper:processclk,RESET
TEC-XP+16
VHDL
29
IR15IR14 0X A
10 B 11 CD IR11 0 C 1 D
3 if
3 RESET Timing3
1 0
signal_process:processtiming 32
if
32

010000000000010 3
0011100101 2 CALA
HDML
A 00011 A 00011
MIOREQWE 100
75
if
if Timing = 01000 TECen
elseif expandTiming = 0000 TECen 32
endif;

29
instruction
100000000010 32
01110100 CALA

3
0011 A 17 A
17 DC2 000 IO
17 MIOREQWE
100
8 AB IR3 downto 0 IR
7 downto 4 4 AB 0000 IR7 downto 4

5 AB 0101 PC
PC 8
8 ALU D
CNCZNZ
PC I8~I6 010 B
I8~I6 001 B
I7 0 1

signal_process:processtiming
32
3 instruction:processIR15 downto 8

timeKeeper:processclk,RESETsignal_process:processtiming
FPGA TEC-XP 16
MACH ABEL
FPGA
76
206 204 202 162 160 158
207 205 203 163 161 159
1 2 155 154
3 4 153 152
7 6 151 150
. .
. .
. .
. .
. .
45 46 111 110
47 48 109 108
49 50 107 106
55 57 59 99 101 103
54 56 58 98 100 104
FPGA VHDL
FPGA
RAM ROM ExROM
DataBus0DataBus15 31014182022
AddressBus0AddressBus15 232427293133374145
ExAddressBus0ExAddressBus12 13 187189191195199203
ExAddressBus13ExAddressBus15
ExDataBus0ExDataBus15 162168172176178181
/MIO,REQ,/WE 205,204,206
CLK pin182Reset pin160,
Pin56 Pin90Pin148
Pin46Pin49Pin150Pin152Pin154Pin161
P2 LED
57 58 59 60 61 62 63 67
68 69 70 71 73 74 75 81
82 83 84 86 87 88 89 9024
P3 LED
94 95 96 97 9899100101
108109110111112113114115
132136138139140141147149
VHDL TEC-XP+FPGA CPU

TEC-XP+(FPGA) CPU VHDL
77
library ieee;
use ieee.std_logic_unsigned.all;
entity CPU is
port( CLK :in std_logic;
RESET :in std_logic;
MIO :out std_logic;
REQ :out std_logic;
WE :out std_logic;
HndIns :in std_logic;
Link :in std_logic;
SWTOIB :out std_logic;
OMIO :out std_logic;
ALU_Y :out std_logic_vector(15 downto 0);
FLAGOUT :out std_logic_vector(3 downto 0);
OB :inout std_logic_vector(15 downto 0);
ADDR :buffer std_logic_vector(15 downto 0);
IRout :buffer std_logic_vector(15 downto 0);
DC_2 :inout std_logic_vector(2 downto 0);
stateOut :out std_logic_vector(3 downto 0);
addra :inout std_logic_vector(3 downto 0);
addrb :inout std_logic_vector(3 downto 0);
SSHSCI :inout std_logic_vector(2 downto 0);
resultOper :inout std_logic_vector(2 downto 0);
funcChoose :inout std_logic_vector(2 downto 0);
dataOrigin :inout std_logic_vector(2 downto 0);
SST :inout std_logic_vector(2 downto 0);
DC_1 :inout std_logic_vector(2 downto 0);
GMEM :out std_logic );
end CPU;
architecture CPU_architecture of CPU is

component AM2901
port(
CLK :in std_logic;
dataOrigin :in std_logic_vector(2 downto 0);
funcChoose :in std_logic_vector(2 downto 0);
resultOper :in std_logic_vector(2 downto 0);
SSHSCi :in std_logic_vector(2 downto 0);
SST :in std_logic_vector(2 downto 0);
addrA :in std_logic_vector(3 downto 0);
addrB :in std_logic_vector(3 downto 0);
D :in std_logic_vector(15 downto 0);
resultOut :out std_logic_vector(15 downto 0);
FLAG :out std_logic_vector(3 downto 0)
);
end component;
component controllor
port(
IR :in std_logic_vector(15 downto 0);
C,Z :in std_logic;
78
state :out std_logic_vector(3 downto 0);
RESET :in std_logic;
MIO :out std_logic;
REQ :out std_logic;
WE :out std_logic;
addrA :out std_logic_vector(3 downto 0);
addrB :out std_logic_vector(3 downto 0);
SSHSCI :out std_logic_vector(2 downto 0);
resultOper :out std_logic_vector(2 downto 0);
funcChoose :out std_logic_vector(2 downto 0);
dataOrigin :out std_logic_vector(2 downto 0);
SST :out std_logic_vector(2 downto 0);
DC1 :out std_logic_vector(2 downto 0);
DC2 :out std_logic_vector(2 downto 0);
clk :in std_logic;
Link :in std_logic);
end component;
component data_IB
Port (DC1 :in std_logic_vector(2 downto 0);
ALU :in std_logic_vector(15 downto 0);
FLAG :in std_logic_vector(3 downto 0);
IR :in std_logic_vector(15 downto 0);
WE :in std_logic;
MIO :in std_logic;
IB :out std_logic_vector(15 downto 0);
OB :inout std_logic_vector(15 downto 0);
Link :in std_logic);
end component;
signal state :std_logic_vector(3 downto 0);

signal ALU,IReg,IB,ADDR_temp :std_logic_vector(15 downto 0);
signal FLAG,PORTA, PORTB :std_logic_vector(3 downto 0);
signal SSHSCi_T :std_logic_vector(2 downto 0);
signal DC2,DC1 :std_logic_vector(2 downto 0);
signal MIO_T,REQ_T,WE_T :std_logic;
signal C_T,Z_T :std_logic;
signal SWIBOUT_T :std_logic_vector(2 downto 0);
signal GMEM_T :std_logic_vector(1 downto 0);
begin
C_T<=FLAG(3);
Z_T<=FLAG(2);
unit1:controllor port
map(IReg,C_T,Z_T,state,RESET,MIO_T,REQ_T,WE_T,addra,addrb,
SSHSCI,resultOper,funcChoose,dataOrigin,SST,DC1,DC2,CLK,Link);
unit2:AM2901 port
map(CLK,dataOrigin,funcChoose,resultOper,SSHSCI,SST,addra,addrb,IB,ALU,FLAG);
unit5:data_IB port map(DC1,ALU,FLAG,Ireg,WE_T,MIO_T,IB,OB,Link);
79
FLAGOUT <= FLAG;
IRout <= IReg;
DC_2 <= DC2(2 downto 0);
ALU_Y <= ALU;
WE <= WE_T;
REQ <= REQ_T;
MIO <= MIO_T;
stateOut <= state;
GMEM_T <=HndIns&Link;
DC_1 <=DC1;
process(clk)
begin
if (GMEM_T="01") TECen GMEM<='0'; else GMEM<='1';
end if;
if ((HndIns='1' and MIO_T='0' and WE_T='1') or Link='0')
TECen SWTOIB<='0'; else SWTOIB<='1';
end if;
if (Link='0' or (HndIns='1' and MIO_T='0'))

TECen OMIO<='0'; else OMIO<='1';
end if;
if(clk='0') TECen
case DC2(2 downto 0) is
when "001" => IReg <= IB;
when "011" => ADDR <= ALU;
when oTECers => NULL;
end case;
else
end if;
end process;
end CPU_architecture;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITEC.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity data_IB is
Port ( dc1 : in std_logic_vector(2 downto 0);
ALU : in std_logic_vector(15 downto 0);
flag: in std_logic_vector(3 downto 0);
ir : in std_logic_vector(15 downto 0);
we : in std_logic;
mio : in std_logic;
ib : inout std_logic_vector(15 downto 0);
ob : inout std_logic_vector(15 downto 0);
Link: in std_logicX);
end data_IB;
architecture Behavioral of data_IB is
80
begin
process(DC1,MIO,WE)
begin
if (Link='1') TECen
case DC1 is
when "000" =>
if(MIO='0' and WE='1') TECen IB <= OB; end if;
when "001" => IB <= ALU;
when "010" =>
case IR(7) is
when '0' => IB <= "00000000"&IR(7 downto 0);
when '1' => IB <= "11111111"&IR(7 downto 0);
when oTECers =>
end case;
when "011" => IB <= flag&"000000000000";
when oTECers =>
end case;
end if;
end process;
process(MIO,WE)
begin
if (Link='1') TECen
if(MIO='0' and WE='0')
TECen OB <= IB; else OB <= "ZZZZZZZZZZZZZZZZ";
end if;
end if;
end process;
end Behavioral;
library ieee;
use ieee.std_logic_unsigned.all;
entity Am2901 is
port(
CLK :in std_logic;
dataOrigin :in std_logic_vector(2 downto 0);
funcChoose :in std_logic_vector(2 downto 0);
resultOper :in std_logic_vector(2 downto 0);
SSHSCi :in std_logic_vector(2 downto 0);
SST :in std_logic_vector(2 downto 0);
addrB :in std_logic_vector(3 downto 0);
addrA :in std_logic_vector(3 downto 0);
D :in std_logic_vector(15 downto 0);
resultOut :out std_logic_vector(15 downto 0);
FLAG :out std_logic_vector(3 downto 0)
);
81
end AM2901;
architecture Behavioral of AM2901 is

signal cin :std_logic;
signal C_out,Z_out,V_out,S_out :std_logic;
signal RAM0,RAM15,Q0,Q15:std_logic;
signal Q,Q_temp,Result_IN :std_logic_vector(15 downto 0);
signal A,B,operant1,operant2,operant1_temp,
operant2_temp,RE,S,result:std_logic_vector(15 downto 0);
signal C,Zero,Over,Sign:std_logic;
subtype regData is integer range 0 to 65535;

type regArray is array(0 to 15) of regData;
signal RAM :regArray;
begin
FLAG<=C_out&Z_out&V_out&S_out;
Control:process(funcChoose,RE,S,Cin)
begin
case funcChoose is
when "000"=>result<=RE+S+cin;
when "001"=>result<=S-RE - not Cin;
when "010"=>result<=RE-S - not Cin;
when "011"=>result<=RE or S;
when "100"=>result<=RE and S;
when "101"=>result<= not(RE) and S;
when "110"=>result<=RE xor S;
when "111"=>result<=not(RE xor S);
when oTECers=>NULL;
end case;
----------------------------------
process(resultOper,operant1,result)
begin
case resultOper is
when "010"=>
resultOut<=operant1;
when oTECers=>
resultOut<=result;
end case;
end process;
------------------ -----------------
process(resultOper,result,RAM0,RAM15)
begin
case resultOper(2 downto 1) is
when "01"=>result_IN<=result;
when "10"=>result_IN<=RAM15&result(15 downto 1);
when "11"=>result_IN<=result(14 downto 0)&RAM0;
when oTECers=>NULL;
end case;
82
end process;
REG_Result_IN:process(Clk,result_IN)
variable addr_A,addr_B:integer range 0 to 15;
begin
addr_A:=CONV_INTEGER(UNSIGNED(addrA));
addr_B:=CONV_INTEGER(UNSIGNED(addrB));
IF CLK='0' TECEN
IF resultOper(2)='1' or resultOper(1)='1'TECEN
RAM(addr_B)<=CONV_INTEGER(UNSIGNED(result_IN));
END IF;
END IF;
A<=STD_LOGIC_VECTOR(CONV_UNSIGNED(RAM(addr_A),16));
B<=STD_LOGIC_VECTOR(CONV_UNSIGNED(RAM(addr_B),16));
end process REG_Result_IN;
Q_Result_IN:process(Clk)
begin
if Clk'event and Clk='1' TECen
case resultOper is
when "000"=> Q<=Q_temp;
when oTECers=>NULL;
end case;
end if;
end process Q_Result_IN;
process(resultOper,Qresult,Q0,Q15)
begin
case resultOper is
when "000"=>
Q_temp<=result;
when "100"=>Q_temp<=Q15&Q(15 downto 1);
when "110"=>Q_temp<=Q(14 downto 0)&Q0;
when oTECers=>NULL;
end case;
end process;
----------------------------------------------------
SSHSCi_Process:process(SSHSCi,C_out,C,result(0),result(15),Q(15))
begin
case SSHSCi is
when "000"=>cin<='0';
when "001"=>cin<='1';
when "010"=>cin<=C_out;
when "100"=>
if resultOper(2)='1' and resultOper(1)='1'
TECen RAM0<='0';
elsif resultOper(2)='1' and resultOper(1)='0'
TECen RAM15<='0';
end if;
83
when "101"=>
TECen RAM0<=C_out;
TECen RAM15<=C_out;
end if;
when "110"=>
TECen
RAM0<=Q(15);
Q0<=not result(15);
TECen
RAM15<=C;
Q15<=result(0);
end if;
when "111"=>
TECen
RAM0<='0';
Q0<='0';
TECen
RAM15<=result(15) xor Over;
Q15<=result(0);
end if;
when oTECers=> NULL;
end case;
end process SSHSCi_Process;
--------------------------------------
SST_Process:process(CLk)
begin
if CLk'event and Clk = '1' TECen
case SST is
when "000"=>
C_out<=C_out;
V_out<=V_out;
Z_out<=Z_out;
S_out<=S_out;
when "001"=>
C_out<=C;
Z_out<=Zero;
V_out<=Over;
S_out<=Sign;
when "010"=>
C_out<=D(15);
Z_out<=D(14);
V_out<=D(13);
S_out<=D(12);
when "011"=>
C_out<='0';
Z_out<=Z_out;
84
V_out<=V_out;
S_out<=S_out;
when "100"=>
C_out<='1';
Z_out<=Z_out;
V_out<=V_out;
S_out<=S_out;
when "101"=>
C_out<=result(0);
Z_out<=Z_out;
V_out<=V_out;
S_out<=S_out;
when "110"=>
C_out<=result(15);
Z_out<=Z_out;
V_out<=V_out;
S_out<=S_out;
when "111"=>
C_out<=Q(0);
Z_out<=Z_out;
V_out<=V_out;
S_out<=S_out;
when oTECers=>null;
end if;
end process SST_Process;
-------------------------------------------------------
R_Data:process(D,operant1,dataOrigin)
Begin
case dataOrigin is
when "000" => RE<=operant1;
when "001" => RE<=operant1;
when "010" => RE<="0000000000000000";
when "011" => RE<="0000000000000000";
when "100" => RE<="0000000000000000";
when "101" => RE<=D;
when "110" => RE<=D;
when "111" => RE<=D;
when oTECers=>NULL;
end case;
end process R_Data;
S_DATA:process(operant1,operant2,Q,dataOrigin)
Begin
case dataOrigin is
when "000" => S<=Q;
when "001" => S<=operant2;
when "010" => S<=Q;
when "110" => S<=Q;
85
when "111" => S<="0000000000000000";
when oTECers=>NULL;
end case;
end process S_DATA;
A_LOCKER:process(Clk,A)
begin
if Clk'event and Clk='0'
TECen operant1_temp<=A;
end if;
if Clk='1'
TECen operant1<=A;
else operant1<=operant1_temp;
end if;
end process A_LOCKER;
B_Locker:process(CLk,B)
begin
if CLK'event and CLk='0'
TECen operant2_temp<=B;
end if;
if CLk='1'
TECen operant2<=B;
else operant2<=operant2_temp;
end if;
end process B_Locker;
end Behavioral;
--***********************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITEC.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity controllor is
Port ( IR : in std_logic_vector(15 downto 0);
c : in std_logic;
z : in std_logic;
Link : in std_logic;
clk : in std_logic;
RESET : in std_logic;
state : out std_logic_vector(3 downto 0);
MIO : out std_logic;
REQ : out std_logic;
WE : out std_logic;
addra : out std_logic_vector(3 downto 0);
addrb : out std_logic_vector(3 downto 0);
SSHSCI: out std_logic_vector(2 downto 0);
86
resultOper: out std_logic_vector(2 downto 0);
funcChoose: out std_logic_vector(2 downto 0);
dataOrigin: out std_logic_vector(2 downto 0);
SST : out std_logic_vector(2 downto 0);
DC1 : out std_logic_vector(2 downto 0);
DC2 : out std_logic_vector(2 downto 0) );
end controllor;
architecture Behavioral of controllor is

signal timing : std_logic_vector (4 downto 0);
signal CMDadd,CMDsub,CMDand,CMDcmp,CMDxor,CMDtest,CMDor,CMDmvrr: boolean;
signal CMDdec,CMDinc,CMDshl,CMDshr,CMDjr,CMDjrc,CMDjrnc,CMDjrz,CMDjrnz: boolean;
signal CMDjmpa,CMDldrr,CMDin : boolean;
signal CMDstrr,CMDpshf,CMDpush,CMDout,
CMDpop,CMDmvrd,CMDpopf,CMDret,CMDcala: boolean;
signal CMDadc,CMDsbb,CMDrcl,CMDrcr,CMDasr,CMDnot,CMDjmpr,CMDjrs: boolean;
signal CMDjrns,CMDclc,CMDstc,CMDei,CMDdi,CMDcalr,CMDldra,CMDldrx,CMDstrx:
boolean;
signal CMDstra,CMDiret: boolean;
signal I : std_logic_vector (8 downto 0);
begin
resultOper <= I(8 downto 6);
funcChoose <= I(5 downto 3);
dataOrigin <= I(2 downto 0);
instruction:
process(IR(15 downto 8))
begin
CMDadd <= (IR(15 downto 8) = "00000000" );
CMDsub <= (IR(15 downto 8) = "00000001" );
CMDand <= (IR(15 downto 8) = "00000010" );
CMDcmp <= (IR(15 downto 8) = "00000011" );
CMDxor <= (IR(15 downto 8) = "00000100" );
CMDtest <= (IR(15 downto 8) = "00000101" );
CMDor <= (IR(15 downto 8) = "00000110" );
CMDmvrr <= (IR(15 downto 8) = "00000111" );
CMDdec <= (IR(15 downto 8) = "00001000" );
CMDinc <= (IR(15 downto 8) = "00001001" );
CMDshl <= (IR(15 downto 8) = "00001010" );
CMDshr <= (IR(15 downto 8) = "00001011" );
CMDjr <= (IR(15 downto 8) = "01000001" );
CMDjrc <= (IR(15 downto 8) = "01000100" );
CMDjrnc <= (IR(15 downto 8) = "01000101" );
CMDjrz <= (IR(15 downto 8) = "01000110" );
CMDjrnz <= (IR(15 downto 8) = "01000111" );
CMDjmpa <= (IR(15 downto 8) = "10000000" );
CMDldrr <= (IR(15 downto 8) = "10000001" );
CMDin <= (IR(15 downto 8) = "10000010" );
CMDstrr <= (IR(15 downto 8) = "10000011" );
CMDpshf <= (IR(15 downto 8) = "10000100" );
CMDpush <= (IR(15 downto 8) = "10000101" );
CMDout <= (IR(15 downto 8) = "10000110" );
87
CMDpop <= (IR(15 downto 8) = "10000111" );
CMDmvrd <= (IR(15 downto 8) = "10001000" );
CMDpopf <= (IR(15 downto 8) = "10001100" );
CMDret <= (IR(15 downto 8) = "10001111" );
CMDcala <= (IR(15 downto 8) = "11001110" );
end process;
timeKeeper:process(clk,RESET)
begin
if (Link='1') TECen timing(4) <= '0';
if (RESET = '1')
TECen timing <= "01000";
elsif ((clk'event) and (clk = '1'))
TECen timing(3) <= '0';
if ((((timing = "00010") and (IR(15) = '1'))

or ((timing = "00110") and (IR(15) = '1'))
or ((timing = "00100") and (IR(15) = '1') and (IR(14) = '1') and (IR(11) = '1'))
or (timing = "00111")) )
else timing(2) <= '0';
end if;
if ( ( (timing = "00000")
or (timing = "00010")
or ((timing = "00110") and (IR(15 downto 11) = "11100"))
or ((timing = "00100") and (IR(15 downto 14) = "11") and (IR(11) = '1')) ) )
end if;
if ((((timing = "00010") and (IR(15) = '0'))

or ((timing = "00110") and (IR(15 downto 11) = "11100"))
or (timing = "00111")
or ((timing = "00100") and (IR(15 downto 14) = "11") and (IR(11) = '1')) ) )
end if;
end if;
end if;
end process;
state <= timing(3 downto 0);
signal_produce_Process:process(timing)
begin
if (Link='1') TECen
--------------------------- 01000 -----------------------------------

if (timing = "01000") TECen
88
MIO <= '1';
REQ <= '0';
WE <= '0';
addra <= "0101";
addrb <= "0101";
SSHSCI <= "001";
I <= "011001001";
SST <= "000";
DC1 <= "000";
DC2 <= "111";
-------------------------- 00000 ------------------------------------

elsif (timing = "00000") TECen
MIO <= '1';
REQ <= '0';
WE <= '0';
addra <= "0101";
addrb <= "0101";
SSHSCI <= "001";
I <= "010000011";
SST <= "000";
DC1 <= "000";
DC2 <= "011";
--------------------------- 00010 --------------------------------------

MIO <= '0';
REQ <= '0';
WE <= '0';
addra <= "0000";
addrb <= "0000";
SSHSCI <= "000";
I <= "001011000";
SST <= "000";
DC1 <= "000";
DC2 <= "001";
------------------------ 00011 ---------------------------------

MIO <= '1';
REQ <= '0';
WE <= '0';
-------------------A -------------------------------------
if (CMDadd or CMDsub or CMDand or CMDcmp or CMDxor or CMDtest or CMDor or CMDmvrr)
TECen addra <= IR(3 downto 0);
elsif (CMDdec or CMDinc or CMDshl or CMDshr)
TECen addra <= "0000";
else addra <= "0101";
end if;
--------------------B -------------------------------------
if (CMDadd or CMDsub or CMDand or CMDcmp or CMDxor or CMDtest
or CMDor or CMDmvrr or CMDdec or CMDinc or CMDshl or CMDshr)
TECen addrb <= IR(7 downto 4);
89
else addrb <= "0101";
end if;
--------------------SSHSCI--------------------------------------
if (CMDsub or CMDcmp or CMDinc)
TECen SSHSCI <= "001";
else SSHSCI <= "000";
end if;
--------------------I(8)-------------------------------------
if (CMDshl or CMDshr)
TECen I(8) <= '1';
else I(8) <= '0';
end if;
---------------------I(7)--------------------------------------
if (CMDcmp or CMDtest or CMDshr)
TECen I(7) <= '0';
elsif (CMDjrc) TECen I(7) <= C;
elsif (CMDjrnc) TECen I(7) <= not(C);
elsif (CMDjrz) TECen I(7) <= Z;
elsif (CMDjrnz) TECen I(7) <= not(Z);
else I(7) <= '1';
end if;
--------------------I(6)----------------------------------------
I(6) <= '1';
--------------------I(5)-I(3)-----------------------------------
if (CMDsub or CMDcmp or CMDdec)
TECen I(5 downto 3) <= "001";
elsif (CMDtest or CMDand) TECen I(5 downto 3) <= "100";
elsif (CMDxor) TECen I(5 downto 3) <= "100";
elsif (CMDor) TECen I(5 downto 3) <= "011";
else I(5 downto 3) <= "000";
end if;
--------------------I(2)-I(0)-------------------------------
if (CMDdec or CMDinc or CMDshr or CMDshl)
elsif (CMDjr or CMDjrc or CMDjrnc or CMDjrz or CMDjrnz)
elsif (CMDmvrr) TECen I(2 downto 0) <= "100";
else I(2 downto 0) <= "001";
end if;
--------------------SST-----------------------------------
if (CMDshl) TECen SST <= "110";
elsif (CMDshr) TECen SST <= "101";
elsif (CMDmvrr or CMDjr or CMDjrc or CMDjrnc or CMDjrz or CMDjrnz)
TECen SST <= "000";
else SST <= "001";
end if;
------------------------DC1---------------------------------
if (CMDjr or CMDjrc or CMDjrnc or CMDjrz or CMDjrnz)
TECen DC1 <= "010";
else DC1 <= "000";
end if;
------------------------DC2---------------------------------
90
DC2 <= "000";
----------------------- 00110 ----------------------------------------

MIO <= '1';
REQ <= '0';
WE <= '0';
----------------------A ----------------------------------------
if (CMDin or CMDstrr or CMDpshf or CMDpush or CMDout)
TECen addra <= "0000";
elsif (CMDpop or CMDpopf or CMDret) TECen addra <= "0100";
elsif (CMDldrr) TECen addra <= IR(3 downto 0);
end if;
----------------------B -----------------------------------------
if (CMDldrr or CMDin or CMDout) TECen addrb <= "0000";
elsif (CMDjmpa or CMDmvrd or CMDcala) TECen addrb <= "0100";
elsif (CMDstrr) TECen addrb <= IR(7 downto 4);
end if;
-----------------------SSHSCI------------------------------------
if (CMDjmpa or CMDpop or CMDmvrd or CMDpopf or CMDret or CMDcala)
TECen SSHSCI <= "001";
else SSHSCI <= "000";
end if;
------------------------I(8~6)---------------------------------
if (CMDldrr or CMDin or CMDstrr or CMDout) TECen I(8 downto 6) <= "001";
elsif (CMDpshf or CMDpush) TECen I(8 downto 6) <= "011";
else I(8 downto 6) <= "010";
end if;
------------------------I(5~3)----------------------------------
if (CMDpshf or CMDpush)
else I(5 downto 3) <= "000";
end if;
-------------------------I(2~0)---------------------------------
if (CMDldrr) TECen I(2 downto 0) <= "100";
elsif (CMDin or CMDout)
else I(2 downto 0) <= "011";
end if;
-------------------------SST-------------------------------------
SST <= "000";
-------------------------DC1------------------------------------
if (CMDin or CMDout)
TECen DC1 <= "010";
else DC1 <= "000";
end if;
--------------------------DC2-----------------------------------
DC2 <= "011";
---------------------- 00100 -----------------------------------
91
--------------------------MRW---------------------------------
MIO <= '0';
if (CMDin or CMDout)
TECen REQ <= '0';
else REQ <= '1';
end if;
if (CMDstrr or CMDpshf or CMDpush or CMDout)

TECen WE <= '0';
else WE <= '1';
end if;
-------------------------addra--------------------------------
if (CMDstrr or CMDpush)
TECen addra <= IR(3 downto 0);
end if;
--------------------------B ----------------------------------
if (CMDldrr or CMDpop or CMDmvrd) TECen addrb <= IR(7 downto 4);
elsif (CMDret or CMDjmpa)
TECen addrb <= "0101";
end if;
--------------------------SSHSCI-------------------------------
SSHSCI <= "000";
---------------------------I(8~6)---------------------------
if (CMDcala) TECen I(8 downto 6) <= "000";
elsif (CMDjmpa or CMDldrr or CMDin or CMDpop or CMDmvrd or CMDret)
else I(8 downto 6) <= "001";
end if;
--------------------------I(5~3)----------------------------
I(5 downto 3) <= "000";
--------------------------I(2~0)-----------------------------
if (CMDpshf or CMDpopf) TECen I(2 downto 0) <= "000";
elsif (CMDstrr or CMDpush or CMDout)
else I(2 downto 0) <= "111";
end if;
---------------------------SST-----------------------------
if (CMDpopf) TECen
SST <= "010";
else
SST <= "000";
end if;
---------------------------DC1----------------------------
if (CMDpshf) TECen
DC1 <= "010";
elsif (CMDstrr or CMDpush or CMDout) TECen
DC1 <= "001";
else
DC1 <= "000";
92
end if;
---------------------------DC2----------------------------
DC2 <= "000";
---------------------- 00111 -----------------------------
--------------------------MRW------------------------------
MIO <= '1';
REQ <= '0';
WE <= '0';
addra <= "0000";

addrb <= "0100";
SSHSCI <= "000";
I <= "011001011";
SST <= "000";
DC1 <= "000";
DC2 <= "011";
---------------------- 00101 ---------------------------------
MIO <= '0';
REQ <= '0';
WE <= '0';
addra <= "0101";
addrb <= "0101";
SSHSCI <= "000";
I <= "010000010";
SST <= "000";
DC1 <= "001";
DC2 <= "000";
end if;
else
addra <= "ZZZZ";
addrb <= "ZZZZ";
SSHSCI <= "ZZZ";
I <= "ZZZZZZZZZ";
SST <= "ZZZ";
DC1 <= "ZZZ";
DC2 <= "ZZZ";
end if;
end process;
end Behavioral;
93
FPGA_CPU
FPGA CPU
CPU
CPU
BASIC TEC-XP+ 16

BASIC TEC-XP+ 16
8
TEC-XP+ 16 8
TEC-XP+ 8
TEC-XP+ TEC-XP+ 16 TEC-XP+FPGA
FPGA
CPU TEC-XP+ 16
TEC-XP+ 16 CPU
MIPS16e
FPGA EDA
CPU
FPGA EDA
94

PC
BASIC
41
16 16
DLX

8 4 4
DR SR
IO /
/ /
8 IR15~IR8
IR15IR14 0X A 10 B 11 CD
IR11 CD IRH11=0 C IRH11=1 D
IR13 IRH13=0 IRH13=1
IR12 0
IR11~IR8
16
3

4
A ADDSUBANDORXORCMPTESTMVRRDECINCSHLSHR
JRJRCJRNCJRZJRNZ
ADCSBBRCLRCRASRNOTCLCSTCEICIJRS
JRNSJMPR
B JMPALDRRSTRRPUSHPOPPSHFPOPFMVRDINOUTRET
C CALRLDRASTRALDRXSTRX
D CALA
IRET

95
A
B I/O
AR I/O
C CALR
AR
AR
D
4 29
19

2~4 ADDSUBMVRR
MVRDJRJMPASTRX
1~2
R ADD R0,R1 R0R0+R1MVRR R0,R1
R1 R0 R
STRR [R8],R9 R9 R8
D MVRD R3,1234 R0 1234
X LDRX R1,12[R2] R2
12 R1
A JMPA 2008 2008 STRA
[2000], R2 R2 2000
4-1 4-2
96
4-1

CZVS

00000000 DRSR ADD DRSR 2 **** DRDR+SR

00000001 DRSR SUB DRSR 2 **** DRDR-SR
00000010 DRSR AND DRSR 2 ** DRDR and SR
00000011 DRSR CMP DRSR 2 **** DR-SR
00000100 DRSR XOR DRSR 2 ** DRDR xor SR
00000101 DRSR TEST DRSR 2 **** DR and SR
00000110 DRSR OR DRSR 2 ** DRDR or SR
A
00000111 DRSR MVRR DRSR 2 DRSR

00001000 DR0000 DEC DR 1 **** DRDR-1

00001001 DR0000 INC DR 1 **** DRDR+1

00001010 DR0000 SHL DR 1 * DRCDR*2
00001011 DR0000 SHR DR 1 * DRCDR/2
01000001 OFFSET JR ADR 1 ADR
01000100 OFFSET JRC ADR 1 C=1 ADR
01000101 OFFSET JRNC ADR 1 C=0 ADR
01000110 OFFSET JRZ ADR 1 Z=1 ADR
01000111 OFFSET JRNZ ADR 1 Z=0 ADR
10000000 0000000 JMPA ADR 1

ADR
ADR16
10000001 DRSR LDRR DR[SR] 2
DR[SR]
10000010 I/O PORT IN I/O PORT 1
R0[I/O PORT]
10000011 DRSR STRR [DR]SR 2
B [DR]SR
10000100 00000000 PSHF 0
FLAG
10000101 0000SR PUSH SR 1
SR
10000110 I/O PORT OUT I/O PORT 1
[I/O PORT]R0
10000111 DR0000 POP DR 1
DR
10001000 DR0000 MVRD DRDATA 2
DRDATA
10001100 00000000 POPF 0
FLAG
10001111 00000000 RET 0

D ADR
11001110 00000000 CALA ADR 1

CZVS *

16 R0~R15
R4 16 SP R5 16 PC
DRSR
97
4-2

CZVS

00100000 DRSR ADC DRSR 2 **** DRDR+SR+C

00100001 DRSR SBB DRSR 2 **** DRDR-SR-C
00101010 DR0000 RCL DR 1 * DR C
00101011 DR0000 RCR DR 1 * DR C
00101100 DR0000 ASR DR 1 * DRDR
A
00101101 DR0000 NOT DR 1 **** DR/DR

01100000 0000SR JMPR SR 1 SR

01100100 OFFSET JRS ADR 1 S=1 ADR

01100101 OFFSET JRNS ADR 1 S=0 ADR
01101100 00000000 CLC 0 0 C=0
01101101 00000000 STC 0 1 C=1
01101110 00000000 EI 0 INTE1
01101111 00000000 DI 0 INTE0
11100000 0000SR CALR SR 1 SR

11100100 DR0000 LDRA DR[ADR] 2 DR[ADR]
11100101 DRSR C
LDRX DROFFSET[SR] 2 DR[DATA+SR]
ADR16
11100110 DRSR
STRX DROFFSET[SR] 2 [DATA+SR]SR
ADR16
11100111 0000SR STRA [ADR]SR 1 [ADR]SR
ADR16
D
1101111 00000000 IRET 0

CZVS *

42
421

PC
/
0000h-0A2F 2K
ROM 0A30h-1FFFh ROM

30
98

PC DOS Debug AUGPTR

D E 8

PC
4 16 h
A
A [adr]
adr A [ ] adr adr
A
^
2
TP
U
U [adr]
15
, U ,
A
U
U
U
G
G [adr]

RET
99
T P
P [adr]
T [adr]
PC
T P T P T
P CALL
CALL
P T
ROM ROM
T P
T P
R
R [reg]reg R0-R15
R
PC F=8
CZVSP1P0 2 00
R
D
D [adr]
120
4 16
8 4 16 8 ASCII
ASCII .
D D
120TEC-XP 16
D ESC
E
E [adr]

422

CR 16 0D TAB 16 09
100
UBLK *256+TAB
10 256 TAB 16
20092
RSADR RSLEN 2600h 2601h

I/O 80h,81h
MAPREG 260Eh 17
16
ORG 0000h 16 0000
0000h~087D
ROM END
END 087Eh~0A2Fh

ROM
RAM RAM 2048 2000h~27FFh

2600h~27FFh RAM
2000h~25FFh RAM
RAM
AUDE 4 2000h RAM
2
16 PC SP
16 PC SP
MAPREG 17
27FEh
2780h

101

0000~0072h
41
GTP
RET
102

U,A,E,D,G,P,T
0

R
(2780,27FE)

1

80,81

E DGA
UTP

27FEh
27FFh
CALA

D E U A G T P R 8
D E
U A GT P
R 8 4
103
1 D E
DADR

R15
,
R15
R3
EADR

R15 R15
2 ,
R12 R15
R2
2
416

. 2

416
2

':,

1
2
0, 1

5

1

15
D E
DADR EADR
42(a) D 42(b) E
D
D R15 D
104
DADR R15D R15 128
D 42a 4
8
.
ESC ESC
E
E R15 E
EADR R15E R15
E E 42b
2 U A
U 15
U R15 U UADR
R15U 15
PC
43
U
0000000000101001 8
00000000 ADD 8
4 DR 0010 R2 4 SR
1001 R9
0000000000101001 ADD R2R9
1 2
1 2 4 16
4 2
2000hh 2000
2000 0029 ADD R2, R9 2

8 4

1 8 2
1 8 1 2 4 8 IO
offset 2
offset
4 0000 R0
4 4
8 16
200516
0100000111111100
JR 8 11111100 offset 4+1+offset
2002 JR 20028
105
16 8 8

UADR R2-R3-
U
R15

R14 R12 1

2

3

R0 R13

88 4
16
R0

2
5

IO
6
IO

DW
7

[,
], 8

,
,[, 9
]

10

UADR

43 U()
A
A R15 A AADR
106
R15A 44
A
ADD R2, R9
1 ADDADD
00 2 R2
R2 2
3 R9
9
0029 0000000000101001
JR 2002 2005
16 41 offset 20022005 1
4 8 FC 16 41FC

3 G T P
G
G PC G
45a

16 PC
SP
MAPREG 17
MAPREG
17
27FEh 2780h
G
LDRR R5[R14]
021Ah PC
PC
2
021Bh 021Bh

107

BUFF
4 STR 1

1 R0
AADR
R15
R13

R13

SAVSP
R15 R8,

2

R14,R13
2

3
BUFF 9

R131

10

AADR 3

'Error',CR,LF

R131
10
44 A()
108

SCHREG
BUFF 4

STR
R11

SEARCH
0 R3

STR R12,
PC

PC SP
1,

SAVSP ,

021B
R0
2

PC

3

,

PCSP

45(a) G

45(b) SCHREG SEARCH

R0
Z0

021Bh
RETMON RET
RET
PC
G
109
T P
T P PC
T P CALA
T 46
T G G
T
T
2
PC
G
RET
46 T
PC
3
1 CALAJMPA JR CALAJMPA
2 R15 JR
OFFSET R15
2 RETJRCALAJMPA JRcnd
R15
3 JRCJRNCJRZ JRNZ 2
R15
OFFSET R15

46
2
JMPA
46
PC JMPA
JMPA
46 GPT
16
PC SP
R
P T CALA
CALA
46 CALA
110

PC
R0
R13

R8,
PC
()
R15,
R2

RET
R15

JR SP2780h

PC
JMPA

IADR8

CALA 2
()R15
T
STEP1
2
BRKINS12,
JRcnd
JMPA STEP2 ,
BRKPT12

PC
2
3 4, 1 2,

1 JRFLAG, R151 R151
SPSAVSP,
SP,
STEP4
PC
2 2
BRKINS34, JMPA 1 2, 3 4
JMPA STEP3 , R151 R151
BRKPT34
STEP2 STEP3
J Rcnd
IADR7 J Rcnd
SP
JRcnd
R15 SP

SP

SP
46 T
4 R
R 16
R
GPT
R
2 47
111

RSTR R8, 2
R3 R0 R15
DISPRG
R0=
2
R
i=1 8 DISPR
Ri=

2 416
'='
R9=

:_
416
i=10 15 2

Ri=
2
F,=,
8

PC

DISPREG CHGR

() ()

UADR
47 R

INLNE 48a
4

2 R2 R3
Backspace
112

BUFF
INDAT 48b
4
E
Backspace
4
4
0~4 16 R15
113
48(a) INLNE

DEL

(R3)1

(R3)

0 Z=1

(R2)1

1(R2)

4 8(b) INDAT

4
4

R15

Z=1
NZ
SEARCH 46b
SEARCH
SCHREG
114
4 4
0 8
0 5
SEARCH 4
0

SCHREG
SEARCH SCHREG
10
SCHREG 2
SEARCH
4 STR
10
10
ASCNUMSTR 4 R15
NUMASC R15

ASCNUM
0 9 0
ASCII 4 A
F ASCII
0 ASCII 7 10 15
4 4 R15
ASCNUM 49a
115
49(b) NUMASC

R2,
0 R15
R2, R0 0 R15
R154
R0R15
4

R0 , R0
0 R0 R0
DISPCH
>9
A''F' ,
16 CHRNU
2 M
R0
C=1, C=0
4

R154

R0,
-1

R0

4
ASC
C
<0'
R10
R0,
NC
NC
Z,NZ
<=9'
C
C

<A'
49(a) ASCNUM NC
NC
<Z'
C
49(c) LDBYTE ASC

NUMASC R15 4
0 9 0 ASCII
10 15 0 ASCII
7 A F
4
116
R15 R15 12 0
4 4 R0
R15 4 0
4
NUMASC 49b
LDBYTE ASC
ASC R0
49C09
AZ 2
C C

A 0-19+1A-1 Z+1
ASCII MVRD
LDBYTE R10 R0
ASC R0
2 2
RSPORT 0 1
0 10
1 1 2 1 80
PORT1D 81PORT1C 2
82PORT2D 83PORT2C

2
IN OUT IN
OUT IN
OUT
1

2 1
CPU

TESTIN

R0 2 R0
C
INCH:

? R0
00FF R0 R0
OUT1CH:
R0
117

OUT2CH 2 2 R0
R0 SHDW R0
8 OUT1CH LOWCH
R0
,
DSP2B R0 OUT2CH
DSP6B DSP2B
RETURN R0 CRLF 0D0A
OUT2B
UCOM2 TAB R0 OUT2CH
UBLK TAB R0 OUT2CH
WSTR1CH R2 0
TEC-XP+ 16
0
R2 R0 0
UPCASE 05E9
R0
INCH 0524
R0 R0 0
LBYTE 0531
R0 0
HBYTE 0535
R0 0
TESTCR 062B
ZNZ
STBYTE 063D R12
R0 R12 R12 1
SHDW 0654
R0 8
SHD4 0656
R0 4
SHUP 065B
R0 8
SHU4 065D
R0 4
118
DISPCH 0685
R0 4 16 16 '0_9A_Z
CHRNUM 06B0
R0 16 NCC R0
TESTRC 0719 R10
R10 ]
Z NZ
TESTLC 06F5
R10 [
Z NZ
MOVSTR 0736 R10
STR 4 [R10] 4
STR
GETVAL 0725 R10
STR 4 16 R15ZNZ
PAUSE 075C
ESC
SIGEXT 0825
R0 1 0FFh, 00h
TESTCM 06F5 R10

C=1 C=0
TSTINS 07AA
R0 Z: NZ:
USCHOP 07E7
R0 Z
NZ:R2R3
INSINLNE 05C1
BUFF R2:Z 0
REMOVESP 082D R3
BUFF
SHOWR 0847
R0~R8 R9~R15
USCHC 07BC
R0 Z 0
4 Z 1
CHGR 0186
R0
SAVREG 0220

R15~R6R3~R0
SAVREG 0220
119
SAVSP
R15~R6R3~R0
RESREG 023A
SAVSP R0~R3
R6~R15
RECV 078B
PC
SEND 0769
RSADR RSLEN
16 16
DSPDAT 0662 R14

[R14] R15R14 1 16 R15
INSINLNE 05C1 R2 BUFF
BUFF , R2, Z
0
4 3 PC
PCEC IBM-PC IBM-PC
PC
PCEC
1 PCEC
IBM-PC PCEC816 PCEC16
PC 1 2
96008 1
IBM-PC
2
PC F10 ,
0--Return to CRT Monitor
1--Send a file to TEC-2
2--Reeceivee a file from TEC-2
3--Return to IBM-PC MSDOS
0
3 IBM-PC
1
ASEC816
ASEC16.COD ORG
RAM
2 PC 2
IBM-PC PC
E 27CFH27CEH
8 8 27CDH27CCH
8 8
3 PCEC
120
SHIFT/F10 SCR.TMP
SHIFT/F10 PCEC
44
441
PC
16 TEC-2 PASCAL 8
16 TEC-2000
TEC2000 16 8
116 8
16 8
16 8 16
8
Generate8BitCode
true 8 16
16 8
2
1
16 8
a TEC2000 16
8 b
16 16 8 8 4
16 8
16
JRC JC
2 include
TEC2000
MSDOS
COPY
C #include #include
#include
include C #include
SrcFiles
include
121
include
include
include
include
8 include 7
1
3
8 16
_
1 2
2 .cod
3
4
RowScan RowAsm
Turbo Pascal
Turbo Pascal

Turbo Pascal
4
8 3 8 2
8 3 TEC2000
Borland
2
10 16 10 3030D
30d 30 30h30H0A1h 16
+-*/
-128127 ,
3
TEC2000 16 8
122

shl asl pshf Pushf
mvrd mvd jrc jcjraejaejrnb jnb
jrnc jncjrnaejnaejrb jb jrz jzjre je
16 jrnz jnzjrne jne jmpa Jmp
cala call ei Sti
di cli ldra Read
stra writ write jrs Js
jrns jns
pshf pushf jz Je
8
jnz jne jc jae jnb

jnc jnae jb writ Write

16 8 8 46
8 16
8

OP DR, SR add r0, r1
1 2 1 OP DR, [SR] OP DR SR ldrr r2, [r3]
OP [DR], SR strr [r4], r5
21 1 1 OP PORT OP PORT in 80h
22 1 1 OP SR OP 0000 SR push r0
23 1 1 OP DR OP DR 0000 dec r0
TEC
3 0 1 OP OP 00000000 Stc
2000
OP DR, ADDR OP DR 0000 ADDR ldra r0, 1000h
16
41 2 2 OP DR, DATA OP DR 0000 DATA mvrd r1, 2000h
OP ADDR, SR OP 0000 SR ADDR stra 3000h, r2
OP DR, ADDR[SR] ldrx r0, 1000h[r1]
42 2 2 OP DR SR ADDR
OP ADDR[SR], DR strx 2000h[r2], r3
5 1 1 OP OFFSET OP OFFSET jrz 40h
6 1 2 OP ADDR OP 00000000 ADDR jmpa 4000h
1 2 1 OP DR2, SR2 OP4 DR2 SR2 add r0, r1
21 1 1 OP DR2 OP6 DR2 dec r0
22 1 1 OP DRi OP6 DRi inc r8
23 1 1 OP PORT2 OP6 PORT2 in 0
TEC
3 0 1 OP OP Stc
2000
4 2 2 OP DR2, DATA8 OP6 DR2 DATA8 mvd r0, 10h
8
5 1 2 OP OFFSET OP OFFSET jz 40h
6 2 3 OP DR2, ADDR OP6 DR2 ADDR read r0, 1000h
7 1 3 OP ADDR OP ADDR jump 1000h
8 1 2 OP PORT OP PORT inpt 80h
123
1 OP
8 DR SR 4 PORT 8 ADDR
16 DATA 16 OFFSET 8 OPDR
SRPORTDATA
DRi R0 R3 R8 R15 12 4
45

1 BASIC
2 BASIC 3
BASIC
451 BASIC
4
1 TEC-2000 BASIC main modulev1.00
2 TEC-2000 BASIC
ROM 0A30
3 G 0A30 BASIC
2
TEC-2000 BASIC
BASIC

new BASIC
run BASIC
delete BASIC
list BASIC
system
BASIC run

let
dim
input
print
fornext
goto
gosub
return
end

+-*/\^ mod
>>= < <= <>
notand orxor
124
sin costanatan
log10 exp10
sgn absintsqr
3
057fh056bh0589h
4

16bit 16bit
BSASIC
452 BASIC
BASIC 6
8
5
5
10 for i=1 to 5
20 input ai
30 next i
40 for i=1 to 4
50 for j=i+1 to 5
60 if ai>aj TECen b=ai : ai=aj : aj=b
70 next j
80 next i
90 for i=1 to 5
100 print ai
110 next i
120 end
100 1
10 dim a100
20 for i=2 to 100
30 j=i
40 j=j+1
50 if i*j<100 TECen ai*j=1 : goto 40
60 next i
70 for i=2 to 99
80 if ai=0 TECen print i,
90 next i
100 end
125
10 dim src10, dst10, tmp10
20 input n
30 i=n : srcn=1 : dstn=2 : tmpn=3
40 i=i-1 : srci=srci+1 : dsti=tmpi+1 : tmpi=dsti+1
50 if i>0 TECen 40
60 i=i+1 : if i>n TECen end
70 if srci-1<>srci TECen 60
80 print srci; --- >; dsti,
90 i=i-1 : srci=tmpi+1 : dsti=dsti+1 : tmpi=srci+1
100 if i>0 TECen 40
110 goto 60
8 8 *8
8
10 dim colstate7, fdiagstate14, bdiagstate14, queenpos7

20 i=0 : count=0
30 queenposi=0
40 if colstatequeenposi +fdiagstatei-queenposi+7+bdiagstatei+queenposi
>0
TECen 170
50 colstatequeenposi =1 : fdiagstatei-queenpsi+7=1 : bdiagstatei+queenpos
i=1
60 if i<7 TECen i=i+1 : goto 30
70 count=count+1
80 print : print Result: ; count; :
90 j=0
100 k=0
110 if k=queenposj TECen print 0 ; : goto 130
120 print . ;
130 k=k+1 : if k<8 TECen 110
140 print
150 j=j+1 : if j<8 TECen 100
160 colstatequeenposi =0 : fdiagstatei-queenpsi+7=0 : bdiagstatei+queenpos
i=0
170 queenpsi= queenpsi+1 : if queenposi<8 TECen 40
180 i=i-1 : if i>=0 TECen 160
190 print : print Total results: ; cout
200 end
100 2
10 for i=4 to 100 step 2

20 for j=i to i-2
30 n=j
40 gosub 200
50 if p=0 TECen 100
60 n=i-j
70 gosub 200
80 if p=0 TECen 100
90 print I ; = ; + ; n , : goto 100
100 next j
110 next i
120 end
126
200p=0
210if n/2 <2 TECen 250
220for k=2 to n/2
230if n mod k =0 TECen 260
240next k
250p=1
260return
0~360
10 pi=3.14159
20 for i=0 to 20
30 angle=pi*i/10
40 for j=1 to 40+25*sinangle
50 pring ;
60 next j
70 print *
80 next i
90 end
453
BASIC
32 R0 R1
R2 R3 R2 R3 R0 R1
CZ
32 16
32 16
IEEE 8 23

2
2
2
410
Z C Z=1Z=0
C=1R0R1>=R2R3C=0
R0R1<R2R3
127

R3
C

2 2
S=0 C=1
R3R1 R1R3

R2R0 R0R2
410

2
411
0
0 R2R3
R0R1
2 0
2
2 R6 R7
R8 R6
24 24
2
16 16 R9
0
2
R9 1 1 24
128
R9
0 2
2
411
129

R3R12
0R2
R6

R1
0
0
R1 C=0

R0 R12
0 R0R1
R1

R6
1
R7
1

>= 24
R8,

R6

'0' R0R1

R8, R7
R6

R1 R3

1

R9

R9 0

=1 < 16 ?
=1

R3 R2 16
16R2
R9C
R9R30
2

R7 = 0 ?

R3 R2 R9
11
411
130

412
2 0
0
2 2
1272 127 2
127 2 R7
R1 R0
R3 R2 R9 R0
R2 R8
R2 0 0 R3 R2 8
16 R2
0 24
R2 C C=1
R2 R2
8 24 R0 R1
R9

413
0 0 0 R11=1
0 0 0
C=0
2 2
1272 127
127 2 R7
R1 R0
R3 R2 R8 R9
R10

0
0
26
R0 R1

131

=0
C=0
'0' R0R1
=0
C=0

R6
,
R7
R8=0
R9=0
16
R2 =0 ? 8 R10,
0' R3

16 R0
R2 C

C =0 ?

C
R2C,

1

C R3= 0 ?
R0
C R1
R2 R9
412
132
0
R11=0
0 0

0
R11=1 R7
0 R8
C=0 0 R9
26R10

R1R3
R0R2
R0
R1 26
0' R9
413
133

3 3 1
3 TEC-2000
TEC-XP

BASIC
51
511

CPU
CPU
TEC-2000
PC
PC
PC
Tec2ksim.exe 51
134
51
52
16 8
16 8

16 53
135
53 16

2 .cod
.cod BASIC
BASIC 54
1 BASIC COD MAIN.COD 54
54
55
136
55
2 BASIC G0A30
BASIC BASIC
10 FOR I=1 TO 10
20 PRINT ISINI
30 NEXT I
40 END
LIST RUN SYSTEM BASIC
56 BASIC
BASIC .tba BASIC
512

PC
TEC-2000
PC Windows
137
1
2 TEC-2000 16
3 TEC-2000 16
4 TEC-2000 16
TEC-2000 16
1
2
3 16
4
5 R /D
E
6 A U
G TP
7

16

A 2000 16 2000 RAM
2000: MVRD R00036 6 ASCII R0
2002: OUT 80 6 80
2003: RET RET
2004
2000h
16 h RET
RET

209
A 2020
MVRD R200OA
MVRD R00030 0 ASCII
OUT 80 R0
DEC R2 1
JRZ 202E 10
PUSH R0 R0
2028IN 81
SHR R0
JRNC 2028
POP R0 R0
INC R0
JR 2024
202ERET
138

2020
G 2020
: IN 81SHR R0JRNC 2028 4 MVRR R0R0
AZ 26
309
2040 :
A 2040
MVRD R20030
MVRD R30039
2044IN 81
SHR R0
SHR R0
JRNC 2044
IN 80 R0
MVRD R1, 00FF
AND R0, R1 R0 0
CMP R0 R2 0
JRNC 2053
CMP R0 R3 9
JC 2053
OUT 80
JMPA 2044 2044
2053RET
AZ0
9
4 1 10
A 2060
MVRD R10000 0
MVRD R200OA
MVRD R30000
2066INC R3
ADD R1 R3
CMP R3 R2
JRNZ 2066
RET
R R1
5
E 20F0 6 A~F 20F0
41 42 43 44 45 46
139
A 2080
MVRD R3 0006
MVRD R9 20F0
2084LDRR R0, [R2] R0
MVRD R8 2100 2100
CALR R8
DEC R3
JRZ 208C
INC R2
JR 2084 2084
208CRET
A 2100 2100
OUT 80 R0
MVRD R1 0020 R0
ADD R0 R1
STRR [R2],R0 R0 LDRR
2105IN 81
SHR R0
JRNC 2105
RET
D 20F0
20F0
0061 0062 0063 0064 0065 0066
5 A

TEC-2000
52
Von Neumann
521

140

CPU
CPU
TEC-2000
TEC-2000
16
TEC-2000
TEC-2000
TEC-2000
TEC-2000
Windows

522
TEC-2000
Windows
TEC-2000 PC TEC-2000 16
57
141
57 TEC-2000 16

OFF/ON
Time MACH GAL
Reset
TEC-2000
3 34
IRALU
DR
TEC-2000 data
TCE-2000 TEC 2000
Time
Mach Gal Mach gal

34

142

ON /OFF OFF

57 ON
Time Mach Gal
Mach Gal Mach
Gal 7 Gal

Mach gal Mach Gal
gal1gal7

58 Mach gal

PC
143
59

Reset
510

144
ALU 511
511
BASIC 2

MVRDADD RET
MVRD R0, 0
MVRD R1, 1
ADD R0, R1
RET

16
512 513
512

145
512
513
523

146

PC
PC Windows
a)
8
9
10
11

1.
2.
3.
4.
5.

TEC-2000 ADC DR,SR
5
ADC DR,SR SR DR
C
DR DRDR+SR+C
8 DR4
SR4

A 00100000
6
ADD ADC 3
iARPC
iiIRPCPC+1
iiiDRDR+SR+C

7
i ii A
iii
0011
CI3~0 SCC3~0 MRW I2~0 I8~6 I5~3 B A SST SSHSCI DC2 DC1
0011 0000 100 001 011 000 0000 0000 001 0010 000 000
iii
8

147

ADC
9
TEC-2000 Gal MACH
7
BASIC 4
53
531
TEC-2000 PC TEC-2000 16
514
514 TEC-2000

148

TEC-2000 ROMS
ROM
ALU
MAPROMROM1~ROM7 8 UltraEdit
MAPROMROM1~ROM7 8
3-8 ROM 515 8
.bin
515
ROMS
516 Update
149
516

514
517
517 16

MVRDADD RET
150
MVRD R0, 0
MVRD R1, 1
ADD R0, R1
RET

TEC-2000

518
518
151
519
TEC-2000

01
01

1000100000000000
0000000000000000
1000100000010000
0000000000000001
0000000000000001
1000111100000000
TEC-2000
.txt
.COD .BIN

Reset
152
532
TEC-2000

PC
PC Windows

6.
7.
8.
9.

10.
11.
12.
13.
14.

TEC-2000 ADC DRSR
15.
ADC DRSR SR DR
C
DR DRDR+SR+C
8 DR4
SR4

A 00100000

16.
ADD ADC 3
iARPC
iiIR
PCPC+1
iiiDRDR+SR+C

17.
iiiiii
CI3~0 SCC3~0 0MRW 0I2~0 SAI8~6 SBI5~3 B A 0SST SSHSCI DC2 DC1
0011 0000 0100 0001 1011 1000 0000 0000 0001 0010 0000 0000
153
iii
00110000 16 30

18.

50
ROM
ROMS 50
update ADC
20 20 MPROM 50
16
19.
ADC
20.
TEC-2000

21.

22.

23.
24.
25.
154

技术说明

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技术说明

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Copyright:

Available Formats

TEC-XP+

TEC-XP+ CPU 1 CPU

TEC-XP+ 2 CPU TEC-XP VHDL FPGA

FPGA CPU CPU

5000 10000 CPLD FPGA EDA

VHDL ABEL MACHFPGA EDA

/CC FtoIB FLAG AR15~8 AR7~0

74LS04 IR15~8 IR7~0 IRLtoIB ALUtoIB ALUtoIB 74LS245 74LS245

5 74LS244 SWtoIB SWtoIB

TEC-XP+ MACH 130

ABEL VHDL EDA

ISTYPE COM ISTYPE REG,

S1 = Y4& !K11&!K10 & !X1&!K1&C1 # !X1&K1&!C1 # X1&!K1&!C1 # X1&K1&C1

S2 = Y4& !K11&!K10& !X2&!K2&C2 # !X2&K2&!C2 # X2&!K2&!C2 # X2&K2&C2

CZVS RAM15 Q015

I8~6 I5~3 I2~0 SST C Z V S

SSH SCI Cin/ Shift

I8-6 I5-3 I2-0 SST A B SCI SSH

R0+1 Y15-Y0 1234 1235

58C65 ROM /CE/OE

2 58C65 ROM 8K ROM

ROM RAM 58C65 ROM

/CE/OE/WE 58C65 ROM

GND 1 135 Y6 VCC 40 39 87 REQ

"Instruction Macros "29

"************************* TIMING16 GAL**********************

"************************DC1 138 ****************************

"*************************DC2 138 *****************************

!_MIO = C_M& T==[0,0,1,0] " C-M#

_WE = C_M& T==[0,0,1,0]

!I0 = C_M& T==[0,0,1,0]

B3 = C_M& T==[0,0,1,1] &ADD#SUB#AND#OR#XOR_#CMP#TEST

SST2 = C_M& T==[0,0,1,1]&SHL#SHR

CCM = !SCC3& SCC2& SCC1& SCC0& IR8

A 2000 ; 16 2000 RAM

2000: MVRD R0,0036 ; 6 ASCII R0

SW MVRD R0, 1234 1 8800MVRD B

MRW I2-0 I8-6 I5-3 B A SST SSHSCI DC2 DC1

MRW I2-0 I8-6 I5-3 B A SST SSHSCI DC2 DC1

/M R /W I2-0 I8-6 I5-3 B A SST SSH SCI DC2 DC1

/M R /W I2-0 I8-6 I5-3 B A SST SSH SCI DC2 DC1

1 ADD DR, SR 0000 0000 04

3 AND DR, SR 0000 0010 06

5 XOR DR, SR 0000 0100 08

7 TEST DR, SR 0000 0101 0A

9 INC DR 0000 1001 0C

11 SHL DR 0000 1010 0E

12 SHR DR 0000 1011 0F

13 JRC OFFSET 0100 0100 10

15 JRZ OFFSET 0100 0110 10

16 JRNZ OFFSET 0100 0111 10

18 IN PORT 1000 0010 12

20 PSHF 1000 0100 15

22 POP DR 1000 0111 17

24 STRR [DR], SR 1000 0011 19

25 LORR DR, [SR] 1000 0001 1B

26 MVRD DR, DATA 1000 1000 1D

27 JMPA ADR 1000 0000 1E

28 CALA ADR 1100 1110 1F

3AH 31H 3AH

A 2000 ; 16 2000 RAM

2000: MVRD R0,0036 ; 6 ASCII R0

SW MVRD R0, 1234 1 8800MVRD B

SWHSWL OUT 80 1000 0110 1000 00008680H

"*** TIMING16 GAL

"DC1 138 ****

"*DC2 138 *****