A New Voltage Balancing Controller

Applied on 7-Level PUC Inverter

Hani Vahedi, Student, IEEE, Kamal Al-Haddad, Fellow, IEEE, Hadi Y. Kanaan, Senior Member, IEEE
GREPCI, cole de Technologie Suprieure, University du Quebec, Montreal, Canada
cole Suprieure dIngnieurs of Beirut, Saint-Joseph University, Beirut 1107 2050, Lebanon
Hani.Vahedi@etsmtl.ca, Kamal.Al-Haddad@etsmtl.ca, Hadi.Kanaan@usj.edu.lb

Abstract In this paper a novel model of the packed U-cell multilevel inverter is another topology that could not attract
(PUC) inverter is derived considering the concept of single-phase industries due to complicated voltage control of the capacitors
multilevel converters. Based on the proposed model, a voltage [21, 22]. in continue the PUC converter has been introduced in
balancing controller is designed to apply on the 7-level PUC
[23] which has the less switches compared to other multilevel
inverter. The applied controller is in charge of fixing the
capacitor voltage in PUC structure at a desired value to have the inverters while generating more voltage levels at the output.
seven levels of the voltages at the output. The 7-level pulse width This topology is a blend of FC and CHB configurations. As a
modulation (PWM) technique is used to produce the associated first prototype it could generate 7-level voltage at the output
pulses for firing the PUC switches. The performance of the using one independent DC source and one controlled DC
introduced controller is investigated via simulations in various capacitor. The seven-level waveform has low harmonics
conditions including changes in the load and DC bus voltage
which is suitable for photovoltaic energy conversion
variations. The results prove the ability of the good dynamic
performance and fast response of the controller in stable and applications. A solar panel can be connected to the inverter as
unstable conditions. a DC source through a chopper and the multilevel output
voltage would be generated by applying a controller to fix the
Index Terms Multilevel Inverter, Packed U-Cell, voltage capacitor voltage and producing the appropriate switching
Controller, Voltage Balancing, Multicarrier PWM. pulses [24]. in addition to the proposed controller applied on
 this converter, a hysteresis current control has been designed
and tested on the PUC converter which both showed
I. INTRODUCTION acceptable results [25]. The PUC converter remained veiled
while it has an interesting potential in low power applications
Power electronics converters are replacing bulky
due to low cost of using less components and generating more
transformers due to high technology and recent developments
voltage levels at the output than the popular aforementioned
in power semiconductor switches. Multilevel converters are
topologies. The performed studies on PUC were dedicated to
new generation of the power electronics equipment utilizing
design controllers based on a modelling which has been
more active switches to generate various voltage levels at the
derived by assuming that each switches in a multilevel inverter
output with low harmonic contents and delivers higher amount
can act separately. This assumption should be revised due to
of energy to the consumers. The low costs of the power
the fact that in multilevel inverters, the switches cannot act
switches make these types of converters acceptable to the
individually; they should be turned ON in a group to generate
industries in respect to economy [1-3].
the desired voltage level at the output. Thus, the modelling of
For a decade multilevel converters have been attracting the
the multilevel inverters should be performed in a way that
attention of researchers for high power applications due to low
considers the switching cases for a group of switches.
dv/dt of the used switches and low switching frequency.
In this paper a new modelling of the single-phase PUC
Nowadays, multilevel converters are matter of controversy as
inverter is presented based on the above-mentioned concept of
low and medium power applications. These converters
multilevel inverter switching. A new controller is designed
produce high-level smooth output voltage containing less
based on the derived model of the PUC. Some simulations are
harmonics that eliminate the need of large size filters. As well,
done to prove the efficiency of the controller in fixing the
the lower switching frequency, the lower power losses and the
capacitor voltage and producing desired seven voltage levels
higher efficiency. In this regard, the renewable energy
at the output. Simulation results show that the implemented
conversion and grid interfaces are the most suitable
controller is capable of dealing with all probabilistic situations
application for multilevel inverters [4-8].
including changes in the load and or DC bus voltage
Many topologies have been proposed for multilevel
variations. The dynamic performance and fast response of the
converters [9-15]. Neutral point clamped (NPC) [16, 17] and
whole system are tested by applying mentioned changes in the
cascaded H-bridge (CHB) multilevel converters are two most
load and DC bus voltage.
popular ones that have found industrial applications such as
high-power machine drives [18-20]. Flying capacitor (FC)

k,((( 
 II. PUC CONFIGURATION AND MODELLING
PUC converter has been introduced by Al-Haddad in 2010
under the US patent law [23]. It is a single-phase multilevel
converter which can be extended to three-phase. Since the
goal of inventor was low power applications, the single-phase
structure is shown in figure 1. It consists of 6 active switches
and one DC bus and one DC capacitor. The interesting
advantage of PUC is the number of components comparable to
other topologies. The less switches, the lower power losses,
the less gate drives, the lower cost. The output voltage levels
are listed in table 1. It should be mentioned that switches S4,
S5 and S6 are working in complementary of S1, S2 and S3. So
each pair of (S1, S4), (S2, S5) and (S3, S6) cannot conduct
simultaneously.
bus voltage in multi levels to decrease the load voltage
harmonics. This procedure reduces the required filters size at
the output of the inverter. As well, the power losses produced
by the reactive power would be diminished due to low
harmonic contents.
In order to distinguish the ongoing research from previous
works, the old modelling of the PUC has been described as
follows [24]:
The switching functions of the PUC inverter shown in
figure 1 are defined as:
0 if Si is Off
Si = i = 1, 2, 3 (1)
1 if Si is On
The inverter output voltage can be formulated as:

Vad = Vab + Vbc + Vcd (2)

Where the points a, b, c and d are demonstrated in figure 1

and each voltage can be computed based on the switching
function:

Vab = ( S1 1)V1
Vbc = (1 S 2 )(V1 V2 ) (3)
Vcd = (1 S3 )V2

By substituting equation (3) into (2), therefore:

Vad = ( S1 1)V1 + (1 S 2 )(V1 V2 ) + (1 S3 )V2

= V1S1 + (V2 V1 ) S 2 V2 S3 + V1 V2 (4)
= ( S1 S 2 )V1 + ( S 2 S3 )V2

Since one of switches in each pair of S1&S4, S2&S5 and

S3&S6 are turned ON, the switches current can be shown as a
Figure 1: Single-phase PUC inverter
function of load current and switching function
TABLE 1
ALL VOLTAGE LEVELS GENERATED BY PUC INVERTER
i1 = S1il
S1 S2 S3 Vl

1 0 0 V1 i2 = S 2il (5)
i = Si
1 0 1 V1-V2 3 3l
1 1 0 V2
1 1 1 0 Where,
0 0 0 0
0 0 1 -V2 i3 = ic + i2 (6)
0 1 0 V2-V1
0 1 1 -V1 ic = ( S3 S 2 )il (7)

To have all seven levels at the output voltage waveform, the dV2 ( S S 2 )il i i
= 3 = l S 2 + l S3 (8)
capacitor voltage (V2) should be 1/3 of the DC bus voltage dt C C C
(V1=3V2), so the output voltage levels would be 0, V2, 2V2,
3V2. As it is clear, the PUC inverter cannot produce voltage As well, for the voltage and load current the KVL law is
level more than the DC bus voltage amplitude. The maximum written as below:
load voltage is equal to the DC bus voltage. in other words, it
could be explained that the PUC advantage is to divide the DC


 dil dil
Vl = Vad il R f L f (9) Vad = il R f + L f + Vl (13)
dt dt

Calculating the equation (9) based on the other formulas, dil Rf V V

the following relation will be obtained: = il l ad (14)
dt Lf Lf Lf

dil V V V2 V Rf V
= 1 S1 + 1 S2 2 S3 il l (10) The main point of new modelling is using inverter voltage
dt Lf Lf Lf Lf Lf in general form not as the detailed model derived previously.
Since the V1=3V2, the Vad can be shown as:
Considering the average model based on the following
equation, the average model of the PUC inverter can be 1 2
Vad = dV1 , d = 0, , , 1 (15)
attained using relations (8) and (10). 3 3

dX d is the duty cycle which is modulated by a multicarrier

= A( X ) + B ( X )U + C (11)
dt PWM to generate appropriate pulses for the switches of PUC
inverter to have seven levels of voltage at the output.
By choosing the state variables as x1=il and x2=V2 and using So the new average model is:
duty cycles (d1, d2, d3) of switches (S1, S2, S3) as input matrix,
the following state space average model of the PUC inverter is dil Rf Vl V1
derived. dt = L il L + [d] (16)
f f L f
dil Rf V
dt - il - l III. PROPOSED CONTROLLER
= Lf Lf
dV2 To balance the capacitor voltage and keep the output

dt 0 voltage and current sinusoidal, the concept of MIMO systems
(12) should be considered due to having one input and many
V1 V1 - V2 V2
L - d1 outputs for the derived model of PUC inverter. Based on
Lf
d2
Lf
+ f derived average model the proposed controller is designed to
i il compensate the capacitor voltage by the inverter current.
0 - l d3 Deviation of the capacitor voltage from the reference should
C C
be reduced to have a constant voltage. So a PI controller can
Although the detailed model of the PUC inverter describes minimize the voltage error appropriately.
the performance of the system, it is not suitable to design a By choosing x1=il, and u1=d, then:
controller due to the fact that in multilevel inverters the duty
cycle as input signal should be modulated by a multilevel dx1 Rf V1 Vl
dt = L [ x1 ]+ [ u1 ] (17)
PWM technique. In multilevel PWM method, the reference
f L f L f
wave is compared to multicarrier waves in order to produce
different levels of voltage by firing various combinations of 1
switches. Based on these explanations, the main issue of using V Rf Vl
the separate duty cycles for each switch in PUC inverter is
[ u1 ] = 1 F +

[ x1 ] +

(18)
L f L f L f
losing the control on producing desired level of the voltage at
the output. In other words, noticing the table 1, each individual Where F is the linearized signal of the variables feedbacks
switch does not make a path for load current and also does not and will be formulated later.
generate a voltage level at the output, while a set or group of Since charging and discharging of the capacitor takes place
switches should be fired to produce the desired voltage level at by inverter current as well as make the current waveform
the output. Thus, generating pulses for switches separately sinusoidal, the capacitor voltage error signal is multiplied by a
would have conflict with the multilevel converters switching unit sin function as the current reference waveform. Then the
concept. If each switch works separately it means the desired current reference should be compared by the actual current
voltage levels as well as order of levels would not be and this error should be minimized by a PID controller. The
respected. PID is also responsible in stabilizing and accelerating the
To solve the above-mentioned problem, the PUC inverter system dynamic performance in load change condition
shown in figure 1 has been modelled in a new way as follows: because it affects the system current directly.
The output voltage of the inverter is Vad which is used in the The F signal can be derived and formulated as:
following KVL:


 V k Figure 4 shows the simulation results in a case without any
F = il - (V2 - 1 )(k p1 + i1 )( Sin t ) changes in system parameters. The DC bus voltage is V1=150
3 s (19) V and the load resistance is 20 . The capacitor voltage has
ki 2 been controlled at 50 V as 1/3 of the DC bus voltage.
(k p 2 + + kd 2 s )
s
Load Voltage (V)
200
The signal u1 is then calculated by equation (18) and sent to
the multicarrier PWM to produce the required switching 0

pulses to generate the 7-level voltage at the output of the -200

inverter. This controller is responsible to produce 7-level Load Current (A)

sinusoidal voltage and keep the capacitor voltage fixed at 1/3 10

of the DC source voltage. 0

The overall controller diagram is shown in figure 2. Figure

-10
3 contains the multicarrier PWM sketch for the 7-level
Capacitor Voltage (V)
inverter. The reference wave is the u1 signal and Cr1 to Cr6 are 100

the level shifted modulating carriers which are compared with 50

the reference waveform to generate pulses.
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Time (s)

Figure 4: simulation results of a 7-level PUC inverter in usual condition

To check the result accurately, figure 5 shows the zoomed

version of figure 4.
Figure 2: block diagram of proposed controller for 7-level PUC inverter Load Voltage (V)
200
1

-200

Load Current (A)

10

0
0
-10

Capacitor Voltage (V)

52

50

48
3 3.02 3.04 3.06 3.08 3.1 3.12 3.14 3.16 3.18 3.2
Time (s)
-1
Reference Wave Cr
1
Cr
2
Cr
3
Cr
4
Cr
5
Cr
6
Figure 5: zoomed results of figure 4

Figure 3: multicarrier PWM for 7-level PUC inverter The load voltage is seven-level with total harmonic
distortion (THD) of 12%. The load current is sinusoidal and
IV. SIMULATION RESULTS the capacitor voltage ripples is acceptable.
Moreover, figure 6 depicts the PUC inverter output voltage
The simulation of the 7-level PUC inverter with
before the line inductance. This voltage was used in the
Matlab/SPS has been performed encountering various
modelling as Vad. It is clear that the PUC inverter output
conditions including change in reference DC voltage value
voltage has seven levels and the voltage sharing between
and load. These changes are performed to prove the acceptable
levels has been performed identically.
dynamic performance of the controller to fix the capacitor
In next attempt, the applied controller has been tested under
voltage as well as producing sinusoidal current and 7-level
variations conditions. At first the DC bus voltages (V1) has
voltage at the output. System parameters are listed in table 2.
TABLE 2 been increased to 240 V and then back to 150 V. figure 7-a
SIMULATED SYSTEM PARAMETERS shows the load voltage and current which they have been
Load voltage frequency 60 Hz increased during the DC voltage variation. Figure 7-b shows
DC source voltage (V1) 150 V and 240 V
the capacitor voltage (V2) which is tracking the reference
Switching Frequency 1000 Hz
AC side resistance (Rf) 0.1 voltage equal to V1/3.
AC side inductance (Lf) 3 mH Second, the load resistance has been decreased to 10 and
Load resistance 10 and 20 then back to 20 again. Figure 8 shows the load voltage and
Load inductance 10 mH current waveforms as well as the capacitor voltage kept
DC Capacitor 3mF
constant by the applied proposed controller.


 Inverter Voltage Vad (V) Load Voltage (V)
200
150
100
100 0

-100
50
-200
0
Load Current (A)
20
-50 10

0
-100
-10
-150 -20
3 3.02 3.04 3.06 3.08 3.1 3.12 3.14 3.16 3.18 3.2 0 10 20 30 40 50 60
Time (s) Time (s)
Figure 6: PUC inverter output voltage (Vad) (a)

Load Voltage (V) DC Capacitor Voltage (V)

500 80

70
0
60
-500
50

Load Current (A) 40

20
30

0
20

10
-20
0 10 20 30 40 50 60
Time (s) 0
0 10 20 30 40 50 60
(a)
(b)
DC Capacitor Voltage (V)
100
Figure 8: simulation results during load changes

90 Changing in the load is a regular situation occurs in power

network. Figure 8-a shows that during a load change, the load
80
voltage is fixed while the load current is changed
70 consequently. Figure 8-b illustrates that the capacitor voltage
60 is constant during this variations. Although the capacitor
50 voltage ripples has been increased due to decreasing the load
power factor significantly, it still is less than 5% of the
40
capacitor voltage.
30 To prove the robustness of the controller some simulation
20 cases have been performed including changes in load and Dc
10
bus. As well, it should be mentioned that the proposed
controller even works in a condition where the load and DC
0
0 10 20 30 40 50 60 source value vary simultaneously. In all above cases it is clear
Time (s)
that the controller performs well in tracking the reference
(b) voltage at 1/3 of the DC bus value as well as producing the
Figure 7: simulation results during DC bus voltage (V1) variation pulses for generating 7-level voltage at the output. Applying
the proposed controller on PUC inverter makes it much more
Figure can prove the ability of the controller in situations
useful due to reducing the number of independent DC bus. As
where the DC bus has been connected to a solar panel or a
an example for application, in renewable energy conversion
rectifier in which would be some voltage sag and swell or
systems, especially for photovoltaic applications the proposed
voltage flickers.
controller with PUC inverter can play an important role in


delivering the required power to the household consumers or
street lighting systems.
V. CONCLUSION
The new modelling of the PUC inverter led to designing the
proposed robust controller which is able to work in any
condition including change in the load and DC bus variations,
and produce seven-level voltage at the output which has
around 12% of THD. Therefore, it can remove the need of
transformers in single-phase applications and convert the DC
voltage to AC form which is desirable for grid loads. The
proposed topology with designed controller needs only one
DC source which can have many applications in low and
medium power systems. Low manufacturing costs, less
number of components and low THD are some main
advantages of applying proposed controller with high dynamic
performance on PUC inverter.
ACKNOWLEDGMENT
Authors gratefully thank the Agence Universitaire de la
Francophonie (AUF) for their financial support as well as the
Canada Research Chair on Electrical Energy Conversion and
Power Electronics (CRC-EECPE).
REFERENCES
[1] L. G. Franquelo, J. Rodriguez, J. I. Leon, S. Kouro, R. Portillo, and M.
A. M. Prats, "The age of multilevel converters arrives," Industrial
Electronics Magazine, IEEE, vol. 2, pp. 28-39, 2008.
[2] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B.
Wu, et al., "Recent advances and industrial applications of multilevel
converters," Industrial Electronics, IEEE Transactions on, vol. 57, pp.
2553-2580, 2010.
[3] M. Mobarrez, M. Fazlali, M. A. Bahmani, and T. Thiringer,
"Performance and loss evaluation of a hard and soft switched 2.4 MW, 4
kV to 6 kV isolated DC-DC converter for a wind energy application," in
IECON 2012-38th Annual Conference on IEEE Industrial Electronics
Society, 2012, pp. 5086-5091.
[4] H. Vahedi, A. Sheikholeslami, M. Tavakoli Bina, and M. Vahedi,
"Review and simulation of fixed and adaptive hysteresis current control
considering switching losses and high-frequency harmonics," Advances
in Power Electronics, vol. 2011, 2011.
[5] H. Vahedi and A. Sheikholeslami, "Variable hysteresis current control
applied in a shunt active filter with constant switching frequency," in
Power Quality Conference (PQC), 2010 First, 2010, pp. 1-5.
[6] S. Alepuz, S. Busquets-Monge, J. Bordonau, J. Gago, D. Gonzlez, and
J. Balcells, "Interfacing renewable energy sources to the utility grid
using a three-level inverter," Industrial Electronics, IEEE Transactions
on, vol. 53, pp. 1504-1511, 2006.
[7] J. M. Carrasco, L. G. Franquelo, J. T. Bialasiewicz, E. Galvn, R. P.
Guisado, M. A. Prats, et al., "Power-electronic systems for the grid
integration of renewable energy sources: A survey," Industrial
Electronics, IEEE Transactions on, vol. 53, pp. 1002-1016, 2006.
[8] F. Sebaaly, H. Y. Kanaan, and N. Moubayed, "Three-level neutral-point-
clamped inverters in transformerless PV systemsState of the art," in
Mediterranean Electrotechnical Conference (MELECON), 2014 17th
IEEE, 2014, pp. 1-7.
[9] H. Vahedi and K. Al-Haddad, "Half-Bridge Based Multilevel Inverter
Generating Higher Voltage and Power," in Electric Power and Energy
Conference (EPEC), Canada, 2013, pp. 51-56.
[10] H. Vahedi, K. Al-Haddad, P. A. Labbe, and S. Rahmani, "Cascaded
Multilevel Inverter with Multicarrier PWM Technique and Voltage

Balancing Feature," in ISIE 2014-23rd IEEE International Symposium
on Industrial Electronics, Turkey, 2014, pp. 2151-2156.
[11] H. Vahedi, K. Al-Haddad, Y. Ounejjar, and K. Addoweesh, "Crossover
Switches Cell (CSC): A New Multilevel Inverter Topology with
Maximum Voltage Levels and Minimum DC Sources," in IECON 2013-
39th Annual Conference on IEEE Industrial Electronics Society, Austria,
2013, pp. 54-59.
[12] J. Rodriguez, J. S. Lai, and F. Z. Peng, "Multilevel inverters: a survey of
topologies, controls, and applications," Industrial Electronics, IEEE
Transactions on, vol. 49, pp. 724-738, 2002.
[13] J. Rodrguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, "Multilevel
voltage-source-converter topologies for industrial medium-voltage
drives," Industrial Electronics, IEEE Transactions on, vol. 54, pp. 2930-
2945, 2007.
[14] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, "Medium-voltage
multilevel convertersState of the art, challenges, and requirements in
industrial applications," Industrial Electronics, IEEE Transactions on,
vol. 57, pp. 2581-2596, 2010.
[15] M. Sharifzade, H. Vahedi, A. Sheikholeslami, H. Ghoreishy, and K. Al-
Haddad, "Selective Harmonic Elimination Modulation Technique
Applied on Four-Leg NPC," in ISIE 2014-23rd IEEE International
Symposium on Industrial Electronics, Turkey, 2014, pp. 2163-2168.
[16] L. Yacoubi, K. Al-Haddad, L.-A. Dessaint, and F. Fnaiech, "A DSP-
based implementation of a nonlinear model reference adaptive control
for a three-phase three-level NPC boost rectifier prototype," Power
Electronics, IEEE Transactions on, vol. 20, pp. 1084-1092, 2005.
[17] L. Yacoubi, K. Al-Haddad, L.-A. Dessaint, and F. Fnaiech, "Linear and
nonlinear control techniques for a three-phase three-level NPC boost
rectifier," Industrial Electronics, IEEE Transactions on, vol. 53, pp.
1908-1918, 2006.
[18] A. Nabae, I. Takahashi, and H. Akagi, "A new neutral-point-clamped
PWM inverter," Industry Applications, IEEE Transactions on, pp. 518-
523, 1981.
[19] J. Rodriguez, S. Bernet, P. K. Steimer, and I. E. Lizama, "A survey on
neutral-point-clamped inverters," Industrial Electronics, IEEE
Transactions on, vol. 57, pp. 2219-2230, 2010.
[20] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, "A
survey on cascaded multilevel inverters," Industrial Electronics, IEEE
Transactions on, vol. 57, pp. 2197-2206, 2010.
[21] C. Feng, J. Liang, and V. G. Agelidis, "Modified phase-shifted PWM
control for flying capacitor multilevel converters," Power Electronics,
IEEE Transactions on, vol. 22, pp. 178-185, 2007.
[22] P. Roshankumar, P. Rajeevan, K. Mathew, K. Gopakumar, J. I. Leon,
and L. G. Franquelo, "A Five-Level Inverter Topology with Single-DC
Supply by Cascading a Flying Capacitor Inverter and an H-Bridge,"
Power Electronics, IEEE Transactions on, vol. 27, pp. 3505-3512, 2012.
[23] K. Al-Haddad, Y. Ounejjar, and L. A. Gregoire, "Multilevel Electric
Power Converter," US Patent 0280052 A1, 2010.
[24] Y. Ounejjar, K. Al-Haddad, and L. A. Grgoire, "Packed U cells
multilevel converter topology: theoretical study and experimental
validation," Industrial Electronics, IEEE Transactions on, vol. 58, pp.
1294-1306, 2011.
[25] Y. Ounejjar, K. Al-Haddad, and L. A. Dessaint, "A Novel Six-Band
Hysteresis Control for the Packed U Cells Seven-Level Converter:
Experimental Validation," Industrial Electronics, IEEE Transactions on,
vol. 59, pp. 3808-3816, 2012.