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ISSN: 2278-0181
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Carry and Odd Parity show the status of each Flag operations e.g. Parity, Carry, Overflow.
Flag for result of the ALUs operation in each The Flags play crucial role in Digital System
clock cycle. Zero Counter counts number of Design. The 32 BIT ALU can perform
zeros in the result. The modern ALU must be advantageous Flag operations e.g. Parity, Carry,
capable to perform all the binary arithmetic and Overflow. The Flags play crucial role in Digital
logical operations to meet the requirements of System Design. Parity Flag can detect the error
modern VLSI industry. So, the paper is a and thus be used in Digital communication.
forward step to design the ALU and meets the
demand of present FPGA based technology. The
paper presents a number of new operations
(Parity,Overflow,Zero,Zero counter etc.) that an
ALU can perform than so far designed ALU in
VHDL.
1. INTRODUCTION
Design of ALU in VHDL has been more
complex to meet the requirements in terms of
number of operations and fast operation and so it
has been more efficient over the years. The
number of operations performed by an ALU has
been consistently increasing. ALU is a core
Fig.2.1: Entity 32 bit ALU
component of all Processor and is an Integral
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International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 2 Issue 5, May - 2013
iii).Design of Comparator
Design of Microprocessor through VHDL is The ALU compares upon the two inputs and
importantly dependent over the efficiency of results either Ain>Bin, Ain<Bin or Ain=Bin. The
ALU design and synthesis. The less the delay Select Line (4 BIT) decides which operation is
propagation the more ALU is efficient to speed to be performed by the ALU e.g. XOR,
up digital signal operation. Software-based NOR,NAND ,Addition, Subtraction etc. The
Programmable Network Interfaces excel in their Flags e.g. Parity, Zero etc are independent of
ability to implement various services. These Select Line. So, Flags will be HIGH or LOW in
services can be added or removed in the network each clock cycle.
interface simply by upgrading the code in the
system. However, programmable network III. Table I
interfaces suffer from instruction processing
overhead. Programmable NICs must spend time Select Line Operation
executing instructions to run their software 0000 Ain AND Bin
whereas ASIC based network interfaces 0001 Ain OR Bin
implement their functions directly in hardware.
0010 Ain AND (NOT Bin)
i). Design of Arithmetic Block: 0011 Ain XNOR Bin
The ALU can perform 32 BIT Addition and 0100 NOT Bin
Subtraction operation and Overflow Logic will 0101 Ain NAND Bin
be HIGH if the result exceeds 32 BIT. Full 0110 Ain NOR Bin
Adders and Full Subtractor have been designed 0111 XNOR
using Carry Ripple adder concept. Carry Flag 1000 NOT(Ain XNOR Bin)
RT
show the result status whether output contains 1001 NOT(Ain NAND Bin)
carry or not. Overflow Flag will be HIGH when
1010 NOT (Ain NOR Bin)
31st carry and 32nd bit of carry gets HIGH upon
1011 Carry Ripple Adder, Carry,
IJE
Fig.2.2RTL Schematic
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International Journal of Engineering Research & Technology (IJERT)
ISSN: 2278-0181
Vol. 2 Issue 5, May - 2013
2. Simulation:
Simulation of Behavioral Model for 32 BIT ALU has been performed for 1000 nano-seconds. Each
Clock(CLK) cycle has 50 ns rise and fall time. Input Setup time:5 ns, Output Valid delay:3 ns;
The simulation of 32-BIT ALU(if rising_edge(CLK) and EN=0) generated from Testbench Waveform
is given in figure 2.1 below:
RT
IJE
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Vol. 2 Issue 5, May - 2013
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ISSN: 2278-0181
Vol. 2 Issue 5, May - 2013
possible assistance. They have been extremely [3]Rupali Jarwal and Ulka Khire,4-Bit
motivating and helped during the execution of Arithmetic And Logic Unit Design Using
this project work that has led us to the successful Structural Modelling In VHDLInternational
completion of our project titled: Design and Journal of Engineering Research & Technology
Synthesis of a 32-bit ALU on Xilinx ISE v9.1i (IJERT),Vol. 2 Issue 3, March - 2013
using VHDL. We highly appreciate the efforts
and numerous suggestions that they structured Books:
our work with their valuable tips and accorded
to us in every respect of our work. At last, we [1] D. L. Perry, VHDL, Tata Mcgraw Hill
humbly extend our sincere appreciation to other Edition, 4th Edition, 2002.
faculty also who help and encouraged us in [2] C. Maxfiled, The Design Warriors Guide to
some way or during our working project FPGAs, Elsevier, 2004.
environment. [3] J. Bhaskar, VHDL Primer, Pearson
Education, 3rd Edition, 2000.
References: [4] J. Bhaskar, VHDL Synthesis Primer,
Pearson Education, 1st Edition, 2002.
Journal: [5]V.A.Pedroni,Circuit Design with VHDL,
[1] Suchita Kamble1, Prof .N. N. Mhala Cambridge, Massachusetts, London, England,
VHDL Implementation of 8-Bit ALU, IOSR 2004.
Journal of Electronics and Communication [6] P.J.Ashenden, The VHDL Cookbook,
Engineering (IOSRJECE) ISSN : 2278-2834 University of Adelaide, South Australia, July,
Volume 1, Issue 1 (May-June 2012) 1990.
[2]Geetanjali and Nishant Tripathi. VHDL [7]Stephen Brown and Zvonko Vranesic
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Implementation of 32-Bit Arithmetic Fundamentals of Digital Logic with VHDL
Logic Unit (Alu),International Journal of Design Department of Electrical and Computer
Computer Science and Communication Engineering, University of Toronto, 3rd Edition,
IJE
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