Professional Documents
Culture Documents
DATA SHEET
USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED.
SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYS-
TEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics.
As used herein :
1. Life support devices or systems are those which (a) are 2. A critical component is any component of a life support
intended for surgical implant into the body, or (b) support device or system whose failure to perform can reason-
or sustain life, and whose failure to perform, when prop- ably be expected to cause the failure of the life support
erly used in accordance with instructions for use pro- device or system, or to affect its safety or effectiveness.
vided with the product, can be reasonably expected to
result in significant injury to the user.
ST639x DATASHEET INDEX
Pages
ST6391, ST6392, ST6393
ST6395, ST6397, ST6399 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ST639x CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MEMORY SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
WAIT & STOP MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ON-CHIP CLOCK OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
INPUT/OUTPUT PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
HARDWARE ACTIVATED DIGITAL WATCHDOG FUNCTION . . . . . . . . . . . . . . . . . . . 31
SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6-BIT PWM D/A CONVERTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AFC A/D COMPARATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DEDICATED LATCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ON-SCREEN DISPLAY (OSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SOFTWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ORDERING INFORMATION TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
ST6391, ST6392, ST6393
ST6395, ST6397, ST6399
8-BIT HCMOS MCUs
FOR TV FREQUENCY SYNTHESIS WITH OSD
PRELIMINARY DATA
DA0 1 42 V DD
DA1 2 41 PC0 (SCL)
DA2 3 40 PC1 (SDA)
DA3 4 39 PC2
DA4 5 38 PC3 (SEN)
DA5 6 37 PC4
PB1 7 36 PC5
PB2 8 35 PC6 (IRIN)
AFC 9 34 PC7
PB4 10 33 RESET
PB5 11 32 OSCout
PB6 12 31 OSCin
PA0 13 30 TEST
PA1 14 29 OSDOSCout
PA2 15 28 OSDOSCin
PA3 16 27 VSYNC
PA4 17 26 HSYNC
PA5 18 25 BLANK
PA6 19 24 B
PA7 20 23 G
VSS 21 22 R
VA00339
DA0 1 42 V DD DA0 1 42 V DD
DA1 2 41 PC0 (SCL) DA1 2 41 PC0 (SCL)
DA2 3 40 PC1 (SDA) DA2 3 40 PC1 (SDA)
DA3 4 39 PC2 DA3 4 39 PC2
62.5kHz OUT 5 38 PC3 (SEN) DA4 5 38 PC3 (SEN)
(1)
PB0 6 37 PC4 (PWRIN) PB0 6 37 PC4 (PWRIN )
PB1 7 36 PC5 PB1 7 36 PC5
PB2 8 35 PC6 (IRIN) PB2 8 35 PC6 (IRIN)
PB3 9 34 PC7 PB3 9 34 PC7
PB4 10 33 RESET PB4 10 33 RESET
PB5 11 32 OSCout PB5 11 32 OSCout
PB6 12 31 OSCin PB6 12 31 OSCin
PA0 13 30 TEST PA0 13 30 TEST
PA1 14 29 OSDOSCout PA1 14 29 OSDOSCout
PA2 15 28 OSDOSCin PA2 15 28 OSDOSCin
PA3 16 27 VSYNC PA3 16 27 VSYNC
PA4 17 26 HSYNC PA4 17 26 HSYNC
PA5 18 25 BLANK PA5 18 25 BLANK
PA6 (HD0) 19 24 B PA6 (HD0) 19 24 B
PA7 (HD1) 20 23 G PA7 (HD1) 20 23 G
VSS 21 22 VSS 21 22 R
R
VA00340 VA00337
2/64
ST6391,92,93,95,97,99
GENERAL DESCRIPTION
The ST639x microcontrollers are members of the 8- (Timer), a digital hardware activated watchdog
bit HCMOS ST638x family, a series of devices spe- function (DHWD), a 14-bit voltage synthesis tuning
cially oriented to TV applications. Different ROM size peripheral, a Serial Peripheral Interface (SPI), up
and peripheral configurations are available to give to six 6-bit PWM D/A converters, an AFC A/D con-
the maximum application and cost flexibility. All verter with 0.5V resolution, an on-screen display
ST639x members are based on a building block ap- (OSD) with 15 characters per line and 128 charac-
proach:a common core is surrounded by a combina- ters (in two banks each of 64 characters). In addi-
tion of on-chip peripherals (macrocells) available tion the following memory resources are available:
from a standard library. These peripherals are de- program ROM (up to 20K), data RAM (256 bytes),
signed with the same Core technology providing full EEPROM (up to 384 bytes). Refer to pin configura-
compatibility and short design time. Many of these tions figures and to ST639x device summary (Ta-
macrocells are specially dedicated to TV applica- ble 1) for the definition of ST639x family members
tions. The macrocells of the ST639x family are: two and a summary of differences among the different
Timer peripherals each including an 8-bit counter types.
with a 7-bit software programmable prescaler
3/64
ST6391,92,93,95,97,99
PORT C
PC2, PC4 - PC7 *
PC0 / SCL
DATA ROM PC1 / SDA
USER SELECTABLE SERIAL PERIPHERAL PC3 / SEN
USER PROGRAM INTERFACE
ROM DATA RAM
UP TO 20 kBytes 256 Bytes
TIMER 1
DATA EEPROM
384 Bytes
TIMER 2
DIGITAL
PC WATCHDOG/TIMER
STACK LEVEL 1
STACK LEVEL 2 D / A Outputs DA0 - DA5
STACK LEVEL 3 8-BIT CORE
STACK LEVEL 4 AFC Input AFC
STACK LEVEL 5
STACK LEVEL 6
ON-SCREEN R, G, B, BLANK
POWER SUPPLY OSCILLATOR RESET DISPLAY HSYNC, VSYNC
LOW SPI
ROM RAM EEPROM COLOUR PWRIN 62.5kHz EMULATING
DEVICE AFC D/A POWER IN CLK FREQ.
(Bytes) (Bytes) (Bytes) PINS PIN Pin DEVICES
RESET (kHz)
4/64
ST6391,92,93,95,97,99
PIN DESCRIPTION
VDD and VSS. Power is supplied to the MCU using Open-drain. PC0 is connected to the SPI clock sig-
these two pins. VDD is power and VSS is the ground nal (SCL), PC1 with the SPI data signal (SDA)
connection. while PC3 is connected with SPI enable signal
OSCin, OSCout. These pins are internally con- (SEN, used in S-BUS protocol). Pin PC4 and PC6
nected to the on-chip oscillator circuit. A quartz can also be inputs to software programmable edge
crystal or a ceramic resonator can be connected sensitive latches which can generate interrupts;
between these two pins in order to allow the cor- PC4 can be connected to Power Interrupt while
rect operation of the MCU with various stabil- PC6 can be connected to the IRIN/NMI interrupt
ity/cost trade-offs. The OSCin pin is the input pin, line.
the OSCout pin is the output pin. DA0-DA5. These pins are the six PWM D/A out-
RESET. The active low RESET pin is used to start puts of the 6-bit on-chip D/A converters. These
the microcontroller to the beginning of its program. lines have open-drain outputs with 12V drive. The
Additionally the quartz crystal oscillator will be dis- output repetition rate is 31.25KHz (with 8MHz
abled when the RESET pin is low to reduce power clock).
consumption during reset phase (ST6392/99 only). AFC. This is the input of the on-chip 10 levels com-
TEST. The TEST pin must be held at VSS for nor- parator that can be used to implement the AFC
mal operation. function. This pin is an high impedance input able
to withstand signals with a peak amplitude up to
PA0-PA7. These 8 lines are organized as one I/O 12V.
port (A). Each line may be configured as either an
input with or without pull-up resistor or as an output OSDOSCin, OSDOSCout. These are the On
under software control of the data direction regis- Screen Display oscillator terminals. An oscillation
ter. Pins PA4 to PA7 are configured as open-drain capacitor and coil network have to be connected to
outputs (12V drive). On PA4-PA7 pins the input provide the right signal to the OSD.
pull-up option is not available while PA6 and PA7 HSYNC, VSYNC. These are the horizontal and
have additional current driving capability (25mA, vertical synchronization pins. The active polarity of
VOL:1V). PA0 to PA3 pins are configured as push- these pins to the OSD macrocell can be selected
pull. by the user as ROM mask option. If the device is
PB0-PB2, PB4-PB6. These 6 lines are organized specified to have negative logic inputs, then these
as one I/O port (B). Each line may be configured as signals are low the OSD oscillator stops. If the de-
either an input with or without internal pull-up resis- vice is specified to have positive logic inputs, then
tor or as an output under software control of the when these signals are high the OSD oscillator
data direction register. stops.
PC0-PC7. These 8 lines are organized as one I/O R, G, B, BLANK. Outputs from the OSD. R, G and
port (C). Each line may be configured as either an B are the color outputs while BLANK is the blank-
input with or without internal pull-up resistor or as ing output. All outputs are push-pull. The active po-
an output under software control of the data direc- larity of these pins can be selected by the user as
tion register. Pins PC0 to PC3 are configured as ROM mask option.
open-drain (5V drive) in output mode while PC4 to 62.5kHz OUT. This pin is available only on the
PC7 are open-drain with 12V drive and the input ST6392/99. The pin is an open drain (12V) output
pull-up options does not exist on these four pins. at the frequency of 62.5kHz (with an 8MHz clock).
PC0, PC1 and PC3 lines when in output mode are The pin can be used to drive the SGS-THOMSON
ANDed with the SPI control signals and are all TEA5640 Chroma Processor. Refer to the
TEA5640 Data sheet for more information.
5/64
ST6391,92,93,95,97,99
PA6-PA7 I/O, Open-Drain, 12V, No Input Pull-up, Schmitt Trigger Input, High Drive
6/64
ST6391,92,93,95,97,99
7/64
ST6391,92,93,95,97,99
STACK LEVEL 4
Normal instruction ........ PC= PC+1 STACK LEVEL 5
STACK LEVEL 6
VA000424
8/64
ST6391,92,93,95,97,99
D7 D6 D5 D4 D3 D2 D1 D0
9/64
ST6391,92,93,95,97,99
MEMORY SPACES
The MCUs operate in three different memory lower 2K byte of the 4K program space are bank
spaces: Stack Space, Program Space, and Data switched while the upper 2K byte can be seen as
Space. A description of these spaces is shown in static space. Table 3 gives the different codes that
Figure 11. allows the selection of the corresponding banks.
Stack Space Note that, from the memory point of view, the Page
1 and the Static Page represent the same physical
The stack space consists of six 12 bit registers that memory: it is only a different way of addressing the
are used for stacking subroutine and interrupt return same location. On the ST6392,95,97, a total of
addressesplus the current programcounterregister. 2048, bytes of ROM have been implemented;
Program Space 20140 are available as user ROM while 340 are re-
The program space is physically implemented in served for testing.
the ROM and includes all the instructions that are
to be executed, as well as the data required for the Figure 12. ST639x 20K Bytes Program Space
immediate addressing mode instructions, the re- Addressing Description
served test area and user vectors. It is addressed
Program
thanks to the 12-bit Program Counter register (PC counter 0000h 4FFFh
register) and so, the ST639x Core can directly ad- space
dress up to 4K bytes of Program Space. Neverthe- 0FFFh
less, the Program Space can be extended by the
addition of 2-Kbyte ROM banks as it is shown in Static Page
Page 1
Figure 13 in which a 20K bytes memory is de-
scribed. These banks are addressed by pointing to 0800h
the 000h-7FFh locations of the Program Space 07FFh
thanks to the Program Counter, and by writing the
Page 1
appropriate code in the Program ROM Page Reg- Page 0 Static Page Page 9
ister (PRPR) located at the CAh address of the
0000h
Data Space. Because interrupts and common sub-
routines should be available all the time only the
00 00h 000h
083h W R EGISTER
084h
R AM
ROM 0C0 h
D ATA R OM
WI N D OW SELEC T
D ATA R AM
0FF0h BAN K SELEC T
IN TER RU PT &
VR001568
10/64
ST6391,92,93,95,97,99
Memory
D7-D5. These bits are not used. PRPR3 PRPR2 PRPR1 PRPR0 PC11
Page
PRPR4-PRPR0. These are the program ROM
banking bits and the value loaded selects the cor- Static
responding page to be addressed in the lower part X X X X 1 Page
of 4K program address space as specified in Table (Page 1)
3. This register is undefined on reset. 0 0 0 0 0 Page 0
Note. The number of bits implemented depends
on the size of the ROM of the device. Only the Page 1
lower part of address space has been bank- 0 0 0 1 0 (Static
switched because interrupt vectors and common Page)
subroutines should be available all the time. The
0 0 1 0 0 Page 2
reason of this structure is due to the fact that it is
not possible to jump from a dynamic page to an- 0 0 1 1 0 Page 3
other, unless jumping back to the static page,
changing contents of PRPR, and, than, jumping to 0 1 0 0 0 Page 4
a different dynamic page.
0 1 0 1 0 Page 5
Care is required when handling the PRPR as it is
write only. For this reason, it is not allowed to 0 1 1 0 0 Page 6
change the PRPR contents while executing inter-
rupts drivers, as the driver cannot save and than 0 1 1 1 0 Page 7
restore its previous content. Anyway, this opera-
1 0 0 0 0 Page 8
tion may be necessary if the sum of common rou-
tines and interrupt drivers will take more than 2K 1 0 0 1 0 Page 9
bytes; in this case could be necessary to divide the
11/64
ST6391,92,93,95,97,99
0000h-007Fh Reserved
PAGE 0
0080h-07FFh User ROM
0000h-000Fh Reserved
PAGE 2
0010h-07FFh User ROM
0000h-000Fh Reserved
PAGE 3
0010h-07FFh User ROM
0000h-000Fh Reserved
PAGE 4
0010h-07FFh User ROM
0000h-000Fh Reserved
PAGE 5
0010h-07FFh User ROM
0000h-000Fh Reserved
PAGE 6
0010h-07FFh User ROM
0000h-000Fh Reserved
PAGE 7
0010h-07FFh User ROM (End of 16K ST6391,93,99)
0000h-000Fh Reserved
PAGE 8
0010h-07FFh User ROM
0000h-000Fh Reserved
PAGE 9
0010h-07FFh User ROM (End of 20K ST6392,95,97)
12/64
ST6391,92,93,95,97,99
Figure 14. ST639x Data Space Figure 15. ST639x Data Space (Continued)
b7 b0 b7 b0
000h RESERVED 0D9h
DATA RAM/EEPROM/OSD TIMER 2 PRESCALER REGISTER 0DAh
BANK AREA TIMER 2 COUNTER REGISTER 0DBh
03Fh TIMER 2 STATUS CONTROL REG. 0DCh
040h 0DDh
DATA ROM RESERVED
WINDOW AREA 0DFh
07Fh DA0 DATA/CONTROL REGISTER 0E0h
X REGISTER 080h DA1 DATA/CONTROL REGISTER 0E1h
Y REGISTER 081h DA2 DATA/CONTROL REGISTER 0E2h
V REGISTER 082h DA3 DATA/CONTROL REGISTER 0E3h
W REGISTER 083h AFC, IR & OSD RESULT REGISTER 0E4h
084h OUTPUTS CONTROL REGISTER 0E5h
DATA RAM DA4 DATA/CONTROL REGISTER 0E6h
0BFh DA5 DATA/CONTROL REGISTER 0E7h
PORT A DATA REGISTER 0C0h DATA RAM BANK REGISTER 0E8h
PORT B DATA REGISTER 0C1h DEDIC. LATCHES CONTROL REG. 0E9h
PORT C DATA REGISTER 0C2h EEPROM CONTROL REGISTER 0EAh
RESERVED 0C3h SPI CONTROL REGISTER 1 0EBh
PORT A DIRECTION REGISTER 0C4h SPI CONTROL REGISTER 2 0ECh
PORT B DIRECTION REGISTER 0C5h OSD CHARAC. BANK SELECT REG. 0EDh
PORT C DIRECTION REGISTER 0C6h 0F0h
RESERVED 0C7h RESERVED
INTERRUPT OPTION REGISTER 0C8h 0FEh
DATA ROM WINDOW REGISTER 0C9h ACCUMULATOR 0FFh
PROGRAM ROM PAGE REGISTER 0CAh
RESERVED 0CBh
SPI DATA REGISTER 0CCh
0CDh OSD CONTROL REGISTERSLOCATED
RESERVED IN PAGE 6 OF BANKED DATA RAM
0D1h
TIMER 1 PRESCALER REGISTER 0D2h VERTICAL START ADDRESS REG. 010h
TIMER 1 COUNTER REGISTER 0D3h HORIZONTALSTART ADDRESS REG. 011h
TIMER 1 STATUS/CONTROL REG. 0D4h VERTICAL SPACE REGISTER 012h
0D5h HORIZONTAL SPACE REGISTER 013h
RESERVED BACKGROUND COLOUR REGISTER 014h
0D7h GLOBAL ENABLEREGISTER 017h
WATCHDOG REGISTER 0D8h
13/64
ST6391,92,93,95,97,99
Example:
DWR=28h 0 0 1 0 1 0 0 0
DATA SPACE ADDRESS
0 1 0 1 1 0 0 1 59h
ROM
ADDRESS:A19h 0 0 1 0 1 0 0 0 0 1 1 0 0 1
VR01573B
14/64
ST6391,92,93,95,97,99
DRBR Value
Selection
Hex. Binary
15/64
ST6391,92,93,95,97,99
16/64
ST6391,92,93,95,97,99
17/64
ST6391,92,93,95,97,99
INTERRUPT (Continued)
Table 6. Interrupt Vectors/Sources Interrupt Option Register
Relationships The Interrupt Option Register (IOR register, loca-
tion C8h) is used to enable/disable the individual
Inte rrupt Source
Associated
Vector Address
interrupt sources and to select the operating mode
Vector of the external interrupt inputs. This register can be
PC6/IRIN Interrup t
addressed in the Data Space as RAM location at
(1) 0FFCh-0FFDh the C8h address, nevertheless it is write-only reg-
Pin Vector # 0 (NMI)
ister that can not be accessed with single-bit op-
Timer 2
Interrup t
0FF6h-0FF7h
erations. The operating modes of the external
Vector # 1 interrupt inputs associated to interrupt vectors #1
Interrup t
and #2 are selected through bits 4 and 5 of the IOR
Vsync
Vector # 2
0FF4h-0FF5h register.
Timer 1
Interrup t
0FF2h-0FF3h
Figure 20. Interrupt Option Register
Vector # 3
Interrup t IOR
PC4/PWRIN 0FF0h-0FF1h
Vector # 4
Interr upt Option Register
Note 1. This pin is associated with the NMI Interrupt Vector (C8h, Write Only)
Interrupt Vectors/Sources D7 D6 D5 D4 D3 D2 D1 D0
18/64
ST6391,92,93,95,97,99
INTERRUPT (Continued)
Interrupt Procedure Figure 21. Interrupt Processing Flow-Chart
The interrupt procedure is very similar to a call pro-
cedure; the user can consider the interrupt as an
asynchronous call procedure. As this is an asyn-
INSTRUCTION
chronous event the user does not know about the
context and the time at which it occurred. As a re-
sult the user should save all the data space regis- FE TCH
ters which will be used inside the interrupt routines. INST RUCTION
There are separate sets of processor flags for nor-
mal, interrupt and non-maskable interrupt modes EX ECUTE
which are automatically switched and so these do INST RUCTION
not need to be saved.
The following list summarizes the interrupt proce- WA S NO LOAD PC FROM
dure (refer also to Figure 21. Interrupt Processing THE INST RUCTION
A RETI
INTERRUPT VECTOR
( FF C / FFD )
Flow Chart):
YE S
- Interrupt detection YES
IS THE CORE
SET
- The flags C and Z of the main routine are ex-
changed with the flags C and Z of the interrupt
? ALREADY IN
NORMAL MODE ?
INTE RRUPT MAS K
NO
routine (resp. the NMI flags)
CLEA R PUSH THE
- The value of the PC is stored in the first level of
the stack - The normal interrupt lines are inhib-
INTERRUPT MAS K PC INTO THE STAC K
stack) NO
CHECK IF THERE IS
AN INTERRUPT REQUES T
?
- The source of the interrupt is found by polling AND INTE RRUPT MASK
19/64
ST6391,92,93,95,97,99
INTERRUPT (Continued)
TIMER 2 Interrupt (#1). The TIMER 2 Interrupt is PWR Interrupt (#4). The PWR Interrupt is con-
connectedto the interrupt #1 (0FF6h). The TIMER 2 nected to the fifth interrupt #4 (0FF0h). If the
interrupt generatesa low level (which is latchedin the PWRINT is disabled at the PWR circuitry, then it
timer). Only the low level selection for #1 can be used. will be high. The #4 interrupt input detects a low
Bit 6 of the interrupt option register C8h has to be set. level. A simple latch is provided from the PC4
VSYNC Interrupt (#2). The VSYNC Interrupt is (PWRIN)pin in order to generate the PWRINT sig-
connected to the interrupt #2. When disabled the nal. This latch can be triggered by either the posi-
VSYNC INT signal is low. The VSYNC INT signal is tive or negative edge of the PWRIN signal.
inverted with respect to the signal applied to the PWRINT is inverted with respect to the latch. The
VSYNC pin. Bit 5 of the interrupt option register latch can be reset by software.
C8h is used to select the negative edge (ES2=0) or Notes Global disable does not reset edge sensi-
the positive edge (ES2=1); the edge will depend tive interrupt flags. These edge sensitive interrupts
on the application. Note that once an edge has become pending again when global disabling is re-
been latched, then the only way to remove the leased. Moreover, edge sensitive interrupts are
latched signal is to service the interrupt. Care must stored in the related flags also when interrupts are
be taken not to generate spurious interrupts. This globally disabled, unless each edge sensitive inter-
interrupt may be used for synchronize to the rupt is also individually disabled before the inter-
VSYNC signal in order to change characters in the rupting event happens. Global disable is done by
OSD only when the screen is on vertical blanking clearing the GEN bit of Interrupt option register,
(if desired). This method may also be used to blink while any individual disable is done in the control
characters. register of the peripheral. The on-chip Timer pe-
TIMER 1 Interrupt (#3). The TIMER 1 Interrupt is ripherals have an interrupt requestflag bit (TMZ), this
connected to the fourth interrupt #3 (0FF2h) which bit is set to one when the device wants to generate an
detects a low level (latched in the timer). interrupt request and a mask bit (ETI) that must be set
to one to allow the transfer of the flag bit to the Core.
20/64
ST6391,92,93,95,97,99
RESET
The ST639x devices can be reset in two ways: by the Watchdog Reset
external reset input (RESET) tied low and by the The ST639x devices are provided with an on-chip
hardware activated digital watchdog peripheral. hardware activated digital watchdog function in or-
RESET Input der to provide a graceful recovery from a software
The external active low reset pin is used to reset the upset. If the watchdog register is not refreshed and
ST638x devices and provide an orderly software the end-of-count is reached, then the reset state
startup procedure. The activation of the Reset pin will be latched into the MCU and an internal circuit
may occur at any time in the RUN or WAIT mode. pulls down the reset pin. This also resets the
Even short pulses at the reset pin will be accepted watchdog which subsequently turns off the pull-
since the reset signal is latched internally and is only down and activates the pull-up device at the reset
cleared after 2048 clocks at the oscillator pin. The pin. This causes the positive transition at the reset
clocks from the oscillator pin to the reset circuitry are pin. The MCU will then exit the reset state after
buffered by a schmitt trigger so that an oscillator in 2048 clocks on the oscillator pin.
start-up conditions will not give spurious clocks.
When the reset pin is held low, the external crystal os- Application Notes
cillator is also disabled in order to reduce current con-
sumption. The MCU is configured in the Reset mode An external resistor between VDD and the reset pin
as long as the signal of the RESET pin is low. The is not required because an internal pull-up device
processingof theprogramis stoppedandthe standard is provided. The user may prefer to add an external
Input/Outputports (port A, port B and port C) are in the pull-up resistor.
input state. As soon as the level on the reset pin be- An internal Power-on device does not guarantee
comes high, the initialization sequence is executed. that the MCU will exit the reset state when VDD is
Refer to the MCU initialization sequencefor additional above 4.5V and therefore the RESET pin should
information. be externally controlled.
OSCILLATOR ST6
SIGNAL INTERNAL RESET
COUNTER
1.0k TO ST6
RESET RESET
(ACTIVE LOW)
VDD
300k
WATCHDOG RESET
VA000200
21/64
ST6391,92,93,95,97,99
RESET (Continued)
Figure 23. Reset & Interrupt Processing Figure 24. Restart Initialization Program
Flow-Chart Flow-Chart
RESET
RESET
JP JP: 2 BYTES/4 CYCLES
RESET VECTOR
INITIALIZATION
ROUTINE
PUT FFEh
VA 000181
ON ADDRESS BUS
22/64
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23/64
ST6391,92,93,95,97,99
Table 7. Intructions Timing with 8MHz Clock Figure 27. OSCin, OSCout Diagram
Execution
Instruc tion Type Cycles
Time
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INPUT/OUTPUT PORTS
The ST639x microcontrollers use three standard Details of I/O Ports
I/O ports (A,B,C) with up to eight pins on each port; When programmed as an input a pull-up resistor (if
refer to the device pin configurations to see which available) can be switched active under program
pins are available. control. When programmed as an output the I/O
Each line can be individually programmed either in port will operate either in the push-pull mode or the
the input mode or the output mode as follows by open-drain mode according to the hardware fixed
software. configuration as specified below.
- Output Port A. PA0-PA3 are available as push-pull when
- Input with on-chip pull-up resistor (selected by outputs. PA4-PA7 are available as open-drain (no
software) push-pull programmability) capable of withstand-
ing 12V (no resistive pull-up in input mode). PA6-
- Input without on-chip pull-up resistor (selected PA7 has been specially designed for higher driving
by software) capability and are able to sink 25mA with a maxi-
Note: pins with 12V open-drain capability do not mum VOL of 1V.
have pull-up resistors. Port B. All lines are configured as push-pull when
In output mode the following hardware configura- outputs.
tions are available: Port C. PC0-PC3 are available as open-drain ca-
- Open-drain output 12V (PA4-PA7, PC4-PC7) pable of withstanding a maximum VDD+0.3V. PC4-
PC7 are available as open-drain capable of
- Open-drain output 5V (PC0-PC3)
withstanding 12V (no resistive pull-up in input
- Push-pull output (PA0-PA3, PB0-PB6) mode). Some lines are also used as I/O buffers for
The lines are organized in three ports (port A,B,C). signals coming from the on-chip SPI.
The ports occupy 6 registers in the data space. In this case the final signal on the output pin is
Each bit of these registers is associated with a par- equivalent to a wired AND with the programmed
ticular line (for instance, the bits 0 of the Port A data output.
Data and Direction registers are associated with
If the user needs to use the serial peripheral, the
the PA0 line of Port A).
I/O line should be set in output mode while the
There are three Data registers (DRA, DRB, DRC), open-drain configuration is hardware fixed; the
that are used to read the voltage level values of the corresponding data bit must set to one. If the
lines programmed in the input mode, or to write the latched interrupt functions are used (IRIN, PWRIN)
logic value of the signal to be output on the lines then the corresponding pins should be set to input
configured in the output mode. The port Data Reg- mode.
isters can be read to get the effective logic levels of
the pins, but they can be also written by the user On ST639x the I/O pins with double or special
functions are:
software, in conjunction with the related Data Di-
rection Register, to select the different input mode - PC0/SCL (connected to the SPI clock signal)
options. Single-bit operations on I/O registers (bit - PC1/SDA (connected to the SPI data signal)
set/reset instructions) are possible but care is nec-
essary because reading in input mode is made - PC3/SEN (connected to the SPI enable signal)
from I/O pins and therefore might be influenced by - PC4/PWRIN (connected to the PWRIN inter-
the external load, while writing will directly affect rupt latch)
the Port data register causing an undesired - PC6/IRIN (connected to the IRIN interrupt
changes of the input configuration. The three Data latch)
Direction registers (DDRA, DDRB, DDRC) allow
the selection of the direction of each pin (input or All the Port A,B and C I/O lines have Schmitt-trig-
output). ger input configuration with a typical hysteresis of
1V.
All the I/O registers can be read or written as any
other RAM location of the data space, so no extra
RAM cell is needed for port data storing and ma-
nipulation. During the initialization of the MCU, all
the I/O registers are cleared and the input mode
with pull-up is selected on all the pins thusavoiding
pin conflicts(with the exception of PC2 that is set in
output mode and is set high ie. high impedance).
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D7 D6 D5 D4 D3 D2 D1 D0
PA0 - PA7 = Data Direction Bits
PB0 - PB7 = Data Direction Bits
PC0 - PC7 = Data Direction Bits
A0 - PA7 = Data Bits
0 Defines bit as Inpu t
PB0 - PB7 = Data Bits
1 Defines bit as Outpu t
PC0 - PC7 = Data Bits
PA7-PA0. These are the I/O port A data bits. Reset PA7-PA0. These are the I/O port A data direction
at power-on. bits. When a bit is cleared to zero the related I/O
PB7-PB0.These are the I/O port B data bits. Reset line is in input mode, if bit is set to one the related
at power-on. I/O line is in output mode. Reset at power-on.
PC7-PC0. Set to 04h at power-on. Bit 2 (PC2 pin) PB7-PB0. These are the I/O port B data direction
is set to one (open drain therefore high im- bits. When a bit is cleared to zero the related I/O
pedence). line is in input mode, if bit is set to one the related
I/O line is in output mode. Reset at power-on.
PC7-PC0. These are the I/O port C data direction
bits. When a bit is cleared to zero the related I/O
line is in input mode, if bit is set to one the related
I/O line is in output mode. Set to 04h at power-on.
Bit 2 (PC2 pin) is set to one (output mode se-
lected).
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TIMERS
The ST639x devices offer two on-chip Timer periph- The prescaler decrements on rising edge. The
erals consisting of an 8-bit counter with a 7-bit pro- prescaler input is the oscillator frequency divided
grammable prescaler, thus giving a maximum count by 12.
of 215, and a control logic that allows configuring the Depending on the division factor programmed by
peripheral operating mode. Figure 32 shows the PS2/PS1/PS0 (see Table 9) bits in the TSCR, the
timer block diagram. The content of the 8-bit count- clock input of the timer/counter register is multi-
ers can be read/written in the Timer/Counter regis- plexed to different sources.
ters TCR that can be addressed in the data space as On division factor 1, the clock input of the prescaler is
RAM location at addresses D3h (Timer 1) and DBh also that of timer/counter; on factor2, bit 0 of prescaler
(Timer 2). The state of the 7-bit prescaler can be register is connectedto the clock input of TCR.
read in the PSC register at addresses D2h (Timer 1) This bit changes its state with the half frequency of
and DAh (Timer 2). The control logic is managed by prescaler clock input. On factor 4, bit 1 of PSC is
TSCR registers at D4h (Timer 1) and DCh (Timer 2) connected to clock input of TCR, and so on. On di-
addresses as described in the following paragraphs. vision factor 128, the MSB bit 6 of PSC is con-
The following description applies to both Timer 1 nected to clock input of TCR. The prescaler
and Timer 2. The 8-bit counter is decrement by the initialize bit (PSI) in the TSCR register must be set
output (rising edge) coming from the 7-bit pres- to one to allow the prescaler (and hence the
caler and can be loaded and read under program counter) to start. If it is cleared to zero then all of
control. When it decrements to zero then the TMZ the prescaler bits are set to one and the counter is
(timer zero) bit in the TSCR is set to one. If the ETI inhibited from counting.
(enable timer interrupt) bit in the TSCR is also set The prescaler can be given any value between 0
to one an interrupt request, associated to interrupt and 7Fh by writing to the related register address,
vector #3 (for Timer 1) and #1 for Timer 2, is gener- if bit PSI in the TSCR register is set to one. The tap
ated. The interrupt of the timer can be used to exit of the prescaler is selected using the PS2/PS1/PS0
the MCU from the WAIT mode. bits in the control register. Figure 33 shows the
timer working principle.
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TIMERS (Continued)
Figure 33. Timer Working Principle
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TIMERS (Continued)
Figure 34. Timer Status Control Registers The TSCR1 and TSCR2 registers are cleared on
reset. The correct D4-D5 combination must be
TSCR
written in TSCR1 by users software to enable the
Imer 1&2 Status Control Registers operation of Timer 1 and Timer 2.
DAh Timer 1, DCh Timer 2,
Read/ Write
Table 9. Prescaler Division Factors
D7 D6 D5 D4 D3 D2 D1 D0
PS2 PS1 PS0 Divided By
*
Only Available in TSCR1 1 0 0 16
1 0 1 32
TMZ. Low-to-high transition indicates that the timer 1 1 0 64
count register has decrement to zero. This bit must
be cleared by user software before to start with a 1 1 1 128
new count.
ETI. This bit, when set, enables the timer interrupt
(vector #3 for Timer 1, vector #1 for Timer 2) request. Figure 35. Timer Counter Registers
If ETI=0 the timer interrupt is disabled. If ETI= 1 and
TMZ= 1 an interrupt request is generated.
TCR
D5. This is the timers enable bit D5. It must be
cleared to 0 together with a set to 1 of bit D4 to en- Timer Counter 1&2 Register
D3h Timer 1, DBh Timer 2, Read/ Write
able both Timer 1 and Timer 2 functions. It is not
implemented on TSCR2 register. D7 D6 D5 D4 D3 D2 D1 D0
D4. This is the timers enable bit D4. This bit must
be set to 1 together with a clear to 0 of bit D5 to en-
able both Timer 1 and Timer 2 functions. It is not
implemented on TSCR2 register. D7 - D0 = Counter bits
D5 D4 Timers
0 0 Disabled Figure 36. Timer Counter Registers
0 1 Enabled
PSC
1 X Reserved
TimerPrescaler 1&2 Register
PS1. Used to initialize the prescaler and inhibit its D2h Timer 1, DAh Timer 2, Read/ Write
countingwhile PSI = 0 the prescaler is set to 7Fh and
the counter is inhibited. When PSI = 1 the prescaler D7 D6 D5 D4 D3 D2 D1 D0
is enabled to count downwards. As long as PSI= 0
both counter and prescaler are not running.
D6 - D0 = Prescaler bits
PS2-PS0. These bits select the division ratio of the Always read as 0
prescaler register. (see Table 9)
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SSDR
D7 D6 D5 D4 D3 D2 D1 D0
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SCR1 SCR2
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
2
S-BUS/I C BUS Selection BSY = Busy Bit 0
STD/SPI Enable ACN = Acknowledge Bit
STP = Stop Bit VRY/S = Verify/Sync.Enab le
STR = Start Bit TX/RX = Enable Bit
Unused Unuse d
D7-D4. These bits are not used. D7-D4. These bits are not used.
STR. This is Start bit for I2CBUS/S-BUS. This bit is TX/RX.Write Only. When this bit is set, current byte
meaningless when STD/SPI enable bit is cleared to operation is a transmission. When it is reset, cur-
zero. If this bit is set to one STD/SPI bit is also set to rent operation is a reception. Set to zero after re-
1 and SPI Start generation, before beginning of set.
transmission, is enabled. Set to zero after reset. VRY/S.Read Only/Write Only. This bit has two dif-
STP. This is Stop bit for I2CBUS/S-BUS. This bit is ferent functions in relation to read or write opera-
meaningless when STD/SPI enable bit is cleared tion. Reading Operation: when STD and/or TRX
to zero. If this bit is set to one STD/SPI bit is also bits is cleared to 0, this bit is meaningless. When
set to 1 and SPI Stop condition generation is en- bits STD and TX are set to 1, this bit is set each
abled. STP bit must be reset when standard proto- time BSY bit is set. This bit is reset during byte op-
col is used (this is also the default reset eration if real data on SDA line are different from
conditions). Set to zero after reset. the output from the shift register. Set to zero after
STD, SPI Enable. This bit, in conjunction with S- reset. Writing Operation : it enables (if set to one)
BUS/I2CBUS bit, allows the SPI disable and will or disables (if cleared to zero) the interrupt coming
select between I2CBUS/S-BUS and Standard from VSYNC pin. Undefined after reset. Refer to
shift register protocols. If this bit is set to one, it OSD description for additional information.
selects both I2CBUS and S-BUS protocols; final ACN.Read Only. If STD bit (D1 of SCR1 register) is
selection between them is made by S- cleared to zero this bit is meaningless. When STD
BUS/I2CBUS bit. If this bit is cleared to zero when is set to one, this bit is set to one if no Acknowledge
S-BUS/I2CBUS is set to 1 the Standard shift has been received. In this case it is automatically
register protocol is selected. If this bit is cleared reset when BSY is set again. Set to zero after re-
to 0 when S-BUS/I2CBUS is cleared to 0 the SPI set.
is disabled. Set to zero after reset. BSY.Read/Set Only. This is the busy bit. When a
S-BUS/I2CBUS Selection. This bit, in conjunction one is loaded into this bit the SPI interface start the
with STD/SPI bit, allows the SPI disable and will transmission of the data byte loaded into SSDR
select between I2CBUS and S-BUS protocols. If data register or receiving and building the receive
this bit is cleared to 0 when STD bit is also 0, the data into the SSDR data register. This is done in
SPI interface is disabled. If this bit is cleared to zero accordance with the protocol, direction and
when STD bit is set to 1, the I2CBUS protocol will start/stop condition(s). This bit is automatically
be selected. If this bit is set to 1 when STD bit is cleared at the end of the current byte operation.
set to 1, the S-BUS protocol will be selected. Cleared to zero after reset.
Cleared to zero after reset. Note :
Table 10. SPI Modes Selection The SPI shift register is also the data transmission
register and the data received register; this feature
D1 D0 is made possible by using the serial structure of the
2 SPI Function ST639x and thus reducing size and complexity.
STD/SP S-BUS/I C BUS
0 0 Disabled
0 1 STD Shift Reg.
1 0 I2C BUS
1 1 S-BUS
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MSB
Figure 44.Master Reads Slave Immediately After First Byte (read Mode)
ACKNOWLEDGE ACKNOWLEDGE NO ACKNOWLEDGE
FROM SLAVE FROM MASTER FROM MASTER
MSB MSB
Figure 45.Master Reads After Setting Slave Register Address (Write Address, Read Data)
ACKNOWLEDGE ACKNOWLEDGE
FROM SLAVE FROM SLAVE
MSB MSB
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2
Note: The third pin, SEN, should be high; it is not used in the I CBUS. Logically SDA is the AND of the S-BUS SDA and SEN.)
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(a) (b)
(c)
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STD SPI Protocol (Shift Register) Register 1 (SCR1 Add. EBh). Bit 0 named I2C must
This protocol is similar to the I2CBUS with the ex- be set at one and bit 1 named STD mut be reset.
ception that there is no acknowledge pulse and When the standard bus protocol is selected bit 2 of
there are no stop or start bits. The clock cannot be the SCR1 is meaningless.
slowed down by the externalperipherals. This bit named STOP bit is used only in I2CBUS or
In this case all three outputs should be high in or- SBUS. However take care thet THE STOP BIT
der not to lock the software I/Os from functioning. MUST BE RESET WHEN THE STANDARD PRO-
TOCOL IS USED. This bit is set to ZERO after RE-
SPI Standard Bus Protocol: The standard bus SET.
protocol is selected by loading the SPI Control
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Figure 50. DA0-DA5 Data/Control Registers Figure 52. AFC Inputs Configuration Diagram
D7 D6 D5 D4 D3 D2 D1 D0
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Unused
Unused
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D7, D6, D5, D4, D3, D1, D0. These bits are not
used.
A/D Shift. This bit determines the voltage range of
the AFC input. Writing a zero will select the 0.5V to
4.5V range. Writing a one will select the 1.0V to
5.0V range. Undefined after reset.
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VSAR HSAR
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7. This bit is not used D7. This bit is not used.
FR. Fringe Background.This bit changes the back- SBD. Space Blanking Disable. This bit controls
ground from a box background to a fringe back- whether or not the background is displayed when
ground. The background is enabled by word as outputting spaces. If two background colours are
defined by either BG0 or BG1. used on adjacent words, then the background
0 -The background is defined to be a box which is should not be displayed on spaces in order to
7 x 9 dots. make a nice break between colours. If an even
background around an area of text is desired, as in
1 -The background is defined to be a fringe. a menu, then the background should be displayed
VSA5-VSA0. Vertical Start Address. These bits when outputting spaces.
determine the start position of the first line in the 0 -The background during spaces is controlled by
vertical direction. The 6 bits can specify 63 display the background enable bits (BG0 and BG1) lo-
start positions of interval 4H. The first start position cated in the Background Control register.
will be the fourth line of the display. The vertical
start address is defined VSA0 by the following for- 1 -The background is not displayed when output-
mula. ting spaces.
Vertical Start Address = 4H(25(VSA5) + 24(VSA4) HSA5, HSA0 - Horizontal Start Address bits.
+ 23(VSA3) + 22(VSA2) + 21(VSA1) + 20(VSA0)) These bits determine the start position of the first
character in the horizontal direction. The 6 bits can
The case of all Vertical Start Address bits being specify 64 display start positions of interval 2/fosc or
zero is illegal. 400ns. The first start position will be at 4.0s be-
cause of the time needed to access RAM and
ROM before the first character can be displayed.
The horizontal start address is defined by the fol-
lowing formula.
Horizontal Start Address = 2/fosc(10.0 + 25(HSA5)
+ 24(HSA4) + 23(HSA3) + 22(HSA2) + 21(HSA1) +
20(HSA0))
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VSR HSR
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7. This bit is not used GS2,GS1. Global Size. These bits along with the
SCB. Screen Blanking. This bit allows the entire size bit (S) located in the Character format word
screen to be blanked. specify the character size for each line as defined
in Table 13.
0 -The blanking output signal (VBLK) is active
only when displaying characters. Table 13. Horizontal Space Register Size
1 -The blanking output signal (VBLK) is always Setting.
active. Characters in the display RAM are still
displayed. Horizontal
GS2 GS1 S Vertical Height
Length
When this bit is set to one, the screen is blanked
also without setting the Global Enable bit to one 0 0 0 18H 6 TDOT
(OSD disabled). 0 0 1 36H 12 TDOT
VS5 , VS0. Vertical Space. These bits determine
the spacing between lines if the Vertical Space En- 0 1 0 18H 6 TDOT
able bit (VSE) in the format character is one. If VSE 0 1 1 54H 18 TDOT
is zero there will be no spaces between lines. The
Vertical Space bits can specify one of 63 spacing 1 0 0 36H 12 TDOT
values from 4H to 252H. The space between lines 1 0 1 54H 18 TDOT
is defined by the following formula.
1 1 0 36H 12 TDOT
Space between lines = 4H(25(VS5) + 24(VS4) +
23(VS3) + 22(VS2) + 21(VS1) + 20(VS0)) 1 1 1 72H 24 TDOT
The case of all Vertical Start Address bits being Note: TDOT= 2/fOSC
zero is illegal. HS5, HS0 . Horizontal Space . These bits deter-
mine the spacing between words if the Horizontal
Space Enable bit (HSE) located in the space char-
acter is a one. The space between words is then
equal to the width of the space character plus the
number of tdots specified by the Horizontal Space
bits. The 6 bits can specify one of 64 spacing val-
ues ranging from 2/fosc to 128/fosc. The formula is
shown below for the smallest size character(18H).
If larger size characters are being displayed the
spacing between words will increase proportion-
ately. Multiply the value below by 2, 3 or 4 for char-
acter sizes of 36H, 54H and 72H respectively.
Space between words (not including the space
character)=2/fosc(1+25(HS5)+24(HS4)+23(HS3)
+22(HS2)+ 21(HS1)+20(HS0))
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Notes: FT. The format character required for each line. Characters In page 5 (load 20H in the register 0E8h), there are
in columns 1 thru 15 are displayed. 64 bytes of RAM, the ones of the first 4 rows (16
Ch. (Byte) Character (Index into OSD character generator) or bytes each row, 15 characters per row maximum,
space character plus an hidden leading formatcharacter). In page 6
(load 40H in register 0E8h), the 16 bytes of the fifth
Emulator Remarks row (0..0Fh), and the 6 control registers
There are a few differences between emulator and (10H..14H,17H).
silicon. For noise reasons, the OSD oscillator pins
3 - The video RAM is a dual port ram. That means
are not available: the internal oscillator cannot be that it can be addressed either from the Core or
disabled and replaced by an external coil. In the from the OSD circuitry itself. To reduce the com-
emulator, the Character Bank Select register can
plexity of the circuitry, and thus its cost, some re-
be written also with Global Enable bit set, while this
strictions have been introduced in the use of the
is not allowed in the device. OSD.
Application Notes a. The Core can Only write to any of the 86 loca-
1 - The OSD character generator is composed of a tions (either video RAM or control registers).
dual port video ram and some circuitry. It needs b. The Core can Only write to any of the leading
two input signals VSYNC and HSYNC to syncron- 85 locations when the OSD oscillator is OFF.
ize its dedicated oscillator to the TV picture. It gen-
Only the last location (control register 17H in
erates 4 output signals, that can be used from the page 6) can be addressed at any time. This is
TV set to generate the characters on the screen. the Global Enable Register, which contains
For instance, they can be used to feed the SCART
only the GE bit. If it is set, the OSD is on, if it is
plug, providing an adequate buffer to drive the low reset the OSD is off.
impedance (75 ) of the SCART inputs.
4 - The timing of the on/off switching of the OSD
2 - The Core sees the OSD as a number of RAM oscillator is the following:
locations (80) plus a certain number of control reg-
isters (6). These 86 locations are mapped in two a. GE bit is set. The OSD oscillator will start on
pages of the dynamic data ram address range the next VSYNC signal.
(0h..3Fh). b. GE bit is reset. The OSD oscillator will be im-
mediately switched off.
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SOFTWARE DESCRIPTION
The ST63xx software has been designed to fully Program Counter Relative. The relative address-
use the hardware in the most efficient way possible ing mode is only used in conditional branch instruc-
while keeping byte usage to a minimum; in short to tions. The instruction is used to perform a test and,
provide byte efficient programming capability. The if the condition is true, a branch with a span of -15
ST63xx Core has the ability to set or clear any to +16 locations around the address of the relative
register or RAM location bit of the Data space with instruction. If the condition is not true, the instruc-
a single instruction. Furthermore, the program may tion that follows the relative instruction is executed.
branch to a selected address depending on the The relative addressing mode instruction is one-
status of any bit of the Data space. The carry bit is byte long. The opcode is obtained in adding the
stored with the value of the bit when the SET or three most significant bits that characterize the kind
RES instruction is processed. of the test, one bit that determines whether the
Addressing Modes branch isa forward (when it is 0) or backward (when
it is 1) branch and the four less significant bits that
The ST63xx Core has nine addressing modes give the span of the branch (0h to Fh) that must be
which are described in the following paragraphs. added or subtracted to the address of the relative
The ST63xx Core uses three different address instruction to obtain the address of the branch.
spaces : Program space, Data space, and Stack
space. Program space contains the instructions Bit Direct. In the bit direct addressing mode, the
which are to be executed, plus the data for imme- bit to be set or cleared is part of the opcode, and
diate mode instructions. Data space contains the the byte following the opcode points to the address
Accumulator, the X,Y,V and W registers, peripheral of the byte in which the specified bit must be set or
and Input/Outputregisters, the RAM locations and cleared. Thus, any bit in the 256 locations of Data
Data ROM locations (for storage of tables and space memory can be set or cleared.
constants). Stack space contains six 12-bit RAM Bit Test & Branch. The bit test and branch ad-
cells used to stack the return addresses for subrou- dressing mode is a combination of direct address-
tines and interrupts. ing and relative addressing. The bit test and branch
Immediate. In the immediate addressing mode, instruction is three-byte long. The bit identification
the operand of the instruction follows the opcode and the tested condition are included in the opcode
location. As the operand is a ROM byte, the imme- byte. The address of the byte to be tested follows
diate addressing mode is used to access constants immediately the opcode in the Program space. The
which do not change during program execution third byte is the jump displacement, which is in the
(e.g., a constant used to initialize a loop counter). range of -126 to +129. This displacement can be
determined using a label, which is converted by the
Direct. In the direct addressing mode, the address assembler.
of the byte that is processed by the instruction is
stored in the location that follows the opcode. Direct Indirect. In the indirect addressing mode, the byte
addressing allows the user to directly address the processed by the register-indirect instruction is at
256 bytes in Data Space memory with a single the address pointed by the content of one of the
two-byte instruction. indirect registers, X or Y (80H,81H). The indirect
register is selected by the bit 4 of the opcode. A
Short Direct. The Core can address the four RAM register indirect instruction is one byte long.
registers X,Y,V,W (locations 80H, 81H, 82H, 83H)
in the short-direct addressing mode. In this case, Inherent. In the inherent addressing mode, all the
the instruction is only one byte and the selection of information necessary to execute the instruction is
the location to be processed is contained in the contained in the opcode. These instructions are
opcode. Short direct addressing is a subset of the one byte long.
direct addressing mode. (Note that 80H and 81H
are also indirect registers).
Extended. In the extended addressing mode, the
12-bit address needed to define the instruction is
obtained by concatenating the four less significant
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) that use the
extended addressing mode are able to branch to
any address of the 4K bytes Program space.
An extended addressing mode instruction is two-
byte long.
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Flags
Instruction Addressing Mode Bytes Cycles
Z C
LD A, X Short Direct 1 4 *
LD A, Y Short Direct 1 4 *
LD A, V Short Direct 1 4 *
LD A, W Short Direct 1 4 *
LD X, A Short Direct 1 4 *
LD Y, A Short Direct 1 4 *
LD V, A Short Direct 1 4 *
LD W, A Short Direct 1 4 *
LD A, rr Direct 2 4 *
LD rr, A Direct 2 4 *
LD A, (X) Indirect 1 4 *
LD A, (Y) Indirect 1 4 *
LD (X), A Indirect 1 4 *
LD (Y), A Indirect 1 4 *
LDI A, #N Immediate 2 4 *
LDI rr, #N Immediate 3 4 * *
Notes:
X,Y. Indirect Register Pointers, V & W Short Direct Registers
# . Immediate data (stored in ROM memory)
rr. Data space register
. Affected
* . Not Affected
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Addressing Flags
Instruction Bytes Cycles
Mode Z C
SET b,rr Bit Direct 2 4 * *
RES b,rr Bit Direct 2 4 * *
Notes:
b. 3-bit address; * . Not Affected
rr. Data space register;
Addressing Flags
Instruction Bytes Cycles
Mode Z C
NOP Inherent 1 2 * *
RET Inherent 1 2 * *
RETI Inherent 1 2
STOP (1) Inherent 1 2 * *
WAIT Inherent 1 2 * *
Notes:
1. This instruction is deactivated and a WAITis automatically executed instead of a STOP if the hardware activated
watchdog function is selected.
. Affected
* . Not Affected
Addressing Flags
Instruction Bytes Cycles
Mode Z C
CALL abc Extended 2 4 * *
JP abc Extended 2 4 * *
Notes:
abc.12-bit address;
* . Not Affected
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Opcode Map Summary. The following table containsan opcode map for the instructions used on the MCU.
Low Low
0 1 2 3 4 5 6 7 8 9 A B C D E F
0000 0001 0010 0011 010 0 0101 0110 0111 10 00 1001 1010 1011 1100 1101 1110 1111
Hi Hi
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 LDI 2 JRC 4 LD
0 e abc e b0 ,rr,ee e # e a,(x) e abc e b0 ,rr e rr,nn e a,(y) 0
00 00 0000
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 pcr 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 LDI 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD
1 e abc e b0 ,rr,ee e x e a,n n e abc e b0 ,rr e x e a,rr 1
00 01 0001
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 pcr 2 dir
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 CP 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 COM 2 JRC 4 CP
2 e abc e b4 ,rr,ee e # e a,(x) e abc e b4 ,rr e a e a,(y) 2
00 10 0010
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 pcr 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 CPI 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 CP
3 e abc e b4 ,rr,ee e a,x e a,nn e abc e b4 ,rr e x,a e a,rr 3
0011 0011
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 1 pcr 2 ext 1 pcr 2 b.d. 1 pcr 1 sd 1 pcr 2 dir
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 ADD 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RETI 2 JRC 4 ADD
4 e abc e b2 ,rr,ee e # e a,(x) e abc e b2 ,rr e e a,(y) 4
01 00 0100
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 pcr 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 ADDI 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 ADD
5 e abc e b2 ,rr,ee e y e a,n n e abc e b2 ,rr e y e a,rr 5
0101 0101
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 pcr 2 dir
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 INC 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 STOP 2 JRC 4 INC
6 e abc e b6 ,rr,ee e # e (x) e abc e b6 ,rr e e (y) 6
0110 0110
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 pcr 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 INC
7 e abc e b6 ,rr,ee e a,y e # e abc e b6 ,rr e y,a e rr 7
0111 0111
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 pcr 2 dir
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 JRC 4 LD
8 e abc e b1 ,rr,ee e # e (x),a e abc e b1 ,rr e # e (y),a 8
1000 1000
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 pcr 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD
9 e abc e b1 ,rr,ee e v e # e abc e b1 ,rr e v e rr,a 9
1001 1001
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 pcr 2 dir
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 AND 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 RLC 2 JRC 4 AND
A e abc e b5 ,rr,ee e # e a,(x) e abc e b5 ,rr e a e a,(y) A
1010 1010
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 pcr 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 ANDI 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 AND
B e abc e b5 ,rr,ee e a,v e a,nn e abc e b5 ,rr e v,a e a,rr B
1011 1011
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 pcr 2 dir
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 SUB 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RET 2 JRC 4 SUB
C e abc e b3 ,rr,ee e # e a,(x) e abc e b3 ,rr e e a,(y) C
1100 1100
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 pcr 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 SUBI 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 SUB
D e abc e b3 ,rr,ee e w e a,n n e abc e b3 ,rr e w e a,rr D
1101 1101
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 pcr 2 dir
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 DEC 2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 WAIT 2 JRC 4 DEC
E e abc e b7 ,rr,ee e # e (x) e abc e b7 ,rr e e (y) E
1110 1110
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 pcr 1 ind
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 DEC
F e abc e b7 ,rr,ee e a,w e # e abc e b7 ,rr e w,a e rr F
1111 1111
1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 pcr 2 dir
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THERMAL CHARACTERISTIC
Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
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EEPROM INFORMATION
The ST63xx EEPROM single poly process has been specially developed to achieve 300.000
Write/Erase cycles and a 10 years data retention.
DC ELECTRICAL CHARACTERISTICS
(TA = 0 to +70C unless otherwise specified)
Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
VIL Input Low Level Voltage All I/O Pins 0.2xV DD V
VIH Input High Level Voltage All I/O Pins 0.8xVDD V
VHYS All I/O Pins
Hysteresis Voltage(1) 1.0 V
VDD = 5V
DA0-DA5, PB0-PB6, OSD
Outputs, PC0-PC7,
O0, O1, PA0-PA5
VOL Low Level Output Voltage
VDD = 4.5V
IOL = 1.6mA 0.4 V
IOL = 5.0mA 1.0 V
PA6-PA7
VDD = 4.5V
VOL Low Level Output Voltage
IOL= 1.6mA 0.4 V
IOL= 25mA 1.0 V
OSDOSCout,
OSCout
V OL Low Level Output Voltage 0.4 V
VDD = 4.5V
IOL= 0.4mA
PB0-PB7, PA0-PA3, OSD
Outputs
VOH High Level Output Voltage 4.1 V
VDD = 4.5V
IOH = 1.6mA
OSDOSCout, OSCout,
V OH High Level Output Voltage VDD = 4.5V 4.1 V
IOH= 0.4mA
PB0-PB6, PA0-PA3, PC0-
Input Pull Up Current
IPU PC3 100 50 25 mA
Input Mode with Pull-up
VIN= VSS
OSCin
IIL 10 1 0.1
Input Leakage Current VIN= VSS A
IIH 0.1 1 10
VIN= VDD
IIL Input Pull-down OSCIN
100 A
current in Reset
All I/O Input Mode
IIL no Pull-up
Input Leakage Current 10 10 A
IIH OSDOSCin
VIN= VDD or VSS
RAM Retention Voltage in
VDD RAM 1.5 V
RESET
IIL Reset Pin with Pull-up
Input Leakage Current 50 30 10 A
IIH VIN= VSS
AFC Pin
IIL VIH= VDD 1
Input Leakage Current A
IIH VIL= VSS 1
VIH= 12.0V 40
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AC ELECTRICAL CHARACTERISTICS
(TA = 0 to +70C, fOSC=8MHz, VDD=4.5 to 6.0V unless otherwise specified )
Value
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
PA6, PA7
tO HL High to Low Transition Time 100 ns
VDD = 5V, CL = 1000pF (2)
ST6391,92,93,99 62.50
f SIO SIO Baud Rate(1) kHz
ST6395,97 100
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Dim. mm inches
Min Typ Max Min Typ Max
A 5.08 0.200
A1 0.51 0.020
B 0.35 0.59 0.014 0.023
B1 0.75 1.42 0.030 0.056
C 0.20 0.36 0.008 0.014
D 36.32 39.12 1.430 1.540
D1
E 18.54 0.730
E1 13.72 0.540
K1
K2
L 2.54 3.81 .100 0.150
e1 1.78 0.070
Number of Pins
N 42
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Notes:
(d) 1= ST6391, 2 = ST6392, 3 = ST6393, 4 = ST6395, 5 = ST6397, 6 = ST6399
(p) B= Dual in Line Plastic
(t) 1= 0 to 70C
Marking: the default marking is equivalent to the sales type only (part number).
CHECK LIST:
YES NO
ROM CODE [ ] [ ]
OSD Code: ODD & EVEN [ ] [ ]
EEPROM Code (if Desired) [ ] [ ]
Signature ...................................
Date ...........................................
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ST6391,92,93,95,97,99
Note: XX Is the ROM code identifier that is allocated by SGS-THOMSON after receipt of all required options and the related ROM file.
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the
express written approval of SGS-THOMSON Microelectronics.
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