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TPA3110D2
SLOS528F JULY 2009 REVISED APRIL 2017
TPA3110D2 15-W Fil ter-Free Stereo Class-D Audio Power Amplifier With Speakerguard
1 Features 3 Description
1 15-W/ch into an 8- Loads at 10% THD+N From The TPA3110D2 is a 15-W (per channel) efficient,
a 16-V Supply Class-D audio power amplifier for driving bridged-tied
stereo speakers. Advanced EMI Suppression
10-W/ch into 8- Loads at 10% THD+N From a Technology enables the use of inexpensive ferrite
13-V Supply bead filters at the outputs while meeting EMC
30-W into a 4- Mono Load at 10% THD+N From requirements. SpeakerGuard speaker protection
a 16-V Supply circuitry includes an adjustable power limiter and a
90% Efficient Class-D Operation Eliminates Need DC detection circuit. The adjustable power limiter
allows the user to set a "virtual" voltage rail lower
for Heat Sinks
than the chip supply to limit the amount of current
Wide Supply Voltage Range Allows Operation through the speaker. The DC detect circuit measures
From 8 V to 26 V the frequency and amplitude of the PWM signal and
Filter-Free Operation shuts off the output stage if the input capacitors are
damaged or shorts exist on the inputs.
SpeakerGuard Speaker Protection Includes
Adjustable Power Limiter Plus DC Protection The TPA3110D2 can drive stereo speakers as low as
Flow Through Pin Out Facilitates Easy Board 4 . The high efficiency of the TPA3110D2, 90%,
Layout eliminates the need for an external heat sink when
playing music.
Robust Pin-to-Pin Short Circuit Protection and
Thermal Protection With Auto Recovery Option The outputs are also fully protected against shorts to
GND, VCC, and output-to-output. The short-circuit
Excellent THD+N / Pop-Free Performance protection and thermal protection includes an auto-
Four Selectable, Fixed Gain Settings recovery feature.
Differential Inputs
Device Information(1)
2 Applications PART NUMBER PACKAGE BODY SIZE (NOM)
TPA3110D2 HTSSOP (28) 9.70 mm 4.40 mm
Televisions
Consumer Audio Equipment (1) For all available packages, see the orderable addendum at
the end of the data sheet.
GAIN0
GAIN1
OUTPR FERRITE
15W
BEAD
OUTNR FILTER 8W
PLIMIT
PBTL
Fault
SD PVCC 8 to 26V
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3110D2
SLOS528F JULY 2009 REVISED APRIL 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 9.2 Functional Block Diagram ....................................... 14
2 Applications ........................................................... 1 9.3 Feature Description................................................. 15
3 Description ............................................................. 1 9.4 Device Functional Modes........................................ 20
4 Revision History..................................................... 2 10 Application and Implementation........................ 21
10.1 Application Information.......................................... 21
5 Device Comparison Table..................................... 4
10.2 Typical Applications ............................................. 21
6 Pin Configuration and F unctions ........................ 4
11 Power Supply Recommendations ..................... 25
7 Specifications......................................................... 5
11.1 Power Supply Decoupling, CS ............................. 25
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 6 12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
7.3 Recommended Operating Conditions...................... 6
12.2 Layout Example .................................................... 26
7.4 Thermal Information .................................................. 6
7.5 DC Characteristics: 24 V.......................................... 6 13 Device and Documentation Support ................. 27
7.6 DC Characteristics: 12 V.......................................... 7 13.1 Device Support .................................................... 27
7.7 AC Characteristics: 24 V.......................................... 7 13.2 Documentation Support ........................................ 27
7.8 AC Characteristics: 12 V.......................................... 7 13.3 Community Resources.......................................... 27
7.9 Typical Characteristics ............................................. 8 13.4 Trademarks ........................................................... 27
13.5 Electrostatic Discharge Caution ............................ 27
8 Parameter Measurement Information ................ 14
13.6 Glossary ................................................................ 27
9 Detailed Description ............................................ 14
9.1 Overview ................................................................. 14 14 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Added < 10 V/ms to VI in the Absolute Maximum Ratings table, added Note 2 .................................................................... 5
Changed the PBTL Select section. Added text - "The voltage slew.......series with the terminals." .................................... 19
Added a 100k resistor to AVCC Pin 14 and Note 1 to Figure 46 ...................................................................................... 24
Replaced the Dissipations Ratings table with the Thermal Information table ........................................................................ 6
Changed Changed the Stereo Class-D Amplifier with BTL Output and Single-Ended Input illustration Figure 42 -
Corrected the pin names. ..................................................................................................................................................... 21
Changed Changed the Stereo Class-D Amplifier with PBTL Output and Single-Ended Input illustration Figure 46 -
Corrected the pin names. ..................................................................................................................................................... 24
PWP Package
28-Pin HTSSOP With PowerPAD
Top View
SD 1 28 PVCCL
FAULT 2 27 PVCCL
LINP 3 26 BSPL
LINN 4 25 OUTPL
GAIN0 5 24 PGND
GAIN1 6 23 OUTNL
AVCC 7 22 BSNL
AGND 8 21 BSNR
GVDD 9 20 OUTNR
PLIMIT 10 19 PGND
RINN 11 18 OUTPR
RINP 12 17 BSPR
NC 13 16 PVCCR
PBTL 14 15 PVCCR
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage AVCC, PVCC 0.3 V 30 V V
VCC +
0.3 V V
(2)
0.3 V
SD, GAIN0, GAIN1, PBTL, FAULT
< 10
VI Interface pin voltage V/ms
PLIMIT GVDD +
0.3 V
0.3
RINN, RINP, LINN, LINP 0.3 6.3 V
See Thermal
Continuous total power dissipation
Information
BTL: PVCC > 15 V 4.8
RL Minimum Load Resistance BTL: PVCC 15 V 3.2
PBTL 3.2
TA Operating free-air temperature 40 85 C
(3)
TJ Operating junction temperature range 40 150 C
Tstg Storage temperature 65 150 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-k resister in series
with the pins.
(3) The TPA3110D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 DC Characteristics: 24 V
TA = 25C, VCC = 24 V, RL = 8 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage (measured
| VOS | VI = 0 V, Gain = 36 dB 1.5 15 mV
differentially)
ICC Quiescent supply current SD = 2 V, no load, PVCC = 24 V 32 50 mA
ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 24 V 250 400 A
VCC = 12 V, IO = 500 mA, High Side 240
rDS(on) Drain-source on-state resistance m
TJ = 25C Low side 240
GAIN0 = 0.8 V 19 20 21
GAIN1 = 0.8 V dB
GAIN0 = 2 V 25 26 27
G Gain
GAIN0 = 0.8 V 31 32 33
GAIN1 = 2 V dB
GAIN0 = 2 V 35 36 37
ton Turn-on time SD = 2 V 14 ms
tOFF Turn-off time SD = 0.8 V 2 s
GVDD Gate Drive Supply IGVDD = 100 A 6.4 6.9 7.4 V
tDCDET DC Detect time V(RINN) = 6 V, VRINP = 0 V 420 ms
7.6 DC Characteristics: 12 V
TA = 25C, VCC = 12 V, RL = 8 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage (measured
| VOS | VI = 0 V, Gain = 36 dB 1.5 15 mV
differentially)
ICC Quiescent supply current SD = 2 V, no load, PVCC = 12V 20 35 mA
ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 12V 200 A
VCC = 12 V, IO = 500 mA, High Side 240
rDS(on) Drain-source on-state resistance m
TJ = 25C Low side 240
GAIN0 = 0.8 V 19 20 21
GAIN1 = 0.8 V dB
GAIN0 = 2 V 25 26 27
G Gain
GAIN0 = 0.8 V 31 32 33
GAIN1 = 2 V dB
GAIN0 = 2 V 35 36 37
tON Turn-on time SD = 2 V 14 ms
tOFF Turn-off time SD = 0.8 V 2 s
GVDD Gate Drive Supply IGVDD = 2 mA 6.4 6.9 7.4 V
Output Voltage maximum under PLIMIT
VO V(PLIMIT) = 2 V; VI = 1 V rms 6.75 7.90 8.75 V
control
7.7 AC Characteristics: 24 V
TA = 25C, VCC = 24 V, RL = 8 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
200 mVPP ripple at 1 kHz,
KSVR Power Supply ripple rejection 70 dB
Gain = 20 dB, Inputs ac-coupled to AGND
PO Continuous output power THD+N = 10%, f = 1 kHz, VCC = 16 V 15 W
THD+N Total harmonic distortion + noise VCC = 16 V, f = 1 kHz, PO = 7.5 W (half-power) 0.1%
65 V
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
80 dBV
Crosstalk VO = 1 Vrms, Gain = 20 dB, f = 1 kHz 100 dB
Maximum output at THD+N < 1%, f = 1 kHz,
SNR Signal-to-noise ratio 102 dB
Gain = 20 dB, A-weighted
fOSC Oscillator frequency 250 310 350 kHz
Thermal trip point 150 C
Thermal hysteresis 15 C
7.8 AC Characteristics: 12 V
TA = 25C, VCC = 12 V, RL = 8 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
200 mVPP ripple from 20 Hz1 kHz,
KSVR Supply ripple rejection 70 dB
Gain = 20 dB, Inputs ac-coupled to AGND
PO Continuous output power THD+N = 10%, f = 1 kHz; VCC = 13 V 10 W
THD+N Total harmonic distortion + noise RL = 8 , f = 1 kHz, PO = 5 W (half-power) 0.06%
65 V
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
80 dBV
Crosstalk Po = 1 W, Gain = 20 dB, f = 1 kHz 100 dB
Maximum output at THD+N < 1%, f = 1 kHz,
SNR Signal-to-noise ratio 102 dB
Gain = 20 dB, A-weighted
fOSC Oscillator frequency 250 310 350 kHz
Thermal trip point 150 C
Thermal hysteresis 15 C
10 10
Gain = 20 dB Gain = 20 dB
VCC = 12 V VCC = 18 V
ZL = 8 + 66 H ZL = 8+ 66 H
1 1
0.1 0.1
PO = 5 W PO = 10 W
PO = 1 W
0.01 PO = 0.5 W 0.01
PO = 2.5 W PO = 5 W
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f Frequency Hz f Frequency Hz
G001 G002
Figure 1. Total Harmonic Distortion vs Frequency (BTL) Figure 2. Total Harmonic Distortion vs Frequency (BTL)
10 10
Gain = 20 dB Gain = 20 dB
VCC = 24 V VCC = 12 V
ZL = 8 + 66 H ZL = 6 + 47 H
THD Total Harmonic Distortion %
THD Total Harmonic Distortion %
1 1
0.1 PO = 10 W 0.1
PO = 5 W
PO = 1 W
PO = 0.5 W
0.01 0.01
PO = 2.5 W
PO = 5 W
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f Frequency Hz f Frequency Hz
G003 G004
Figure 3. Total Harmonic Distortion vs Frequency (BTL) Figure 4. Total Harmonic Distortion vs Frequency (BTL)
10 10
Gain = 20 dB Gain = 20 dB
VCC = 18 V VCC = 12 V
ZL = 6 + 47 H ZL = 4 + 33 H
THD Total Harmonic Distortion %
1 1
PO = 10 W
0.1 0.1 PO = 10 W
PO = 1 W
0.01 0.01
PO = 1 W
PO = 5 W
PO = 5 W
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f Frequency Hz f Frequency Hz
G005 G006
Figure 5. Total Harmonic Distortion vs Frequency (BTL) Figure 6. Total Harmonic Distortion vs Frequency (BTL)
f = 1 kHz f = 20 Hz
f = 20 Hz
0.1 f = 1 kHz 0.1
0.01 0.01
f = 10 kHz f = 10 kHz
0.001 0.001
0.01 0.1 1 10 50 0.01 0.1 1 10 50
PO Output Power W PO Output Power W
G007 G008
Figure 7. Total Harmonic Distortion + Noise vs Output Figure 8. Total Harmonic Distortion + Noise vs Output
Power (BTL) Power (BTL)
10 10
Gain = 20 dB Gain = 20 dB
THD+N Total Harmonic Distortion + Noise %
f = 1 kHz
f = 1 kHz
f = 20 Hz
0.1 0.1
0.01 0.01
f = 20 Hz
f = 10 kHz f = 10 kHz
0.001 0.001
0.01 0.1 1 10 50 0.01 0.1 1 10 50
PO Output Power W PO Output Power W
G009 G010
Figure 9. Total Harmonic Distortion + Noise vs Output Figure 10. Total Harmonic Distortion + Noise vs Output
Power (BTL) Power (BTL)
10 10
Gain = 20 dB Gain = 20 dB
THD+N Total Harmonic Distortion + Noise %
VCC = 18 V VCC = 12 V
ZL = 6 + 47 H ZL = 4 + 33 H
1 1
f = 1 kHz f = 1 kHz
f = 20 Hz
0.1 0.1
0.01 0.01
f = 20 Hz
f = 10 kHz
f = 10 kHz
0.001 0.001
0.01 0.1 1 10 50 0.01 0.1 1 10 50
PO Output Power W PO Output Power W
G011 G012
Figure 11. Total Harmonic Distortion + Noise vs Output Figure 12. Total Harmonic Distortion + Noise vs Output
Power (BTL) Power (BTL)
ZL = 8 + 66 H ZL = 4 + 33 H
12
25
PO Output Power W
10
20
8
15
6
10
4
2 5
0 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 1 2 3 4 5 6
VPLIMIT PLIMIT Voltage V VPLIMIT PLIMIT Voltage V
G013 G014
Phase
30 0 30
Po - Output Power - W
25 50 25
Gain dB
Phase
15 150 15
CI = 1 F THD= 1%
Gain = 20 dB
10 200 10
Filter = Audio Precision AUX-0025
VCC = 12 V
5 VI = 0.1 Vrms 250 5
ZL = 8 + 66 H
0 300 0
20 100 1k 10k 100k 6 8 10 12 14 16 18 20 22 24 26
f Frequency Hz Vcc - Supply Voltage - V
G015
The figure is measured with heatsink(1) on EVM(2)
SPACE Figure 16. Output Power vs Supply Voltage (BTL)
Figure 15. Gain and Phase vs Frequency (BTL)
40 30
Gain = 20 dB Gain = 20 dB
ZL = 6 : + 47PH ZL = 4 : + 33PH
35
25
30
Po - Output Power - W
Po - Output Power - W
20
25 THD = 10%
THD = 10%
20 15
15 THD= 1%
THD= 1%
10
10
5
5
0 0
6 8 10 12 14 16 18 20 22 24 26 6 8 10 12 14 16 18
Vcc - Supply Voltage - V Vcc - Supply Voltage - V
The figure is measured with heatsink(1) on EVM(2) The figure is measured with heatsink(1) on EVM(2)
Figure 17. Output Power vs Supply Voltage (BTL) Figure 18. Output Power vs Supply Voltage (BTL)
h Efficiency %
60 60
50 50
40 40
30 30
20 20
Gain = 20 dB
10 Gain = 20 dB 10 LC Filter = 22 H + 0.68 F
ZL = 8 + 66 H RL = 8
0 0
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25
PO Output Power W PO Output Power W
G018 G032
90 VCC = 12 V 90 VCC = 12 V
VCC = 18 V
80 80
VCC = 18 V
70 70
h Efficiency %
h Efficiency %
60 60
50 50
40 40
30 30
20 20
Gain = 20 dB
10 Gain = 20 dB 10 LC Filter = 22 H + 0.68 F
ZL = 6 + 47 H RL = 6
0 0
0 5 10 15 20 25 0 5 10 15 20 25
PO Output Power W PO Output Power W
G019 G033
Note: Dashed Lines represent thermally limited regions. Figure 22. Efficiency vs Output Power (BTL With LC Filter)
Figure 21. Efficiency vs Output Power (BTL)
100 100
90 90
VCC = 12 V VCC = 12 V
80 80
70 70
h Efficiency %
h Efficiency %
60 60
50 50
40 40
30 30
20 20
Gain = 20 dB
10 Gain = 20 dB 10 LC Filter = 22 H + 0.68 F
ZL = 4 + 33 H RL = 4
0 0
0 3 6 9 12 15 18 0 5 10 15 20 25
PO Output Power W PO Output Power W
G020 G034
0.4
Gain = 20 dB 0.4
0.2 ZL = 8 + 66 H
0.0 0.0
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30
PO(Tot) Total Output Power W PO(Tot) Total Output Power W
G021 G022
Note: Dashed Lines represent thermally limited regions. Note: Dashed Lines represent thermally limited regions.
Figure 25. Supply Current vs Total Output Power (BTL) Figure 26. Supply Current vs Total Output Power (BTL)
20 0
Gain = 20 dB Gain = 20 dB
30
VCC = 12 V Vripple = 200 mVpp
KSVR Supply Ripple Rejection Ratio dB
40 VO = 1 Vrms 20 ZL = 8 + 66 H
ZL = 8 + 66 H
50
40
60
Crosstalk dB
70
60 VCC = 12 V
80
Right to Left
90
80
100
130 120
20 100 1k 10k 20k 20 100 1k 10k 20k
f Frequency Hz f Frequency Hz
G023 G024
VCC = 24 V VCC = 24 V
ZL = 4 + 33 H ZL = 4 + 33 H
THD Total Harmonic Distortion %
1 1
PO = 5 W f = 1 kHz
0.1 0.1
PO = 0.5 W
0.01 0.01
PO = 2.5 W f = 20 Hz
f = 10 kHz
0.001 0.001
20 100 1k 10k 20k 0.01 0.1 1 10 50
f Frequency Hz PO Output Power W
G025 G026
Figure 29. Total Harmonic Distortion vs Frequency (PBTL) Figure 30. Total Harmonic Distortion + Noise vs Output
Power (PBTL)
50 Gain = 20 dB
35 50 ZL = 4 : + 33PH
45
Phase
30 0 40
Po - Output Power - W
25 50 35 THD = 10%
Gain dB
Phase
Gain 30
20 100
25
15 150 20 THD= 1%
CI = 1 F
10 Gain = 20 dB 15
200
Filter = Audio Precision AUX-0025
VCC = 24 V 10
5 VI = 0.1 Vrms 250
5
ZL = 8 + 66 H
0 300 0
20 100 1k 10k 100k 6 8 10 12 14 16 18 20 22 24
f Frequency Hz Vcc - Supply Voltage - V
G027
The figure is measured with heatsink(1) on EVM(2)
Figure 31. Gain and Phase vs Frequency (PBTL) Figure 32. Output Power vs Supply Voltage (PBTL)
100 2.8
2.6 Gain = 20 dB
90 ZL = 4 + 33 H
2.4
80 2.2
VCC = 18 V
2.0
ICC Supply Current A
70
VCC = 12 V
h Efficiency %
1.8
60
1.6 VCC = 12 V
50 1.4
1.2 VCC = 18 V
40
1.0
30 0.8
20 0.6
0.4
10 Gain = 20 dB
ZL = 4 + 33 H 0.2
0 0.0
0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 45
PO Output Power W PO Output Power W
G029 G030
20 ZL = 8 + 66 H
40
60 VCC = 12 V
80
100
120
20 100 1k 10k 20k
f Frequency Hz
G031
(1) Detailed parameters of heatsink: please refer to datasheet heatsink with part number ATS-TI10P-521-C1-R1.
(2) Related parameters of the two-layer EVM: copper thickness of top layer and bottom layer are both 0.03556mm.
9 Detailed Description
9.1 Overview
The TPA3110D2 is a 15-W Class-D audio power amplifier. It is designed to drive BTL stereo speakers. This
device is able to use inexpensive ferrite bead filters at the outputs while meeting EMC requirements. The
TPA3110D2 can drive stereo speakers as low as 4 and its high efficiency eliminates the need for an external
heat sink. The device is fully protected against shorts to GND, VCC and output-to-output. The short-circuit
protection and thermal protection includes an auto-recovery feature.
OUTPL FB
LINP PGND
PWM
Gain
PLIMIT Logic
Control GVDD
LINN PVCCL
BSNL
PVCCL
OUTNL FB
OUTNL FB
FAULT
Gate
Drive OUTNL
SD
TTL
Buffer
GAIN0 SC Detect
Gain PGND
GAIN1 Control
DC Detect
Ramp Biases and Startup Protection
Generator References Logic Thermal
Detect
PLIMIT
PLIMIT Reference UVLO/OVLO
GVDD
PVCCL
BSNR
AVDD
PVCCL
AVCC LDO
Regulator
GVDD
Gate
Drive OUTNR
GVDD
OUTNN FB OUTNR FB
RINN
PGND
Gain PWM
PLIMIT Logic
Control
GVDD PVCCL
RINP
BSPR
PVCCL
OUTNP FB
Gate
Drive OUTPR
TTL PBTL PBTL Select
PBTL Buffer Select OUTPR FB
AGND
PGND
OUTP
OUTN
No Output
OUTP
OUTP-OUTN 0V
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN 0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
OUTP-OUTN 0V
-PVCC
Speaker 0A
Current
Figure 36. The TPA3110D2 Output Voltage And Current Waveforms Into An Inductive Load
50
Limit Level - dBmV/m
40
30
20
10
0
30M 230M 430M 630M 830M
f - Frequency - Hz
9.3.1.2 Efficiency: LC Filter Required With The Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3110D2 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
33 mH
OUTN
C3
L2
1 mF
Figure 38. Typical LC Output Filter, Cutoff Frequency of 27 Khz, Speaker Impedance = 8
15 mH
OUTP
L1 C2
2.2 mF
15 mH
OUTN
L2 C3
2.2 mF
Figure 39. Typical Lc Output Filter, Cutoff Frequency Of 27 Khz, Speaker Impedance = 4
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 40. Typical Ferrite Chip Bead Filter (Chip Bead Example)
9.3.4 PLIMIT
The voltage at pin 10 can used to limit the power to levels below that which is possible based on the supply rail.
Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also
be used if tighter tolerance is required. Also add a 1F capacitor from pin 10 to ground.
Vinput
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to fixed maximum value. This limit can be thought of as a virtual voltage rail which is lower than the supply
connected to PVCC. This "virtual" rail is 4 times the voltage at the PLIMIT pin. This output voltage can be used to
calculate the maximum output power for a given maximum input voltage and speaker impedance.
2
RL
x VP
RL + 2 x RS
POUT = for unclipped power
2 x RL
Where:
RS is the total series resistance including RDS(on), and any resistance in the output filter.
RL is the load resistance.
VP is the peak amplitude of the output possible within the supply rail.
POUT (10%THD) = 1.25 POUT (unclipped) (1)
9.3.8 DC Detect
TPA3110D2 has circuitry which will protect the speakers from DC current which might occur due to defective
capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on
the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the
state of the outputs to Hi-Z. To clear the DC Detect it is necessary to cycle the PVCC supply. Cycling S D will
NOT clear a DC detect fault.
A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 14% (for example,
+57%, -43%) for more than 420 msec at the same polarity. This feature protects the speaker from large DC
currents or AC currents less than 2Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low
at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive
and negative inputs to avoid nuisance DC detect faults.
The minimum differential input voltages required to trigger the DC detect are show in table 2. The inputs must
remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
PVCC
100 k
Control 1 28
SD PVCCL
System 1 k
2 27
FAULT PVCCL
1 mF 3 26 0.22 F
LINP BSPL FB
1 mF 4 25
LINN OUTPL 1000 pF
5 24
GAIN0 PGND
6 23
PVCC 10
GAIN1 OUTNL 1000 pF
7 22
AVCC BSNL FB
1 mF 0.22 F
TPA3110D2
8 21 0.22 F
AGND BSNR FB
1 mF 9 20 1000 pF
GVDD OUTNR
1 mF
10 k 10 19
PLIMIT PGND
10 k
1 mF 11 18
RINN OUTPR 1000 pF
Audio 12 17 FB
RINP BSPR
Source 1 mF
0.22 F
13 16
NC PVCCR
100 F 0.1 F 1000 pF
14 15
PBTL PVCCR
GND
29
PowerPAD
PVCC
Figure 42. Typical Application Schematic With BTL Output and Single-Ended Inputs With Power Limiting
Zf
Ci
Zi
Input IN
Signal
The 3-dB frequency can be calculated using Equation 2. Use the ZI values given in Table 2.
1
f =
2p Zi Ci (2)
-3 dB
1
fc =
2p Zi Ci
fc (3)
The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZI is 60 k and the specification calls for a flat bass response down to 20 Hz. Equation 3 is
reconfigured as Equation 4.
1
Ci =
2p Zi fc (4)
In this example, CI is 0.13 F; so, one would likely choose a value of 0.15 F as this value is commonly used. If
the gain is known and is constant, use ZI from Table 2 to calculate CI. A further consideration for this capacitor is
the leakage path from the input source through the input network (CI) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the dc level there is held at 3 V, which is likely higher than the source dc level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset
voltages and it is important to ensure that boards are cleaned properly.
30 25
Gain = 20 dB Gain = 20 dB
ZL = 8 + 66 H ZL = 4 + 33 H
25
20
PO Output Power W
PO Output Power W
20
THD = 10%
15
THD = 10%
15
THD = 1%
THD = 1% 10
10
5
5
0 0
6 8 10 12 14 16 18 20 22 24 26 6 8 10 12 14 16 18
VCC Supply Voltage V VCC Supply Voltage V
G016 G017
Note: Dashed Lines represent thermally limited regions. Note: Dashed Lines represent thermally limited regions.
Figure 44. Output Power vs Supply Voltage (BTL) Figure 45. Output Power vs Supply Voltage (BTL)
10.2.2 Stereo Class-D Amplifier With PBTL Output and Single-Ended Input
PVCC
100 k
Control 1 28
SD PVCCL
System 1 k
2 27
FAULT PVCCL
3 26
LINP BSPL
0.47 F
4 25
LINN OUTPL
5 24
GAIN0 PGND
6 23 FB
AVCC GAIN1 OUTNL
1000 pF
7 22
PVCC AVCC BSNL
10 TPA3110D2
1 mF 8 21
AGND BSNR
1000 pF
1 mF
9 20
GVDD OUTNR
FB
10 19
PLIMIT PGND
0.47 F
1 mF 11 18
RINN OUTPR
Audio 12
BSPR
17
RINP
Source 1 mF
13 16
NC PVCCR
(1) 100 F 0.1 F 1000 pF
100 kW 14 15
AVCC PBTL
GND
PVCCR
29
PowerPAD
PVCC
(1) 100 k resistor is needed if the PVCC slew rate is more than 10 V/ms.
Figure 46. Typical Application Schematic With PBTL Output and Single-Ended Input
30
PO Output Power W
25
THD = 10%
20
THD = 1%
15
10
0
6 8 10 12 14 16 18 20
VCC Supply Voltage V
G028
12 Layout
13.4 Trademarks
SpeakerGuard, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 20-Apr-2017
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
HPA01070PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3110D2
& no Sb/Br)
TPA3110D2PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3110D2
& no Sb/Br)
TPA3110D2PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3110D2
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 20-Apr-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Automotive: TPA3110D2-Q1
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Apr-2017
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Apr-2017
Pack Materials-Page 2
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