Professional Documents
Culture Documents
F. Xavier Moncunill
Fall 2015
The aim of this practice is to present the design process of digital circuits using standard
cells, from the VHDL language description to the layout design ready to be manufactured.
1
Verilog .cel2 pin
placement project_vars.sh
source (optional) setup file (affects all parts of the flow)
file hints file
Yosys
BLIF +
netlist
Qrouter Magic
Yosys/ABC Graywolf
Routing
Display
Synthesis
Placement
BLIF placement DEF file .sim netlist
netlist results GDS2 output
blifFanout
place2def
blif2cel
decongest
DEF file
.cel input for
placement
Figure 1
By default, Qflow uses the open-source 0.35 m standard cell set provided by Oklahoma State
University (OSU). The standard cells can be downloaded from http://www.opencircuitdesign.
com/qflow/example/osu035_stdcells.gds2.
Additional open-source standard cells for other technologies provided by OSU can be down-
loaded from http://vcag.ecen.okstate.edu/projects/scells/download/MOSIS_SCMOS/osu_
stdcells_v2.4/ (download osu_stdcells_lib.v2.4.tar.gz or later).
a) Write a VHDL file describing a simple logic function. You may consider describing the
AND function,
F =AB
Task 2. Repeat the whole process starting now from the more complex Verilog file map9v3.v
provided as example by the Qflow web site.