LT1010

Fast 150mA Power Buffer

FTEATURES DESCRIPTION
n 20MHz Bandwidth The LT1010 is a fast, unity-gain buffer that can increase
n 75V/s Slew Rate the output capability of existing IC op amps by more than
n Drives 10V Into 75 an order of magnitude. This easy-to-use part makes fast
n 5mA Quiescent Current amplifiers less sensitive to capacitive loading and reduces
n Drives Capacitive Loads > 1F thermal feedback in precision DC amplifiers.
n Current and Thermal Limit
n
Designed to be incorporated within the feedback loop, the
Operates from Single Supply 4.5V
n
buffer can isolate almost any reactive load. Speed can be
Very Low Distortion Operation
n
improved with a single external resistor. Internal operating
Available in 8-Pin miniDIP, Plastic TO-220
currents are essentially unaffected by the supply voltage
and Tiny 3mm 3mm 0.75mm 8-Pin DFN Packages
range. Single supply operation is also practical.
This monolithic IC is supplied in 8-pin miniDIP, plastic
APPLICATIONS TO-220 and 8-pin DFN packages. The low thermal re-
n Boost Op Amp Output sistance power package is an aid in reducing operating
n Isolate Capacitive Loads junction temperatures.
n Drive Long Cables L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
n Audio Amplifiers
n Video Amplifiers
n Power Small Motors
n Operational Power Supply
n FET Driver

TYPICAL APPLICATION
Very Low Distortion Buffered Preamplifier

V+
18V 0.4
C2 VOUT = 10VP-P
22pF R7
RL = 400
50
R1
HARMONIC DISTORTION (%)

1k V+ 0.3
3 7
+ R6 BOOST R8
6 100 IN OUT 100
LT1056CN8 LT1010CT OUTPUT
R2 C1 0.2
2
1M 22pF
R3
4 R4 V
1k 10k
V+ 0.1

LM334
NOTE 1: ALL RESISTORS 1% METAL FILM RSET
NOTE 2: SUPPLIES WELL BYPASSED AND LOW ZO 33.2
ISET = 2mA V 0
1% 10 100 1k 10k 100k
V+ 1010 TA01 FREQUENCY (Hz)
18V 1010 TA02

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LT1010
ABSOLUTE MAXIMUM RATINGS PRECONDITIONING
(Note 1)
100% Thermal Limit Burn InLT1010CT
Total Supply Voltage ..............................................22V
Continuous Output Current (Note 2).................. 150mA
Input Current (Note 3).......................................... 40mA
Junction Temperature Range
LT1010C................................................. 0C to 125C
Storage Temperature Range.................... 65C to 150C
Lead Temperature (Soldering, 10 sec)................... 300C

PIN CONFIGURATION
TOP VIEW
TOP VIEW FRONT VIEW
V+ 1 8 INPUT
V+ 1 8 INPUT 5 OUTPUT
BIAS 2 7 NC 4
9 BIAS
BIAS 2 7 NC
OUT 3 6 V V 3 V (TAB)
NC 4 NC OUT 3 6 V
5 2 V+
NC 4 5 NC
1 INPUT
DD PACKAGE N8 PACKAGE T PACKAGE
8-LEAD (3mm 3mm) PLASTIC DFN 8-LEAD PDIP 5-LEAD PLASTIC TO-220
TJMAX = 150C, JA = 43C/W, JC = 7.5C/W TJMAX = 150C, JA = 100C/W, JC = 45C/W TJMAX = 125C, JA = 50C/W, JC = 3C/W
EXPOSED PAD (PIN 9) V CAN BE SOLDERED TO PCB
TO REDUCE THERMAL RESISTANCE (NOTE 7)

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1010CDD#PBF LT1010CDD#TRPBF LBWZ 8-Lead (3mm 3mm) Plastic DFN 0C to 100C
LT1010CN8#PBF LT1010CN8#TRPBF LTC1010CN8 8-Lead PDIP 0C to 100C
LT1010CT#PBF LT1010CT#TRPBF LTC1010CT 5-Lead Plastic TO-220 0C to 100C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1010CDD LT1010CDD#TR LBWZ 8-Lead (3mm 3mm) Plastic DFN 0C to 100C
LT1010CN8 LT1010CN8#TR LTC1010CN8 8-Lead PDIP 0C to 100C
LT1010CT LT1010CT#TR LTC1010CT 5-Lead Plastic TO-220 0C to 100C
OBSOLETE PACKAGE
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

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 LT1010
ELECTRICAL
The CHARACTERISTICS l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25C. (See Note 4. Typical values in curves.)
SYMBOL PARAMETER CONDITIONS (Note 4) MIN TYP MAX UNITS
VOS Output Offset Voltage (Note 4) 0 150 mV
l 20 220 mV
VS = 15V, VIN = 0V 20 100 mV
IB Input Bias Current IOUT = 0mA 0 250 A
IOUT 150mA 0 500 A
l 0 800 A
AV Large-Signal Voltage Gain l 0.995 1.00 V/V
ROUT Output Resistance IOUT = 1mA 5 10
IOUT = 150mA 5 10
l 12
Slew Rate VS = 15V, VIN = 10V, VOUT = 8V, RL = 100 75 V/s
VSOS+ Positive Saturation Offset IOUT = 0 (Note 5) 1.0 V
l 1.1 V
VSOS Negative Saturation Offset IOUT = 0 (Note 5) 0.2 V
l 0.3 V
RSAT Saturation Resistance IOUT = 150mA (Note 5) 22
l 28
VBIAS Bias Terminal Voltage RBIAS = 20 (Note 6) 700 840 mV
l 560 880 mV
IS Supply Current IOUT = 0, IBIAS = 0 9 mA
l 10 mA

Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Dissipation must be based on a thermal resistance. See
Application Information for power dissipation.
Note 3: In current limit or thermal limit, input current increases sharply
with input-output differentials greater than 8V; so input current must be
limited. Input current also rises rapidly for input voltages 8V above V+ or
0.5V below V.
Note 4: Specifications apply for 4.5V VS 40V,
V + 0.5V VIN V+ 1.5V and IOUT = 0, unless otherwise stated.
Temperature range is 0C TC 100C.
Note 5: The output saturation characteristics are measured with 100mV
output clipping. See Applications Information for determining available
output swing and input drive requirements for a given load.
Note 6: The output stage quiescent current can be increased by connecting
a resistor between the BIAS pin and V+. The increase is equal to the bias
terminal voltage divided by this resistance.
Note 7: Thermal resistance varies depending upon the amount of PC board
metal attached to the pin (Pin 9) of the device. JA is specified for a certain
amount of 1oz copper metal trace connecting to Pin 9 as described in the
thermal resistance tables in the Applications Information section.

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LT1010
TYPICAL PERFORMANCE CHARACTERISTICS
Bandwidth Phase Lag Phase Lag
50 50 50

RL = 200
40

PHASE LAG (DEGREES)

PHASE LAG (DEGREES)

FREQUENCY (MHz)

30 RL = 50 20 20
RL = 50 RL = 50 RL = 200
RL = 200
20
10 10
VIN = 100mVP-P CL = 100pF CL = 100pF
10 CL 100pF RS = 50 RS = 50
AV = 3dB IBIAS = 0 RBIAS = 20
TJ = 25C TJ = 25C TJ = 25C
0 5 5
0 10 20 30 40 2 5 10 20 2 5 10 20
QUIESCENT CURRENT (mA) FREQUENCY (MHz) FREQUENCY (MHz)
1010 G01 1010 G02 1010 G03

Small-Step Response Output Impedance Capacitive Loading

150 100 10
RL = 100 IBIAS = 0 RS = 50
TJ = 25C TJ = 25C IBIAS = 0
100 TJ = 25C
OUTPUT IMPEDANCE ()
VOLTAGE CHANGE (mV)

VOLTAGE GAIN (dB)

50 0
INPUT OUTPUT 3nF 100pF
0 10

50 10
0.1F
100

150 1 20
0 10 20 30 0.1 1 10 100 0.1 1 10 100
TIME (ns) FREQUENCY (MHz) FREQUENCY (MHz)
1010 G04 1010 G05 1010 G06

Slew Response Negative Slew Rate Supply Current

20 400 80
VS = 15V VS = 15V
15 0 VIN 10V VIN = 10V
IL = 0
POSITIVE RL = 200 TC = 25C
10 300 60
SUPPLY CURRENT (mA)
OUTPUT VOLTAGE (V)

SLEW RATE (V/s)

RL = 100
5 VS = 15V
RL = 100
0 IBIAS = 0 TJ = 25C 200 40
RL = 50
f 1MHz
5
NEGATIVE
10 100 20
RBIAS = 20
15

20 0 0
50 0 50 100 150 200 250 0 10 20 30 40 0 1 2 3 4 5
TIME (ns) QUIESCENT CURRENT (mA) FREQUENCY (MHz)
1010 G07 1010 G08 1010 G09

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 LT1010
TYPICAL PERFORMANCE CHARACTERISTICS
Output Offset Voltage Input Bias Current Input Bias Current
200 200 200
VIN = 0 VIN = 0 VS = 15V
RL = 75

150 150 150

OFFSET VOLTAGE (mV)

TJ = 125C

BIAS CURRENT (A)

BIAS CURRENT (A)

V+ = 38V
V+ = 38V V = 2V
= 2V TJ = 25C
V
100 100 100

V+ = 2V TJ = 55C
V = 38V V+ = 2V
50 50 V = 38V 50

0 0 0
50 0 50 100 150 50 0 50 100 150 150 100 50 0 50 100 150
TEMPERATURE (C) TEMPERATURE (C) OUTPUT CURRENT (mA)
1010 G10 1010 G11 1010 G12

Voltage Gain Output Resistance Output Noise Voltage

1.000 12 200
IOUT = 0 IOUT 150mA TJ = 25C

10
VS = 40V 150

NOISE VOLTAGE (nV/Hz)

OUTPUT RESISTANCE ()

0.999 8
GAIN (V/V)

6 100
VS = 4.5V
0.998 4 RS = 1k
50
2 RS = 50

0.997 0 0
50 0 50 100 150 50 0 50 100 150 10 100 1k 10k
TEMPERATURE (C) TEMPERATURE (C) FREQUENCY (Hz)
1010 G14 1010 G15
1010 G13

Positive Saturation Voltage Negative Saturation Voltage Supply Current

4 4 7
VIN = 0
IOUT = 0
IBIAS = 0 TJ = 55C
IL = 150mA IL = 150mA
SATURATION VOLTAGE (V)

SATURATION VOLTAGE (V)

3 3 6
SUPPLY CURRENT (mA)

TJ = 25C
2 2 5
IL = 50mA IL = 50mA

IL = 5mA IL = 5mA TJ = 125C

1 1 4

0 0 3
50 0 50 100 150 50 0 50 100 150 0 10 20 30 40
TEMPERATURE (C) TEMPERATURE (C) TOTAL SUPPLY VOLTAGE (V)
1010 G16 1010 G17 1010 G18

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LT1010
TYPICAL PERFORMANCE CHARACTERISTICS
Bias Terminal Voltage Total Harmonic Distortion Total Harmonic Distortion
1.0 0.4 0.8
VS = 20V RL = 50 IBIAS = 0
f = 10kHz VS = 15V
VS = 15V VOUT = 10V
0.9
BIAS TERMINAL VOLTAGE (V)

HARMONIC DISTORTION (%)

HARMONIC DISTORTION (%)

0.3 TC = 25C 0.6 TC = 25C

0.8
RBIAS = 100
0.2 0.4
RBIAS = 20 IBIAS = 0 RBIAS = 50 RL = 50
0.7

0.1 0.2 RL = 100

0.6

0.5 0 0
50 0 50 100 150 0.1 1 10 100 1 10 100 1000
TEMPERATURE (C) OUTPUT VOLTAGE (VP-P) FREQUENCY (kHz)
1010 G20 1010 G21
1010 G19

Shorted Input Characteristics Peak Power Capability Peak Output Current

50 10 0.5
VS = 15V TC = 85C VS = 15V
VOUT = 0 VOUT = 0
TJ = 25C
8 0.4
25 SINK

OUTPUT CURRENT (A)

INUPT CURRENT (mA)

PEAK POWER (W)

6 0.3
SOURCE
0
TO-220
4 0.2

25
2 0.1

50 0 0
15 10 5 0 5 10 15 1 10 100 50 0 50 100 150
INPUT VOLTAGE (V) PULSE WIDTH (ms) TEMPERATURE (C)
1010 G23
1010 G22 1010 G24

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 LT1010
APPLICATIONS INFORMATION
General idealized buffer with the unloaded gain specified for the
These notes briefly describe the LT1010 and how it is LT1010. Otherwise, it has zero offset voltage, bias current
used; a detailed explanation is given elsewhere.1 Emphasis and output resistance. Its output also saturates to the
here will be on practical suggestions that have resulted internal supply terminals.2
from working extensively with the part over a wide range V+
of conditions. A number of applications are also outlined
that demonstrate the usefulness of the buffer beyond that VSOS+
IB
of driving a heavy load. R

VOS
Design Concept INPUT
+ A1
ROUT
OUTPUT

The schematic below describes the basic elements of the

buffer design. The op amp drives the output sink transistor, R R = RSAT ROUT

Q3, such that the collector current of the output follower, VSOS

Q2, never drops below the quiescent value (determined by V 1010 AI02

I1 and the area ratio of D1 and D2). As a result, the high

frequency response is essentially that of a simple follower Loaded voltage gain can be determined from the unloaded
even when Q3 is supplying the load current. The internal gain, AV, the output resistance, ROUT, and the load resis-
feedback loop is isolated from the effects of capacitive tance, RL, using:
loading by a small resistor in the output lead.
A VRL
A VL =
V+ ROUT +RL
D1 D2
BIAS Maximum positive output swing is given by:
I2
(V + VSOS+ )RL
+
A1
Q2 VOUT + =
RSAT +RL
Q1 INPUT
R1
I1 OUTPUT
The input swing required for this output is:
Q3
R
V VIN+ = VOUT + 1+ OUT VOS + VOS
RL
1010 AI01

The scheme is not perfect in that the rate of rise of sink
current is noticeably less than for source current. This
can be mitigated by connecting a resistor between the
bias terminal and V+, raising quiescent current. A feature
of the final design is that the output resistance is largely
independent of the follower quiescent current or the output
load current. The output will also swing to the negative rail,
which is particularly useful with single supply operation.
Equivalent Circuit
Below 1MHz, the LT1010 is quite accurately represented
by the equivalent circuit shown here for both small- and
large-signal operation. The internal element, A1, is an
where VOS is the 100mV clipping specified for the satu-
ration measurements. Negative output swing and input
drive requirements are similarly determined.
Supply Bypass
The buffer is no more sensitive to supply bypassing than
slower op amps as far as stability is concerned. The
0.1F disc ceramic capacitors usually recommended for
op amps are certainly adequate for low frequency work.
As always, keeping the capacitor leads short and using
1R. J. Widlar, Unique IC Buffer Enhances Op Amp Designs; Tames Fast Amplifiers,
Linear Technology Corp. TP-1, April, 1984.
2See electrical characteristics section for guaranteed limits.

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LT1010
APPLICATIONS INFORMATION
a ground plane is prudent, especially when operating at
high frequencies.
The buffer slew rate can be reduced by inadequate sup-
ply bypass. With output current changes much above
100mA/s, using 10F solid tantalum capacitors on both
supplies is good practice, although bypassing from the
positive to the negative supply may suffice.
When used in conjunction with an op amp and heavily
loaded (resistive or capacitive), the buffer can couple into
supply leads common to the op amp causing stability
problems with the overall loop and extended settling time.
Adequate bypassing can usually be provided by 10F solid
tantalum capacitors. Alternately, smaller capacitors could
be used with decoupling resistors. Sometimes the op amp
has much better high frequency rejection on one supply,
so bypass requirements are less on this supply.
Power Dissipation
In many applications the LT1010 will require heat sinking.
Thermal resistance, junction to still air is 50C/W for the
TO-220 package and 100C/W for the miniDIP package.
Circulating air, a heat sink or mounting the package to
a printed circuit board will reduce thermal resistance.
In DC circuits, buffer dissipation is easily computed. In
AC circuits, signal waveshape and the nature of the load
determine dissipation. Peak dissipation can be several
times average with reactive loads. It is particularly im-
portant to determine dissipation when driving large load
capacitance.
With AC loading, power is divided between the two output
transistors. This reduces the effective thermal resistance,
junction to case is 3C/W for the TO-220 package as long
as the peak rating of neither output transistor is exceeded.
The typical curves indicate the peak dissipation capabilities
of one output transistor.
Overload Protection
The LT1010 has both instantaneous current limit and
thermal overload protection. Foldback current limiting has
not been used, enabling the buffer to drive complex loads
without limiting. Because of this, it is capable of power
dissipation in excess of its continuous ratings.
8
Normally, thermal overload protection will limit dissipa-
tion and prevent damage. However, with more than 30V
across the conducting output transistor, thermal limiting
is not quick enough to ensure protection in current limit.
The thermal protection is effective with 40V across the
conducting output transistor as long as the load current
is otherwise limited to 150mA.
Drive Impedance
When driving capacitive loads, the LT1010 likes to be driven
from a low source impedance at high frequencies. Certain
low power op amps (e.g., the LM10) are marginal in this
respect. Some care may be required to avoid oscillations,
especially at low temperatures.
Bypassing the buffer input with more than 200pF will solve
the problem. Raising the operating current also works.
Parallel Operation
Parallel operation provides reduced output impedance,
more drive capability and increased frequency response
under load. Any number of buffers can be directly paral-
leled as long as the increased dissipation in individual
units caused by mismatches of output resistance and
offset voltage is taken into account.
When the inputs and outputs of two buffers are connected
together, a current, IOUT, flows between the outputs:
VOS1 VOS2
IOUT =
ROUT1 +ROUT2
where VOS and ROUT are the offset voltage and output
resistance of the respective buffers.
Normally, the negative supply current of one unit will
increase and the other decrease, with the positive supply
current staying the same. The worst-case (VIN V+)
increase in standby dissipation can be assumed to be
IOUTVT, where VT is the total supply voltage.
Offset voltage is specified worst case over a range of sup-
ply voltages, input voltage and temperature. It would be
unrealistic to use these worst-case numbers above because
paralleled units are operating under identical conditions.
1010fe
 LT1010
APPLICATIONS INFORMATION
The offset voltage specified for VS = 15V, VIN = 0V and At lower frequencies, the buffer is within the feedback loop
TA = 25C will suffice for a worst-case condition. so that its offset voltage and gain errors are negligible. At
higher frequencies, feedback is through CF, so that phase
V+ shift from the load capacitance acting against the buffer
output resistance does not cause loop instability.
IS
IS Stability depends upon the RFCF time constant or the
VIN
A1
VOUT
closed-loop bandwidth. With an 80kHz bandwidth, ring-
LT1010
ing is negligible for CL = 0.068F and damps rapidly for
IOUT CL = 0.33F. The pulse response is shown in the graph.

A2 Pulse Response
LT1010
CL = 0.068F
IS IOUT IS + IOUT 5

OUTPUT VOLTAGE (V)

1010 AI03

5
V

CL = 0.33F
Output load current will be divided based on the output 5
resistance of the individual buffers. Therefore, the avail-
0
able output current will not quite be doubled unless output
5
resistances are matched. As for offset voltage, the 25C
limits should be used for worst-case calculations. 0 50 100 150 200
TIME (s)
Parallel operation is not thermally unstable. Should one 1010 AI05

unit get hotter than its mates, its share of the output and
its standby dissipation will decrease. Small-signal bandwidth is reduced by CF, but considerable
isolation can be obtained without reducing it below the
As a practical matter, parallel connection needs only some
power bandwidth. Often, a bandwidth reduction is desirable
increased attention to heat sinking. In some applications,
to filter high frequency noise or unwanted signals.
a few ohms equalization resistance in each output may be
wise. Only the most demanding applications should require RF
2k
matching, and then just of output resistance at 25C.
CF
Isolating Capacitive Loads 1nF

RS A1 A2
The inverting amplifier below shows the recommended 2k LT118A LT1010 VOUT
VIN +
method of isolating capacitive loads. Noninverting ampli- CL

fiers are handled similarly. 1010 AI06

RF
RS 20k The follower configuration is unique in that capacitive
VIN
load isolation is obtained without a reduction in small-
CF
100pF
signal bandwidth, although the output impedance of the

A1 A2 buffer comes into play at high frequencies. The precision
VOUT
LT1007 LT1010 unity-gain buffer above has a 10MHz bandwidth without
+ CL
capacitive loading, yet it is stable for all load capacitance
1010 AI04
to over 0.3F, again determined by RFCF.

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LT1010
APPLICATIONS INFORMATION
This is a good example of how fast op amps can be made
quite easy to use by employing an output buffer.
Integrator
A lowpass amplifier can be formed just by using large CF
in the inverter described earlier, as long as the increasing
closed-loop output impedance above the cutoff frequency
stage. Feedback is arranged in the conventional manner,
although the 68F-0.01F combination limits DC gain to
unity for all gain settings. For applications sensitive to
NTSC requirements, dropping the 25 output stage bias
value will aid performance.
R2
800

is not a problem and the op amp is capable of supplying

C1
the required current at the summing junction. 15pF

A1 A2
CI HA2625 LT1010 VOUT
1010 AI09

IIN VIN +
RF
20k R1
100

A1 A2
LT1012 LT1010 VOUT
+
1010 AI07
This shows the buffer being used with a wideband ampli-
CF
500pF
fier that is not unity-gain stable. In this case, C1 cannot
be used to isolate large capacitive loads. Instead, it has an
optimum value for a limited range of load capacitances.
If the integrating capacitor must be driven from the buffer The buffer can cause stability problems in circuits like this.
output, the circuit above can be used to provide capacitive With the TO-220 packages, behavior can be improved by
load isolation. As before, the stability with large capacitive raising the quiescent current with a 20 resistor from the
loads is determined by RFCF. bias terminal to V+. Alternately, devices in the miniDIP can
be operated in parallel.
Wideband Amplifiers
It is possible to improve capacitive load stability by oper-
This simple circuit provides an adjustable gain video
ating the buffer class A at high frequencies. This is done
amplifier that will drive 1VP-P into 75. The differential
by using quiescent current boost and bypassing the bias
pair provides gain with the LT1010 serving as an output
terminal to V with more than 0.02F.
15V TYPICAL SPECIFICATIONS R2
1VP-P INTO 75 1.6k
AT A = 2
8.2k 25 0.5dB TO 10MHz
3dB DOWN AT 16MHz
+ AT A = 10
BIAS
22F + 0.5dB TO 4MHz A1 A2
OUTPUT
22F 3dB = 8MHz HA2625 LT1010 1010 AI10
INPUT +
LT1010 OUTPUT
(75) R1
400

15V
PEAKING
5pF to 25pF
900
Putting the buffer outside the feedback loop as shown
INPUT Q1 Q2 here will give capacitive load isolation, with large output
Q1, Q2: 2N3866
1k
GAIN SET
capacitors only reducing bandwidth. Buffer offset, referred
5.1k
+ to the op amp input, is divided by the gain. If the load re-
15V
0.01F 68F sistance is known, gain error is determined by the output
resistance tolerance. Distortion is low.
1010 AI08
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 LT1010
APPLICATIONS INFORMATION
R3 current boost. The appearance is always worse with fast
800
rise signal generators than in practical applications.
C1
20pF R4
39
Track and Hold
A1 A2
INPUT LT1010 OUTPUT 1
+
HA2625
The 5MHz track and hold shown here has a 400kHz power
bandwidth driving 10V. A buffered input follower drives
R1 R2 the hold capacitor, C4, through Q1, a low resistance FET
50 200
R5 switch. The positive hold command is supplied by TTL
39
A3
LT1010 OUTPUT 2 logic with Q3 level shifting to the switch driver, Q2. The
1010 AI11
output is buffered by A3.
OTHER When the gate is driven to V for HOLD, it pulls charge
SLAVES
out of the hold capacitor. A compensating charge is put
The 50 video line splitter here puts feedback on one into the hold capacitor through C3. The step into hold is
buffer with the others slaved. Offset and gain accuracy of made independent of the input level with R7 and adjusted
slaves depend on their matching with master. to zero with R10.
When driving long cables, including a resistor in series Since internal dissipation can be quite high when driving
with the output should be considered. Although it reduces fast signals into a capacitive load, using a buffer in a power
gain, it does isolate the feedback amplifier from the effects package is recommended. Raising buffer quiescent current
of unterminated lines which present a resonant load. to 40mA with R3 improves frequency response.
When working with wideband amplifiers, special attention This circuit is equally useful as a fast acquisition sample
should always be paid to supply bypassing, stray capaci- and hold. An LT1056 might be used for A3 to reduce drift
tance and keeping leads short. Direct grounding of test in hold because its lower slew rate is not usually a problem
probes, rather than the usual ground lead, is absolutely in this application.
necessary for reasonable results.
Current Sources
The LT1010 has slew limitations that are not obvious
from standard specifications. Negative slew is subject A standard op amp voltage to current converter with a
to glitching, but this can be minimized with quiescent buffer to increase output current is shown here. As usual,

V+

R1 R3
2k 20 Q1 A3
INPUT + 2N5432 LT118A OUTPUT
A1 A2 S D
LT118A LT1010 +
C1 C3
50pF R2 100pF
+
D2*
2k A4 6V
C2 LT118A
D1 R4 C4
150pF HP2810 2k 1nF R8
5k
R5 Q3 R9
1k C5
2N2907 Q2 10pF 10k
HOLD
2N2222
R6 R10
1k R7 R11
200k 50k 6.2k
1010 AI12
V *2N2369 EMITTER BASE JUNCTION

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LT1010
APPLICATIONS INFORMATION
excellent matching of the feedback resistors is required to
R2
get high output resistance. Output is bidirectional. C1 2k
1nF R3
A1 A2 2
R1 R2 R2(V2 V1) LT118A LT1010 OUTPUT
100k 100k IOUT =
R1R4 + R4
0.01% 0.01% 2k
V1 R5
0.1% 2k
D1 0.1%
R4 1N457
A3
10
LT118A
A1 A2 0.1%
IOUT
+
LT1012 LT1010 R1 C2 D2
10pF 1N457 R6
R3
+ 2k 99.8k
100k 0.1%
R7
0.01% VV VI
99.8k
V2 1010 AI13
1V/V 0.1% 10mA/V
R4
100k 1010 AI15

0.01%

This circuit uses an instrumentation amplifier to eliminate enables the current regulator to get control of the output
the matched resistors. The input is not high impedance current from the buffer current limit within a microsecond
and must be driven from a low impedance source like for an instantaneous short.
an op amp. Reversal of output sense can be obtained by In the voltage regulation mode, A1 and A2 act as a fast
grounding Pin 7 of the LM163 and driving Pin 5. voltage follower using the capacitive load isolation tech-
nique described earlier. Load transient recovery as well as
capacitive load stability are determined by C1. Recovery
A2
LT1010 VIN from short circuit is clean.
IOUT =
10R1
Bidirectional current limit can be obtained by adding another
R1
VIN 10 op amp connected as a complement to A3.
2 0.1%
7
IOUT
6 A1
LM163
Supply Splitter
10 3
Dual supply op amps and comparators can be operated
+
5

1010AI14
from a single supply by creating an artificial ground at
half the supply voltage. The supply splitter shown here
Output resistances of several megohms can be obtained can source or sink 150mA.
with both circuits. This is impressive considering the The output capacitor, C2, can be made as large as neces-
150mA output capability. High frequency output charac- sary to absorb current transients. An input capacitor is
teristics will depend on the bandwidth and slew rate of the also used on the buffer to avoid high frequency instability
amplifiers. Both these circuits have an equivalent output that can be caused by high source impedance.
capacitance of about 30nF.
V+
Voltage/Current Regulator C3
R1 0.1F
10k
This circuit regulates the output voltage at VV until the load A1
V+/2
current reaches a value programmed by VI. For heavier LT1010
C1 R2 C2
loads, it is a precision current regulator. 1nF 10k 0.01F

With output currents below the current limit, the current

regulator is disconnected from the loop by D1 with D2
1010 AI16

keeping its output out of saturation. This output clamp

1010fe

12
 LT1010
APPLICATIONS INFORMATION
High Current Booster 5V

The circuit below uses a discrete stage to get 3A output INPUT

Q1
2N5486
capacity. The configuration shown provides a clean, quick A A2 B
OUTPUT
LT1010
way to increase LT1010 output power. It is useful for high 10M
current loads such as linear actuator coils in disk drives. 5V
0.1F
The 33 resistors sense the LT1010s supply current 4 + 3
10k
with the grounded 100 resistor supplying a load for Q2
2N2222
6 A1
LTC1050
the LT1010. The voltage drop across the 33 resistors 0.01F
7
2
10M 100
biases Q1 and Q2. Another 100 value closes a local 2000pF
1k
0.1F
5V
feedback loop, stabilizing the output stage. Feedback 5V

to the LT1056 control amplifier is via the 10k value. Q3 1010 AI18

and Q4, sensing across the 0.18 units, furnish current

similarly filtered version of the input signal. The amplified
limiting at about 3.3A.
difference between these signals is used to set Q2s bias,
15pF and hence, Q1s channel current. This forces Q1s VGS to
10k whatever voltage is required to match the circuits input
15V
and output potentials. The 2000pF capacitor at A1 provides
0.18 stable loop compensation. The RC network in A1s output
+ 1k
prevents it from seeing high speed edges coupled through
Q3
68pF 22F 33
2N3906 Q2s collector-base junction. A2s output is also fed back to
the shield around Q1s gate lead, bootstrapping the circuits
INPUT
10k

Q1
MJE2955
effective input capacitance down to less than 1pF.
LT1056 LT1010 OUTPUT

+ 100
100 Gain-Trimmable Wideband FET Amplifier
Q2
MJE3055
A potential difficulty with the previous circuit is that the
gain is not quite unity. The figure labeled A on the next
33 Q4 1k page maintains high speed and low bias while achieving
2N3904
15V 1010 AI17
a true unity-gain transfer function.
0.18
+ 22F
This circuit is somewhat similar except that the Q2-Q3
HEAT SINK OUTPUT TRANSISTORS stage takes gain. A2 DC stabilizes the input-output path and
A1 provides drive capability. Feedback is to Q2s emitter
Wideband FET Input Stabilized Buffer from A1s output. The 1k adjustment allows the gain to be
The figure below shows a highly stable unity-gain buffer precisely set to unity. With the LT1010, output stage slew
with good speed and high input impedance. Q1 and Q2 and full power bandwidth (1VP-P) are 100V/s and 10MHz
respectively. 3dB bandwidth exceeds 35MHz. At A = 10
constitute a simple, high speed FET input buffer. Q1 func-
(e.g., 1k adjustment set at 50), full power bandwidth
tions as a source follower with the Q2 current source load
stays at 10MHz while the 3dB point falls to 22MHz.
setting the drain-source channel current. The LT1010 buffer
provides output drive capability for cables or whatever With the optional discrete stage, slew exceeds 1000V/s
load is required. Normally, this open-loop configuration and full power bandwidth (1VP-P) is 18MHz. 3dB band-
would be quite drifty because there is no DC feedback. The width is 58MHz. At A = 10, full power is available to 10MHz,
LTC1050 contributes this function to stabilize the circuit. with the 3dB point at 36MHz.
It does this by comparing the filtered circuit output to a

1010fe

13
LT1010
APPLICATIONS INFORMATION
Figures A and B show response with both output stages. Thermal Considerations for the MiniDIP Package
The LT1010 is used in Figure A (Trace A = input, Trace B
The miniDIP package requires special thermal consider-
= output). Figure B uses the discrete stage and is slightly
ations since it is not designed to dissipate much power. Be
faster. Either stage provides more than adequate perfor-
aware that for applications requiring large output currents,
mance for driving video cable or data converters and the
another package should be used.
LT1012 maintains DC stability under all conditions.

Gain-Trimmable Wideband FET Amplifier

15V

10pF
1k 470

Q1 Q3
INPUT 2N3906 15V
2N5486
Q2 A A2 B
2N3904 OUTPUT
LT1010
0.01F
3k

1k 2N3904

1k
3
GAIN
ADJ A B
10M 10k 2k 300 50 5.6k 3k 10M
3

0.1F 2N3906
15V +
3k
A1
LT1012 0.1F
1k
15V
0.002F

1010 AI19

(A) (B)

A = 0.2V/DIV A = 0.2V/DIV
B = 0.2V/DIV B = 0.2V/DIV
1010 AI20
10ns/DIV 10ns/DIV 1010 AI21

Figure A. Waveforms Using LT1010 Figure B. Waveforms Using Discrete Stage

1010fe

14

APPLICATIONS INFORMATION
Typical thermal calculations for the miniDIP package are
detailed in the following paragraphs.
For 4.8mA supply current (typical at 50C, 30V supply
voltagesee supply current graphs) to the LT1010 at
15V, PD = power dissipated in the part is equal to:
(30V)(0.0048A) = 0.144W
LT1010
Thermal Resistance of DFN Package
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.

The rise in junction is then: The following table lists thermal resistance for several
different board sizes and copper areas. All measurements
(0.144W)(100C/WThis is JA for the N package) were taken in still air on 3/32" FR-4 board with one ounce
= 14.4C. copper.
This means that the junction temperature in 50C ambient Table 1. DFN Measured Thermal Resistance
air without driving any current into a load is: COPPER AREA THERMAL RESISTANCE
TOPSIDE BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
14.4C + 50C = 64.4C
2500 sq mm 2500 sq mm 2500 sq mm 40C/W
Using the LT1010 to drive 8V DC into a 200 load using 1000 sq mm 2500 sq mm 2500 sq mm 45C/W
15V power supplies dissipates PD in the LT1010 where: 225 sq mm 2500 sq mm 2500 sq mm 50C/W

P =
(V +
)
VOUT ( VOUT )
100 sq mm 2500 sq mm 2500 sq mm

For the DFN package, the thermal resistance junction-to-

62C/W

D
RL
=
(15V 8V )(8V ) = 0.280W
200
This causes the LT1010 junction temperature to rise another
(0.280W)(100C/W) = 28C.
This heats the junction to 64.4C + 28C = 92.4C.
An example of 1MHz operation further shows the limita-
tions of the N (or miniDIP) package. For 15V operation:
PD at IL = 0 at 1MHz* = (10mA)(30V) = 0.30W
This power dissipation causes the junction to heat from
50C (ambient in this example) to 50C + (0.3W)(100C/W)
= 80C. Driving 2VRMS of 1MHz signal into a 200 load
causes an additional
case (JC), measured at the Exposed Pad on the back of
the die, is 7.5C/W.
Continuous operation at the maximum supply voltage
and maximum load current is not practical due to thermal
limitations. Transient operation at the maximum supply
is possible. The approximate thermal time constant for a
2500sq mm 3/32" FR-4 board with maximum topside and
backside area for one ounce copper is 3 seconds. This
time constant will increase as more thermal mass is added
(i.e., vias, larger board and other components).
For an application with transient high power peaks, average
power dissipation can be used for junction temperature
calculations as long as the pulse period is significantly less
than the thermal time constant of the device and board.
*See Supply Current vs Frequency graph.

2V
PD = (15 2) = 0.130W
200

to be dissipated, resulting in another (0.130W)(100C/W)

= 13C rise in junction temperature to 80C + 13C = 93C.

1010fe

15
LT1010
SCHEMATIC DIAGRAM (Excluding protection circuits)
R6
15
V+
R7 R10
Q11 Q18
300 200
R5
BIAS
1.5k
Q17 Q19

Q5 R2 R3 R4 R11
1k 1k 1k 200
C1 Q20
30pF
Q6 Q7 R12
Q8 Q21 R14
3k 7
Q3 Q12 R8 OUTPUT
1k
Q2 Q15
R13
Q4 Q13 200
Q22

Q1 R1 Q9 Q10 Q14 R9 Q16 INPUT

4k 4k
V
1010 SD

DEFINITION OF TERMS
Output Offset Voltage: The output voltage measured with Saturation Resistance: The ratio of the change in output
the input grounded (split supply operation). saturation voltage to the change in current producing it,
going from no load to full load.*
Input Bias Current: The current out of the input terminal.
Slew Rate: The average time rate of change of output
Large-Signal Voltage Gain: The ratio of the output volt-
voltage over the specified output range with an input step
age change to the input voltage change over the specified
between the specified limits.
input voltage range.*
Bias Terminal Voltage: The voltage between the bias
Output Resistance: The ratio of the change in output volt-
terminal and V+.
age to the change in load current producing it.*
Supply Current: The current at either supply terminal with
Output Saturation Voltage: The voltage between the
no output loading.
output and the supply rail at the limit of the output swing
*Pulse measurements (~1ms) as required to minimize thermal effects.
toward that rail.
Saturation Offset Voltage: The output saturation voltage
with no load.

1010fe

16
 LT1010
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)

0.70 0.05

3.5 0.05 1.65 0.05

2.10 0.05 (2 SIDES)

PACKAGE
OUTLINE

0.25 0.05
0.50
BSC
2.38 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED R = 0.125 0.40 0.10
TYP
5 8

3.00 0.10 1.65 0.10

(4 SIDES) (2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD8) DFN 0509 REV C

4 1
0.200 REF 0.75 0.05 0.25 0.05
0.50 BSC
2.38 0.10
0.00 0.05 BOTTOM VIEWEXPOSED PAD

NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE

1010fe

17
LT1010
PACKAGE DESCRIPTION
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)

.400*
(10.160)
.300 .325 .045 .065 .130 .005 MAX
(7.620 8.255) (1.143 1.651) (3.302 0.127)
8 7 6 5

.065
.255 .015*
(1.651)
.008 .015 TYP (6.477 0.381)
(0.203 0.381) .120
(3.048) .020
+.035 MIN (0.508) 1 2 3 4
.325 .015
MIN

( )
.100 .018 .003 N8 1002
+0.889 (2.54)
8.255 (0.457 0.076)
0.381
BSC
NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

T Package
5-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1421)

.147 .155 .165 .180

.390 .415 (3.734 3.937) (4.191 4.572) .045 .055
(9.906 10.541) DIA (1.143 1.397)

.230 .270
(5.842 6.858)
.570 .620
.620
.460 .500 (14.478 15.748)
(15.75)
(11.684 12.700) TYP
.330 .370
.700 .728
(8.382 9.398)
(17.78 18.491)

.095 .115
SEATING PLANE
(2.413 2.921)
.152 .202
.260 .320 (3.861 5.131) .155 .195*
(6.60 8.13) (3.937 4.953)

.013 .023
(0.330 0.584)
.067
BSC .028 .038 .135 .165
(1.70)
(0.711 0.965) (3.429 4.191) * MEASURED AT THE SEATING PLANE
T5 (TO-220) 0801

1010fe

18
 LT1010
REVISION HISTORY (Revision history begins at Rev E)

REV DATE DESCRIPTION PAGE NUMBER

E 5/11 Revised temperature ranges and values in Absolute Maximum Ratings and Pin Configuration sections 2
Revised Notes 2 and 4 in Electrical Characteristics section 3
Updated temperature values in Power Dissipation, Thermal Considerations for the MiniDIP Package, and Thermal 8, 15
Resistance of DFN Package sections of the Applications Information section

1010fe

19
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT1010
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1206 250mA, 60MHz Current Feedback Amplifier 900V/s, Excellent Video Characteristics
LT1210 1.1A, 35MHz Current Feedback Amplifier 900V/s Slew Rate, Stable with Large Capacitive Loads
LT1795 Dual 500mA, 50MHz CFA 500mA IOUT ADSL Driver
LT1886 Dual 700MHz, 200mA Op Amp DSL Driver

1010fe

20 Linear Technology Corporation

LT 0511 REV E PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 1991