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II Year II SEM
LAB MANUAL
II Year II SEM
DEPARTMENT
OF
ELECTRONICS & COMMUNICATION ENGINEERING
LABORATORY PRACTICE
I HEAR, I FORGET
I SEE, I REMEMBER
I DO, I UNDERSTAND
Auroras Technological and Research Institute CO Lab Manual
PART - II
Code of Conduct 4
General instructions 5
List of experiments 7
Common Emitter Amplifier 8
Common Source Amplifier 16
Two Stage RC Coupled Amplifier 23
Current shunt and voltage series Feedback Amplifier 29
Cascode amplifier 32
Wein Bridge Oscillator using transistors 36
RC Phase Shift Oscillator using transistors 40
Class A Power Amplifier (Transformer Less) 44
Class B Complementary Symmetry Amplifier 50
Common base (BJT)/common gate (JFET) amplifier 52
HARDWARE
Transformer Coupled Class A Power Amplifier 54
Class C Power amplifier 60
Single Tuned Voltage Amplifier 64
Hartley Oscillator 69
Darlington Pair Amplifier 73
MOS common source Amplifier 75
Auroras Technological and Research Institute CO Lab Manual
Auroras Technological and Research Institute CO Lab Manual
All students must observe the Dress Code while in the laboratory.
All students are liable for any damage to equipment due to their own negligence.
All equipment, apparatus, tools and components must be RETURNED to their original
place after use.
Students are strictly PROHIBITED from taking out any items from the laboratory.
Students are NOT allowed to work alone in the laboratory without the Lab Supervisor
It is important that the experiments are done according to the timetable and completed within the
scheduled time.
You should complete the prelab work in advance and utilize the laboratory time for verification
only.
The aim of these exercises is to develop your ability to understand, analyze and test them in the
laboratory.
A member of staff and a Lab assistant will be available during scheduled laboratory sessions to
provide assistance.
Always attempt experiments; first without seeking help.
When you get into difficulty; ask for assistance.
Assessment
The laboratory work of a student will be evaluated continuously during the semester for 25 marks.
Of the 25 marks, 15 marks will be awarded for day-to-day work. For each experiment marks are
awarded under three heads:
Lab Reports
Note that, although students are encouraged to collaborate during lab, each must individually
prepare a report and submit.
They must be organized, neat and legible.
Your report should be complete, thorough, understandable and literate.
You should include a well-drawn and labeled engineering schematic for each circuit investigated
Your reports should follow the prescribed format, to give your report structure and to make sure that
you address all of the important points.
Graphics requiring- drawn straight lines should be done with a straight edge. Well drawn free-hand
sketches are permissible for schematics.
Space must be provided in the flow of your discussion for any tables or figures. Do not collect
figures and drawings in a single appendix at the end of the report.
Reports should be submitted within one week after completing a scheduled lab session.
Presentation
Experimental facts should always be given in the past tense.
Discussions or remarks about the presentation of data should mainly be in the present tense.
Discussion of results can be in both the present and past tenses, shifting back and forth from
experimental facts to the presentation.
Any specific conclusions or deductions should be expressed in the past tense.
Report Format
Lab write ups should consist of the following sections:
Abstract: A concise statement describing the experiment and the results. This is usually not more
than 3 sentences. Since the abstract is a summary of what you have done, its a good idea to write
this last.
Introduction: Several paragraphs that explain the motivation of the experiment. Usually in this
statement you state what you intent to accomplish as well as the expected results of the experiment.
Equipment and Components: Describe what equipment and components you used to conduct the
experiment.
Results and Analysis: This is the main body of the report. Graphs, tables, schematics, diagrams
should all be included and explained. Results of any calculations should be explained and shown.
State the results of the experiment. Include any problems encountered.
Conclusion: Explain how the experiment went, and whether you were able to achieve the expected
results stated in the introduction.
Auroras Technological and Research Institute CO Lab Manual
(Hardware)
List of Experiments
EXPERIMENT NO. 1
REALIZATION OF LOGIC GATES
AIM: To verify the truth tables of OR, AND, NOT, NAND, NOR and X-OR gates.
APPARATUS:
1. OR gate - IC 7432
2. AND gate - IC 7408
3. X-OR gate - IC 7486
4. NAND gate - IC 7400
5. NOR gate - IC 7402
6. NOT gate - IC 7404
7. Bread board trainer kit.
8. Patch cords.
CIRCUIT DIAGRAM:
AND GATE:
SYMBOL: PIN DIAGRAM TRUTH TATABLE:
NAND GATE:
SYMBOL: PIN DIAGRAM: TRUTH TABLE:
Auroras Technological and Research Institute CO Lab Manual
NOR GATE:
SYMBOL: PIN DIAGRAM: TRUTH TABLE:
INPUT OUTPUT
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
NOT GATE:
SYMBOL: PIN DIAGRAM: TRUTH TABLE:
EX-OR GATE:
SYMBOL : PIN DIAGRAM: TRUTH TABLE:
INPUT OUTPUT
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
Auroras Technological and Research Institute CO Lab Manual
PROCEDURE:
RESULT:
Truth tables of AND, OR, NOR, NAND, NOR and X-OR gates are verified.
Auroras Technological and Research Institute CO Lab Manual
EXPERIMENT NO. 2
DESIGN A FULL ADDER USING GATES
AIM: To verify the operation of Full adder using IC 7408,IC 7486,IC 7432.
APPARATUS:
1. IC 7408 - 2no.
2. IC 7486 - 2no.
3. IC 7432 - 1no.
3. Bread board IC trainer kit.
4. Connecting wires.
5. Patch chords
CIRCUIT DIAGRAM:
TRUTH TABLE:
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
Auroras Technological and Research Institute CO Lab Manual
1 1 1 1 1
THEORY:
When two binary numbers have to be added, it is not sufficient if only two bits are
added. One would get the carry from the lesser significant position (except while adding
the LSBs). This carry also has to be added. One should therefore, have a circuit that adds
three bits. A half adder is not sufficient for this purpose and so we use an adder known as
Full adder. The expression for sum and carry are given as
SUM =
CARRY=
PROCEDURE:
PRECAUTIONS:
RESULT:
EXPERIMENT NO. 3
(A) 8 x 1 MULTIPLEXER
AIM: To verify the operation of 8*1 multiplexer using IC 74151.
APPARATUS:
1. IC74151 -1 no.
2. Bread board IC trainer kit.
3. Patch cords.
4. Connecting wires.
PROCEDURE:
RESULT:
EXPERIMENT NO. 4
DESIGN AND IMPLEMENT A 3 to 8 DECODER USING GATES
APPARATUS:
1. IC 74138.
2. Bread board trainer kit
3. Patch cords
4. Connecting wires.
Truth Table:
Auroras Technological and Research Institute CO Lab Manual
PROCEDURE:
1. Connect the circuit as shown in the figure.
2. Apply Vcc=+5v to the Pin-16 of IC 74138.
3. Connect the inputs to Pins-1, 2&3.
4. Pins-4, 5, 6 are the enable inputs.
5. When E11 is high and E21 ,E3 are low then all the outputs are high irrespective of
inputs A0 ,A1 ,A2 .
6. Similarly when E21is high, all the outputs are high irrespective of the inputs.
7. When E3 is low all the outputs are high irrespective of E11 and E21 and high.
8. If E11 and E21 are low and E31 is high, the inputs are low, the outputs O01 will be
low with all the other outputs are low.
9. Similarly by changing the inputs we get (one) 1 output as low and all other
outputs as high.
10. When all inputs are high O71 will be low and all other will be high.
EXPERIMENT NO. 5
Design A 4-BIT COMPARATOR USING GATES /ICs
APPARATUS:
1. IC 7485.
2. Bread board IC trainer kit.
3. Patch cords.
FUNCTION TABLE:
PROCEDURE:
1. Connect the circuit as per Pin diagram.
2. Give the inputs A [A3 ,A2, A1, A0] and B [B3,B2,B1,B0] according to function table.
3. Give the cascaded inputs IA>B ,IA=B ,IA<B and verify the outputs.
4. Tabulate the inputs and outputs according to function table.
RESULT:
EXPERIMENT NO. 6
APPARATUS:
1. Bread board.
2. IC 7495.
3. Patch cords.
4. Connecting wires.
PIN DIAGRAM:
Auroras Technological and Research Institute CO Lab Manual
CIRCUIT DIAGRAM:
THEORY:
A shift register is an n-bit register with a provision for shifting its stored data by one
bit position at each tick of the clock. The serial input, SERIN, specifies a new bit to be
shifted into one end at each clock tick. This bit appears at the serial output, SEROUT, after
n clock ticks, and is lost one tick later. Thus, an n-bit serial-in, serial-out shift register can
be used to delay a signal by n clock ticks.
A serial-in, parallel-out shift register has outputs for all of its stored bits, making
them available to other circuits. Such a shift register can be used to perform serial-to-
parallel conversion.
Conversely, it is possible to build a parallel-in, serial-out shift register. At each clock
tick the register either loads new data from inputs 1D-ND or it shifts its current contents,
depending on the value of the LOAD/SHIFT control input. The device uses a 2-input
multiplexer on each flip-flops D input to select between the two cases. A parallel-in, serial-
out shift register can be used to perform parallel-to-serial conversion.
By providing outputs for all of the stored bits in a parallel-in shift register, we
obtain the parallel-in, parallel-out shift register. Such a device is general enough to be used
in any of the applications of the previous shift registers.
Auroras Technological and Research Institute CO Lab Manual
PROCEDURE:
1. Mount the IC 7495 on logic trainer and make the required connections.
2. Connect pins-2, 3, 4, 5 of the IC to logic switches SW1, SW2, SW3 and SW4 for
applying low and high logic levels at this input.
3. The serial input is given to pin-1 and mode control to pin-6.
4. Pins-8 and 9 are shorted and connected to clock pulse.
5. Connect Vcc=+5v to pin-14.
6. Pin-7 is grounded.
Clearing Function:
1. After the register has been cleared, any 4-bit serial number can be loaded into
the register.
2. Set mode control switch to low.
3. Set the serial input to high.
4. Apply a clock pulse which will shift the serial input 1 into the register, in this
case QA is 1.
5. Return serial input switch SW3 to low and apply three clock pulses. The register
will show an output of 00001.
We can load any 4-bit number into the register in this way.
3. As you apply clk pulse, the word will be shifted out serially from QD and after
four clock pulses the register will be cleared.
PRECAUTIONS:
VIVA QUESTIONS:
1. What is a register?
2. What is a shift register?
3. What are the operations performed by a shift register?
4. Applications of SISO shift register.
5. Applications of PISO shift register.
6. Applications of SIPO shift register.
7. Applications of PIPO shift register.
8. What is the IC package?
9. What is a universal shift register?
10. What are the operations performed by a universal shift register?
11. Applications of SISO universal shift register.
12. Applications of PISO universal shift register.
13. Applications of SIPO universal shift register.
14. Applications of PIPO universal shift register.
15. What is the IC package?
16. Difference b/w shift register and universal shift register.
RESULT:
EXPERIMENT NO. 7
APPARATUS:
1. IC 7490
2. Bread board IC trainer kit.
3. Connecting wires.
4. Patch cords.
Decimal
QD QC QB QA Equivalent
output
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
Auroras Technological and Research Institute CO Lab Manual
PROCEDURE:
1. Connect the circuit as shown in the figure.
2. The clock pulse is given to pin-14 of IC 7490.
3. The Vcc supply is given to pin-5 of IC 7490.
4. Pin-12 and pin-1 to be shorted.
5. Pins-2, 3 are Master Reset (MR) inputs and pins-6, 7 are Master Set (MS) inputs.
6. Pins-13, 14 has no connections.
7. Pins-2, 3, 6, 7 are inputs and is always 0.
8. Pins-12, 9,8,11 are outputs.
9. Feed MR terminal with 1 and MS terminals with 0 then the display shows 0.
10. Feed MR terminal with 0 and MS terminals with 1 then the display shows 9.
11. Feed MR terminal with 0 and MS terminals with 0,now apply clock then the
output varies between the values 0 and 9.
RESULT: