Department of EEE

ASSIGNMENT - 3

Prepared For- Tahseen kamal

Lecturer,
Dept. of Electrical & Electronic Engineering
East West University

Prepared by-
Student Name: SANIUL ISLAM
Student ID: 2006-3-80-004
Department of EEE
East West University

Date of submission : 15-04-2009

4.22:

The main logic elements/gates in a ROM chip are decoder and OR gates.

4.23:

Fig: Block Diagram of 16 X 4 ROM that will increment a 4bit unsigned number.

Truth table:

OE INPUT OUTPUT
E A3 A2 A1 A0 Z3 Z2 Z1 Z0
1 0 0 0 0 0 0 0 1
1 0 0 0 1 0 0 1 0
1 0 0 1 0 0 0 1 1
1 0 0 1 1 0 1 0 0
1 0 1 0 0 0 1 0 1
1 0 1 0 1 0 1 1 0
1 0 1 1 0 0 1 1 1
1 0 1 1 1 1 0 0 0
1 1 0 0 0 1 0 0 1
1 1 0 0 1 1 0 1 0
1 1 0 1 0 1 0 1 1
1 1 0 1 1 1 1 0 0
1 1 1 0 0 1 1 0 1
1 1 1 0 1 1 1 1 0
1 1 1 1 0 1 1 1 1
1 1 1 1 1 0 0 0 0
4.24:

Programmable Array Logic (PAL) and Programmable Logic Array (PLA) are the same thing.
Both PLA and PAL has array of and, or gates with programmable interconnects.
The difference is PLA has both AND and OR gates in programmable format whereas PAL has
only and gates programmable i.e.: OR gates are fixed.

A Programmable Read Only Memory (PROM) is a special kind of computer memory chip. An
EPROM is an array of columns and rows.

Programmable electrically erasable logic (PEEL) devices are available for instant reprogramming
just like an EPROM.

4.25:

EPROM

An EPROM is an array of columns and rows. Each intersection is called a cell and each cell has a
floating gate transistor and a control gate transistor. These two transistors are separated by a fine
oxide layer.

The floating gate is connected to the grid row (wordline) through the control gate. The cell's value
is 1 if the floating gate's connection to the wordline through the control gate exists. All cells of a
blank EPROM have a value of 1.

To configure an EPROM chip, we need to change certain cells from 1 to 0. The cell value 0 is
attained if the connection between the floating gate transistor and the wordline is removed. This is
done through a process known as Fowler-Nordheim tunneling.

To accomplish tunneling, a charge of electricity, typically 10-13 volts, is passed through the
column (bitline). This electric charge proceeds to the floating gate. In reaction, the floating gate
releases electrons which are in turn trapped on the oxide layer. The electric charge, in effect,
rearranges the floating gate's electron configuration. The excited electrons become a barrier
between the floating gate and the control gate. The link between the control gate and the wordline
is subsequently eliminated and the cell's value changes from 1 to 0.

EEPROM

The EEPROM chip is physically similar to the EPROM chip. It is also composed of cells with
two transistors. The floating gate is separated from the control gate by a thin oxide layer. Unlike
the EPROM chip, however, the EEPROM chip's oxide layer is much thinner. In EEPROM chips,
the insulating layer is only around 1 nanometer thick whereas in EPROM chips, the oxide layer is
around 3 nanometers thick. The thinner oxide layer means lower voltage requirements for
initiating changes in cell value.

Tunneling the electrons of the floating gate towards the oxide layer separating the floating gate
and the control gate is still the method of changing a bit's value from 1 to 0. To erase EEPROM
programming, the electron barrier still has to be overcome by the application of enough
programming voltage.
4.27:

Fig: 4 bit adder/subtractor

4.28:
5.12:

Advantage of Master slave flip-flop:

The master-slave configuration has the advantage of being edge-triggered, making it easier
to use in larger circuits, since the inputs to a flip-flop often depend on the state of its
output.

An advantage of the some aspects of the invention is to provide a master-slave type flip-
flop circuit made to plan reduction in power consumption and EMI in the case of being
realized with a gate array.

5.15

DA =B ⊕x
DB = DA
Y = DB

State Table:

Present State Input Next State FF Input Output

A B x An+1 Bn+1 DA DB Y
0 0 0 0 0 0 0 1
0 0 1 1 1 1 1 0
0 1 0 1 1 1 1 0
0 1 1 0 0 0 0 1
1 0 0 0 0 0 0 1
1 0 1 1 1 1 1 0
1 1 0 1 1 1 1 0
1 1 1 0 0 0 0 1

Reduce Table:

Present State Next State FF Input Output

x=0 x =1 x=0 x=1 x=0 x=1
A B
An+1 Bn+1 An+1 Bn+1 DA DB DA DB Y Y
0 0 0 0 1 1 0 0 1 1 1 0
0 1 1 1 0 0 1 1 0 0 0 1
1 0 0 0 1 1 0 0 1 1 1 0
1 1 1 1 0 0 1 1 0 0 0 1

State Diagram:
5.18

DA = B + x
DB = DA
Y = DB. D B = 0

State Table:

Present State Input Next State FF Input Output

A B x An+1 Bn+1 DA DB Y
0 0 0 1 1 1 1 0
0 0 1 1 1 1 1 0
0 1 0 0 0 0 0 0
0 1 1 1 1 1 1 0
1 0 0 1 1 1 1 0
1 0 1 1 1 1 1 0
1 1 0 0 0 0 0 0
1 1 1 1 1 1 1 0

Reduce Table:

Present State Next State FF Input Output

x=0 x=1 x=0 x=1 x=0 x=1
A B
An+1 Bn+1 An+1 Bn+1 DA DB DA DB Y Y
0 0 1 1 1 1 1 1 1 1 0 0
0 1 0 0 1 1 0 0 1 1 0 0
1 0 1 1 1 1 1 1 1 1 0 0
1 1 0 0 1 1 0 0 1 1 0 0

State Diagram:
5.16

Da = abx +ab
Db = xb +xb = x ⊕b
y = b x +a

State Table:

Present State Input Next State FF Input Output

a b x An+1 Bn+1 DA DB Y
0 0 0 0 0 0 0 1
0 0 1 0 1 0 1 0
0 1 0 1 1 1 1 0
0 1 1 1 0 1 0 0
1 0 0 0 0 0 0 1
1 0 1 1 1 1 1 1
1 1 0 0 1 0 1 1
1 1 1 0 0 0 0 1

Reduce Table:

Present State Next State FF Input Output

x=0 x=1 x=0 x=1 x=0 x=1
a b
An+1 Bn+1 An+1 Bn+1 DA DB DA DB Y Y
0 0 0 0 0 1 0 0 0 1 1 0
0 1 1 1 1 0 1 1 1 0 0 0
1 0 0 0 1 1 0 0 1 1 1 1
1 1 0 1 0 0 0 1 0 0 1 1

State Diagram:
Logic Diagram:
http://www.falstad.com/circuit/e-masterslaveff.html

http://www.freshpatents.com/-dt20090101ptan20090002044.php?type=description

http://www.tech-faq.com/eeprom.shtml

http://www.vlsibank.com/sessionspage.asp?titl_id=3438