Chandigarh University

B.E. (Electronics and Communication)

Semester 8th
ECT422-: Digital System Design

Time: 3hours Max.Marks:60

Answer six Questions only

Question Number one is Compulsory
Answer not more than two Questions from each of the sections B, C & D

SECTION A
(Compulsory Question)

Q1. (a)What is the significant of Hardware Description Language?

(b)What are the various operator used in VHDL?
(c)With the block diagram differentiate between ROM and PLA.
(d)Give example of two dimensional array in VHDL.
(e)Create the architecture block for the 3-inlut XOR gate add a 25ns inertial delay to the XOR
assignment statement
(5 x 2 = 10)
SECTION B
Q2. With examples differentiate between data flow and behavioral style of circuit modeling in VHDL.
. (10)
Q3. Write a VHDL code for negative edge triggered JK flip-flop having preset, and clear signal also
in the design. (10)
Q4. Discus all possible data types in VHDL with the help of example for each data type (10)
.
SECTION C
Q5. Differentiate between procedure and functions, with suitable example. (10)
Q6. Design a MOD 10 counter. Implement this counter using VHDL code. The counter should change
its state with rising edge of the clock. This clock also has an active low asynchronous clear input.
(10)
Q7. Implement the CPU of a basic computer using VHDL. This CPU is to perform at least arithmetic
and logical functions on an 8 bit data? (10)

SECTION D
Q8. What are programmable logic devices? Explain architecture of a general FPGA. (10)
Q9. Implement the CPU of a basic computer using VHDL. This CPU is to perform at least arithmetic
and logical functions on an 8 bit data? (10)
Q10.a. Differentiate between FPGA and CPLD in context of architecture details? (5)

10.b. Explain the difference between a ROM and PLA and discuss the PLA implementation with the
help of suitable examples. (5)