Wikibooks CDR

Contents
Articles
Clock and data recovery 1
Clock and data recovery/Introduction 2
Clock and data recovery/Introduction/Definition of (phase) jitter 3
Clock and data recovery/Introduction/Jitter is far from sinusoidal.. 6
Clock and data recovery/Introduction/Models can only be linear.. 7
Clock and data recovery/Introduction/Acquisition, tracking and jitter performances 10
Clock and data recovery/Buffer Memory (Elastic Buffer) 12
Clock and data recovery/Buffer Memory (Elastic Buffer)/Clock domains 14
Clock and data recovery/Buffer Memory (Elastic Buffer)/Overflow and Underflow 16
Clock and data recovery/Buffer Memory (Elastic Buffer)/Transit delay inside the elastic buffer 17
Clock and data recovery/Structures and types of CDRs 18
Clock and data recovery/Structures and types of CDRs/The CDR phase comparator 21
Clock and data recovery/Structures and types of CDRs/Examples 27
Clock and data recovery/Structures and types of CDRs/The jitter tolerance function 40
Clock and data recovery/Structures and types of CDRs/The (slave) CDR based on a second order
PLL 42
PLL/The jitter transfer function 45
PLL/The error function 46
PLL/The jitter tolerance function 48
PLL/The unit step response 51
PLL/The jitter transfer and tolerance of two cascaded CDRs 52
Clock and data recovery/Design values used in practice 54
Clock and data recovery/Design values used in practice/Continuous transmission mode 55
Clock and data recovery/Design values used in practice/Burst transmission mode 57
Clock and data recovery/Design values used in practice/Burst transmission mode/Step response of
a phase aligner 58
Clock and data recovery/Miscellanea 63
Clock and data recovery/Conclusion 71
References
Article Sources and Contributors 73
Image Sources, Licenses and Contributors 74
Article Licenses
License 76
Clock and data recovery 1
Clock and data recovery

This is a reference textbook for readers that desire to
complete and to render systematic their knowledge on
this subject.
This book provides the electronic engineer with the

knowledge of:
- what the CDR function and structure are
- where a CDR is used in a communication

network
- the mathematical models (just two!) needed to

understand the CDR operation (no matter how
complex its actual implementation is!).
Prior knowledge of calculus, and at least some

experience with Fourier and Laplace transforms, are
required.
• Introduction
• Definition of (phase) jitter
• Jitter is far from sinusoidal..
• Models can only be linear..
• Acquisition, tracking and jitter performances
• Buffer Memory (Elastic Buffer)
• Clock domains
• Overflow and Underflow
• Transit delay inside the elastic buffer
• Structures and types of CDRs
• The CDR phase comparator
• Examples
• The jitter tolerance function
• The (slave) CDR based on a second order PLL
• The jitter transfer function
• The error function
• The jitter tolerance function
• The unit step response
• The jitter transfer and tolerance of two cascaded CDRs
• Design values used in practice
• Continuous transmission mode
• Burst transmission mode
• Step response of a phase aligner
• Miscellanea
• Conclusion
Clock and data recovery/Introduction 2
Clock and data recovery/Introduction

Introduction - Timing in serial data transmission
To transmit digital information along distances longer than the internal bus of a computer, it is necessary to serialise
it encoding together the bit stream and its clock.
The resulting signal, during its journey, is less affected by the noise and by the transfer function of the transmission
medium.
The data signal and its clock travel together and experience the very same delay.
At the receiving end, the signal is equalised and the noise filtered out as much as possible. Then the timing
information is extracted, and the bit stream regenerated.
The action of recuperating the clock signal from the received signal is inevitably affected by some deterioration: the
square wave extracted is not exactly synchronous with the transmit clock. Timing information, that is essentially
carried by the level transitions of the received signal, has been affected by the noise and by the intersymbol
interference and has acquired:
• some inevitable delay, due to the physical transit time, and to the extraction process,
• some inaccuracy (= phase modulation, called jitter)
• some errored bits with a (very) low probability, or –in other words- a bit error rate of very low value (e.g. < 10⁻¹⁹)
The jitter can be kept to a minimum with sophisticated clock extraction circuits, but not eliminated. On the other
hand, in the network topology there are always points where signals that had been originated by the same clock and
have cumulated different jitters along different transmission paths, must be put together again. To absorb the jitter
differences an elastic buffer (i.e. a buffer memory) is used.
Note: a serialised transmission, with clock and data encoded together, becomes necessary when the bit rate
and the wavelength at the bit rate frequency become comparable (when different paths travelled by parallel
streams can be different by 25% or more of a wavelength).
For example: at 1 Gbps the wavelength to refer to is:
c/(1 GHz) = 3 * 10^8 m/s / 10^9 sec-1 = 30 cm.
Considering that on PCB the speed is 60% lower than in vacuum, the reference distance is 60% of 30 cm, or
about 20 cm. As a result, serial encoded transmission @ 1 Gbps becomes necessary when distance differences
amongst parallel paths are 5 cm or more.
The delay difference amongst different parallel paths causes bits, that have been sent at the same instant on
different paths, to be received at different clock cycles of the clock at the receiving end. To put them back in
sync, it is necessary to insert redundant bits inside each path, so that a frame sync can be detected. Then
buffer memories on each path will be used to put back in sync all the bits of the parallel paths. Interfaces with
this structure have been proposed, and are in use in some systems.
In most practical applications though, the approach of serialising several parallel streams of bits (typically 8),
with the multiplication of the clock frequency, has been found to be preferable to the alternative approach of
adding the sync structure on each bit stream at the transmit end and to recover that, with use of buffer
memories, at the receive end.
Clock and data recovery/Introduction/Definition

of (phase) jitter
Definition of (phase) jitter
Although the term jitter, strictly speaking, can be applied to several properties of a signal, most often it refers to the
phase of the signal.
In this book it always means jitter of the signal phase, only.
Eye diagram
On the screen of an oscilloscope, triggering the display with the clock signal, it is possible to display such clock and
an NRZ data stream associated with it.
Signals on the scope
The subsequent traces of the data waveform trace different patterns, owing to the random nature of the source data.
Note that the physical limitation of slew rate and of signal bandwidth reduce the slope and smooth the corners of the
signal transitions.
The presence of noise, of intersymbol interference and of various types of distortions, that affect any real
transmission, make the individual traces spread out and differ from each other.
In practice, the pattern of a train of “eyes”, the "eye pattern" will appear on the scope.
Why call it an "eye" diagram?
During the signal transmission, noise, intersymbol interference, channel non linearities and jitter are added to the
signal.
The eye diagram at the receiving end (using the original, un-jittered clock to trigger the scope) shows a closing eye.
The closing eye corresponds in fact to a signal that is less easily detected (= less “visible”).
When the data stream is a coded multilevel signal, the diagram shows a stack of eyes.
3-level eye diagram
Relative phase
The received signal can be strongly amplified and then limited, so that , as a result, it switches rapidly between two
opposite levels.
The time position of its abrupt level transitions still betray the analog and imperfect nature of the signal.
In the signal, the transitions through the mid-level amplitude carry the timing information.
The positions of the level transitions move continuously back and forth in an irregular, almost nervous, manner (=
they jitter).
If the vibration reaches as far as the middle point before the next transition (= the center of the eye diagram), the bit
level in the received signal may be falsely detected (= errored bit).
Jitter (and wander) definition

For a precise mathematical definition of the jitter, the first step is to clearly define the reference.
The instantaneous phase of the signal originated by the transmit clock (= that is the phase of the transmit clock
itself) is the reference, and it is represented by t.
Any further processing of the signal will add a fixed delay d plus a small, irregularly variable (= jittery) contribution
to the signal phase, that will become then: t + d + j(t).
The jitter j(t) is the part additional to the phase of the original signal and to the transit delay.
The reference frequency of the signal is (radian/second).
0
A periodic signal (the shape is not important) is defined as:
p( t)
0
where 0 is a constant. In other words, t can be viewed as the output phase of an ideal, noiseless and drift less
0
oscillator of angular frequency 0.
A signal of the type:
p( t + x(t))
0
where x(t) is in radian, represents an angular phase and describes a deviation from the perfectly linear phase increase
t, is a jittered version of p( 0t), and x(t) is the jitter.
0
The jitter added to the (otherwise linear) phase of a constant frequency signal
In some practical cases it is useful to distinguish between the AC part of x(t) – and call it jitter in a restricted sense -
from its very low frequency components – and call that wander -.
The wander part of the jitter is made up by the low frequency (or truly DC, which is nothing but a frequency drift)
components.
More precisely, the wander components are the low frequency ones that impact in the topic under study only with
unidirectional, slow but large, deviations. During the duration of the phenomenon being studied, the drift
components last less than one half cycle at their frequency (their period is more than twice the interval of time being
considered).
The jitter proper is made by the components relevant to the topic under study as periodic functions of time (or as
functions of j ).
A slow, large deviation of the signal phase from 0t would be seen on the scope as a drift of the eye diagram to the left
(negative phase variation) or to the right (positive phase variation).
The eye drift of a real signal, although slow, exhibits in practice the same random behavior of the jitter in general.
This drifting sometimes to the right, sometimes to the left, is called wander.
Clock and data recovery/Introduction/Jitter is far

from sinusoidal..
It should be noted that the study of the CDR system frequency responses (that is the functions that have j as the
independent variable) gives us in actuality a representation of the CDR behaviour in the presence of sinusoidal jitter.
Some periodicity in the bit stream due to framing, or to periodic data patterns, may induce -via intersymbol
interference- periodic components of jitter, but the real jitter will be essentially noisy.
On the other hand, sinusoidal jitter represents the worst case jitter with respect to jitter tolerance and jiiter transfer is
best described by the jitter transfer function.
Therefore sinusoidal jitter considerations are the most adequate and even give some margin with respect to the
reality of the circuit application.
The use of the CDR system frequency responses, that is the most important tool used in this book, may therefore be
seen as a pretty good and safe tool to describe the CDR behavior.
Clock and data recovery/Introduction/Models can

only be linear..
The reference models
Today' CDR circuits are implemented using a PLL architecture, and are realized mostly or entirely with CMOS
digital circuitry.
The complexity of the circuitry is often so large that -not unfrequently- the architecture is not clearly identified and
consequently the circuit operation is not fully understood.
It is very useful to make reference to relatively simple analog circuits that implement the CDR in a first or second
order PLL architecture.
The comprehension of the characteristics of the model and of the mathematical equations that describe its behaviour
are well suited for the understanding of almost all the actual circuits and not unfrequently even allow a better design
of them.
Mathematical descriptions
Block diagrams can be used to describe a physical system, or its schematic diagram can be used, or the set of
mathematical equations characterizing its parts.
However mathematical models, in the form of systems equations, are needed when detailed relationships are
required.
Every control system may theoretically be characterized by mathematical equations.
The solution of these equations represents the system’s behavior.
Often this solution is difficult if not impossible to find.
In these cases, certain simplifying assumptions must be made in the mathematical description.
Linear models
For a large number of control systems these approximations and simplifications lead to systems describable by linear
ordinary differential equations. Moreover, techniques for solving these equations are well documented in the
literature of mathematics and engineering.
In modern communication systems the implementation of the clock and data recovery circuits (CDR) is primarily
digital, and the circuits can be very complex (in particular the loop filters and the local oscillator).
The designer sometimes may find it difficult to choose the right architecture and also to understand the operation of
the circuit itself in some conditions.
The best way to solve this is to choose a system architecture that corresponds to the structure of a well understood
model of CDR, and to refer to the mathematical description of it to understand the closed loop operation in all
conditions and to actually design the system circuitry blocks.
Not only do these first or second order CDR models offer choice of the best compromises possible between stability
and performance, but they can also be well described mathematically and their operation understood. Once familiar
with their operation, the circuit designer will be able to decide what circuit choices to make, in terms of structure of
the blocks and even of the order of its CDR.
Simulators can include some non-linearities

The formal modeling of systems is based on a mathematical model, which attempts to find analytical solutions
enabling the prediction of the behaviour of the system from a set of parameters and initial conditions.
Computer simulation is often used as an adjunct to, or substitution for, modeling systems for which simple closed
form analytic solutions are not possible, for instance when some strong non-linearities are essential to make a
prediction. This is also the case of the acquisition phase of a CDR.
There are many different types of computer simulation, but the common feature they all share is the attempt to
generate a sample of representative scenarios for a model in which a complete enumeration of all possible states
would be prohibitive or impossible.
To make a good prediction of the acquisition phase of a 1st or 2nd order CDR, a simple simulation program has
been developed.
Some of the figures that follow in this book have been generated using it.
The simulator is based on a spreadsheet. It may be useful for practicing some of the concepts presented in this book.
It can be freely downloaded from Windows Live™ - SkyDrive [1],
and it is also presented in some detail at the end of this book, in: Miscellanea, a simple acquisition simulator.
Just two architectures are of practical use

This book will show a list of possible models, and suggest that the choice is made between just two!
In all practical cases, just either of those two models is the tool needed for a good understanding of the CDR
operation.
Linear, time-invariant idealizations of the CDR circuits will be therefore described here.
The two fundamental cases of:
1. a first order loop for the burst-mode CDR (often, but not always, a phase aligner)
2. a second order loop for the slave CDR
will be presented and emphasized as the only really important models to use. Although such idealizations may not
perfectly describe our circuit in some specific aspects (non-linearity of some circuit blocks, etc.) they serves to
simplify the mathematics, keep us from getting lost in a welter of algebraic quantities, and –most of all- produce
results that can be interpreted quite usefully.
Further on in the book, a section called Structures and types of CDRs/Examples does show the characteristic
functions of these two architectures, as well as the characteristic functions of some other architectures.
The other architectures that are presented in Structures and types of CDRs/Examples are there only for didactical
purposes, but are of no practical use for the electronic engineer.
The two fundamental architectures instead, are further developed in two dedicated sections :
1. first order loop, the burst-mode CDR, at: Design values used in practice/Burst transmission mode
2. second order loop, the slave CDR, at : Structures and types of CDRs/The (slave) CDR based on a second order
PLL .
References
[1] http:/ / cid-a0b14219829a3f6f. skydrive. live. com/ browse. aspx/
PaB%20in%20Windows%20Live%20SkyDrive?authkey=dJjdFK6n*jw%24|
Clock and data

recovery/Introduction/Acquisition, tracking and
jitter performances
Requirements and characteristics
What are, in general, the different requirements of the extraction of the clock from an incoming (encoded) bit
stream?
They are essentially related to two different phases of the CDR operation:
1. Acquisition of the phase lock
2. Tracking of the acquired phase timing once the acquisition is sufficient.
Acquisition
To study the acquisition phase, the best mathematic tool is the unit step response of the loop.
As long as the received signal is not present, the CDR is kept idle by the LOS control signal, which is generated by
the first stages of the receiver, (LOS = Loss Of Signal).
When the LOS is deactivated, the CDR is released and the acquisition phase begins.
The phase of the incoming signal has at that moment (in all practical cases) a random difference from the phase of
the local oscillator of the CDR. The CDR then reacts (like any control system does react) to the abrupt step change
of the input signal.
There are only two CDR architectures of practical use, and the acquisition behaviors of the two are markedly
different.
As we will see, one of the two architectures (the simplest one, called "first order loop of type 1") has the best
acquisition performances.
Its response to an abrupt change of phase (step input), even if combined with a frequency difference between the
timing of the received signal and the free running frequence of the local oscillator (ramp input), is always free from
initial overshhoots.
In fact the phase difference during the acquisition is always a decreasing function and the acquisition transient of this
type of circuit is always free of initial "slips".
There are other CDRs (based on the more sophisticated architecture, called "second order loop of type 1") whose
acquisition is inevitably long and sometimes a series of slips precedes the achievement of a stable acquisition.
Although the presence of slips at the beginning of the acquisition is considered acceptable in some application
(Regenerator CDRs, see here below), it should be restricetd only to cases of real necessity for two reasons:
• it is impossible to model it because of the intrinsic strong non linearities (and therefore it is difficult to have
absolute confidence in it)
• it is really inelegant!
Tracking
Poor tracking: when the input jitter becomes larger, the loop slips twice, then locks-in again.
All CDRs
To study the tracking state, the fundamental characteristic of all CDRs is:
• the ability to operate correctly (that is with a low enough Bit Error Rate = BER) in the presence of a given jitter.
This is called Jitter Tolerance (or Jitter Acceptance), and is often specified as a mask of jitter amplitude versus
jitter frequency. The circuit must operate correctly at any condition defined by a jitter amplitude and a jitter
frquency within the boundary set by the mask. In other words, the locus of the conditions of onset of BER shall be
measured and found above the boundary set by the mask.
and, if the CDRs are intermediate stages in a series of links and resend the regenerated data stream further on,
Regenerator CDRs
two other characteristics are important as well:
• the filtering of jitter frequencies above the frequency range involved in the lock-in and tracking. This is called
Jitter Transfer Function, and there often exists a mask setting an upper limit for the curve that characterises our
circuit (the jitter transfer function is the ratio, at any given frequency, of the amplitude of the jitter at the output to
the amplitude of the jitter at the input).
The presence of a filter block in the 2nd order PLL allows one more degree of design freedom (instead of τ
only, ωn and ζ can be chosen). The 2nd order architecture is used when a particular requirement for jitter
filtering makes the 1st order PLL inadequate. The quantity ωn essentially defines the cut off frequency of the
low pass effect that such PLL has on the incoming jitter.
• the amount of Generated Jitter inside our circuit (phase noise added to the retrieved timing signal). Often
specified as a rms or peak value of the output jitter with zero input jitter.
The ITU-T, in its Recommendations Telecommunication Standardization Sector (ITU-T) [1], is an unvaluable source
of theory and practical knowledge on the subject. It primarily deals with the requirements of large, geographical,
networks, and therefore these Recommendations are especially useful, and exact in their quantitative references, for
the engineer that studies Telecom digital networks, but they can also provide a lot of insight if other fields of
application of CDRs are being targeted.
References
[1] http:/ / www. itu. int/ publications/ sector. aspx?lang=en& sector=2
Clock and data recovery/Buffer Memory (Elastic

Buffer)
Data Buffers [1] in association with CDRs
The CDR function is primarily a layer 1 function, in the sense of the OSI Reference Model[2].
In the scope of CDR applications, a Telecommunication buffer, as in: Wikipedia/Data buffer/Telecommunication
buffer [3] is a hardware device that simply adds a convenient delay to a serial data stream.
The Buffer Memory. (Up to about 20 bits of

memory size, the memory structure can be as
simple as a shift register. Beyond, it is
implemented as a memory bank)
Such buffer, in principle, consists of a R/W memory with circularly sequential addresses, and of two counters.
The write counter times the writing into the memory of an incoming serial flow of information, and the read counter
sets, in turn, the timing of the reading operation.
Clock and data recovery/Buffer Memory (Elastic Buffer) 13
Elastic buffers
If the buffer is meant to absorb delay variations due to the transit along a transmission line (that is: designed to
absorb jitter), then its size in bytes (or in bits) is smaller, the control of the phase relation of the write and of the read
clocks is more accurate, and its name specialises into “elastic buffer”.
An adder compares the content of the two counters.
At the start-up of the system, the write counter is set to 0, and the reading counter is set to half the memory depth. It
is possible to program the initial value of the read counter to less than half the memory depth, to use less than the
entire memory - thereby reducing the transit delay.
In general a buffer memory may be used to absorb delays, or just delay variations (jitter), generated by transmission
over physical media, or by software elaboration, or other types of delays.
Phase aligners
A special case of elastic buffer is the "phase aligner"
The phase aligner is an elastic buffer used inside a single clock domain. It is typically implemented as a
1st order PLL.
A more formal definition, without mention of the operation within a single clock domain, can be:
The phase aligner is a CDR that shifts the phase of the received signal so that it matches the phase of a
reference clock (and then regenerates the aligned signal with that clock).
References
[1] http:/ / en. wikipedia. org/ wiki/ Data_buffer|
[2] http:/ / en. wikipedia. org/ wiki/ OSI_model
[3] http:/ / en. wikipedia. org/ wiki/ Data_buffer

Buffer)/Clock domains
Inside a clock domain all the clocks are locked to a master.
They may jitter with respect to the master and with respect to each other, but they do not drift.
The domain of a master clock
In general, the slave clock needs not run at the same frequency of the master.
There are cases where the frequencies are different (by the ratio of two integer numbers).
When the frequencies differ, since the jitter is measured in radian (i.e. as a fraction of 2 * clock period), the same
jitter amount if measured in time (i.e. seconds) will represent, if measured in radian, an amount of jitter different at
the slave than at the master, by the ratio:
If a slave gets disconnected from its master, a new domain is created.

A slave creates his own domain
If two clocks exhibit a phase difference because they have followed different paths inside the same clock domain, or
because they belong to different clock domains, a buffer memory can be used to compensate that difference.
The figure below illustrates the second case, where, to compensate for the phase difference of two clocks of different
domains, a buffer memory is used at the point of border connection.
A buffer inserted between clock domains


Buffer)/Overflow and Underflow
Overflow and Underflow
Two clocks that differ slightly in frequency (=that wander) with respect to each other, or that jitter significantly with
respect to the one another, will -from time to time- cumulate more phase difference than the buffer can absorb and
abruptly change their respective positions.
The slower clock does “slip” with respect to the other and the period that it loses is a “slip”.
When the reading (reading clock faster than the writing clock) takes place synchronously or before the corresponding
writing cycle, then an underflow occurs (with a repetition of some information elements).
If this condition instead is approached because the reading clock is too slow with respect to the writing clock, then an
overflow occurs (and some information elements are skipped = cancelled).
In case of over/underflow, the reading counter is reinitialised, half a memory behind the write clock (to restart with
the maximum margin against another future occurrence).
A clock signal that has cumulated jitter along a transmission path is re-syncronized with the system clock.
The figure above shows a case where two different clocks (the system clock and its copy after many
regenerations) are to be re-synchronised together. This is not the most general case, because the two clocks
represented here belong to the same clock domain (i.e. are generated from the same clock, apart from fixed
delay and jitter).
If two clocks that do not share a link with a common clock source (=they belong to different clock domains)
and are to be reconciled (by an elastic buffer), then the thing is complicated by the fact that, in addition to
jitter, they exhibit a frequency difference ( a wander), although small.
If an elastic buffer, of depth equal to n clock cycles, is at the boundary between different clock domains of
frequencies f1 and f1-Δf, it will be subject to periodic slips (under or overflows), with a frequency given by:
• 'Deliberate Slips (overflow or underflow execution with minimum inconvenience to the “payload”)
• In some cases, when the incoming data flow is framed, if a slip is inevitable it may be convenient to slip
(cancel or replicate) an entire frame, exactly from beginning to end (e.g. TDM frames of layer 1
synchronization).
• Or, if the incoming data have a layer 2 packet structure, it may be convenient to drop or duplicate
inter-frame idle characters (e.g. Ethernet inter-frame characters). To do so, when the reading clock gets
close (e.g. within +/- 5% of the buffer size) to the writing clock and a slip appears inevitable within a short
time, the decision to slip is taken, but it is put to effect a little later, in coincidence with the start of the next
frame. Obviously, the buffer must be long at least 10% more than one entire frame.
The cost is not significantly different whether the buffer memory is organised by bit or by byte. The saving in
transit time when organising by bit with respect to organising by byte, is not significant either, as the average
delay is expected to be several bytes.

Buffer)/Transit delay inside the elastic buffer
TRANSIT DELAY inside the elastic buffer
The elastic buffer essential function is to add a delay to the information stream that, added to the jittered delay in
the incoming stream, makes the total delay a fixed amount:
• first the additional delay is calculated
• and then it is added.
In this way the clock at the receiving end can be made again synchronous to the clock that originated it (or -more
generally- to a clock that has followed a different path and cumulated a different jitter).
As the figure indicates, the buffer memory (or elastic buffer, that is a more appropriate name in this special case
where the memory accomplishes the task of adding such complementary delay) is a delay line.
The bit stream enters with the transmission line clock obtained after several regenerations, is delayed by the
necessary amount, and gets out with the system clock: the bit stream (and in several cases also the byte or frame
synchronisation) is again perfectly synchronous with the system timings.
In many cases the elastic buffer is written with blocks of bits at every write operation, and discharged by the
same amount of bit at every read operation. In this case the frequency of the write and of the read clock is a
corresponding submultiple of the transmission line clock and of the system clock.
In practice the write and read cycle treat an entire byte or an entire frame at each time. The byte or the frame
sync is embedded in the bit stream by the addition at the transmit end of some redundant bits with a pattern
that be at the same time difficult to simulate by the information bits and easy to recognize at the receive end.
The sync timing is detected at the receive end and can also be used for the write and read operations of the
elastic buffer.
It should also be noted that an elastic buffer is sometimes built by several sections that operate on parallel bit
streams received. One example can be the re-sync of truly parallel streams of bits received from a parallel
interface, another can be the multiple sampling of a received pulse in a serial transmission for subsequent
processing in a DSP.
It is important to understand that, inside the elastic buffer, the information of how much delay the buffer memory
is adding in any given moment is available.
This point may be relevant when –for instance- it is necessary to measure the transmission line length measuring the
transit time. In such case the time spent during the transit throughout the elastic buffer must be deducted.
For instance, in the figure that we have already seen in the previous section, let's consider the delay that the signal
Clock and data recovery/Buffer Memory (Elastic Buffer)/Transit delay inside the elastic buffer 18
suffers along the external loop (with 9 regenerations):
A clock signal that has cumulated jitter along a transmission path is re-syncronized with the system clock.
It is easy to measure the total delay in periods of the system clock at the output of the elestic memory( but it will be
inclusive of the delay added by the elastic buffer). Then the delay of the elastic buffer shall be deducted, and the
transmission delay exactly computed. (In the system of the figure above it would also include the time added by the 9
regenerators!).
Clock and data recovery/Structures and types of

CDRs
At the receiving end of a data transmission link, the received signal is amplified, filtered and equalized. Then a
“slicer” circuit reshapes it and retains just the level transitions and the levels that represent the nominal values of the
received signal in that interval between two consecutive transitions. The CDR functions are to process the “sliced”
signal
• to extract the clock signal embedded in its transitions (clock recovery) and
• to sample and retime the pulses of the “sliced” signal(data recovery).
Clock recover circuits include:
• the phase locked loop architecture (PLL) -- the most common method of clock recovery
• the synchronous oscillator -- less common, but has some advantages over PLL[1]
Many good books are available, with theory and practical examples, like[2] .
It is useful however, in order to get the best out of them, to have the ability to recognize in each case the fundamental
architecture, that is the "Control Systems" model to refer to.
Importance of good reference models

The function of a CDR is a relatively simple one. The architectures possible for it are, accordingly, just a few, simple
ones (actually just two!). It is nonetheless important to have a good knowledge of those architectures and a good
understanding of their mathematical descriptions because these models are the best tools for the engineer that must
deal with CDRs.
Starting from the definition and specification of (a communication system and of its) CDR(s), and all the way
through all the different engineering tasks that logically follow like design, verification, validation, manufacturing
tests, failure analysis, system operation and maintenance, those models can be an invaluable reference for the
engineer. He will need them to imagine, specify, design, check, measure and interpret the behavior of a possible or
of an existing CDR.
The actual implementation of the CDR may differ from the neat, simple analog structure that the mathematical
model depicts. Complex digital blocks, DLLs, DSPs may render the analogy difficult to detect, but the fundamental
signals and operation of the CDR can not differ. Yielding to the temptation of forgetting the models is a very risky
and error prone short cut.
The essential signals and blocks of the model must be clearly identified in the actual system. The use of the reference
model will be the best way to make sure that all aspects of the CDR operation are identified and taken into
consideration.
The CDR is always designed with the architecture of a PLL (with the obvious addition of the regeneration block,
where the received pulses are re-sampled with the local clock). Let’s study the PLL, that is the essential part. It
should be kept in mind that such PLL will be specialized for application inside a CDR.
A PLL in a CDR is of unity feedback, of the first or of the second order and of type 1.
The PLLs inside CDRs are in all cases of the unity feedback kind. The input of the circuit is the phase of a reference
signal (a clock or a serial data signal) and the output is the phase of a signal (a serial data stream or a simple clock).
The output is locked -as much s the circuit can- to the input signal. The input signal is contrasted with the output
signal in a phase comparator, whose output is the error signal. The error signal is processed and then used to control
another circuit block that produces the output signal.
Essential parts of a CDR

It is important to identify the essential parts (listed below) of the CDR system but also to identify where the received
signal and the local clock fit in the architecture. Either one (the received signal or the local clock) may act as input,
while the other would simply act as an internal input signal inside the block called “Controlled element” (the block
that generates the output signal of the PLL).
The received signal acts as reference input for the PLL when the PLL function is to generate a clock slaved to the
received signal itself.
The local clock acts instead as reference signal for the PLL when the PLL function is simply to “phase align” the
received signal to it, in the cases where the received signal timing is derived from the local clock itself (following a
short loop inside a unique clock domain where the local clock is master).
The list of the parts that shall be clearly identified in the CDR are:
1. the phase information (carried by the level transitions) of the received signal
2. the phase information (carried by the level transitions) of the local clock
3. the phase comparator that measures the relative phase of the local clock with respect to the phase of (a signal
related to) the received signal
4. an integration block (1/s in the language of Control Systems) or an accumulator if the implementation is of the
discrete time type. It makes the control loop able to squeeze down to zero the steady state frequency error (and to
a finite, small value the corresponding phase error)
5. the regeneration of (a signal related to) the received signal by the local clock.
Order and type of a CDR

The order of a control loop (causal, linear and time invariant in our models of CDRs) is the order of the differential
equation that describes it.
In the language of control systems, the order is the number of poles of the (open or closed loop) system transfer
function.
• 1st order systems are unconditionally stable, are characterised by one parameter only and are a good model to
represent CDR PLLs that have been deliberately designed with a simple behaviour…….
• 2nd order systems are unconditionally stable, are characterised by two parameters and can be used to model
practically all CDR PLLs for which the 1st order model is too simple.
• 3rd and higher order systems are not of practical use in the study of CDRs. They may be unstable in some
conditions and, moreover, they are more complex to use but do not offer a better behavior for CDR use than the
2nd order systems. ( Some complexity beyond the simple 2nd order system can be useful to model more
accurately some parasitic effects of a CDR circuit, but not to design nor to model performances within the range
of functionality of the CDR).
The type of a control loop is the number of poles at the origin of the open loop transfer function (that is, how many
times the factor 1/s appears in the open loop transfer function).
The type of a loop tells how well the loop itself is able to track a deviation of their input signal from the nominal
value.
It should be reminded that a CDR can operate with a small phase (= sampling time) error without deterioration of
performances, provided the error is small enough (a few degrees of jitter around the optimum sampling time do not
deteriorate significantly the bit error rate!)
• Type 0 systems are able to track a step function ( a phase deviation of the input from the nominal phase expected
by the circuit itself) with a small, but finite error. A type 0 PLL can not track at all a linear ramp of phase
variation in the received signal (that is a step change of the frequency of the received signal with respect to the
frequency of the -free running- local oscillator!). Therefore they are not of large use for CDRs.
• Type 1 systems are able to track signals that exhibit a step change of phase, without steady-state error. They are
not able to track unit ramp inputs without a finite error, though.
Type 1 system are the preferred type for CDRs, because they can be designed to phase lock:
1. with zero phase error when there is no frequency (just phase) difference
2. with a very small phase error when the master clock embedded in a received signal stream has a frequency
different from the free running frequency of the local oscillator.
• Type 2 systems are not used in the study of CDRs because two poles in the open loop transfer function (in a unity
feedback loop!) do not allow any margin for designing other needed performances of the PLL. Type 2 is
incompatible with 1st order, and is also too much of a requirement for a 2nd order PLL with other useful
characteristics.
References
[1] "The Synchronous Oscillator" (http:/ / www. tapr. org/ ss_g1pvz. html#synch_osc) James A. Vincent, 1993
[2] Behzad RAZAVI, Monolithic Phase-Locked Loops and Clock Recocvery Circuits .- Theory and Design. IEEE PRESS 1996 - ISBN
0-7803-1149-3

CDRs/The CDR phase comparator
The non-linearities of the phase comparator are the most critical for the CDR
modeling
Mathematical models of a circuit can be very useful. This is especially true if the circuit operation can be considered
as linear: in such case the mathematical terms are very neat and describe the circuit in all its different conditions.
Unfortunately the reality is never exactly linear. Rather, it is seldom very close to linear and sometimes can be
markedly distant from linearity.
The phase comparator is the CDR component that deviates more often and to a larger extent from linearity.
Inevitable non-linearities of the phase comparator
Linear range
Even if a circuit operates as linear (to any practical purpose), it has a finite range of operation. The EXOR circuit is
probably the best introductory example:
The figure above represents a clock signal on the lower input that changes its delay with respect to the upper input.
The output is a periodic signal of twice the frequency of the inputs (the EXOR is a “multiplier”). If such delay
reaches one full half cycle of the period of the two signals (180o), the output reaches its maximum level. If the delay
is further increased, then the output gradually decreases to its minimum level. If the two inputs are exactly in phase
with each other (0o), the output is again at its minimum. If the phase difference is gradually varied, the entire
input-output characteristic of this circuit can be obtained. It is a triangular sawtooth of period 180o (= π) and
amplitude +/- π (or 0 to 1, depending on the circuit implementation!).
The useful signal is the filtered output, not the output of the EXOR, that has useless wide swings at the clock
frequency. In fact the phase comparator always works at the bit line frequency (very high) but the CDR loop just
needs the low frequency components of the phase comparison (Low frequency means in this case “not higher than
the maximum frequency of significance for the control loop operation”, which is at least 10 times less than the bit
line frequency, but often 100 or more times lower). In the figure above, two points might be emphasized:
1. Only one of the two slopes of the sawtooth characteristic correspond to stable operation of the loop. Operation on
the other one is unstable and the working point would quickly move to the closest end of the nearest stable slope.
2. The gain of this comparator, along any stable slope of its characteristic, is 1V / π/4 radian, that is 1.273 V/radian.
Uneven density of transitions in the reference signal

In a digital transmission, the incoming signal carries its phase information with its transitions from one level to
another. The NRZ bit stream (the most often used for data transmission) has a variable density of transitions. (It is
sometimes replaced by a coded signal, but the problem of variable density of signal transitions remains). In a NRZ
signal, a transition occurs when a bit 1 is followed by a bit 0, or viceversa.
Introduction to the NRZ-to-Clock phase comparator. See the next figure for the full circuit.
When a bit is followed by a bit of the same polarity, no transition occurs. A phase comparator of easy making is one
that generates a pulse every time a signal transition is received, like the EXOR multiplier of the previous section
above does when comparing two clock signals. That comparator (as well as the one in the figure above) is
considered “linear” because the duration of the generated pulses is proportional to the phase distance between the
transition of the incoming signal and the corresponding transition of the other signal that enters the other input of the
comparator. The pulses obtained in the figure above tell -with their duration- the phase distance between each
transition of the incoming signal and the next sampling edge of the local clock (such distance should be 900 , or π/2,
for optimum sampling of the received waveform). Unfortunately such pulses can only be obtained when a signal
transition is present. What to do when no transition is received? This is similar to the dilemma of a car driver at night
when temporarily dazzled by an excess of light.
• 1. To steer abruptly to one side? Certainly not! But this is what our waveform in the figure above would make our
CDR do, because it stays at its lowest level when no transitions are present!
• 2. The equivalent to keeping the steering wheel in its mid position would be obtained with the following retrofit to
our phase comparator, that adds pulses exactly corresponding to perfect phase lock whenever the information
carrying pulse can not be obtained because a transition is missing:
NRZ-to-Clock phase comparator
The gain of this phase comparator will be a function of the ratio between the actual number of
transitions in the incoming signal, and the number of transitions corresponding to a continuous
10101010.. data pattern in it. Let's call this ratio DT, which will vary between 0 and 1.
The comparator gain can be calculated considering that the couple of output pulses corresponding to one
input transition yield 0 V for a clock sampling the transition (clock phase = 0 radian), 0.5 V for a clock
sampling the center of the received pulse (clock phase = π radian) and 1 V for a clock sampling the end
transition of the received pulse (clock phase = 2π radian) :
Gain = DT / 2π [V/radian.]
The characteristic of this comparator as a function of the phase difference of its inputs is again a
sawtooth, but, in this case, with normally oblique stable slopes and vertical unstable slopes.
Characteristic of the phase comparator. No consideration about the transition density of the incoming signal is made, therefore assuming it to be
100%.
It is important to point out that the transition density DT in practical cases is never very close to zero
because the presence of different elaborations of the bits that are actually transmitted contributes to
bring DT towards its average value of 0.5. The possible presence of factors that may modify DT, like bit
scrambling, error correcting coding, framing, 8B10B character coding, etc., shall be taken into
consideration to evaluate the actual behavior of the phase comparator and its gain.
• 3. It would be best for our driver -temporarily blind- to maintain for a while the position of the steering wheel that
he had just before the loss of vision. The same holds good for the output of our phase comparator. But our phase
comparator operates at the line bit frequency, and its memory span can not be extended beyond a few flip-flops,
that is not beyond a few periods of the local clock. After that, any memory of the last meaningful phase
comparison is lost by the phase comparator. To find inside our CDR a memory element similar to the memory of
our driver, we must involve the loop filter, and use it to maintain memory of the last meaningful information from
the phase comparator. But if the blindness (=the lack of transitions) persists beyond a certain time, our
unfortunate driver should not insist keeping the steering wheel turned, but shall gradually take it back to its
central position. With a strong analogy, we shall not freeze our filter status for too long, but allow it to evolve
towards its discharged state (= towards driving the local oscillator to its free running frequency). In this latter
sense, an elegant solution to the need of mitigating the problem (of uneven density of transitions in the received
signal) can be seen in [1] . (A sub-circuit detects when a transition is missing in the incoming NRZ data stream
[i.e. when the next data bit is NOT the opposite of the previous data bit]. In such occasions the output of the
phase comparator would be unable to generate the couple of pulses whose average duration tells the phase
difference between the local clock and the data transitions. The sub-circuit then forces the Low Pass Filter of the
PLL to the same filter output that would result from the addition of a “dummy” couple of pulses equal to the last
one from the output of the phase comparator.)
Deliberately non-linear phase comparator

A not infrequent choice amongst designers is the so called “bang-bang phase detector”.
It is a circuit easy to understand and easy to design.
Unfortunately it is strongly nonlinear: its operations consists in the generation of a pulse of fixed amplitude and
duration at every received transition, with the same sign of the phase difference it detects.
The term detector is more appropriate in this case than the term comparator.
To justify the adoption of a bang-bang phase detector, the designer often may say that a good jitter tolerance can be
obtained.
• Bang-bang drawbacks: primarily noise generation (and difficulty to model its behavior). A CDR that uses a
bang-bang phase detector generates a lot of phase noise because it “overestimates” the small amplitude jitter. In
fact it behaves like a linear comparator of very high gain when the input jitter is of small amplitude, and it
behaves like a linear comparator of low gain when the jitter amplitude is large.
• Bang-bang (supposed) advantage : jitter tolerance. In presence of jitter with large amplitude, this type of
comparator approximates a low gain linear comparator. The low gain corresponds to an over-damped loop, that
has no undershoot in its jitter tolerance characteristic, as we will see when analyzing the jitter tolerance of a
(slave) CDR based on a second order PLL
• Bang-bang compromise: Cascade of a CDR1 (with some desirable jitter tolerance but poor jitter filtering and
generation) followed by a CDR2 (with good jitter filtering). The second CDR will be a linear one, with good jitter
transfer characteristics (= will filter out most of the jitter generated by the first), cascaded to the first based on the
bang-bang.. This compromise imitates a solution that has in general some merits, described later on in Cascade of
CDRs. The second CDR will correct to a good extent the shortcomings of the first (noise generation) while the
jitter tolerance of the first will not be reduced. It remains to be seen, however, why a good design of the cascade
of two linear CDRs (the first one to give a good jitter tolerance, the second to give a good jitter transfer and
filtering) would not be a better solution in many -if not all- respects.
References
[1] A Monolithic 156 Mb/s Clock and Data Recovery PLL Circuit Using the Sample -and-Hold Technique by Noboru Ishihara and Yukio
Akazawa, IEEE Journal of Solid-State Circuits, vol. SC-29, pp. 1566-1571, December 1994

CDRs/Examples
Examples
To fix the concepts introduced in the previous section, and to better understand them, let’s see a few examples.
Amongst them, just two will be further developed in the remainder of the book, because they represent the two really
useful models of CDR. The others are useful just as examples and not so much as models of how CDRs should be
made.
Notes:
1. A CDR shall be called "a slave CDR" if its local clock is phase locked to the incoming signal.
2. A slave CDR belongs to (and extends) the clock domain mastered by the remote transmit clock.
3. In some cases the characteristic of certain individual blocks in the block diagram (like the gain of the phase
comparator, or the oscillator gain, or other characteristics) are not explicitly considered. More abstract
quantities, like the natural frequency n, or the damping ratio , are used instead for the formulas and for the
time or frequency diagrams. This is done for two reasons:
• the characteristics of the blocks that operate at the (high) frequency of the data stream (phase comparator
and local oscillator are the best examples) are frequently imposed by technology choices and are not for the
designers to play with;
• the general behavior of the CDR is more generally represented and more easily understood.
1st order, type 0

In a PLL of first order and of type 0, the local oscillator is controlled in phase by the low pass version of the phase
comparator output.
The PLL in this CDR is of unity feedback, of the first order and of type 0.
The relation of the output to the input (= the transfer function) is:
and it tells us a few things:
• that the loop tracks the jitter frequencies below , and is unable to follow higher jitter
frequencies;
• that there remains a steady state error, which is minimised if is >> 1. In fact a type 0 loop like this one
needs a small phase error to track a delta phase in the incoming signal (with respect to the phase of
the free running oscillator!) of . In other words, if the local oscillator is synchronous with the received signal
(i.e. both are within a single clock domain), this circuit provides a strong reduction of the phase difference
between the two, that is reduced from to .
• A circuit of this type may be useful to phase align (with a small residual error) the clock, delayed by the
amplification buffers of the clock tree, to the original reference clock, inside an IC chip (= inside a single clock
domain). As long as the residual phase error is kept small by a large loop gain, it may be acceptable in such an
application. The unconditional stability and the fast response are useful, while the mediocre jitter filtering at
high frequencies, as well as the small steady state error may not be important in the application.
The unit step response

1st order, type 1

The general architecture of the CDR in this case is represented on the left in the Figure below:
The Phase Locked Loop in this case is of the first order. The unity feedback (always the case for PLLs) corresponds to a loop of type 0.
Oscillator controlled in frequency ("first order slave CDR")

This example has value in that it introduces this type of architecture, with the integration in the forward path (but
without any other filtering, which prevents its use in any but the simplest, undemanding, applications).
Its architecture is shown on the right in the Figure above.
Its response to a unit step variation of the input signal phase, its jitter transfer function and its jitter tolerance function
( The jitter tolerance function ) are shown in the Figures here below.
This architecture clearly shows:

• a good jitter tolerance, with the 20 dB/decade asymptote towards zero frequency. It comes from the pole 1/s
present in the forward path of the control loop. This is certainly a desirable characteristic when the CDR must
operate as a slave and track frequencies that can wander around their nominal value;
• a mediocre (20 dB/decade) jitter filtering towards high frequencies;
• only one degree of liberty for the designer (that is K in the figures above, i.e. the open loop d.c. gain).
All these characteristics together make this architecture not preferred in actual designs of slave CDRs. For these, the
second order, type 1 architecture is chosen instead (the slave CDR, described further down in this Section) .
Addition of the complementary delay ("phase aligner")
1st order type 1 (with the complementary delay): the phase aligner
= the CDR with good acquisition characteristics.
This is the first architecture of two that must be remembered.
A second example of unity feedback, first order and type 1. The local oscillator is fixed and an adder compensates the phase deviations of the
incoming signal before its regeneration with the local clock
This example is of particular interest because:

- a clock independent from the PLL operation (i.e. in the Figure above) is used for the regeneration, while it
is -y(s) instead that represents the output of the PLL system.
- as a consequence of the point above, the CDR incorporates an "elastic buffer" function, located in the
processing of the input signal through the adder block and through the subsequent re-sampling by the local
clock ( ).
This example in fact describes the abstract model of the phase aligner. The CDRs that match this model are found in
network points where a signal (jittered and possibly regenerated by slave CDRs one or more times along a
transmission path) is brought back in phase with the clock that was used to generate it[1] .
For sake of simplicity in the following calculations - and without loss of generality in the results- the local clock
is used as reference for the phase of all the signals.
Therefore its jitter is identically zero. Additionally it is assumed that the initial phase value .
• Jitter transfer function
It can be easily derived as follows:
-y = ( - x + y)*G/s = - x*G/s + y*G/s
xG/s = y (1 + G/s)
x = y (s/G + 1)
The jitter transfer function in this case describes a characteristic of the PLL as usual, but becomes meaningless for
the whole CDR, because of the phase alignement resulting from the elastic buffer feature of this CDR.
• Unit step response
In this particular case, as already pointed out for the transfer function, this characteristic only describes the PLL
operation, while it is meaningless for the whole CDR.
It can easily be obtained from the transfer function:
and can be seen as the waveform at the output of the phase adder ( x-y signal in the Figure above ) resulting from a
phase step of the input ( x(s) in the Figure above ).
• Jitter tolerance function ( The jitter tolerance function )
The phase jitter tolerance of this circuit is limited both by the range of linearity of the phase adder and by the range
of linearity of the phase comparator.
Let's see each one separately. Then, the tolerance function at any frequency will simply be the lower of the two,
because the signal in either of the two circuit blocks does not influence the characteristic of the other block.
• Adder tolerance function ( Tolerance of phase adders )
The adder is normally made by a delay line, that adds a delay to the input signal ( x(s) in the
Figure above ) equal to the signal present on the control input (- y(s) in the Figure above ).
- Defining as D (measured in radian - if D is in seconds, then use ) the total phase
delay that the delay line can add, and
- defining as zero the phase delay added when the control signal is set at the mid point of its
control range,
then the tolerance of the adder inserted in the CDR circuit of the above Figure is:
(-D/2 + ) < Amplitude of [y(jω)] < (+D/2 - ).
using the relation (see the relevant subsection on the jitter transfer function of this example)
then
Magnitude of [x(jω)] =
• Comparator tolerance function ( Tolerance of phase comparators )
The tolerance limit is reached when the phase difference between and x-y (again on the right
part of the Figure above) exceeds an error :
Magnitude of [x(jω) − y(jω)] =
then
Magnitude of [x(jω)] =
The relevant diagrams of response to a unit step variation of the input signal phase, of jitter transfer function and of
jitter tolerance function ( The jitter tolerance function ) are shown in the Figures here below.
The unit step response and the jitter transfer function of this CDR do not differ from the typical 1st order, type 1
CDR.
The jitter tolerance of this CDR shows a new example. It is limited at low frequencies by the jitter tolerance of the
adder and, at medium and high frequencies, by the jitter tolerance of the phase comparator. In fact the actual design
choices always assure that
(-D/2 + ) >> .
In conclusion, this example shows a CDR that:
• is not able to tolerate a wander of the input signal frequency. There is no increasing jitter tolerance with a 6
dB/oct asymptote towards zero frequency, but just the flat tolerance limited by the adder range. This CDR can
only phase align a signal (jittering but) synchronous with its local clock;
• can lock in quickly into a signal burst after a period of loss of signal;
• offers the inherent elastic buffer feature typical of phase aligners.
2nd order, type 1
Oscillator controlled in frequency ("slave CDR")

This is probably the most common architecture for a CDR, both in the technical literature and in real applications.
Some of its characteristics, very valuable for the “slave” application, associated with a complexity that is still
manageable, have led to its widespread use.
2nd order type 1 : the slave CDR

=
the CDR with good tracking characteristics.
This is the second architecture of two that must be remembered.
The classic architecture, preferred for slave CDR applications. The loop is a second order, type 1 with unity feedback.
The structure is depicted in the above figure.

• The oscillator is controlled in frequency. It converts an input signal into a frequency, that is into the integral of
a phase: its transfer function in the s domain is in fact V0/s. (It is therefore a type 1 system).
• Between the output of the phase comparator and the input of the oscillator, a single pole low pass circuit filters
the higher frequencies of the error signal. (Combined with the oscillator, this low pass in the forward path
makes the loop a second order, unity feedback, system).
The presence of an independent block to perform the low pass with a precise cut-off frequency (represented by in
the figure above) gives the designer one more degree of freedom to find the best performance compromise.
The figures that follow, as in the previous examples, plot the unit step response, the jitter transfer function and the
jitter tolerance function of this architecture. In order to appreciate some of the peculiarities of this new example, also
the corresponding curves for the fist order slave (Oscillator controlled in frequency ("first order slave CDR")) have
been plotted as well.

The increased complexity of this architecture versus a first order one is responsible for the delayed reaction to an
input phase step.
In fact this architecture is not superior to the first order alternative (no matter how smartly the design parameters are
adjusted) when the lock-in phase of the system is of prime importance.

The ability to filter out the high frequency components of the incoming jitter is the strong point of this architecture.
When a sequence of regenerations takes place along a chain of telecom link, the jitter accumulation must be avoided,
and the low pass action must have a (relatively) abrupt cut off.
This second order architecture (see the relevant figure) has a jitter transfer with a 40 dB/decade roll-off, while the
first order only offers a 20 dB/decade performance.
• Jitter tolerance function
The advantages offered for the jitter filtering are partially balanced by some weakness in presence of strong jitter
components concentrated around the corner frequency of the PLL (fortunately not very likely in practice).
While the first order loop presents a tolerance larger than 1 Unit Interval at all frequencies, this second order loop
always has a frequency range where its tolerance is lower than 1 UI.
This dip of the tolerance is more evident for lower values of the damping ratio , and the above figure uses the two
plots ( = 0.7 and = 0.5) to give evidence of that.
The importance of this architecture is such that an entire section is devoted to it further down in the book (link),
where all time and frequency functions of the previous diagrams are described in detail and further developed.
At this stage it is sufficient to have understood in which ways this architecture is different from the other
architectures presented in this series of examples.
Addition of the complementary delay ("second order phase aligner")
The architecture, too complex and non preferred for phase aligner CDR applications. The loop is a second order, type 1 with unity feedback.
The structure depicted in the above figure is meant as another example, but has no value for a real CDR application.
Its special characteristics, very valuable for the “slave” application, are wasted in the phase aligner application.
The essential points are the same of the previous example.
• The oscillator is controlled in frequency. It converts an input signal into a frequency, that is into the integral of a
phase: its transfer function in the s domain is in fact V0/s. (It is therefore a type 1 system).
• Between the output of the phase comparator and the input of the oscillator, a single pole low pass filters the
higher frequencies of the error signal. (Combined with the oscillator, this low pass in the forward path makes the
loop a second order, unity feedback, system).
The following figures, as in previous examples, plot the unit step response, the jitter transfer function and the jitter
tolerance function of this architecture.
In order to appreciate some of the peculiarities of this new example, also the corresponding curves for the first order
phase aligner have been plotted as well.

The increased complexity of this architecture versus a first order one is responsible for the delayed reaction to an
input phase step.
As a result this architecture is inferior to the first order alternative (no matter how smartly the design parameters are
adjusted) during the lock-in phase for a phase aligner application. (On the other hand, it has the disadvantage of
limited tolerance at low jitter frequencies, when compared to the classic 2nd order circuit for slave CDR
applications, as it will be shown in the following paragraphs.)
The time function and its time diagram figure are identical to the ones of the previous example.
The ability to filter out the high frequency components of the incoming jitter is the strong point of this architecture.
But this type of performance is valuable as long as the CDR is a slave and sends the regenerated clock with the data
stream to another slave. In this example of a phase aligner however, this ability is not useful at all, because the phase
aligner uses the PLL output only for its internal operation, and uses the local system clock for its output data stream.
The jitter transfer function can be derived with the same steps used for the first order phase aligner:
y=( - x + y) = (G / (s * (1 + s( )) * (- x + y)
-y s (1 + s )=-Gx+Gy
Gx = y (G + s + s2 )
=
n
=1 / 2
The j function and the figure are identical to the ones of the previous example.
• Jitter tolerance function
The inherent weakness of this type of architecture (undershoot of the tolerance below 1 U.I. around n ) remains ,
and it can not be offset by the corresponding jitter transfer advantages that are meaningless for a phase aligner
system.
Following the approach of the first order phase aligner, let’s find separately the tolerance due to the adder and the
tolerance due to the phase comparator. The circuit tolerance, at any frequency, is the lower of the two.
• Tolerance of the phase adder ( Tolerance of phase adders )
The adder is normally made by a delay line, that adds a delay to the input signal ( x(s) in the
Figure above ) equal to the signal present on the control input (- y(s) in the Figure above ).
- Defining as D (measured in radian - if D is in seconds, then use ) the total phase
delay that the delay line can add, and
- defining as zero the phase delay added when the control signal is set at the mid point of its
control range,
then the tolerance of the adder inserted in the CDR circuit of the above Figure is:
(-D/2 + ) < Amplitude of [y(jω)] < (+D/2 - ).
then
Tolerance(j ) = Magn |x(jω)| =

• Tolerance of the phase comparator ( Tolerance of phase comparators )
The tolerance limit is reached when the phase difference between and x-y (again on the the
Figure above) exceeds an error :
Magn |x(jω) − y(jω)| =

using the relation (see the relevant subsection on the jitter transfer function of this example):
then:
Magn |x(jω)| = Magn |
It is easy to see that the tolerance is equal (for > 0.707) to the tolerance of the first order phase aligner, or inferior
for lower values of .
In conclusion, the importance of this architecture is limited to its use as example for didactic purposes. Its first order
alternative, simpler and more efficient, is preferred in practice for phase aligners.
References
[1] A robust phase detector for 1.25 Gbit/s burst mode data recovery (from the INTEC team of Ghent University) IEICE Electronic Express, Vol.
1, No. 18, 562-567 http:/ / www. jstage. jst. go. jp/ article/ elex/ 1/ 18/ 1_562/ _article

CDRs/The jitter tolerance function
The tolerance function
In a feedback loop, like in a PLL for CDR use, the operation will be linear, and the linear modeling will remain
valid, as long as all blocks in the loop operate within their linearity range.
Increasing the input signal amplitude, a point will be reached where one block reaches the limit of its range of linear
operation.
Increasing further the input signal amplitude, the linear model will lose its adherence to the real system and the
actual operation will deviate from the expected behavior.
In a CDR the onset on non-linearity often corresponds to the appearance of errored bits in the output data stream.
The input signal to the CDR will be said to have exceeded the level of the CDR tolerance (such level is a function of
the frequency of the input signal).
When the quantity of interest is the phase of the input signal (the input jitter), the tolerance function is of particular
interest, because it corresponds to an important characteristic of the CDR that is often a precise requirement,
specified and measured as a function of the sinusoidal jitter of the input signal phase.
A mathematical derivation of such jitter tolerance function can be made finding out:
1. the block in the loop that is first to reach its limit of non-linear operation and generate errored bits;
2. the value of the signal amplitude inside such block that is the limit of linear operation
3. the input signal (function of j ) that generates such signal amplitude.
The function so obtained is called the jitter tolerance function.
• Even if the amplitude at point 2. above is simply set at a normalized value of 1, the plot of such function will
replicate very well, in its characteristic asymptotes and corner frequencies, the actual behavior of the diagram that
is obtained with an actual measurement.
• When the onset of non-linearity is rather abrupt (which is often the case at the end of range of many phase
comparators, or at the onset of saturation of operational amplifiers, or at the end of range of certain digital
counters) the correspondence between the theory and the reality of the measurement results will be strikingly
good.
Clock and data recovery/Structures and types of CDRs/The jitter tolerance function 41
• In a type 1 loop (often the case in CDR PLLs) the behavior towards zero frequency in a Bode magnitude plot
will show:
1. an asymptote towards amplitudes of jitter (often a desirable characteristic) if the 1/s block is between the
non-linear block and the phase comparator, or
2. an asymptote towards 0 amplitudes of jitter (rarely –if ever- a desirable characteristic) if the 1/s block is between
the input point of the phase comparator and the non-linear block.
Tolerance of (linear) phase comparators

The border of linear operation of a phase comparator (that sets in most PLLs the border of the jitter tolerance) is
typically found when the distance in phase between its two inputs exceeds a certain value.
It does not depend on the absolute value of either input, but on their difference only.
Mathematically such border can be modeled as:
Magnitude of [ Magnitude of [ ]= max
In most practical cases is independent of j .
max
See the examples of the phase aligners of the first and second order in the previous page, where the tolerances of the
phase comparators are derived as functions of the complex frequency j .
Tolerance of phase adders

The border of linear operation (= of the tolerance) of a phase adder is typically found when the sum of the phases of
its two inputs exceeds a certain value.
It does not depend on the value of either input, even though in practice such limit of tolerance is often reached when
one input simply swings too wide.
The mathematical model shall be:
Magnitude of [x(j ) + y(j )] < max
where +/- are the largest values that the adder can process linearly.
max
In many practical cases though, the phase adder is implemented in the form of a delay line. The input of the delay
line is one input of the adder, while the other input simply controls the amount of delay added to the signal that
enters the delay line.
Such adders can tolerate an added delay between zero and the maximum length of the delay line, Dmax.
The delay is measured as a phase, in units of radians at the angular frequency of interest.
If a delay is known in seconds, then it shall be converted into radian multiplying it by the angular clock frequency: [
]*[ ]=[ ].
The tolerance limit will be in such cases modeled as:
0 < addd delay < Dmax.
When the adder is inserted in a PLL, the control loop may set the adder, as initial condition, at half the maximum
delay, that is Dmax/2.
The locked loop will thenafter exhibit a tolerance between the limits of:
- (Dmax/2 - ) and + (Dmax/2 - )
where the reduction of radians,
at both ends of the tolerated range of input jitter,
corresponds to the initial difference in phase between (the first active level transitions of)
the input signals of the adder at the beginning of the loop operation.
See the examples of the phase aligners of the first and second order in the previous section, where the tolerances of
the phase adders are derived as functions of the complex frequency j .
Clock and data recovery/Structures and types of CDRs/The (slave) CDR based on a second order PLL 42

CDRs/The (slave) CDR based on a second order
PLL
Limits of the first order CDR
The CDR of the first order, type 1, in spite of its simplicity, has several good characteristics that are unsurpassable in
many application.
For instance, it is unbeatable to implement a phase aligner (Definition of phase aligner), or it may be a good choice
for a simple slave CDR when the incoming bit stream has a high transition density.
On one hand, this architecture generates CDRs that are able to acquire the phase of the incoming signal really fast,
and without stutterings in all conditions.
On then other hand, this quick acquisition goes together with a correspondingly quick decay of the phase lock
information if the latter is not constantly refreshed:
The information of the correction needed to keep the incoming signal in phase lock fades rapidly in the (first
order) loop.
The exact measure of the loop memory is in fact the time constant of the pulse response of this loop.
This is an architecture that has a "very short memory".
Pulse response of the 1st order CDR

st
If the (1 order) CDR works in a slave configuration, its local oscillator has a free-running frequency that is
somewhat different and incorrelated from the frequency of the incoming signal.
If the incoming stream lacks transitions for a time comparable or longer than the time constant of the loop, the local
oscillator drifts from its locked state to its free-running frequency.
The sampling instant of the CDR drifts accordingly, from the locked condition when it samples the received pulses at
the optimum instant (best eye opening) to a continuously slipping condition and samples in drifting phases each
subsequent received pulse.
This conditions persists until new transitions appear and bring the CDR back to the locked state.
If the lack of transitions has been long (and if the free-running frequency is markedly different from the received
signal inherent frequency) there may be errored bits and even duplication or cancellation of bit intervals (bit slips).
To avoid this risk, the CDR architecture should be modified so that a "longer memory" is created, and long
sequences of received pulses can be tolerated without errors or slips.
From 1st order to 2nd order: why a more sophisticated architecture.
Addition of some memory to the phase comparator output, to sample correctly during long sequences of
identical pulses
The first order loop returns to its free-running frequency when no transitions are present in the incoming signal.
This frequency drifts exponentially with a time constant equal to τ, the time constant of the loop itself.
To improve the tracking ability, it is necessary to introduce some memory in the loop, at the output of the phase
comparator, that is the information which must be remembered longer.
The simplest implementation is the addition of a low pass filter of the first order (For sake of generality, it is
convenient to introduce a first order low pass combined with a flat gain block).
The added filter changes the loop order form first to second: the loop can exhibit two real poles or a pair of complex
poles, depending on the gain and cut-off frequency of the added circuit block. In practice, the added block is always
chosen so that the poles are complex and the damping coefficient ζ is not far from 1 (at ζ = 1 or larger, the two poles
become real and the loop behaves like two first order loops in cascade).
The loop is analyzed in detail in the following pages. But we can immediately see that it can track longer sequences
of pulses without transitions, and that its unit step response is slower and starts with an especially slow and
“uncertain” beginning.
This second order loop has lost the ability to lock-in without slips in all cases, in return for the ability of staying in
lock for much longer periods without transitions.
It should be noted that the two blocks of the first order loop (the phase comparator and the VCO) are necessarily
working at the line pulse speed (that is the highest speed in a CDR). This makes them more complex technologically
and more expensive to modify when an improvement of the loop performances is required. The added filter block
instead works at lower frequencies, and its design is correspondingly more flexible. The filter block is used to
implement the desired values of ω and ζ in the second order loop.
Once again it is good design approach to implement a filter that be linear (at least in its practical behavior). The loop
modeling and simulation remain possible in all conditions and are simpler than the modeling and simulation of a
non-linear loop, whose models and simulations do not always exist.
Formulae that apply

Parts per million [1], denoted as ppm, is used to give a relative measure of the frequency difference of two oscillators.
For instance, the free running frequency of a slave CDR may differ no more than 0.05 ppm from the frequency of its
remote master, 200 ppm ,or 10000 ppm, or ...
What is gained
The ability to stay in lock even when signal transitions are missing for a while is the first requirement that a first
order architecture is not able to satisfy.
There are others. For instance:
• the need to be insensitive to jitter of medium frequencies
• to be a CDR part of a regenerator chain
• to reject noise at certain frequencies
What is lost
1. fast acquisition
2. ability to lock without slips in all conditions
3. rejection of medium frequency noise from the VCO
The (slave) CDR based on a second order PLL - Fundamental equations

A linear, time-invariant model of the circuit is described here.
The case of a second order loop, fit for a slave CDR function, is presented.
This model is in fact the best for applications where the CDR is used in a regeneration application, to recover a clock
and to resend the data stream further, as the introductory example has shown. This is also probably the most common
scheme of CDR in the technical literature.
The case of R3 = 0 corresponds to a second order system with just two poles and no zero, and is studied in detail in
the next pages.
The most important functions that describe the relations amongst the variables shown in the figure, expressed for the
sinusoidal jitter condition, are described in the following three subchapters.
The fourth subchapter that follows gives the equations and the diagram for the time function that describes how this
circuit reacts to an abrupt change of phase in the received signal.
Essential difference
There is always some sort of filtering at the output of a phase comparator.
This filtering does not necessarily turn a first order loop into a second order loop...
References
[1] http:/ / en. wikipedia. org/ wiki/ Parts_per_million|

PLL/The jitter transfer function
Jitter transfer function of the second order slave CDR
The transfer function for a sinusoidal input (that is the Jitter Transfer function!) is:
The magnitude of the jitter transfer function of jω tells, at each frequency f = ω/2π , the amplitude of the output jitter
for an input jitter with the amplitude of 1 radian ≈ 57.3°.
The following figure is the Bode magnitude plot of the jitter transfer function. Curves for different values of the
parameter ζ (damping ratio) are shown:
The magnitude of jitter filtering, for different values of the damping ratio.Peak amplification for low values of the damping ratio.
It can be seen that the CDR is essentially a low-pass filter for the phase jitter. There is no amplification of the input
jitter but for values of the damping ratio smaller than = 0.707, at some frquencies at and around the resonant
Clock and data recovery/Structures and types of CDRs/The (slave) CDR based on a second order PLL/The jitter transfer
function 46
frequency. The peak amplification occurs at = and is:

PLL/The error function
Error function of the second order slave CDR
Another way of looking at the same critical frequency band of PLL tracking, seen in the previous sectionabout the
jitter transfer function, is to look at the function that describes the phase difference between output and input.
First let's compute the complex function (output - input).
Such function is itself a function of the same complex frequency.
Its magnitude tells, at every jitter frequency, the amplitude of the sinusoidal distance between the output and the
input phases. It is easy to realize that this function is the loop error function:
The phase error function is not very relevant in a pure PLL circuit, whose task is to track the input clock (and to
dejitter it, maybe), but is extremely important if the PLL is serving into a CDR circuit.
The regeneration of the data depends on sampling the received pulses (that have undergone amplification,
equalization and filtering of out-of-band noise) at a time when the remaining noise and intersymbol interference are
not altering the pulse too much, close to the time of maximunm amplitude of that pulse. A significant phase error
makes the probability of a wrong detection higher: in other words a phase error that is not affecting clock tracking
may still increase to intolerable levels the bit error rate!
The following figure plots the magnitude of the error function. The y scale is in radian (1 radian ≈ 57.3°).
Clock and data recovery/Structures and types of CDRs/The (slave) CDR based on a second order PLL/The error function 47
Figure 4. The magnitude phase tracking error, for various damping ratio values. The error overshoots just above the characteristic frequency, and
much more so for low values of the damping ratio.
At low jitter frequencies there is practically no error, because the tracking is very good.
At very high jitter frequencies the error is practically identical to the input: in fact the PLL is not able to track the
jitter and the local clock stays unmoving with respect to it.
At intermediate jitter frequencies, around , the error increases with frequency till it is as large as the input jitter
itself, or even up to the point of becoming larger than it at frequencies just above for low values of ζ.
Large values of ζ ( >> 1) involve a large error even at frequencies much lower than , and small values of ζ ( <
1.0) correspond to large overshoots of the phase error just above .
Values of ζ between 1.0 and 1.5 are therefore an inevitable design choice, but other considerations can be drawn
from the study of the jitter tolerance function and suggest an even tighter range of ζ values for the CDR design.
It can be noted that both the jitter transfer and the jitter error functions are true "transfer functions". They tell the
ratio of an output to an input (The function in the figure above can be easily seen as representing the magnitude of
the error transfer function, and not just the error magnitude for an input of fixed, 1 radian, value). The function in the
next sub section instead -the jitter tolerance function- is not a transfer function. In fact even the aspect of causality
(that in a transfer function is the fact that the input generates the output) is not present. The jitter tolerance function
describes the values of input jitter that generate a fixed value of phase error.
In real applications the PLL circuit will not operate correctly any more when the phase difference between input and
ouptput (i.e. when the magnitude of the error funtion) exceeds a certain value that can be called . Depending on
the PLL design, it may slip abruptly by the phase amount of one clock cycle, or it may exhibit other irregularities of
operation. It is good design practice to have the value, in all jitter conditions, be larger than the error phase that
the circuit is expected to tolerate. This situation of irregular operation is essentially encountered when the circuit
non-linearities are reached. The next mathematical function, which corresponds also to a practical measurement
condition for the circuit, is useful in describing the circuit behaviour when the boundaries of the non-linear operation
are reached. This is the Jitter tolerance function, and is the subject of the next page.
Clock and data recovery/Structures and types of CDRs/The (slave) CDR based on a second order PLL/The jitter tolerance
function 48

PLL/The jitter tolerance function
The jitter tolerance function of the second order slave CDR
In Telecom Networks it is established practice (see for instance some of the ITU-T Recommendations G7xx [1]) to
specify, and to characterise by the measurement of, the jitter that can be tolerated by the input ports of an equipment.
At any frequency of interest, a sinusoidal input jitter is added to the phase of an otherwise flawless incoming signal,
and its amplitude is increased as much as the equipment can tolerate. Beyond that limit, the received data stream is
not regenerated perfectly and errored bits or slips begin to appear in the regenerated stream.
The boundary of the area (in the plane of jitter frequencies and amplitudes) where correct operation is found is then
called the curve of jitter tolerance of that equipment.
The errors can either be generated by sampling the received pulses with too large a phase error or by slips of a CDR
clock internal to the equipment.
• Errored bits. If the CDR under test extracts the clock directly from the pulses of the received signal, and then uses
it to regenerate the pulses received, then errored bits will give evidence of the tolerance limit. In this type of CDR
the tolerance limit will be reached when the tracking error (the phase error) makes the sampling of the incoming
signal excessively far (too early or too late) from the optimum point (the point of “maximum eye opening”).
• SLIPS. If the CDR under test extracts the clock from the clock of another CDR inside the same equipment
(typically to dejitter it), then slips will give evidence of the tolerance limit.
In both cases, inside the CDR circuit (or circuits) involved, reaching the limit of tolerance corresponds to reaching a
region of significant non-linearity inside one of the circuit blocks. It is useful to simulate (because this is often the
case in reality, and also because this is very often a good simulation of the behaviour of the real circuit anyway) that
the limit of the range of linearity is reached inside the phase comparator, abruptly, when the phase error reaches a
value of +/- .
In mathematical terms either case above will be described by the phase (= the tracking) error exceeding a certain
phase difference . Whichever occurs first for a smaller phase error is relevant for the value of the phase error best
fit to give an accurate simulation, but the mathematical description (apart from an amplitude coefficient) is exactly
the same.
An elegant mathematical description of the 2nd order PLL in this condition can be easily obtained following (in the
abstract world of Laplace transforms) the steps described above.
Let's consider the "transfer function" of phase error to input jitter, and let's restrict it to the condition .
Although it describes how the cause (the input jitter) corresponds to its effect (the phase error), it still nicely follows
the way that the jitter tolerance is defined.
The function that gives the ratio of the input to the error when radian (that is the jitter tolerance function
) is:
The magnitude of this jitter tolerance function is :

function 49
The Bode magnitude plot ( =2 f) is given in the following figure:
The magnitude of the maximum jitter that can be tolerated, for various damping ratio values.The maximum tolerance undershoots just above the
characteristic frequency, and much more so for low values of the damping ratio.
This function can therefore be seen as the tolerance of our circuit (if = 1 radian) to an input sinusoidal jitter of
the plotted magnitude. If another value of better simulates the circuit tolerance limit, the curve plotted still
applies provided it is translated vertically by the amount .
At low jitter frequencies there is very good tracking, even if the jitter has a large amplitude. The circuit has time to
follow these large but slow variations. It takes an extremely large jitter amplitude to reach the limit of tolerance.
At very high jitter frequencies the circuit is unable to follow the jitter that varies too fast. The tolerance is in practice
exactly the lateral eye opening (or the phase comparator range, whichever limit is reached first). In fact, the PLL is
not able to track the jitter at all and the local clock stays unmoving with respect to it.
At intermediate jitter frequencies, just above , the circuit is tricked by the jitter into overreaching while the jitter
is coming back to its zero value. In the range of such intermediate frequencies, at and above , the tolerance is
correspondingly reduced below its asymptotic value, and especially so for low values of ζ.
The following table gives the values of the maximum tolerance reduction for different values of ζ:
function 50
The tolerance has a minimum that depends in frequency and value on the damping ratio ζ.Minimums are listed
for different values of ζ.The reduction is especially large for low values of the damping ratio.
Values of ζ between 1.0 and 1.5 are therefore an inevitable design choice. The designer shall pay attention to the
fabrication tolerances of the CDR blocks (that may often be as large as ± 20 %) as well as to the dependence of them
from operating conditions like the power supply variations or the density of transitions inside the incoming signal.
It is therefore important to check the behaviour of the CDR circuit (whatever its actual implemetation is, analog,
digital or ..) in the frequency range around the transition from tracking (typical at low jitter frequencies) to unability
to track (typical at very high jitter frequencies): an undershoout of the jitter tolerance may be present, and go
unnoticed otherwise!.
References
[1] http:/ / www. itu. int/ rec/ T-REC-G/ e
Clock and data recovery/Structures and types of CDRs/The (slave) CDR based on a second order PLL/The unit step
response 51

PLL/The unit step response
Unit step response of a second order PLL
The analysis in the frequency domain (jitter transfer function, jitter error function, jitter tolerance function) is the
most commonly used. It investigates well the circuit behavior in the "small signal" condition.
The (unit) step response is also part of the same mathematical model, based on a description of the system with
linear constant coefficient differential equations. This modelling approach comes from the very reasonable
assumption that a CDR circuit behaves as linear, time invariant and causal.
The unit step response gives a time domain perspective of the circuit, that complements the frequency domain
perspective offered by the previous three functions.
It represents very well the response of the CDR output phase to an abrupt (small) variation of the input phase.
The amplitude of the output phase as a result of a (unit) step variation of the input phase, for different values of the damping ratio . The output phase
oveershoots the input after an initial delay, and then gradually settles in good tracking.
It is however important to be cautious when using the step response to model the system in case of large abrupt
variations of the input phase.
Care is necessary because the boundaries of linear operation of the system (the range of the phase comparator, the
swing of the filter output, the control range of the VCO, ..) can easily be reached and exceeded during a (relatively)
large transient.
The CDR will -very likely- still operate correctly but its performances may not be well described by this linear
model during such transient.
and tolerance of two cascaded CDRs 52

PLL/The jitter transfer and tolerance of two
cascaded CDRs
The jitter transfer and tolerance of cascaded CDRs
In complex Telecom systems, the first CDR circuit met by the incoming signal (the first after the input stages of the
receiver that perform amplification, equalisation and filtering) takes care of regenerating the clock with a given jitter
tolerance.
Another CDR circuit, follwing the first along the signal path, takes care of controlling the jitter transfer function and
of filtering out enough of the noise (jitter) generated by the first CDR.
Without loss of generality, let's consider the scheme of the following figure.
Figure: Two CDRs in series (with elastic buffer in between).
The first CDR supplies the regenerated incoming pulse stream and its clock to the input of an elastic buffer, and
supplies its clock also as input to the another CDR. The second CDR in turn, de-jitters the clock, and then uses it to
get the data out of the elastic buffer.
• What is the combined Jitter transfer characteristic of the two CDRs?
• The Jitter Tolerance of the cascade of the two CDRs is the locus of conditions that both can tolerate, and is
therefore represented by the area below both curves (below the dark blue line). The Figure above represents
the case of two similar CDRs, where the second is simply filtering the jitter more than the first. There is no
and tolerance of two cascaded CDRs 53
advantage in having the first CDR more tolerant and better tracking than the second in such case.
• The Jitter Transfer function of the cascade of the two CDRs is the product of the two transfer functions, as the
figure indicates. In practice, the jitter filtering is made by the second CDR only.
An improvement in the combination of the two CDRs in cascade can be obtained if the second CDR (that must in
any case be the one with tighter jitter filtering) has a different Jitter Tolerance characteristic for high jitter
frequencies. The Figure below indicates how the combined characteristic looks, and also suggest one simple method
of increasing the tolerance to high jitter frequencies in the second CDR.
Figure: Two CDRs in series with different filtering and different tolerances (with elastic buffer in between).
The division by 4 (or more), inside CDR2, of both the clock to lock and of the local clock will be effective without
drawbacks if the CDR1 is adequate to track the incoming signal. The divison by 4 will remove from the CDR1
output the high jitter frequencies, and make the CDR2 insensitive to them at the same time. This should not cause
problems, as long a the CDR2 is expected to filter out such high jitter frequencies.
It should be emphasized that the depth of the elastic buffer has no relevance in the jitter characteristics of the
combination of the two CDRs, provided such depth is larger than the CDR2 tolerance at high jitter frequencies. In
fact the buffer is represented in the above figures simply because it happens to be present in practical cases, but its
presence is requested by system considerations other than the jitter characteristics, and is therefore always larger than
required to match the jitter tolerance of CDR2.
Clock and data recovery/Design values used in

practice
Practical design values for , and of CDRs
The function that the CDR implements is a simple one and there is only one distinction to make when studying its
activity.
The transient phase of acquisition of the correct synchronism must be distinguished from the steady-state phase of
tracking.
During the acquisition phase the fundamental performance is the speed with which the lock-in is reached.
During the tracking phase instead, the performances that matter are the jitter tolerance, the rejection of the phase
noise (measured by the jitter transfer function), the minimization of the added noise (measured by the characteristic
of jitter generation).
In a single CDR, the attempt to improve all these performances together creates conflicting requirements. Sometimes
the solution is found by implementing more than a CDR in a cascade configuration. Some other times the best
compromise is sought targeting the specific application that the CDR fits into.
It is even possible, thanks to modern DSP implementation of the loop filter, to change architecture according to the
different operation phases. During acquisition, the first order would be used. Once acquisition is achieved, the filter
parameters could be changed, so that the loop changes into a second order loop with more margin against bit errors
and better jitter filtering. This last approach however should be prudently taken by the designer, because the criteria
to switch between architectures and the actual ways to implement the transition are tricky subjects with room for
mistakes.
It is useful, in order to get a better understanding, to separate the burst-mode applications (those where the
acquisition phase repeats itself regularly and therefore needs an efficient execution) from the continuous-mode
applications (those where the acquisition phase takes place only exceptionally and where the performances to
optimize are those related to the tracking phase).
There are in fact just two architectures used for CDRs. Let’s see the design values to use for each of them. (The
quantity (or where ) shall denote the frequency of the pulses received. In general
, but in some cases, and in particular when acquisition must be very fast, the former may be just a few times larger
than the latter.).
1. first order loop of type 1, that is preferred when the acquisition performances are the prime requirement.
This architecture is typically used for phase aligners, but not only.
The response time is the only quantity that characterises this type of loop.
The quantity can be made as short as the duration of a few received bit pulses.
The phase adjustment in one clock cycle is much larger than the phaser drift associated with the frequency
difference between the remote transmitter and the local clock (in the case of the phase aligner, such difference is
zero by definition).
The acquisition is normally achieved in linear regime, and takes places without any clock slip.
2. second order loop of type 1, that is preferred when the tracking performances are the prime requirement. For it,
as seen in the previous paragraphs, the only parameters to consider are and . In the circuit implementation
described earlier they are related to the circuit parameters as follows:
These CDRs are designed so that their acquisition is inevitably long and a series of slips may precede
the achievement of a stable acquisition.
In such cases, it is impossible to model their acquisition phase because of the intrinsic strong non
linearities. To be confident that one such circuit will eventually achieve lock in all cases, the circuit
concept shall be extensively simulated and the circuit prototype will be tested in the worst case
conditions during the circuit validation phase.

practice/Continuous transmission mode
Continuous transmission mode
where the slave CDR of the second order is preferred
A good part of the communication transmission links are of the continuous-mode type, where the signal is present at
all times.
For this type of links it is not very important that the clock recovery circuit at the receiving end be fast in the initial
phase of acquisition of the timing of the received signal. The acquisition phase can last for a relatively long period,
and the only thing that really matters is that a satisfactory locking of the phase of the received timing is reached
within a reasonable time after the appearance of the received signal.
Examples of such links are:
• High bit rate links inside the core of the networks. These are point-to-point (and bidirectional in all practical
cases) links. The data flows, originated by different users (i.e. from different application processes in the OSIRM
sense) are multiplexed on the link. The link shall be available at any time, given the importance of the traffic and
in particular the need to support all QoS (Quality of Service, which primarily means no added time latency to the
signals being carried by the link);
• Point-to-multipoint links in the access networks (downstream direction).
Multipoint access network with continuous mode downstream and burst mode upstream.
These links serve several users at the same time and shall be active all the time. Typical important cases can be:
Clock and data recovery/Design values used in practice/Continuous transmission mode 56
• Radio links from the base station to mobile phones (the continuous-mode clock recovery circuit to consider is
the one at receiving end, inside the receiver part of the mobile phone);
• Downstream transmission in LANs (Local Area Networks);
• Downstream transmission of a PON (Passive Optical Network).
The clock recovery circuits, in the equipment described above (the ones represented in blue in the Figure above),
must essentially provide good performances after the phase lock has been reached (after acquisition has been
achieved). Performances during the lock-in (= acquisition) phase, that is when the connection is being established,
are less important and can be traded off to some extent, in order to optimize the performances during normal
transmission (that are the jitter transfer, generation and tolerance). The only thing that is really needed is the
certainty that the phase lock will be achieved within a specified (not unreasonably long) time after the received
signal has appeared.
The ITU-T Recommendations (the G.7XX series and the G.8XX series in particular, see for instance the G.825)
describe a lot of the characteristics of clock regeneration recommended for applications in continuous mode. With a
little reverse engineering of the large amount of data available from that source, the preferred values that can be
obtained are:
= 1/2500
= 0.66 (to match the requirement of 0.1 dB of max Jitter amplification).
shall not exceed 0.66 in order to keep the maximum jitter amplification (maximum value of the jitter transfer
function) below 0.1 dB. This is especially important in applications where several CDRs find themselves in a line of
regenerators along a series of cascaded transmission links. Jitter at that particular frequency could be repeatedly
amplified and accumulate along the line. Another aspect that suggests values of a bit larger than the classic 0.7
found in some early literature about PLL design, is the overshoot when tracking a sinusoidal jitter. Both the diagram
of the jitter tolerance and the diagram of the jitter error show that (for just above 1) there is an extra deterioration
of the tracking performances for low values of . Finally the construction tolerances when actually building the
physical CDR circuit are to be considered. They can affect the design parameters significantly (sometimes as much
as +/- 30%, like in the case of monolithic integrated circuits). In practice CDR for continuous mode applications will
typically be designed with:
= 1/50 to 1/10,000 (typ. 1/1000) of
= 1.0 to 1.3 (typ. 1.1).
An extreme case with << can be found in long distance links on coaxial cable, where a high number of
regenerators are located in series along the line, each one with its own CDR.
In that case the jitter accumulation is the performances to care about. The jitter transfer characteristic (that represents
how the incoming jitter is filtered by the CDR) will have a very small bandwidth, with / = 1/10000, while
stays higher than 0.7 to limit the jitter amplification at any frequency to be less than +0.1 dB in the worst case.[1]
References
[1] ITU-T Rec.G.783 (03/2006), in particular Table 15-2 / G.783 - Jitter transfer parameters and 15.1.3 Jitter and wander transfer

practice/Burst transmission mode
Burst transmission mode
where the first order phase aligner is often preferred
Applications of CDRs where the transmission is deliberately started and stopped (burst), with longer periods on
inactivity in between bursts, are not less frequent than continuous mode applications.
These burst-mode links are re-activated whenever significant data are to be transmitted, and stay inactive at any
other time, to save energy from the transmitter supply and/or to leave time for other users to use the link.
Examples can be:
• Remote controls for TV sets, for other appliances or industrial equipment, or for car keys (where battery energy
must be saved);
• Upstream segments in multipoint access networks (where access time is to be shared with the other users, and
where often also the energy taken from the transmitter battery or power supply must be used sparingly), like:
• Radio links from mobile phones to the base station (the burst-mode clock recovery circuit to consider is the
one at receiving end, inside the receiver part of the base station);
• Upstream segment in a LAN (Local Area Network);
• Upstream segment of a PON (Passive Optical Network).
• All point-to-point links, like walkie-talkies, where batteries must be spared.
In these cases of burst-mode clock recovery, the lock-in phase must be as short as possible as it represents a
significant –useless- part of the time and energy spent for the connection. Performances in steady-state remain
important, but performances during acquisition of the link become at least as important. There are two different cases
to distinguish, because the clock recovery required is different:
• A. The receiver has neither influence nor knowledge on the phase of the transmitted signal. This is the case of
many point-to-point burst-mode links, and a typical example can be the TV set that receives from a hand-held
remote control. The receiver includes the CDR function in the most straightforward way possible.
• B. The receiver knows that the signal received is synchronous with a clock timing that is available also inside
(often: that has been supplied by) the receiver itself. Such is the case, for instance, in the upstream segment of
radio cells of mobile phone networks, or in LANs, or in PONs, where the clock used for the upstream burst-mode
transmissions is the same that has been sent to the periphery with the continuous-mode downstream signal. When
the frequency is well known to the receiver, what is left to phase lock the clock recovery circuit is simply a
phase-aligner function.
Multipoint access network with continuous mode downstream and burst mode upstream.

practice/Burst transmission mode/Step response
of a phase aligner
The Phase Aligner (in all practical cases, a special type of 1st order CDR) used in the
burst-mode access loop of a single clock domain
The Phase Aligner is a CDR circuit that shifts the phase of the received signal so that it matches the phase of a
reference clock.
The simplest form of the phase aligner is the so-called "gated oscillator". A gated oscillator is inactive until the first
transition of the incoming burst is detected: at that moment the oscillator is immediately released to its free-running
state, starting with the phase that best matches the phase information of that first transition in the burst of pulses.
The gated oscillator is great for applications where the burst is very short and the signal strength high. It could be
found in the old Teleprinter systems, where one character at a time made up one burst, but it can also be seen in
modern applications like PON.
Another kind of phase aligner is the delay-locked loop.[1]
But the best compromise between fast acquisition and immunity from phase noise (jitter) can be found taking
advantage of all the initial transitions available in the incoming burst. The case has been well standardized for the
PON systems where the ITU-T Recommendation G.984.3 specifies that -after some initial pulses without transitions
for assessing the optical gain needed in the receiver for that burst- a preamble of pulses with the maximum possible
number of transitions is sent for the CDR phase acquisition. Then bits that shall be correctly regenerated begin, and
by then the CDR is expected to be already locked and to sample correctly the bits that then begin. This preamble on
Clock and data recovery/Design values used in practice/Burst transmission mode/Step response of a phase aligner 59
each packet is discarded by higher levels of the protocol stack.[2]

The phase aligner that implements the CDR of a modern PON OLT receiver is an interesting example.
In accordance to the definition of phase aligner, it shall incorporate the elastic buffer function, and the most elegant
topology sets the delay line in the CDR as the first stage of processing of the received signal, with the phase
comparator with the local system clock just behind. (Dieter Verhulst, et. al. 2004 is a good reference for further
reading on this aspect[3] ).
Topology of the OLT phase aligner. The received signal, delayed by the delay line, is recovered with (= regenerated by the sampling of) the
system clock. This approach (that the delay line is the first processing done on the received signal) inherently implements also the phase
alignment expected of an elastic buffer.
The circuit of the above figure is in fact a 1st order, type 1, control loop (= a first order PLL), and a complete CDR if
also the gray part in the figure above is included.
The response of such a loop to an abrupt step of the input phase is shown in the figure below, where x(t) represents
the input signal and err funct(t) represents the phase error of the CDR. (The step impulse response is in fact the
function that starts from zero and exponentially reaches the input function).
The burst mode receiving CDR is best made with a 1st order architecture
The simple architecture of the previous figure (PLL of first order and type 1) generates an exponential decay of the phase error after the input step.
The time constant is set by the attenuation in the feedback path.
This step response is the same also for all other 1st order CDRs, but can also be seen as the response of this type of
CDRs to the appearance of the incoming burst.
The local oscillator phase is uncorrelated with the phase of the incoming signal.
Before the incoming signal (= the burst) is detected, there exists a phase difference. In general, the amount of such
difference is unknown to the CDR before the burst is actually received.
As soon as the burst is detected, the phase difference between the first received pulse -delayed by the present length
of the delay line- and the closest transition of the local clock is computed by the phase comparator.
The value of the difference is fed into the control loop: the phase lock starts.
The evolution of the phase lock is described by the step impulse response. The height of the step, in radian, is the
value of the initial phase difference.
A second order loop would be less fit for the burst mode receiver, and this is evident if the unit step responses of the
first and of the second order loops are contrasted:
Responses to an abrupt phase step of 1st and 2nd order PLLs. All functions normalized for = = 1.
The figure clearly shows that the first order loop reacts first, without hesitation and effectively.
The second order loop seems to wait for additional confirmation of the need to respond.
The “prudence” of the 2nd order loop is a characteristic that can not be separated form the better ability of that loop
to reject high frequency jitter,
and this difference of performances is evident in the following figure (again with normalization for both
architectures to = 1).
Rejection of high frequency jitter of 1st and 2nd order PLLs.Note the 6dB/octave of the roll-off on one case, and the 12 dB/octave roll-off of the 2nd
order loop.All functions normalized for \omega_n = \tau = 1.
Discrete time representation is always more complex, sometimes more accurate

In the burst mode receiver, the number of input signal transitions (that are almost the same as the number of clock
cycles available for the acquisition of the lock) are not many.
For instance, in the case of the 2.5 Gbps US/ 1.25 Gbps DS GPON, just 20 to 50 transitions are truly available for the
OLT CDR to lock the phase of an incoming burst.
Is a discrete time representation of our models to be used in order to ensure accuracy?
Luckily, in the case of the regenerator CDRs, that are in all practical cases associated with continuous mode
operation, long acquisition times and tight jitter transfer bandwidth, all the modeling presented so far is
adequate and accurate.
Let’s see the case of the PON OLT receiver, where acquisition times are at the other extreme of the range (=
very short).
The PON OLT receiver circuit described above becomes slightly different in a discrete time representation [4] :
Topology of the OLT phase aligner, in a discrete time implementation.
The unit step response changes as well, but not so fundamentally, as the following figure shows us:
Response to a step phase change of 2.5 radian of the discrete time systems described above, and of a continuous-time similar model.
A continuous time representation is accurate enough also in this case, provided the scale factor of the clock
frequencies of the two simulations is taken properly into account!
This result should come as no surprise, if we consider that the CDR function is essentially an averaging function of
subsequent phase information coming as a discrete time series.
The need to filter severely in some cases (regenerator CDRs) makes discrete time modeling a largely
unnecessary complication.
In the case of burst mode receivers instead, the reaction of the control system has to be so fast as to be
executed within a few clock cycles. In this case as well, luckily, the simplicity of the architecture makes the
discrete time system behave not differently from a system where the phase information was inputted (and the
whole system operated) continuously.
References
[1] Wikipedia: delay-locked loop
[2] Serial Programming/Forming Data Packets
[3] Dieter Verhulst, Xin Yin, Johan Bauwelinck, Peter Ossieur, Xing-Zhi Qiu and Jan Vandewege (the INTEC team of Ghent University), “A
robust phase detector for 1.25Gbit/s burst mode data recovery”, IEICE Electronic Express, Vol. 1, No. 18, pp.562-567, (2004). http:/ / www.
jstage. jst. go. jp/ article/ elex/ 1/ 18/ 1_562/ _article
[4] Alan V. Oppenheim, Ronald W. Schafer, John R. Buck : Discrete-Time Signal Processing, Prentice Hall, ISBN 0-13-754920-2
Clock and data recovery/Miscellanea

Jitter generation
The source of jitter that probably most often troubles practical circuits, is the one coming from supply noise inside
the CMos circuitry of the CDR itself.
The internal supply rails inside an IC are affected by the high current transients generated inside output buffers,
clock trees and other large CMos stages inside the IC itself, even if such blocks are not part of the CDR proper.
Those large current spikes will cause small ripple waves on the voltage supply lines.
Other CMos stages, inside the receive paths and inside the CDR proper, will see –as a result of the supply ripples-
their switching threshold ripple by exactly half the amount of the supply ripple.
The rise and fall edges of the waveforms inside these CMos stages are not perfectly steep, but exhibit a certain non
negligible slope.
It is easy to see that a change of the threshold during the edge transition corresponds exactly to an earlier (or to a
later) switching of the CMos stage: this time change, occurring almost at random at different transitions, will be
nothing but a generated jitter.
It can be minimised (and should be minimised) by careful design and layout of the supply scheme inside the IC.
Just two possible architectures? Not by chance!

There are just two CDR architectures that are used in actuality. They can be identified by the order of their jitter
transfer functions:
1. first order, for the phase aligner CDR, (that was introduced at the beginning of the book as: 1. a first order loop
for the burst-mode CDR)
2. second order, for the regenerator CDR, (that was introduced at the beginning of the book as: 2.a second order
loop for the slave CDR).
This “a posteriori” result can be associated elegantly with an “a priori” mathematical theory.
It is known that any possible transfer function can be well approximated by a rational function of the complex
frequency “s” (i.e. by the ratio of two polynomials in s).
A rational function in turn can be represented by a partial fraction expansion:
F(s) = = =
F(s) = = more complex terms
(the denominator polynomial has roots equal to , roots equal to , ... , roots equal to where
= n)
which –in simpler terms- means that a CDR can be made with a first order loop, or with a second order loop,
or with a product/sum of them.
Common engineering sense dictates that a design be “as simple as it can be made”. Therefore just one of the simplest
possibilities will be chosen:
• a constant is a flat jitter transfer function, and not a real choice;
• a first order (jitter) transfer function will be the choice when the prime considerations are a quick response
(=acquisition) and the maximum resilience to parameter drifts and non-linearities;
• a second order (jitter) transfer function will be the choice when the steady state error (d.c. phase error) and the
tight bandwidth (jitter filtering) are prime concerns, while a slower step response and less resilience to parameter
variations and non-linearities are acceptable;
• any other (inevitably more complex) possibility does not offer much more performances while it makes the circuit
more sensitive (often too sensitive) to parameter variations and to small non-linearities.
PLL Simulator
What it is.
This simulator is a free software based on a simple spreadsheet:[where the spreadsheet can be found and downloaded
[1]
].
It runs on any standard PC and simulates the acquisition phase of a PLL inside a CDR circuit.
It simulates the signals inside a 2nd order PLL circuit.
Non linearity of the phase comparator, as well as of the filter (or of the controlled oscillator) range is taken into
account.
Hardware platform
It has been developed on a Dell INSPIRON ME051, with ® Pentium® M processor, 1.70 GHz, 1.99 GB RAM,
Microsoft Windows XP Professional, 2002 versions with Service Pack 2.
Software platform
This simulator file has been developed with: OpenOffice.org Calc
OpenOffice.org is a free open software that can be downloaded from www.OpenOffice.org
What it does
It accepts a string of input parameters and produces as output some other parameters and three diagrams.
Input parameters
• Comparator range of linear operation
• R1, R2, R3, C
• VCO gain
• input ramp and input sinusoid.
The input parameters define both the characteristics of a second order PLL and the characteristics of its input
signal. They are formatted in a single row of cells for ease of store and retrieval.
Each parameter can be varied independently from the others, to simulate any case of interest.
Possible sets of input parameters for interesting cases are provided. Each set can be copied and pasted in a
single operation, to see the simulation that corresponds to it.
Output
Three items of information are produced:
• The main characteristics of the loop defined by the input parameters, in the form of quantities like ωn, ζ, …
• A time diagram of the quantities (phases and voltages) of the loop nodes during the acquisition phase. This
diagram is in fact the main output of the simulation.
• The loop Jitter Transfer Function and the Transfer Function of the loop filter, in the form of diagrams of
magnitude versus angular frequency.
These two diagrams can be useful for understanding better both:
1. the operation of the loop under consideration and
2. the simulation result.
Purpose
The purpose of the simulator file is essentially didactic, to:
1. identify and point out the fundamental blocks of the PLL, and consequently of the clock recovery part of the
CDR. Each block needs to be identified in its function, its input/output connections, its characteristic and its main
limitations (= its inevitable non-linearities).
The simulated structure is the complete structure of a 2nd order PLL.
The filter is the full feature 1st order filter, represented as an operational amplifier with three resistors
and one capacitor.
Special cases are:
• If C = 0, the filter is a flat gain stage, and the PLL degenerates into a 1st order PLL;
• If R3 = 0, the filter has just a single pole. This is the classic case of a 2nd order PLL, with a jitter transfer
function that has no zeros;
• If R2 = 0, the filter is a low pass still, but with a zero at the origin.
1. understand the overall PLL (= clock recovery) operation.
2. get familiar with the formulas and equations that constitute the mathematical model (and with their
implementation in the simulator spreadsheet).
3. introduce the concept of discrete time, as actual PLLs are often made with digital, discrete-time circuitry. In
fact this tool:
• only uses 500 time steps for the simulation,
• uses difference equations in form of recurrence relations. See also: http://en.wikipedia.org/wiki/
Difference_equations for the formulas used in the simulation of the loop filter and of the VCO.
Copy of the simulator can be downloaded jumping to the [page before the page where the actual download can be
requested [1]]
How it is made
The sequence of 500 spreadsheet rows corresponds to subsequent instants, or time steps in the “discrete time”
representation of the quantities that are simulated.
The columns are used to represent each one a different quantity (the phase or the voltage of the signal at a certain
node of the simulated circuit).
More precisely, each cell contains the value that the quantity assumes at the corresponding instant.
Each quantity value depends on the time instant (i.e. on the row index of the cell that contains it) and on the values of
other quantities in that instant and in previous instants (in this case the present instant and just the previous instant, as
the filter is a first order system).
In order to avoid problems of circular computation, the quantity columns are located so that every quantity depends
only on its past values and on values of other quantities located only at the same level or above and only to the left.
The location “at the same level or above” represents causality in time. Only present or past values of other quantities
influence the present value of the quantity to be computed.
The location “to the left” represents causality in the propagation of signals inside the filter circuit. In fact, the order of
columns corresponds to the signal flow through the PLL forward path.
To close the loop, the (unity) feedback in the loop is obtained as an auxiliary quantity equal to the output signal, but
just delayed by one time step.
Phase Comparator
It implements a sawtooth characteristic a shown in the figure below:
Characteristic of a phase comparator. The transition density of the incoming signal is assumed to be 100%. More about this choice in:[ Clock and
[2]
data recovery: The phase comparator ]
The limited range of the comparator is the first of the two (strong) non-linearities in this simulator.
Loop Filter
This is a generic first order linear filter, with one zero and one pole. Its output is additionally clamped brutally to +/-
1 V.
The reference used to derive the equations is a possible implementation of such filter, based on an operational
amplifier, 3 resistors and one capacitor.
The filter transfer function can be obtained using the concept that the inverting input of an Op Amp stays at the same
voltage of the other input, and that its input impedance is infinite:
x(s)/R1 = y(s)/R2 + y(s)/(R3+1/sC)

y(s)/x(s) = [R2(sCR3 + 1)] / [R1(sCR2 +sCR3 + 1)]
To have a spreadsheet simulate the filter, we consider that time is discrete, and every row of the spreadsheet
represents one instant in a sequence.
Let's use the index of the row 1,2,3,... as the time independent variable.
Then a sequence x[k] can be used as the representation of the input signal and a sequence y[k] as the representation
of the output signal.
A description of the first order filter with difference equations allows the computation of every y[k] from y[k-1], x[k]
and x[k-1].
(A system of higher order would need, for the computation of the output sample, correspondingly older
samples from the input and the output sequences).
(For instance, a second order system would require y[k-1], y[k-2], x[k], x[k-1] and x[k-2] for the
computation of y[k]).
In the case of our first order filter, let's first use the Capacitor equation:
ΔV = (I*Δt)/C
vC[k] – vC[k-1] = iC[k]/C
iC[k] = C(vC[k] – vC[k-1]) (1)
(As the capacitor is the only element with memory, it is the only one that is described by a first order
difference equation.)
As a second equation the Kirchoff's First Law applied to the node of the inverting input (no current
flows into the inverting input of the Op Amp):
iC[k] = x[k]/R1 – y[k]/R2 Note: iC ≡ i3 (2)
The third equation shall be the Kirchoff's Second Law applied to the loop of the Op Amp output
network:
vC[k] = y[k] – R3iC (3)
Combining (1), (2) and (3), we can solve with respect to y[k], eliminate the intermediate variables iC[k]
and vC[k], and get the formula for the spreadsheet:
x[n]/R1 = y[n]/(R2) + y[n]/(R3 + ZC)
x[n]/R1 – y[n]/R2 = C(y[n] – R3iC[n] – (y[n-1] – R3iC[n-1]))
x[n]/R1 – y[n]/R2 = y[n]C - R3C(x[n]/R1 – y[n]/R2) – y[n-1]C + CR3( x[n-1]/R1 – y[n-1]/R2)
– y[n]/R2- y[n]C- y[n]R3C/R2 = -x[n]/R1 - R3C(x[n]/R1 -y[n-1]C + CR3x[n-1]/R1 – y[n-1]CR3/R2
y[n]+y[n]R2 C+y[n]R3C= x[n]R2/R1 +R3C R2 x[n]/R1 +y[n-1]R2C -CR3x[n-1]R2/R1 +y[n-1]CR3
'
y[n] = {y[n-1](CR2+CR3) + ( R2/R1)x[n](1+ R3C) - ( R2/R1)x[n-1](R3C)}/(1+ R2C+ R3C)
'
The clamping of the filter output is the second of the two (strong) non-linearities in the simulator. No other (weak)
linearities are included in it.
The limitation of the range is meant to represent the physical limitation of the filter itself (if made with analog
circuitry, the limit is the voltage swing possible for its output stage; if digital, the limit will be set by the range of the
numbers that can be written inside its registers).
The clamping of the simulated filter can also be used to take into account the limitations of the VCO frequency range
(whichever intervenes first, the filter or the VCO limit).
This saturation range, set at +/- 1 V, can be modified and set to +/- Range by changing the formulas in the
column “Saturated Filter Output” from:
=IF(ABS(F9)>1;SIGN(F9);F9)
to:
=IF(ABS(F9)>Range;SIGN(F9)*Range;F9)
and then propagating the change to the bottom end of the column.
Voltage Controlled Oscillator

The VCO is a voltage-to-frequency converter. The simulator first accumulates the output samples of the filter
(=integration), and then converts from accumulated voltage to phase with the factor specified in the input string as
“VCO gain”.
Feedback
The feedback signal is just the VCO output, but delayed by one time step. This is necessary to avoid errors of
circular reference in the spreadsheet calculation.
Limitations
This simulator is a simple tool and is correspondingly limited.
Necessary cautions are related to:
The frequency of the received line signal does not appear.
The only frequencies that appear are the frequencies that characterize the loop operation. They are
the only ones that are simulated.
The line frequency shall always be -for the cases you want to simulate - significantly higher
(typically 20 or more times higher) than any frequency significant for the loop operation.
The simulator only uses 500 time steps.
The characteristic loop frequency (= n) shall be kept between 0.2 and 0.01, by choosing adequate
sets of input parameters).
The actual n of any loop of practical interest would be much higher.
Scaling is always needed to reconcile the frequencies of the simulator to the frequencies of the actual
circuit.
A PLL is simulated, not an entire CDR. The simulator will show events like :
stuttering of the phase error as the input sinusoidal variations (that represent mostly the intersymbol
interference jitter)
trick the phase comparator back and forth across the tooth edges of the sawtooth characteristic;
clock slips, that are easily detected when the VCO tracks a signal parallel to the input signal, but
with a gap that is multiple of the comparator range;
The simulator will not be able to show:
bit errors, because the simulator does not consider the input bit stream , but only its phase;
loop gain variations that are consequence of the input transition density.
This is because of the same reason already mentioned for the point above.
See: CDR phase comparator [3] for more considerations.
To simulate a transition density lower than 1, the magnitude of the filter transfer function should be
reduced by the same factor (leaving the filter clamp where it is).
In spite of the many limitations, this tool is valid and complex enough to assist the average electronic engineer
towards a better comprehension of the PLL operation inside a CDR.
Burst-mode upstream: 20 to 50 transitions for locking into an incoming burst.

Case of the 2.5 Gbps US/ 1.25 Gbps DS GPON
[ http://www.itu.int/rec/T-REC-G.984.2/en ITU-T Rec. G.984.2 ]
The example of GPON is more significant than EPON could be, because:
• GPON specs are more demanding in the burst acquisition phase, and
• GPON specifications define the fastest burst-mode receiver (in acquisition) that be still good in locked state
performances, at the frequencies of the optical access applications.
Physical Layer Overhead

In the GPON defined with 2.5 Gbps downstream and 1.25 Gbps upstream, the upstream burst is allowed as
many as 96 bits for the so-called Physical Layer Overhead (Plo).
These bits are meant to allow for the detection of the burst appearance, for the phase lock of the CDR circuit
and for the precise identification of the beginning of the reception of information bits of the burst (= burst
delimiting function).
Allocation of the bits of the Plo to the OLT functions

The first 32 bit times of the 96 are allocated to generate the guard time between bursts.
16 of the 32 are allocated to mask the transient of extinction of the remote transmitter of the previous
burst.
The following 16 are allocated to give margin against the transient of activation of the remote
transmitter that takes over and sends the new burst.
The last 20 bits of the 96 are used for the burst delimiting function.
During the intermediate 44 bits of the 96, the remote transmitter in the ONT sends a preamble pattern that
provides maximal transition density for fast level and clock recovery functions.
Depending on implementation choices the OLT receiver may be allowed as many as 50 transitions since the
start of the burst (p1=0, p2=0, p3= 10 repeated 22 times, plus some initial pulses of the delimiter), or as little
as 20 transitions, to achieve lock. The figure that follows shows an actual possible transient in the latter case.
References
[1] https:/ / cid-a0b14219829a3f6f. skydrive. live. com/ browse. aspx/ PaB%20in%20Windows%20Live%20SkyDrive/
Simulator%20to%20download?view=details|
[2] http:/ / en. wikibooks. org/ wiki/ Clock_and_data_recovery/ Structures_and_types_of_CDRs/ The_CDR_phase_comparator|
[3] http:/ / en. wikibooks. org/ wiki/ Clock_and_data_recovery/ Structures_and_types_of_CDRs/ The_CDR_phase_comparator|The
Clock and data recovery/Conclusion

Many things have changed..
Many things have evolved in the domain of CDRs during the recent decades, and –as a consequence- so has the
work of the CDR engineers.
• Unit cost. The CDR is often just a small section of a complex but tiny silicon chip. More than one CDR can be
found inside the chip, and it may even happen that a series of almost identical ones, differing slightly in some
critical circuit elements, are made inside the same chip. Just one of those CDRs , will actually be used. The
characteristics of certain critical circuit elements can not be chosen exactly in the first place because of their
manufacturing variability. The one in the series that will come out of production better balanced is the one that is
chosen. The other are left unused with little concern for their cost that is practically negligible.
• Quantity manufactured of each design. On one side the unit cost declines with the improvement of the
manufacturing technology, on the other each design happens to be manufactured in larger and larger quantities,
following the trend of modern electronics.
• Circuit complexity. Each circuit element can today be implemented using blocks of really complex circuitry, and
there are more and more cases when the (slow speed) functions are made by dedicated software rather than by
hardware.
• Frequency. From MHz to GHz. The widespread use of media with THz of useful bandwidth, like the optical fiber,
opens every day possibilities of higher speed applications. In parallel, the precision of the reference frequency has
evolved from hundreds to tens of ppm, and consumer electronics with frequency accuracy of the reference
oscillator below 1 ppm are becoming common use.
• Application specific CDR. General purpose CDRs have disappeared. In new systems and equipment, the CDR is
defined for a very precise application. If the application is subject to change with the operating conditions of the
equipment, more CDRs are present and the one best fitting the requirement is activated at any moment.
• CAD tool versatility. For high level description, synthesis, simulations as well as for design for testability and for
automatic generation of test software of the resulting circuit.
• Test equipment versatility. The circuit can be stimulated, checked, characterized, troubleshooted to an extent that
was unconceivable not many years ago.
Engineers can become lazy or neglect theory

The CDR engineer has become more and more dependent on predefined solutions of parts of his circuits, on software
for simulation and circuit synthesis, on characterization and test equipment.
The engineer becomes specialized for just one task in the complex organization that deploys so many CDRs in the
world.
The negative side of all this is the possibility to lose the ability to understand the circuit behavior. The need for an
engineer to understand the CDR with its own intelligence may be neglected, and just hardware and software tools
may be relied upon.
Such extremes may be rare, but it is not infrequent to find good technical literature on CDRs that could be improved
if the author had a better knowledge and more command of the fundamental mathematical models.
Just two models are needed for a solid background

“All models are wrong; some models are useful” (W. Edwards Deming)
In the case of CDRs, it might be reworded as: “All CDR models are wrong; there are two models that are useful”
Many problems can be solved better, or quicker –if not avoided altogether-, if the engineer is familiar with and uses
two simple mathematical models, because the fundamental behavior of every CDR can be referred to either of them:
1. The phase aligner (1st type, 1st order)
2. The regenerator (1st type, 2nd order).
Watches in a shop window: hardly two in synch!
Article Sources and Contributors 73
Article Sources and Contributors

Clock and data recovery Source: http://en.wikibooks.org/w/index.php?oldid=1857824 Contributors: Adrignola, BORGATO Pierandrea, Darklama, Panic2k4, Thenub314, Whiteknight,
Wknight8111
Clock and data recovery/Introduction Source: http://en.wikibooks.org/w/index.php?oldid=1630016 Contributors: BORGATO Pierandrea, Panic2k4, 1 anonymous edits
Clock and data recovery/Introduction/Definition of (phase) jitter Source: http://en.wikibooks.org/w/index.php?oldid=1662691 Contributors: BORGATO Pierandrea, Kwi, 3 anonymous
edits
Clock and data recovery/Introduction/Jitter is far from sinusoidal.. Source: http://en.wikibooks.org/w/index.php?oldid=1473922 Contributors: BORGATO Pierandrea
Clock and data recovery/Introduction/Models can only be linear.. Source: http://en.wikibooks.org/w/index.php?oldid=1632982 Contributors: BORGATO Pierandrea
Clock and data recovery/Introduction/Acquisition, tracking and jitter performances Source: http://en.wikibooks.org/w/index.php?oldid=1596446 Contributors: BORGATO Pierandrea
Clock and data recovery/Buffer Memory (Elastic Buffer) Source: http://en.wikibooks.org/w/index.php?oldid=1536714 Contributors: BORGATO Pierandrea
Clock and data recovery/Buffer Memory (Elastic Buffer)/Clock domains Source: http://en.wikibooks.org/w/index.php?oldid=1467336 Contributors: BORGATO Pierandrea, 1 anonymous
edits
Clock and data recovery/Buffer Memory (Elastic Buffer)/Overflow and Underflow Source: http://en.wikibooks.org/w/index.php?oldid=1467339 Contributors: BORGATO Pierandrea
Clock and data recovery/Buffer Memory (Elastic Buffer)/Transit delay inside the elastic buffer Source: http://en.wikibooks.org/w/index.php?oldid=1467567 Contributors: BORGATO
Pierandrea
Clock and data recovery/Structures and types of CDRs Source: http://en.wikibooks.org/w/index.php?oldid=1903268 Contributors: BORGATO Pierandrea, DavidCary, 1 anonymous edits
Clock and data recovery/Structures and types of CDRs/The CDR phase comparator Source: http://en.wikibooks.org/w/index.php?oldid=1616833 Contributors: BORGATO Pierandrea
Clock and data recovery/Structures and types of CDRs/Examples Source: http://en.wikibooks.org/w/index.php?oldid=1569900 Contributors: BORGATO Pierandrea, 4 anonymous edits
Clock and data recovery/Structures and types of CDRs/The jitter tolerance function Source: http://en.wikibooks.org/w/index.php?oldid=1473623 Contributors: BORGATO Pierandrea, 2
anonymous edits
Clock and data recovery/Structures and types of CDRs/The (slave) CDR based on a second order PLL Source: http://en.wikibooks.org/w/index.php?oldid=1695547 Contributors:
BORGATO Pierandrea, Borgato Pierandrea
Clock and data recovery/Structures and types of CDRs/The (slave) CDR based on a second order PLL/The jitter transfer function Source:
http://en.wikibooks.org/w/index.php?oldid=1473689 Contributors: BORGATO Pierandrea, 1 anonymous edits
Clock and data recovery/Structures and types of CDRs/The (slave) CDR based on a second order PLL/The error function Source: http://en.wikibooks.org/w/index.php?oldid=1563970
Contributors: BORGATO Pierandrea
Clock and data recovery/Structures and types of CDRs/The (slave) CDR based on a second order PLL/The jitter tolerance function Source:
http://en.wikibooks.org/w/index.php?oldid=1527051 Contributors: BORGATO Pierandrea
Clock and data recovery/Structures and types of CDRs/The (slave) CDR based on a second order PLL/The unit step response Source:
Clock and data recovery/Structures and types of CDRs/The (slave) CDR based on a second order PLL/The jitter transfer and tolerance of two cascaded CDRs Source:
Clock and data recovery/Design values used in practice Source: http://en.wikibooks.org/w/index.php?oldid=1563967 Contributors: BORGATO Pierandrea, DavidCary
Clock and data recovery/Design values used in practice/Continuous transmission mode Source: http://en.wikibooks.org/w/index.php?oldid=1563968 Contributors: BORGATO Pierandrea
Clock and data recovery/Design values used in practice/Burst transmission mode Source: http://en.wikibooks.org/w/index.php?oldid=1473895 Contributors: BORGATO Pierandrea, Swift
Clock and data recovery/Design values used in practice/Burst transmission mode/Step response of a phase aligner Source: http://en.wikibooks.org/w/index.php?oldid=1454489
Contributors: BORGATO Pierandrea, DavidCary, 1 anonymous edits
Clock and data recovery/Miscellanea Source: http://en.wikibooks.org/w/index.php?oldid=1626329 Contributors: BORGATO Pierandrea, Van der Hoorn
Clock and data recovery/Conclusion Source: http://en.wikibooks.org/w/index.php?oldid=1586016 Contributors: BORGATO Pierandrea

Image Sources, Licenses and Contributors

Image:Clockand data recovery.jpg Source: http://en.wikibooks.org/w/index.php?title=File:Clockand_data_recovery.jpg License: GNU Free Documentation License Contributors:
User:BORGATO Pierandrea
Image:Signals on the scope.png Source: http://en.wikibooks.org/w/index.php?title=File:Signals_on_the_scope.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:eye diagram etymology.png Source: http://en.wikibooks.org/w/index.php?title=File:Eye_diagram_etymology.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:Multilevel eye diagrams.png Source: http://en.wikibooks.org/w/index.php?title=File:Multilevel_eye_diagrams.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:squared eye.png Source: http://en.wikibooks.org/w/index.php?title=File:Squared_eye.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:x(t) is the jitter.png Source: http://en.wikibooks.org/w/index.php?title=File:X(t)_is_the_jitter.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:Just_two_architectures.png Source: http://en.wikibooks.org/w/index.php?title=File:Just_two_architectures.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:Acquisition 1st order.png Source: http://en.wikibooks.org/w/index.php?title=File:Acquisition_1st_order.png License: Creative Commons Attribution-Sharealike 3.0 Contributors:
Original uploader was BORGATO Pierandrea at en.wikibooks
Image:Acquisition after some slips back and forth total lock delay 2 pi.png Source:
http://en.wikibooks.org/w/index.php?title=File:Acquisition_after_some_slips_back_and_forth_total_lock_delay_2_pi.png License: Creative Commons Attribution-Sharealike 3.0 Contributors:
Original uploader was BORGATO Pierandrea at en.wikibooks
Image:Unstable acquisition with periodic slips.png Source: http://en.wikibooks.org/w/index.php?title=File:Unstable_acquisition_with_periodic_slips.png License: Creative Commons
Attribution-Sharealike 3.0 Contributors: Original uploader was BORGATO Pierandrea at en.wikibooks
Image:Buffer_memory.png Source: http://en.wikibooks.org/w/index.php?title=File:Buffer_memory.png License: Public Domain Contributors: User:BORGATO Pierandrea,
User:WikimediaNotifier
Image:Clock domains.png Source: http://en.wikibooks.org/w/index.php?title=File:Clock_domains.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:Disconnected clock domain.png Source: http://en.wikibooks.org/w/index.php?title=File:Disconnected_clock_domain.png License: Public Domain Contributors: User:BORGATO
Pierandrea
Image:Buffer between clock domains.png Source: http://en.wikibooks.org/w/index.php?title=File:Buffer_between_clock_domains.png License: Public Domain Contributors:
Image:Clock_paths_in_the_same_domain.png Source: http://en.wikibooks.org/w/index.php?title=File:Clock_paths_in_the_same_domain.png License: Public Domain Contributors:
Image:CDR_basic_architecture.png Source: http://en.wikibooks.org/w/index.php?title=File:CDR_basic_architecture.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:Exor_phase_comparator.png Source: http://en.wikibooks.org/w/index.php?title=File:Exor_phase_comparator.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:Exor_phase_comparator_of_clocks.png Source: http://en.wikibooks.org/w/index.php?title=File:Exor_phase_comparator_of_clocks.png License: Public Domain Contributors: Original
uploader was BORGATO Pierandrea at en.wikibooks
Image:Exor_and_FF_comparator_for_NRZ_data.png Source: http://en.wikibooks.org/w/index.php?title=File:Exor_and_FF_comparator_for_NRZ_data.png License: Public Domain
Contributors: Original uploader was BORGATO Pierandrea at en.wikibooks
Image:Linear phase comparator for NRZ data input var gain.png Source: http://en.wikibooks.org/w/index.php?title=File:Linear_phase_comparator_for_NRZ_data_input_var_gain.png
License: Public Domain Contributors: Original uploader was BORGATO Pierandrea at en.wikibooks
Image:101010 Ph Comp Characteristic.png Source: http://en.wikibooks.org/w/index.php?title=File:101010_Ph_Comp_Characteristic.png License: GNU Free Documentation License
Image:Bang-Bang_phase_detector.png Source: http://en.wikibooks.org/w/index.php?title=File:Bang-Bang_phase_detector.png License: Public Domain Contributors: Original uploader was
BORGATO Pierandrea at en.wikibooks
Image:CDR_architectures_type_0_first_order.png Source: http://en.wikibooks.org/w/index.php?title=File:CDR_architectures_type_0_first_order.png License: Public Domain Contributors:
Image:1st order type 0 ustep response.png Source: http://en.wikibooks.org/w/index.php?title=File:1st_order_type_0_ustep_response.png License: Public Domain Contributors:
Image:1st order type 0 jitter transfer.png Source: http://en.wikibooks.org/w/index.php?title=File:1st_order_type_0_jitter_transfer.png License: Public Domain Contributors:
Image:1st order type 0 jitter tolerance.png Source: http://en.wikibooks.org/w/index.php?title=File:1st_order_type_0_jitter_tolerance.png License: Public Domain Contributors:
Image:CDR architecture or1 ty1 uf nofilt.png Source: http://en.wikibooks.org/w/index.php?title=File:CDR_architecture_or1_ty1_uf_nofilt.png License: Public Domain Contributors:
Image:Ustep 1st iord ty 1 uf nofilt Quantities.png Source: http://en.wikibooks.org/w/index.php?title=File:Ustep_1st_iord_ty_1_uf_nofilt_Quantities.png License: Public Domain
Image:Jtol 1st iord ty 1 uf nofilt Quantities.png Source: http://en.wikibooks.org/w/index.php?title=File:Jtol_1st_iord_ty_1_uf_nofilt_Quantities.png License: Public Domain Contributors:
Image:Jtransfer 1st iord ty 1 uf nofilt Quantities.png Source: http://en.wikibooks.org/w/index.php?title=File:Jtransfer_1st_iord_ty_1_uf_nofilt_Quantities.png License: Public Domain
Contributors: User:BORGATO Pierandrea
Image:CDR architectures or1 ty1 phase align.png Source: http://en.wikibooks.org/w/index.php?title=File:CDR_architectures_or1_ty1_phase_align.png License: Public Domain
Image:Ustep_1st_iord_ty_1_uf_nofilt_Quantities.png Source: http://en.wikibooks.org/w/index.php?title=File:Ustep_1st_iord_ty_1_uf_nofilt_Quantities.png License: Public Domain
Image:Jtol or1 ty1 phal.png Source: http://en.wikibooks.org/w/index.php?title=File:Jtol_or1_ty1_phal.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:Jtransf or1 ty1 phal.png Source: http://en.wikibooks.org/w/index.php?title=File:Jtransf_or1_ty1_phal.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:Type 1 2nd order slave.png Source: http://en.wikibooks.org/w/index.php?title=File:Type_1_2nd_order_slave.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:USResponse o2 ty1 slave.png Source: http://en.wikibooks.org/w/index.php?title=File:USResponse_o2_ty1_slave.png License: Public Domain Contributors: User:BORGATO
Pierandrea
Image:Jtolerance o2 ty1 slave.png Source: http://en.wikibooks.org/w/index.php?title=File:Jtolerance_o2_ty1_slave.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:Jtransfer o2 ty1 slave.png Source: http://en.wikibooks.org/w/index.php?title=File:Jtransfer_o2_ty1_slave.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:Type 1 2nd order phal.png Source: http://en.wikibooks.org/w/index.php?title=File:Type_1_2nd_order_phal.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:USResponse o2 ty1 phal.png Source: http://en.wikibooks.org/w/index.php?title=File:USResponse_o2_ty1_phal.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:Jtolerance o2 ty1 phal.png Source: http://en.wikibooks.org/w/index.php?title=File:Jtolerance_o2_ty1_phal.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:Jtransfer o2 ty1 phal.png Source: http://en.wikibooks.org/w/index.php?title=File:Jtransfer_o2_ty1_phal.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:1st order loop - pulse response.png Source: http://en.wikibooks.org/w/index.php?title=File:1st_order_loop_-_pulse_response.png License: Creative Commons Attribution-Sharealike
3.0 Contributors: User:BORGATO Pierandrea
Image:CDR std 2nd PLL n variables.png Source: http://en.wikibooks.org/w/index.php?title=File:CDR_std_2nd_PLL_n_variables.png License: Public Domain Contributors: Original
uploader was BORGATO Pierandrea at en.wikibooks
Image:Jitter transfer magnitude plot.png Source: http://en.wikibooks.org/w/index.php?title=File:Jitter_transfer_magnitude_plot.png License: Public Domain Contributors: User:BORGATO
Pierandrea
Image:Phase error magnitude plot.png Source: http://en.wikibooks.org/w/index.php?title=File:Phase_error_magnitude_plot.png License: Public Domain Contributors: User:BORGATO
Pierandrea
Image:Jitter tolerance magnitude plot.png Source: http://en.wikibooks.org/w/index.php?title=File:Jitter_tolerance_magnitude_plot.png License: Public Domain Contributors:
Image:Point of minimum.png Source: http://en.wikibooks.org/w/index.php?title=File:Point_of_minimum.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:Unit step response.png Source: http://en.wikibooks.org/w/index.php?title=File:Unit_step_response.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:CDRs cascade.png Source: http://en.wikibooks.org/w/index.php?title=File:CDRs_cascade.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:CDRs cascade with improved tolerance.png Source: http://en.wikibooks.org/w/index.php?title=File:CDRs_cascade_with_improved_tolerance.png License: GNU Free Documentation
License Contributors: User:BORGATO Pierandrea
Image:multipoint 2.png Source: http://en.wikibooks.org/w/index.php?title=File:Multipoint_2.png License: Public Domain Contributors: User:BORGATO Pierandrea
Image:PON_OLT_Phase_aligner.png Source: http://en.wikibooks.org/w/index.php?title=File:PON_OLT_Phase_aligner.png License: Public Domain Contributors: User:BORGATO
Pierandrea
Image:Phase_aligner_step_response.png Source: http://en.wikibooks.org/w/index.php?title=File:Phase_aligner_step_response.png License: Public Domain Contributors: User:BORGATO
Pierandrea
Image: 1st n 2nd USR contrasted.png Source: http://en.wikibooks.org/w/index.php?title=File:1st_n_2nd_USR_contrasted.png License: Public Domain Contributors: User:BORGATO
Pierandrea
Image: 1st n 2nd JTF contrasted.png Source: http://en.wikibooks.org/w/index.php?title=File:1st_n_2nd_JTF_contrasted.png License: Public Domain Contributors: User:BORGATO
Pierandrea
Image: PON OLT Phase aligner discrete time.png Source: http://en.wikibooks.org/w/index.php?title=File:PON_OLT_Phase_aligner_discrete_time.png License: Public Domain
Image: PhAl response continuous and discrete.png Source: http://en.wikibooks.org/w/index.php?title=File:PhAl_response_continuous_and_discrete.png License: Public Domain
Image:Schematic of simulated PLL.png Source: http://en.wikibooks.org/w/index.php?title=File:Schematic_of_simulated_PLL.png License: Creative Commons Attribution-Sharealike 3.0
Image:1st order filter based on OpAmp Rs n C.png Source: http://en.wikibooks.org/w/index.php?title=File:1st_order_filter_based_on_OpAmp_Rs_n_C.png License: GNU Free
Documentation License Contributors: Original uploader was BORGATO Pierandrea at en.wikibooks
Image:Clocks in a shop window 2.jpg Source: http://en.wikibooks.org/w/index.php?title=File:Clocks_in_a_shop_window_2.jpg License: Creative Commons Attribution-Sharealike 3.0
Contributors: BORGATO Pierandrea
License 76
License
Creative Commons Attribution-Share Alike 3.0 Unported
http:/ / creativecommons. org/ licenses/ by-sa/ 3. 0/

Wikibooks CDR

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Wikibooks CDR

Uploaded by

Copyright:

Available Formats

Contents

Clock and data recovery

This book provides the electronic engineer with the

- what the CDR function and structure are

- where a CDR is used in a communication

- the mathematical models (just two!) needed to

Prior knowledge of calculus, and at least some

Clock and data recovery/Introduction

Clock and data recovery/Introduction/Definition

Signals on the scope

3-level eye diagram

Jitter (and wander) definition

Clock and data recovery/Introduction/Jitter is far

Clock and data recovery/Introduction/Models can

Simulators can include some non-linearities

Just two architectures are of practical use

Clock and data

Clock and data recovery/Buffer Memory (Elastic

The Buffer Memory. (Up to about 20 bits of

Clock and data recovery/Buffer Memory (Elastic

The domain of a master clock

If a slave gets disconnected from its master, a new domain is created.

A slave creates his own domain

A buffer inserted between clock domains

Clock and data recovery/Buffer Memory (Elastic

Clock and data recovery/Buffer Memory (Elastic

suffers along the external loop (with 9 regenerations):

Clock and data recovery/Structures and types of

Importance of good reference models

Essential parts of a CDR

Order and type of a CDR

Clock and data recovery/Structures and types of

Inevitable non-linearities of the phase comparator

Uneven density of transitions in the reference signal

NRZ-to-Clock phase comparator

Deliberately non-linear phase comparator

Clock and data recovery/Structures and types of

1st order, type 0

and it tells us a few things:

The unit step response

1st order, type 1

Oscillator controlled in frequency ("first order slave CDR")

This architecture clearly shows:

Addition of the complementary delay ("phase aligner")

This example is of particular interest because:

• offers the inherent elastic buffer feature typical of phase aligners.

2nd order, type 1

Oscillator controlled in frequency ("slave CDR")

2nd order type 1 : the slave CDR

The structure is depicted in the above figure.

• Unit step response

adjusted) when the lock-in phase of the system is of prime importance.

Addition of the complementary delay ("second order phase aligner")

• Unit step response

Tolerance(j ) = Magn |x(jω)| =

Magn |x(jω) − y(jω)| =

Magn |x(jω)| = Magn |

Clock and data recovery/Structures and types of

Tolerance of (linear) phase comparators

Tolerance of phase adders

Clock and data recovery/Structures and types of

Pulse response of the 1st order CDR