DS34S101//DS34S102/DS34S104/DS34S108: Single/Dual/Quad/Octal TDM-Over-Packet Transport Devices

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DS34S101//DS34S102/DS34S104/DS34S108
Single/Dual/Quad/Octal TDM-Over-Packet Transport Devices
General Description Features
The IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC Full-Featured TDM-Over-Packet
RFC-compliant DS34S108 allows up to eight T1/E1 Supports Adaptive Clock Recovery, Common
links or frame-based serial HDLC links to be Clock (Using RTP), External Clock, and
transported transparently through a switched IP or Loopback Timing Modes
MPLS packet network. Jitter and wander of
recovered clocks conform to G.823/G.824, G.8261, Selectable 32-Bit or 16-Bit Processor Bus
and TDM specifications. This eliminates the need for 10/100 Ethernet MAC That Supports
remote timing sources in cabinets and pedestals. MII/RMII/SSMII
Fully Compatible with IEEE 802.3 Standard
The Ethernet side of the DS34S108 provides high
QoS capabilities to its MII/RMII/SSMII port, while the VLAN Support According to 802.1 p&Q
WAN side supports interfacing to framers and LIUs. Multiprotocol Encapsulation Supports IPv4,
The high level of integration that the DS34S108 IPv6, UDP, RTP, L2TPv3, MPLS, and Metro
brings minimizes cost, board space, and time to Ethernet
market.
End-to-End TDM Synchronization Through
Applications the IP/MPLS Domain by Eight Independent
On-Chip TDM Clock Recovery Mechanisms
TDM Circuit Extension Over PSN
Single Serial Support for RS-530 and V.35
o Leased-Line Services Over PSN
o TDM Over G/E-PON Single DS3/E3/STS-1 to Ethernet
o TDM Over Cable Packet Loss Compensation and Handling of
o TDM Over WiMAX Misordered Packets
Cellular Backhaul Over PSN
Multiservice Over Unified PSN 64 Independent Bundle/Connections
HDLC-Based Traffic Transport Over PSN Glueless SDRAM Buffer Management
Functional Diagram 1.8V Core, 3.3V I/O
CPU Complies with IETF PWE3 RFCs for SAToP,
BUS CESoPSN, TDMoIP, and HDLC
DS34S108 Features continued in Section 7.
Ordering Information
CIRCUIT 10/100 PART PORTS TEMP RANGE PIN-PACKAGE
EMULATION ETHERNET DS34S108GN* 8 -40C to +85C 484 TEBGA
TDM xMII
ENGINE MAC DS34S108GN+* 8 -40C to +85C 484 TEBGA
DS34S104GN 4 -40C to +85C 256 TECSBGA
DS34S104GN+ 4 -40C to +85C 256 TECSBGA
BUFFER DS34S102GN* 2 -40C to +85C 256 TECSBGA
CLAD
MANAGER DS34S102GN+* 2 -40C to +85C 256 TECSBGA
DS34S101GN * 1 -40C to +85C 256 TECSBGA
SDRAM DS34S101GN+* 1 -40C to +85C 256 TECSBGA
CLOCK INPUTS INTERFACE +Denotes a lead-free package.
*Future productContact factory for availability.
Maxim Integrated Products 1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of
any device may be simultaneously available through various sales channels. For information about device errata, go to:
www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or
visit Maxims website at www.maxim-ic.com.
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Table of Contents
1 INTRODUCTION ................................................................................................................................6
2 ACRONYMS AND GLOSSARY.........................................................................................................7
3 STANDARDS COMPLIANCE ............................................................................................................9
4 DETAILED DESCRIPTION ..............................................................................................................10
5 APPLICATION EXAMPLES.............................................................................................................11
5.1 OTHER POSSIBLE APPLICATIONS ...................................................................................................12
5.1.1 Point-to-Multipoint TDM Connectivity over IP/Ethernet ....................................................................... 12
5.1.2 HDLC Transport over IP/MPLS............................................................................................................ 12
5.1.3 Using a Packet Backplane for Multiservice Concentrators .................................................................. 12
6 BLOCK DIAGRAM...........................................................................................................................13
7 FEATURE HIGHLIGHTS..................................................................................................................14
7.1 GLOBAL FEATURES .......................................................................................................................14
7.2 CLOCK SYNTHESIZER ....................................................................................................................14
7.3 TDM-OVER-PACKET ENGINE .........................................................................................................14
7.3.1 TDM-over-Packet User Interfaces ....................................................................................................... 15
7.3.2 Network Port ........................................................................................................................................ 15
7.3.3 Bundles ................................................................................................................................................ 16
7.3.4 Clock Recovery .................................................................................................................................... 16
7.3.5 Delay Variation Compensation ............................................................................................................ 16
7.3.6 CAS Support ........................................................................................................................................ 17
7.4 TEST AND DIAGNOSTICS ................................................................................................................17
7.5 CONTROL PORT ............................................................................................................................17
8 FUNCTIONAL DESCRIPTION AND DEVICE REGISTERS ............................................................18
9 PIN DESCRIPTION ..........................................................................................................................19
9.1 SHORT PIN DESCRIPTIONS ............................................................................................................19
9.2 DETAILED PIN DESCRIPTIONS ........................................................................................................23
10 JTAG INFORMATION ..................................................................................................................34
10.1 JTAG DESCRIPTION......................................................................................................................34
10.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION...............................................................35
10.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS........................................................................37
10.3.1 SAMPLE/PRELOAD ............................................................................................................................ 37
10.3.2 EXTEST ............................................................................................................................................... 37
10.3.3 BYPASS............................................................................................................................................... 37
10.3.4 IDCODE ............................................................................................................................................... 37
10.3.5 HIGHZ .................................................................................................................................................. 37
10.3.6 CLAMP................................................................................................................................................. 38
10.4 JTAG TEST REGISTERS ................................................................................................................38
10.4.1 Bypass Register ................................................................................................................................... 38
10.4.2 Identification Register........................................................................................................................... 38
10.4.3 Boundary Scan Register ...................................................................................................................... 38
11 DC ELECTRICAL CHARACTERISTICS......................................................................................39
12 AC TIMING CHARACTERISTICS................................................................................................40
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13 APPLICATION INTERFACES......................................................................................................41
13.1 CONNECTING A SERIAL INTERFACE TRANSCEIVER ..........................................................................41
13.2 CONNECTING AN EXTERNAL E1/T1 FRAMER ..................................................................................42
13.3 CONNECTING AN ETHERNET MAC OR PHY....................................................................................44
13.4 IMPLEMENTING CLOCK RECOVERY IN HIGH-SPEED APPLICATIONS ..................................................47
13.5 CONNECTING A MOTOROLA MPC860 HOST ...................................................................................47
13.5.1 Connecting the Bus Signals................................................................................................................. 47
13.5.2 Connecting the H_READY_N Signal ................................................................................................... 50
13.6 WORKING IN SPI MODE .................................................................................................................51
13.7 CONNECTING SDRAM DEVICES ....................................................................................................51
14 PIN ASSIGNMENT .......................................................................................................................52
14.1 BOARD DESIGN FOR THE DS34S108 FAMILY OF PRODUCTS ..........................................................52
14.2 DS34S108 PIN ASSIGNMENT ........................................................................................................59
15 PACKAGE INFORMATION..........................................................................................................66
15.1 484-BALL TEBGA (56-G6038-001) ..............................................................................................66
15.2 256-BALL TECSBGA (56-G6028-001) .........................................................................................67
16 THERMAL INFORMATION ..........................................................................................................68
17 DOCUMENT REVISION HISTORY ..............................................................................................69
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List of Figures
Figure 5-1. Metropolitan Legacy Service Over Packet-Switched Network................................................................ 11
Figure 5-2. Cellular 2/3G Backhaul Over Packet-Switched Networks....................................................................... 12
Figure 6-1. DS34S108 Functional Block Diagram..................................................................................................... 13
Figure 10-1. JTAG Block Diagram............................................................................................................................. 34
Figure 10-2. JTAG TAP Controller State Machine .................................................................................................... 35
Figure 13-1. Connecting the First Port to a Serial Transceiver ................................................................................. 41
Figure 13-2. External E1/T1 Framer in Applications with CAS (Single-Clock Mode)................................................ 42
Figure 13-3. External E1/T1 Framer in Applications without CAS (Single-Clock Mode)........................................... 43
Figure 13-4. External E1/T1 Framer in Applications with CAS (Two-Clock Mode) ................................................... 43
Figure 13-5. External E1/T1 Framer in Applications WO/CAS (Two-Clock Mode) ................................................... 44
Figure 13-6. Connecting the Ethernet Port to a PHY in MII Mode ............................................................................ 44
Figure 13-7. Connecting the Ethernet Port to a MAC in MII Mode............................................................................ 45
Figure 13-8. Connecting the Ethernet Port to a PHY in RMII Mode.......................................................................... 45
Figure 13-9. Connecting the Ethernet Port to a MAC in RMII Mode ......................................................................... 45
Figure 13-10. Connecting the Ethernet Port to a PHY in SSMII Mode...................................................................... 46
Figure 13-11. Connecting the Ethernet Port to a MAC in SSMII Mode ..................................................................... 46
Figure 13-12. External Frequency Synthesis ............................................................................................................ 47
Figure 13-13. 32-Bit CPU Bus Connections .............................................................................................................. 48
Figure 13-14. 16-Bit CPU Bus Connections .............................................................................................................. 49
Figure 13-15. Asynchronous ModeConnection of H_READY_N to MPC860 TA .................................................. 50
Figure 13-16. CPLD Logic, Synchronizing H_READY_N to the MPC860 Clock ...................................................... 50
Figure 14-1. DS34S108 Pin Assignment (TEBGA Package) .................................................................................... 62
Figure 14-2. DS34S104 Pin Assignment (TECSBGA Package) ............................................................................... 63
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List of Tables
Table 3-1. TDM-Over-Packet Related Specifications.................................................................................................. 9
Table 9-1. DS34S108 Short Pin Descriptions ........................................................................................................... 19
Table 9-2. Detailed Pin Descriptions ......................................................................................................................... 23
Table 10-1. JTAG Instruction Codes ......................................................................................................................... 37
Table 10-2. JTAG ID Code ........................................................................................................................................ 38
Table 11-1. Recommended DC Operating Conditions .............................................................................................. 39
Table 11-2. DC Electrical Characteristics.................................................................................................................. 39
Table 13-1. SPI Mode I/O Connections..................................................................................................................... 51
Table 13-2. List of Suggested SDRAM Devices........................................................................................................ 51
Table 14-1. Common Board Design Connections ..................................................................................................... 52
Table 14-2. DS34S108 Pin Assignment (Sorted by Signal Name) ........................................................................... 59
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1 Introduction
The DS34S108/DS34S104/DS34S102/DS34S101 (DS34S10x) family of products provides Pseudo Wire Emulation
Edge to Edge (PWE3) Circuit Emulation technology into one die. Dedicated payload-type engines are included for
TDMoIP (AAL1, AAL2), CESoPSN, SAToP, and HDLC.
The DS34S10x products provide a transport technology for simple conversion of T1/E1/J1/T3/E3/STS-1 serial TDM
to IP, MPLS, or pure Ethernet Layer 2 networks. They carry from E1/T1 or provide a carrier for E3, T3, or STS-1
services and serial data across a packet-switched network, transparent to all protocols and signaling. These
products enable service providers to migrate to next generation networks while continuing to provide all their
revenue generating legacy voice and data services. They also benefit data carriers by enabling them to offer
lucrative leased-line services and increase revenues from their packet-switched infrastructure by selling voice as
well as data services. Finally, they enable enterprises to run voice and video over the same IP/Ethernet-based
network that is currently used to run only LAN traffic, thereby minimizing network maintenance and operating costs.
Packet-switched networks, such as IP networks, were not designed to transport TDM data and have no inherent
clock distribution mechanism. Hence, when transporting TDM over packet-switched networks, the receiver needs
to reconstruct the transmitter's TDM clock. The DS34S10x products ensure that jitter and wander levels of the
recovered TDM clock conform to ITU-T G.823/G.824 and G.8261/Y.1361, even for networks which introduce
significant packet delay variation and packet loss.
The Circuit Emulation technology in the DS34S10x products that makes this possible is called TDM-over-Packet
(TDMoP) and complements VoIP in those cases where VoIP is not applicable or where VoIP price/performance is
not sufficient. Most importantly, TDMoP technology provides higher voice quality and lower latency than VoIP.
Unlike VoIP, TDMoP can support all applications that run over E1/T1 circuits, not just voice. TDMoP can provide
traditional leased-line services over IP and is transparent to protocols and signaling. Because TDMoP provides an
evolutionary, as opposed to revolutionary, approach, investment protection is maximized.
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2 Acronyms and Glossary

Listed below are the terms used in this data sheet:
2.5G 2.5 Generation
2G Second Generation
3G Third Generation
AAL1 ATM Adaptation Layer 1
AAL2 ATM Adaptation Layer 2
ATM Asynchronous Transfer Mode
BGA Ball Grid Array
Bridge Bridge
Bundle Bundle
BW Bandwidth
CAS Channel Associated Signaling
CCS Common Channel Signaling
CE Customer Edge
CESoP Circuit Emulation Service over Packet
CESoPSN Circuit Emulation Services over Packet Switched Network
Circuit Switching Circuit Switching
CLAD Clock Rate Adapter
CLEC Competitive Local Exchange Carrier
CPE Customer Premises Equipment
CSMA Carrier Sense Multiple Access
CSMA/CD Carrier Sense Multiple Access with Collision Detection
DS0 Digital Signal Level 0
DS1 Digital Signal 1
DS3 Digital Signal 3
HDLC High-Level Data Link Control
IEEE 802.3 Institute of Electrical and Electronics Engineers 802.3
IEEE 802.X Institute of Electrical and Electronics Engineers 802.X
IETF Internet Engineering Task Force
ILEC Incumbent Local Exchange Carrier
IP Internet Protocol
IP Address Internet Protocol Address
IWF Interworking Function
LAN Local Area Network
LEC Local Exchange Carrier
LIU Line Interface Unit
MAC Media Access Control
MAN Metropolitan Area Network
Message Switching Message Switching
MII Medium Independent Interface
MPLS Multiprotocol Label Switching
OC-3 Optical Carrier Level 3
OCXO Oven-Controlled Crystal Oscillator
OFE Optical Front-End
OSI Open Systems Interconnection
OSI-RM Open Systems InterconnectionReference Model
PAD Packet Assembler/Disassembler
PBX Private Branch Exchange
PCI Peripheral Component Interconnect
PCI Express Peripheral Component Interconnect Express
PCI-X Peripheral Component Interconnect Extended
PDV Packet Delay Variation
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PE Provider Edge
PLCC Plastic Leaded Chip Carrier
PQFP Plastic Quad Flat Pack
PSN Packet Switched Network
PSTN Public Switched Telephone Network
PWE3 Pseudo-Wire Edge-to-Edge Emulation
QoS Quality of Service
RMII Reduced Medium Independent Interface
RPR Resilient Packet Ring
SAToP Structure-Agnostic TDM over Packet
SDH Synchronous Digital Hierarchy
SMII Serial Media Independent Interface
SONET Synchronous Optical Network
SS7 Signal System 7
SSMII Source Synchronous Serial Media Independent Interface
STM-1 Synchronous Transfer Module -1
TDM Time Division Multiplexing
TDMoIP Time Division Multiplexing over Internet Protocol
TDMoP Time Division Multiplexing over Packet
TLS Transport Layer Security
UDP User Datagram Protocol
VoIP Voice over IP
VPLS Virtual Private LAN Services
WAN Wide Area Network
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3 Standards Compliance
The DS34S108 meets all the latest relevant telecommunications specifications. The TDM-over-Packet
specifications and relevant sections are described in Table 3-1.
Table 3-1. TDM-Over-Packet Related Specifications

Y.1413 TDM-MPLS Network InterworkingUser Plane Interworking
TDMoMPLS will meet standards for network interworking that covers the transport label, interworking label, common
interworking indicators, and optional timing information. The common interworking indicators include a control field, a
fragmentation field, length indicator, and the sequence number.
TDMoMPLS shall meet standards for structure agnostic transport.
TDMoMPLS shall meet standards for structure aware transport that contains structure-locked encapsulation and structure-
indicated encapsulation.
Y.1414 Voice ServiceMPLS Network Interworking
The recommendation focuses on the required functions and procedures necessary for support of narrow-band voice services
by MPLS networks. Details of the encapsulation of encoded audio streams in MPLS packets are specified. Clause 10 draft
recommendation shall be met.
Y.1452 (Y.VTOIP) Voice Trunking over IP
This recommendation specifies a method for transporting multiplexed voice services over UDP/IP.
Y.1453 (Y.TDMIP) TDM-IP InterworkingUser Plane Interworking
This recommendation specifies methods for transporting low-rate TDM (T1, E1, T3, E3) over UDP/IP. Y.1453 is a direct
extension of Y.1413.
PWE3-CESoPSN Structure-Aware TDM Circuit Emulation Service over Packet-Switched Network
December 2007 rfc5086.txt revision shall be supported.
The TDM-over-Packet shall meet basic NxDS0 service, and "trunk-specific" NxDS0 service with CAS.
The TDM-over-Packet shall meet CESoPSN packet format for an IPv4/IPv6 PSN, CESoPSN packet format for an MPLS PSN.
Shall also meet CESoPSN payload layer.
PWE3-SAToP Structure-Agnostic TDM over Packet
June 2006 rfc4553.txt revision shall be supported.
The TDM-over-Packet shall meet basic SAToP packet format, SAToP packet format for an IPv4/IPv6, SAToP packet format for
an MPLS PSN, and SAToP payload layer. SATop control word.
PWE3-TDMoIP
December 2007 rfc5087.txt revision shall be supported.
PWE3-HDLC
September 2006 rfc4618.txt revision shall be supported (excluding clause 4.3PPP).
IEEE 802.3
This standard covers the MAC interface to a PHY for MII.
MPLS-Frame Relay Alliance Implementation Agreements 4.1
The purpose of this implementation agreement (IA) is to define network interworking between TDM circuits (Nx64kbps,
E1/T1/E3/T3) over MPLS label switched paths (LSPs) by using AAL1 encapsulation.
MPLS-Frame Relay Alliance Implementation Agreements 5.1
This specification defines MPLS support for the transport of AAL type 2 CPS-packets. Frame formats and procedures required
for this transport are described in this implementation agreement. This specification addresses the transport of any AAL type 2
CPS-packets regardless of the application data that is transported.
MPLS-Frame Relay Alliance Implementation Agreements 8.0.0
This document describes a method for encapsulating TDM signals belonging to the PDH hierarchy (T1, E1, T3, E3, Nx64kbps)
as pseudo wires over an MPLS network.
MEF 8Metro Ethernet Forum 8 Implementation Agreement for the Emulation of PDH Circuits over Metro Ethernet
Networks
This document provides an implementation agreement for the emulation of PDH services across a Metro Ethernet Network.
Specifically it covers emulation of Nx64kbps, DS1, E1, DS3, and E3 circuits. Generically, this is referred to as circuit emulation
services over Ethernet (CESoETH).
G.823/G.824 Jitter and Wander Requirements
G.8261/Y.1361 (G.pactiming) Timing and Synchronization Aspects in Packet Networks
This recommendation defines synchronization aspects in packet networks and specifies the maximum network limits of jitter and wander that
shall not be exceeded and the minimum equipment tolerance to jitter and wander than shall be provided at the boundary of these packet
networks at TDM interfaces. It also outlines the minimum requirements for the synchronization function of network elements.
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4 Detailed Description
The DS34S108 is an 8-port device featuring pseudo-wire circuit emulation that supports T1/J1 or E1. The
DS34S104, DS34S102, and DS34S101 have the same functionality as the DS34S108, the product referenced
throughout this document, but with fewer ports. Each port can connect a TDM stream to the TDM-over-Packet
(TDMoP) circuit to provide a complete solution to IP or MPLS or Ethernet Layer 2 networks. The internal MAC
supports connectivity to a single 10/100Mbps MII//RMII/SSMII. The DS34S108 is configured via a 16- or 32-bit
CPU parallel port.
On the transmit side, clock, data, and frame-sync signals are provided to the TDM backplane. On the receive side,
the TDM backplane provides clock, data, and frame-sync signals to the DS34S108.
The TDM-over-Packet (TDMoP) core is the building block for circuit emulation and other network applications. It
performs transparent transport of legacy TDM traffic over Packet Switched Networks (PSNs). The TDMoP core
implements payload methods such as AAL1 for circuit emulation, AAL2-like method for loop emulation, HDLC
method, structure-agnostic SAToP method, and the structure-aware CESoPSN method.
The AAL1 payload-type machine converts E1/T1/E3/T3/STS-1/serial data flows into IP, MPLS, or Ethernet packets,
and vice versa, according to ITU-T Y.1413, Y.1453, MEF 8, MFA 4.1, and IETF RFC 5087. It supports E1/T1
structured mode with/without CAS, using a time slot size of 8 bits, or unstructured mode (carrying serial interfaces,
unframed E1/T1 or E3/T3/STS-1 traffic).
The AAL2 payload-type machine converts E1/T1 data flows into IP, MPLS or Ethernet packets, and vice versa,
implementing dynamic time slot allocation. It supports E1/T1 structured mode with/without CAS with 8-bit time slot
resolution, according to ITU-T Y.1414 (clause 10), Y.1452, MFA 5.1, and IETF RFC 5087.
The HDLC payload-type machine converts and terminates HDLC-based E1/T1/serial flow into IP/MPLS packets
and vice versa, according to the IETF RFCs 5087 and 4618 (excluding clause 5.3PPP). It supports 2-, 7- and 8-
bit time slot resolution (i.e., 16kbps, 56kbps, and 64kbps, respectively), as well as N x 64kbps bundles (n = 1 to
32). Supported applications of this machine include trunking of HDLC-based traffic (such as frame relay)
implementing dynamic bandwidth allocation over IP/MPLS networks and HDLC-based signaling interpretation
(such as ISDN D-channel signaling terminationBRI or PRI, V5.1/2, or GR-303).
The SAToP payload-type machine converts unframed E1/T1/E3/T3 data flows into IP, MPLS, or Ethernet packets,
and vice versa, according to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0, and IETF RFC 4553. It supports
E1/T1/E3/T3 with no regard for the TDM structure. If TDM structure exists it is ignored, allowing it to be the simplest
way of making payload. The size of the payload is programmable for different services. This emulation suits
applications where the provider edges have no need to interpret TDM data or to participate in the TDM signaling.
The PSN network must have almost no packet loss and a very low PDV for this method.
The CESoPSN payload-type machine converts structured E1/T1/E3/T3 data flows into IP, MPLS, or Ethernet
packets, and vice versa, with static assignment of time slots inside a bundle according to ITU-T Y.1413, Y.1453,
MEF 8, MFA 8.0.0, and IETF RFC 5086. It supports E1/T1/E3/T3 while taking into account the TDM structure. The
level of structure must be chosen for proper payload conversion such as the framing type (i.e., frame, multiframe).
This method is less sensitive to PSN impairments, but lost packets could still cause service interruption. The
payload is simply encapsulated into 24 bytes for T1 and 32 bytes for E1.
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5 Application Examples
In Figure 5-1 the DS34S108 is used to allow TDM services over a packet-switched metropolitan network, using
various access methods (G/E PON, fiber optic, wireless, cable).
Figure 5-1. Metropolitan Legacy Service Over Packet-Switched Network
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Figure 5-2. Cellular 2/3G Backhaul Over Packet-Switched Networks
5.1 Other Possible Applications
5.1.1 Point-to-Multipoint TDM Connectivity over IP/Ethernet
The TDM-over-Packet chip supports DS0-level multiple bundles/connections with and without CAS (Channel
Associated Signaling). There is no need for an external TDM cross-connect, as the packet domain can be used as
a virtual cross-connect; any bundle of time slots can be directed to another remote location on the packet domain.
5.1.2 HDLC Transport over IP/MPLS
TDM traffic streams often contain HDLC-based control and data traffic. These data streams, when transported over
a packet domain, should be treated differently than the time-sensitive TDM payload. The DS34S108 includes
HDLC controller capability, which enables termination of the HDLC frames. HDLC-based control protocols, such as
ISDN BRI and PRI, SS7, etc., and other frame-based traffic, can be managed and transported.
5.1.3 Using a Packet Backplane for Multiservice Concentrators
A communications device with all the above-mentioned capabilities can use a packet-based backplane instead of
the more expensive TDM bus option. This enables a cost-effective and future-proof design of communication
platforms with full support for both legacy and next-generation services.
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6 Block Diagram
Figure 6-1. DS34S108 Functional Block Diagram
SD_DQM[3:0]
SD_RAS_N
SD_CAS_N
SD_BA[1:0]
SD_D[31:0]
SD_A[11:0]
CLK_HIGH
CLK_CMN
SD_WE_N
SD_CS_N
SD_CLK
MCLK
Byte Enable Mask

T1CLK
Bank Select
CLAD E1CLK
Address
Control
38.88MHz
Data
2.048/1.544MHz FSYSCLK
DS34S108
TDMoPacket CLAD
50 or 75MHz CLK_SYS_S
Clock Recovery Payload Type SDRAM
Machines Machines Controller CLK_SYS
TDMn_TX RAW
TDMn_ACLK
TDMn_TSIG_CTS SAToP
TDMn_TCLK MII_TX_ERR
CESoPSN JITTER MII_TX_EN
TDMn_TX_SYNC
BUFFER MII_TXD[3:0]
TDMn_TX_MF_CD
Timeslot CONTROL CLK_SSMII_TX
Assigner AAL1 CLK_MII_TX
Ethernet
MAC MII_CRS
AAL2 10/100 MII_COL
Packet MII_RX_ERR
Classifier MII_RX_DV
HDLC MII_RXD[3:0]
TDMn_RX CLK_MII_RX
TDMn_RCLK
CAS Queue
TDMn_RX_SYNC MDIO
Handler Counters Manager
TDMn_RSIG_RTS MDC
& Status
Registers
CPU
Interface JTAG SCAN/MBIST
MBIST_FAIL
STMD
MBIST_DONE
H_INT[1:0]
Reserved
JTMS
H_CS_N
H_R_W_N
H_WR_BE3..0_N
H_READY_N
JTCLK
JTDO
SCEN
H_D[31:0]
JTDI
H_A[24:1]
JTRST_N
RST_SYS_N
DATA_31_16_N
HIZ_EN
MBIST_EN
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7 Feature Highlights
The following sections describe the features provided by the 8-port DS34S108.
7.1 Global Features

The DS34S108 chip offers:
8 TDMoP interfaces or
1 E3/DS3/STS-1 TDMoP Interface or
1 Serial TDMoP Interface for V.35 and RS530
Ethernet Interface
1 10/100Mbps, MII/RMII/SSMII
Half/full duplex
VLAN support according to 802.1 p&Q
Fully compatible with IEEE 802.3 standard
End-to-end TDM synchronization through the IP/MPLS domain by eight independent on-chip TDM clock
recovery mechanisms, on a per-port basis
64 independent bundles/connections, each with its own:
Transmit and receive queues
Configurable jitter-buffer depth
Connection level redundancy, with traffic duplication option
64 Internal bundle cross-connect capability, with DS0 resolution
Packet loss compensation and handling of misordered packets
Glueless SDRAM interface
Complies with MPLS-Frame Relay Alliance Implementation Agreements 4.1, 5.1, and 8.0
Meets ITU standards Y.1413 and Y.1414
Complies with Metro Ethernet Forum 3 & 8
Conforms to drafts submitted to IETF
23mm x 23mm, 484-pin TEBGA package (1mm pitch) for DS34S108
17mm x 17mm, 256-pin CSBGA package (1mm pitch) for DS34S104/DS34S102/DS34S101
IEEE 1146.1 JTAG boundary scan
1.8V and 3.3V operation with 5.0V tolerant I/O
7.2 Clock Synthesizer

Internal clock synthesis for the E1 and T1 from an input of 38.88MHz, 19.44MHz, 77.76MHz, or 10MHz clock
source
7.3 TDM-over-Packet Engine
TDM-over-Packet enables transport of legacy TDM servicesE1/T1, E3/T3, STS-1, or serial data (on the WAN
side) over packet switched networks and IP, MPLS, or Ethernet (on the network side). This module implements the
following payload methods of TDM transfer over IP, MPLS, or Ethernet networks:
SAToP (Structure-Agnostic TDM over Packet)

Structure-aware format for structured E1/T1 with or without CAS (CESoPSN)
AAL1 format (constant rate/static allocation of time slots)
AAL2 format (dynamic allocation of time slots)
HDLC termination for efficient transfer of frame-based traffic.
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A dedicated payload type engine implements each per the following method:
SAToP hardware engine converts unframed E1/T1/E3/T3/STS-1 or serial data flows into IP, MPLS, or Ethernet
packets and vice versa according to ITU-T Y.1413, Y.1453, MEF 8, MFA 8.0.0, and the IETF PWE3 SAToP
RFC.
CESoPSN hardware engine converts structured E1/T1 data flows into IP, MPLS, or Ethernet packets and vice
versa with static assignment of time slots inside a bundle according to ITU-T Y.1413, Y.1453, MEF 8, MFA
8.0.0, and the IETF PWE3 CESoPSN RFC.
AAL1 hardware engine converts E1/T1/E3/T3/STS-1 or serial data flows into IP, MPLS, or Ethernet packets,
and vice versa, according to ITU-T Y.1413, MEF 8, MFA 4.1, and the IETF PWE3 TDMoIP RFC. For E1/T1 it
supports structured mode with/without CAS using 8-bit time slot resolution, while implementing static time slot
allocation. For E1/T1, E3/T3/STS-1 or serial interface it supports unstructured mode.
AAL2 hardware engine converts E1/T1 data flows into IP/MPLS/Ethernet packets, and vice versa, while
implementing dynamic time slot allocation. It supports E1/T1 structured mode with/without CAS using 8-bit time
slot resolution, according to ITU-T Y.1414 (clause 10), MFA 5.1, and the IETF PWE3 TDMoIP RFC.
HDLC hardware engine converts and terminates HDLC-based E1/T1/serial flow into IP/MPLS/Ethernet packets
and vice versa. It supports 2-, 7-, and 8-bit time slot resolution (i.e., 16kbps, 56kbps, and 64kbps, respectively),
as well as N x 64kbps bundles. This is useful in applications where HDLC-based signaling interpretation is
required (such as ISDN D channel signaling termination, V.51/2, or GR-303), or for trunking packet-based
applications (such as frame relay), according to the IETF PWE3 HDLC RFC.
7.3.1 TDM-over-Packet User Interfaces
The user side consists of either a single high-speed E3, T3, or STS-1 I/F or eight I/Fs, each independently
supporting E1, T1, or serial data transfer.
For the E3/T3/STS-1 option, the AAL1 or SAToP method is used.
For the E1/T1 option, the module supports the following operation modes:
UnframedE1/T1 pass-through mode (AAL1, SAToP, or HDLC payload type method).

StructuredFractional E1/T1 support (all payload type methods).
Structured with CASFractional E1/T1 with CAS support (CESoPSN, AAL1, or AAL2 payload type method).
The serial interface option supports synchronous data transfer (for interfaces such as V.35) over the
IP/MPLS/Ethernet network for legacy data services (such as frame relay or arbitrary continuous bit stream).
The serial port option supports the following synchronous serial data formats:
Arbitrary continuous bit stream (using AAL1 or SAToP payload type method).
In single-interface high-speed mode, the first interface operates at up to STS-1 rate (51.84Mbps) and the other
interfaces are disabled. In this mode, the whole traffic is transferred using a single bundle/connection.
In eight-interface low-speed mode each interface can operate at the rate of N x 64kbps, where N = 1 to 63, with
an aggregate rate of 18.6Mbps.
HDLC-based traffic (such as frame relay transferred using HDLC payload type method). Only the eight-
interface low-speed mode is available (N x 64kbps, where N = 1 to 63, with an aggregate rate of 18.6Mbps).
All serial interface modes can work with a gapped clock.
7.3.2 Network Port
The chip features one 10/100 Ethernet port with the option of MII/RMII/SSMII. The port can work in half-/full-duplex
mode and supports VLAN tagging and priority labeling according to 802.1 p&Q, including VLAN stacking.
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7.3.3 Bundles
A bundle is defined as a stream of bits that have originated from the same physical interface and that are
transmitted from a TDM-over-Packet source device to a TDM-over-Packet destination device. For example,
bundles can comprise any number of 64kbps time slots originating from a single E1 or an entire T3 or E3. Bundles
are single-direction streams, frequently coupled with bundles in the opposite direction to enable full-duplex
communications. More than one bundle can be transmitted between two TDM-over-Packet edge devices.
The chip supports up to 64 bundles; each can be assigned to any port. The bundles are configured independently,
each with its own:
Transmit and receive queues

Configurable receive-buffer depth
Optional connection level redundancy (SAToP, AAL1, CESoPSN only).
The bundles can be assigned to one of the payload type machines or to the CPU. For E1/T1, the chip provides
internal bundle cross-connect functionality, with DS0 resolution.
7.3.4 Clock Recovery
Sophisticated TDM clock recovery mechanisms, one for each E1/T1 interface, allow end-to-end TDM clock
synchronization, despite packet delay variation of IP/MPLS/Ethernet network.
TDM-over-Packet supports the following clock recovery modes:
Adaptive clock recovery

Common clock (using RTP)
External clock
Loopback clock
The clock recovery mechanisms provide both fast frequency acquisition and highly accurate phase tracking:
Jitter and wander of the recovered clock are maintained at levels that conform to G.823/G.824 traffic or
synchronization interfaces and to G.8261/Y.1361. For adaptive clock recovery, the recovered clock
performance depends on packet network characteristics.
Short-term frequency accuracy (1 second) is better than 16ppb (using OCXO reference) or 100ppb (using
TCXO reference)
Capture range is 90ppm
Internal synthesizer resolution of 0.5ppb
High resilience to the packet loss and misordering, up to 2% of packet loss/misordering without degradation of
clock recovery performance
Robust to sudden significant constant delay changes
Automatic transition to hold over is performed upon link-break events.
7.3.5 Delay Variation Compensation
The TDM-over-Packet module provides large configurable jitter buffers, on a per-bundle basis, that compensate for
the delay variation introduced by the IP/MPLS/Ethernet network, with the following depths:
E1: up to 256ms
T1 unframed: up to 340ms
T1 framed: up to 256ms
T1 framed with CAS: up to 192ms
E3: up to 60ms
T3: up to 45ms
STS-1: up to 40ms
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For the SAToP and CESoPSN bundles, TDM-over-Packet performs packet reordering within the range of the jitter
buffer.
Packet loss is compensated by inserting either a preconfigured conditioning value or the last received value.
7.3.6 CAS Support
A CAS handler terminates the E1/T1 CAS when using AAL1/AAL2/CESoPSN in structured-with-CAS mode. This
eliminates the need for CPU intervention.
7.4 Test and Diagnostics

IEEE 1149.1 Support
MBIST
7.5 Control Port
The CPU interface provides a connection to a host with a 16/32-bit data bus. This allows configuration of chip
control registers and statistics collection using the chip counters and status registers. It also provides access to the
CPU transmit and received buffers allocated in the SDRAM, used for packets that are directed to/originate from the
CPU (such as ARP, SNMP, etc.).
32- or 16-bit parallel control port

Software reset supported
Hardware reset pin
Software access to device ID and silicon revision
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8 Functional Description and Device Registers

Refer to the full data sheet for this information.
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9 Pin Description
9.1 Short Pin Descriptions
The following abbreviations are used in the TYPE column of the short pin description: I (Input), Ipu (Input with
Pullup), Ipd (Input with Pulldown), Ia (Analog Input), O (Output), Oz (Output Three-Stateable), Oa (Analog Output),
IO (Bidirectional Inout), IOpd (Bidirectional with Pulldown), and IOpu (Bidirectional with Pullup).
Table 9-1. DS34S108 Short Pin Descriptions

NAME TYPE FUNCTION
SD_D[31:0] IO Synchronous DRAM Data Bus
SD_DQM[3:0] O Byte Enable Mask
SD_A[11:0] O SDRAM Address Bus
SD_BA[1:0] O SDRAM Bank Select
SD_CLK O SDRAM Clock
SD_CS_N O SDRAM Chip Select (Active Low)
SD_WE_N O SDRAM Write Enable (Active Low)
SD_RAS_N O SDRAM Row Address Strobe Enable (Active Low)
SD_CAS_N O SDRAM Column Address Strobe (Active Low)
TDM1_TX O TDM1 Transmit
TDM1_RX Ipu TDM1 Receive
TDM1_TCLK Ipu TDM1 Transmit Clock
TDM1_RCLK Ipu TDM1 Receive Clock
TDM1_ACLK O TDM1 Recovery Clock
TDM1_TX_SYNC Ipd TDM1 Transmit/Receive Sync Pulse
TDM1_TX_MF_CD IOpd TDM1 Transmit Multiframe Sync Pulse/Carrier Detect
TDM1_RX_SYNC Ipd TDM1 Receive Multiframe Sync Pulse/Sync Pulse
TDM1_TSIG_CTS O TDM1 Transmit Signaling/Clear to Send
TDM1_RSIG_RTS Ipu TDM1 Receive Signaling/Request To Send
TDM3_TCLK Ipu TDM3Transmit Clock
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NAME TYPE FUNCTION
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NAME TYPE FUNCTION
TDM8_RX_MF Ipd TDM8 Receive Multiframe Sync Pulse
CLK_MII_RX I Clock Media Independent Interface Receive
MII_RXD[0] I Media Independent Interface Receive Data 0
MII_RX_DV I Media Independent Interface Receive Data Valid
MII_RX_ERR I Media Independent Interface Receive Error
MII_COL I Media Independent Interface Collision
MII_CRS I Media Independent Interface Carrier Sense
CLK_MII_TX I Clock Media Independent Interface Transmit
CLK_SSMII_TX O Clock Source Synchronous Serial Media Independent Interface Transmit
MII_TXD[0] O Media Independent Interface Transmit Data 0
MII_TX_EN O Media Independent Interface Transmit Enable
MII_TX_ERR O Media Independent Interface Transmit Error
MDIO IOpu Management Data Input/Output
MDC O Management Data Clock
CLK_SYS_S I System Clock Selection
CLK_SYS I System Clock
CLK_HIGH I Clock High Synthesis
MCLK I Master Clock
CLK_CMN I Common Clock
H_D[31:1] IO Host Data Bus
H_D[0]/SPI_MISO IO Host Data LSB
H_AD[24:1] I Host Address Bus
H_CS_N I Host Chip Select
H_R_W_N/SPI_CP I Host Read/Write
H_WR_BE0_N/
I H_D[7:0] Write Enable, Active Low
SPI_CLK
H_WR_BE1_N/
SPI_MOSI
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NAME TYPE FUNCTION
H_WR_BE2_N/
SPI_SEL_N
H_WR_BE3_N/
SPI_CI
H_READY_N Oz Host Ready
H_INT[0] O Host Interrupt
DAT_32_16_N Ipu Data 32/16-Bit Select
H_CPU_SPI_N Ipu CPU or SPI Mode
RST_SYS_N Ipu System Reset
JTMS Ipu JTAG Test Mode Select
JTCLK Ipd JTAG Test Clock
JTDI Ipu JTAG Test Data In
JTDO Oz JTAG Test Data Out
JTRST_N Ipu JTAG Test Reset
SCEN I Used for Factory Tests
STMD I Used for Factory Tests
HIZ_N I Used for Factory Tests
MBIST_EN I Used for Factory Tests
MBIST_DONE O Used for Factory Tests
MBIST_FAIL O Used for Factory Tests
TEST_CLK O Used for Factory Tests
DVSS Digital Core Ground for TDM-Over-Packet
DVDDC 1.8V Core Supply Voltage for TDM-Over-Packet
DVDDIO 3.3V Supply Voltage for IO
ACVDD2 Analog CLAD 1.8V Supply 2
ACVSS2 Analog CLAD GND 2
ACVDD1 Analog CLAD 1.8V Supply 1
ACVSS1 Analog CLAD GND 1
Note: Pins with names ending with _N are active low.
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9.2 Detailed Pin Descriptions

The following abbreviations are used in the TYPE column of the detailed pin description: I (Input), Ipu (Input with
Pullup), Ipd (Input with Pulldown), Ia (Analog Input), O (Output), Oz (Output Three-Stateable), Oa (Analog Output),
IO (Bidirectional Inout), IOpd (Bidirectional with Pulldown), and IOpu (Bidirectional with Pullup). The Type column
defines the drive current for any type of output pin.
Table 9-2. Detailed Pin Descriptions
NAME TYPE FUNCTION
SDRAM PINS
IO Synchronous DRAM Data Bus
SD_D[31:0]
8mA SD_D[31:0]: Data bus towards SDRAM. MSB is SD_D[31].
Byte Enable Mask
O SD_DQM[3:0]: Byte enable towards SDRAM. Serve as a mask. SD_DQM[0]
SD_DQM[3:0]
8mA is connected to the least significant byte at SDRAM, while SD_DQM[3] is
connected to the most significant byte at SDRAM.
O SDRAM Address Bus
SD_A[11:0]
8mA SD_A[11:0]: Address bus towards SDRAM. MSB is SD_A[11].
SDRAM Bank Select
O
SD_BA[1:0] SD_BA[1:0]: SDRAM bank select. Selects one bank out of four banks at
8mA
SDRAM.
O SDRAM Clock
SD_CLK
8mA SD_CLK: Drives the SDRAM clock towards the SDRAM.
O SDRAM Chip Select (Active Low)
SD_CS_N
8mA SD_CS_N: SDRAM Chip select towards SDRAM.
O SDRAM Write Enable (Active Low)
SD_WE_N
8mA SD_WE_N: Write enable towards SDRAM.
O SDRAM Row Address Strobe Enable (Active Low)
SD_RAS_N
8mA SD_RAS_N: Row address strobe towards SDRAM.
O SDRAM Column Address Strobe (Active Low)
SD_CAS_N
8mA SD_CAS_N: Column address strobe towards SDRAM.
TDM-OVER-PACKET INTERFACE PINS
TDM1 Transmit
O
TDM1_TX TDM1_TX: First interface serial transmit line. Also used in high-speed
8mA
E3/T3/STS-1 mode.
TDM1 Receive
TDM1_RX Ipu TDM1_RX: First interface serial receive line. This pin is active in external
mode only. Also used in high-speed E3/T3/STS-1 mode.
TDM1 Transmit Clock
TDM1_TCLK Ipu TDM1_TCLK: Used for clocking TDM1_TX and TDM1_RX lines in one-clock
mode, or TDM1_TX in two-clock mode. This pin is active in external mode
only. Also used in high-speed E3/T3/STS-1 mode.
TDM1 Receive Clock
TDM1_RCLK Ipu TDM1_RCLK: Used for clocking TDM1_RX line in two-clock mode. Not used
in one-clock mode. This pin is active in external mode only. Also used in
high-speed E3/T3/STS-1 mode.
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NAME TYPE FUNCTION
TDM1 Recovery Clock
O
TDM1_ACLK TDM1_ACLK: First interface recovered clock. Also used in high-speed
8mA
E3/T3/STS-1 mode.
TDM1 Transmit/Receive Sync Pulse
TDM1_TX_SYNC: First interface transmit frame-sync pulse. Used as both
TDM1_TX_SYNC Ipd transmit and receive frame-sync pulse in one-clock mode. Used as transmit
frame sync in two-clock mode. The pulse frequency can be once every N x
125s, e.g., every 2ms. This pin is active in external mode only.
TDM1 Transmit Multiframe Sync Pulse/Carrier Detect
TDM1_TX_MF_CD IOpd TDM1_TX_MF_CD: First interface transmit multiframe-sync pulse input for
framed interface (PCM), or carrier detect output in case of serial interface.
This pin is active in external mode only.
TDM1 Receive Multiframe Sync Pulse
TDM1_RX_SYNC: First interface receive multiframe-sync pulse or frame-
TDM1_RX_SYNC Ipd sync pulse input. When used as frame-sync pulse the pulse frequency can be
once every N x 125s, e.g., every 2ms. This pin is active in external mode
only.
TDM1 Transmit Signaling/Clear to Send
O
TDM1_TSIG_CTS TDM1_TSIG_CTS: First interface transmit signaling, or clear to send in case
8mA
of serial interface.
TDM1 Receive Signaling/Request To Send
TDM1_RSIG_RTS Ipu TDM1_RSIG_RTS: First interface serial Rx signaling input or request to send
input in case of serial interface. This pin is active in external mode only.
O TDM2 Transmit
TDM2_TX
8mA TDM2_TX: Second Interface serial transmit line.
TDM2 Receive
TDM2_RX Ipu TDM2_RX: Second interface serial receive line. This pin is active in external
mode only. This pin is active in external mode only.
TDM2 Transmit Clock
only. This pin is active in external mode only.
TDM2 Receive Clock
in one-clock mode. This pin is active in external mode only.
O TDM2 Recovery Clock
TDM2_ACLK
8mA TDM2_ACLK: Second interface recovered clock.
TDM2_TX_SYNC: Second interface transmit frame-sync pulse. Used as both
TDM2_TX_MF_CD IOpd TDM2_TX_MF_CD: Second interface transmit multiframe-sync pulse input
for framed interface (PCM), or carrier detect output in case of serial interface.
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NAME TYPE FUNCTION
TDM2_RX_SYNC: Second interface receive multiframe-sync pulse or frame-
only.
O
TDM2_TSIG_CTS TDM2_TSIG_CTS: Second interface transmit signaling, or Clear to Send in
8mA
case of serial interface.
TDM2_RSIG_RTS Ipu TDM2_RSIG_RTS: Second interface serial RX signaling input or Request To
Send input in case of serial interface. This pin is active in external mode only.
O TDM3 Transmit
TDM3_TX
8mA TDM3_TX: Third Interface serial transmit line.
TDM3 Receive
TDM3_RX Ipu TDM3_RX: Third interface serial receive line. This pin is active in external
mode only.
TDM3Transmit Clock
only.
TDM3 Receive Clock
TDM3_ACLK
8mA TDM3_ACLK: Third interface recovered clock.
TDM3_TX_SYNC: First interface transmit frame-sync pulse. Used as both
TDM3_TX_MF_CD IOpd TDM3_TX_MF_CD: Third interface transmit multiframe sync pulse input for
TDM3_RX_SYNC: Third interface receive multiframe-sync pulse or frame-
only.
O
TDM3_TSIG_CTS TDM3_TSIG_CTS: Third interface transmit signaling, or clear to send in case
8mA
TDM3_RSIG_RTS Ipu TDM3_RSIG_RTS: Third interface serial Rx signaling input or request to
send input in case of serial interface. This pin is active in external mode only.
O TDM4 Transmit
TDM4_TX
8mA TDM4_TX: Fourth interface serial transmit line.
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NAME TYPE FUNCTION
TDM4 Receive
TDM4_RX Ipu TDM4_RX: Fourth interface serial receive line. This pin is active in external
mode only.
TDM4Transmit Clock
only.
TDM4 Receive Clock
TDM4_ACLK
8mA TDM4_ACLK: Fourth interface recovered clock.
TDM4_TX_SYNC: Fourth interface transmit frame-sync pulse. Used as both
TDM4_TX_MF_CD IOpd TDM4_TX_MF_CD: Fourth interface transmit multiframe sync pulse input for
TDM4_RX_SYNC: Fourth interface receive multiframe-sync pulse or frame-
only.
O
TDM4_TSIG_CTS TDM4_TSIG_CTS_D2A4: Fourth interface transmit signaling, or clear to
8mA
send in case of serial interface.
TDM4_RSIG_RTS Ipu TDM4_RSIG_RTS: Fourth interface serial Rx signaling input or request to
O TDM5 Transmit
TDM5_TX
8mA TDM5_TX: Fifth interface serial transmit line.
TDM5 Receive
TDM5_RX Ipu TDM5_RX: Fifth interface serial receive line. This pin is active in external
mode only.
TDM5Transmit Clock
only.
TDM5 Receive Clock
TDM5_ACLK
8mA TDM5_ACLK: Fifth interface recovered clock.
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NAME TYPE FUNCTION
TDM5_TX_SYNC: Fifth interface transmit frame-sync pulse. Used as both
TDM5_TX_MF_CD IOpd TDM5_TX_MF_CD: Fifth interface transmit multiframe-sync pulse input for
only.
O
TDM5_TSIG_CTS TDM5_TSIG_CTS: Fifth interface transmit signaling, or clear to send in case
8mA
TDM5_RSIG_RTS Ipu TDM5_RSIG_RTS: Fifth interface serial Rx signaling input or request to send
input in case of serial interface. This pin is active in external mode only.
O TDM6 Transmit
TDM6_TX
8mA TDM6_TX: Sixth interface serial transmit line.
TDM6 Receive
TDM6_RX Ipu TDM6_RX: Sixth interface serial receive line. This pin is active in external
mode only.
TDM6Transmit Clock
only.
TDM6 Receive Clock
TDM6_ACLK
8mA TDM6_ACLK: Sixth interface recovered clock.
TDM6_TX_SYNC: Sixth interface transmit frame-sync pulse. Used as both
TDM6_TX_MF_CD: Sixth interface transmit multiframe-sync pulse input for
TDM6_TX_MF_CD IOpd
TDM6_RX_SYNC: Sixth interface receive multiframe-sync pulse or frame-
only.
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NAME TYPE FUNCTION
O
TDM6_TSIG_CTS TDM6_TSIG_CTS: Sixth interface transmit signaling, or clear to send in case
8mA
TDM6_RSIG_RTS Ipu TDM6_RSIG_RTS: Sixth interface serial Rx signaling input or request to
O TDM7 Transmit
TDM7_TX
8mA TDM7_TX: Seventh interface serial transmit line.
TDM7 Receive
TDM7_RX Ipu TDM7_RX: Seventh interface serial receive line. This pin is active in external
mode only.
TDM7Transmit Clock
TDM7_TCLK: Used for clocking TDM7_TX and TDM7_RX lines in one-clock
TDM7_TCLK Ipu
only.
TDM7 Receive Clock
TDM7_ACLK
8mA TDM7_ACLK: Seventh interface recovered clock.
TDM7_TX_SYNC: Seventh interface transmit frame-sync pulse. Used as
TDM7_TX_SYNC Ipd both transmit and receive frame-sync pulse in one-clock mode. Used as
transmit frame sync in two-clock mode. The pulse frequency can be once
every N x 125s, e.g., every 2ms. This pin is active in external mode only.
TDM7_TX_MF_CD: Fifth interface transmit multiframe-sync pulse input for
TDM7_TX_MF_CD IOpd
TDM7_RX_SYNC: Seventh interface receive multiframe-sync pulse or frame-
TDM7_RX_SYNC Ipd sync pulse input. When used as frame sync pulse the pulse frequency can be
only.
O
TDM7_TSIG_CTS TDM7_TSIG_CTS: Seventh interface transmit signaling, or clear to send in
8mA
case of serial interface.
TDM7_RSIG_RTS Ipu TDM7_RSIG_RTS: Seventh interface serial Rx signaling input or request to
O TDM8 Transmit
TDM8_TX
8mA TDM8_TX: Eighth interface serial transmit line.
TDM8 Receive
TDM8_RX Ipu TDM8_RX: Eighth interface serial receive line. This pin is active in external
mode only.
TDM8Transmit Clock
TDM8_TCLK: Used for clocking TDM8_TX and TDM8_RX lines in one-clock
TDM8_TCLK Ipu
only.
TDM8 Receive Clock
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NAME TYPE FUNCTION
TDM8_ACLK
8mA TDM8_ACLK: Eighth interface recovered clock.
TDM8_TX_SYNC: Eighth interface transmit frame-sync pulse. Used as both
TDM8_TX_MF_CD: Eighth interface transmit multiframe-sync pulse input for
TDM8_TX_MF_CD IOpd
only.
O
TDM8_TSIG_CTS TDM8_TSIG_CTS: Eighth interface transmit signaling or clear to send in
8mA
case of serial interface. This pin is active in external mode only.
TDM8_RSIG_RTS Ipu TDM8_RSIG_RTS: Eighth interface serial Rx signaling input or request to
MAC(10/100) PINS
Clock Media Independent Interface Receive
CLK_MII_RX I
CLK_MII_RX: MII receive clock or SSMII receive clock.
Media Independent Interface Receive Data 0
MII_RXD[0] I
MII_RXD[0]: MII receive data 0 or SSMII receive data.
MII_RXD[1] I
MII_RXD[1]: MII receive data 1 or receive data SSMII sync.
MII_RXD[2] I
MII_RXD[2]: MII receive data 2 or RMII receive data 0.
MII_RXD[3] I
MII_RXD[3]: MII receive data 3 or RMII receive data 1.
Media Independent Interface Receive Data Valid
MII_RX_DV I
MII_RX_DV: MII receive data valid or RMII carrier sense/data valid.
Media Independent Interface Receive Error
MII_RX_ERR I
MII_RX_ERR: MII receive error, or RMII receive error.
Media Independent Interface Collision
MII_COL I
MII_COL: MII collision detection.
Media Independent Interface carrier sense.
MII_CRS I
MII_CRS: MII carrier sense.
Clock Media Independent Interface Transmit
CLK_MII_TX I
CLK_MII_TX: MII transmit clock or RMII ref clock or SSMII ref clock.
O Clock Source Synchronous Serial Media Independent Interface Transmit
CLK_SSMII_TX
12ma CLK_SSMII_TX: SSMII transmit clock (125MHz).
O Media Independent Interface Transmit Data 0
MII_TXD[0]
8mA MII_TXD[0]: MII transmit data 0 or SSMII transmit data.
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NAME TYPE FUNCTION
MII_TXD[1]
8mA MII_TXD[1]: MII transmit data 0 or SSMII transmit sync.
MII_TXD[2]
8mA MII_TXD[2]: MII transmit data 2 or RMII transmit data 0.
MII_TXD[3]
8mA MII_TXD[3]: MII transmit data 3 or RMII transmit data 1.
O Media Independent Interface Transmit Enable
MII_TX_EN
8mA MII_TX_EN: MII transmit enable or RMII transmit enable.
O Media Independent Interface Transmit Error
MII_TX_ERR
8mA MII_TX_ERR: MII transmit error.
IOpu Management Data Input/Output
MDIO
8mA MDIO: Management data, synchronized to MDC.
O Management Data Clock
MDC
8mA MDC: Management data clock.
CLOCK PINS
System Clock Select
CLK_SYS_S: This pin selects the input CLK_SYS frequency. The pin should
CLK_SYS_S Ipd be connected high when a 25MHz CLK_SYS is used. The pin should be
connected low or left unconnected when a 50MHz or 75MHz CLK_SYS is
used.
System Clock
CLK_SYS: Clock input used to drive the TDM-over-Packet internal circuitry.
Requires a 25MHz or 50MHz or 75MHz (+50ppm or better) clock on this pin.
CLK_SYS I The 25MHz CLK_SYS is used to generate a 50MHz or 75MHz internal
system clock for the TDM-over-Packet and SD_CLK. The 50MHz or 75MHz
CLK_SYS is used for the SD_CLK output, and the internal system clock for
the TDM-over-Packet block.
Clock High Synthesis
CLK_HIGH: This clock input is used for the E1/T1 clock recovery machines
of the TDM-over-Packet function. A configuration register sets if the clock
CLK_HIGH I input is going to be 10.00MHz, 19.44MHz, 38.88MHz, or 77.76MHz. It is
recommended that this signal be connected to DVSS when none of the
recovered clock outputs (TDM1_ACLKTDM8_ACLK) are used or when the
chip is in single-port high-speed mode.
Master Clock
MCLK: This signal is not used. Connect to DVSS. The MCLK signal is
MCLK I
provided on the DS34S108 to support pinout compatibility with the products
in the DS34T108/DS34T104/DS34T102/DS34T101 family.
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NAME TYPE FUNCTION
Common Clock
CLK_CMN: Common clock has to be a multiple of 8kHz and in the range of
1MHz to 25MHz. The frequency input should not be too close to an integer
multiple of the service clock frequency. Based on these criteria, the following
frequencies are suggested:
For systems with access to a common SONET/SDH network, a frequency of
19.44MHz (2430 x 8kHz).
CLK_CMN I
For systems with access to a common ATM network, 9.72 MHz (1215 x
8kHz) or 19.44MHz (2430 x 8kHz).
For systems using GPS, 8.184MHz (1023 x 8kHz).
For systems connected by a single hop of 100Mbps Ethernet where it is
possible to lock the physical layer clock, 25MHz (3125 x 8kHz).
When common clock is not used, connect to ground or VDD (3.3V).
MICROPROCESSOR PINS
Host Data Bus
IO
H_D[31:1] H_D[31:1]: Host data bus MSB is HD[31] when the host data bus width is 32
8mA
bits and HD_D[15] when the host data bus width is 16 bits.
Host Data Bus
H_D[0]: In CPU mode (H_CPU_SPI_N = 1), this pin is used as H_D[0], which
is the LSb of the CPU data bus.
IO
H_D[0]/SPI_MISO SPI MISO
8mA
SPI_MISO[0]: In SPI mode (H_CPU_SPI = 0), this pin is used as SPI MISO
output. If the SPI interface is not selected(SPI_SEL_N), this output is three-
state.
Host Address Bus
H_AD[24:1] I H_AD[24:1]: Host address bus, MSB is H_AD[24]. When the host data bus is
32 bits, H_AD[1] should be connected to VSS.
Host Chip Select
H_CS_N I
H_CS_N: Host chip select active low.
Host Read/Write
H_R_W_N: In CPU mode (H_CPU_SPI_N = 1), this input is host read/write.
H_R_W_N/SPI_CP I SPI Clock Phase
SPU_CP: In SPI mode (H_CPU_SPI_N = 0), this input is the SPI clock
phase.
H_D[7:0] Write Enable, Active Low
H_WR_BE0_N: In CPU mode (H_CPU_SPI_N = 1) this input is H_D[7:0]
H_WR_BE0_N/ write enable, active low.
I
SPI_CLK
SPI Clock
SPI_CLK: In SPI mode (H_CPU_SPI_N = 0), this input is SPI clock.
H_WR_BE1_N: In CPU mode (H_CPU_SPI_N = 1), this input is H_D[15:8]
I
SPI_MOSI
SPI_MOSI
SPI_MOSI: In SPI mode (H_CPU_SPI_N = 0), this input is SPI_MOSI.
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NAME TYPE FUNCTION
H_WR_BE2_N: In CPU mode (H_CPU_SPI_N = 1), this input is H_D[23:16]
I
SPI_SEL_N
SPI Select
SPI_SEL_N: In SPI mode (H_CPU_SPI_N = 0), this input is SPI_SEL_N.
H_WR_BE3_N: In CPU mode (H_CPU_SPI_N = 1), H_D[31:24] write
H_WR_BE3_N/ enable, active low.
I
SPI_CI SPI Clock Invert
SPI_CI: In SPI mode (H_CPU_SPI_N = 0), this input is clock invert for SPI
mode.
Host Ready
Oz H_READY_N: Host ready, active low. This pin requires the use of an external
H_READY_N
8mA pullup resistor. The signal is actively driven high 1 before it becomes three-
state.
Host Interrupt
O
H_INT[0] H_INT[0]: Host interrupts are active low. H_INT[0] is used for the TDM-over-
8mA
Packet.
Data 32/16-Bit Select
DAT_32_16_N Ipu DAT_32_16_N: Selects the host data bus width to be 16 when low 0 and 32
when high 1. This pin is ignored in SPI mode.
SPI Mode
H_CPU_SPI_N Ipu
H_CPU_SPI_N: 0 = SPI mode, CPU bus is disabled; 1 = Regular CPU bus.
MISCELLANEOUS PINS
System Reset
RST_SYS_N Ipu
RST_SYS_N: System reset, active low.
JTAG Test Mode Select
JTMS: This pin is sampled on the rising edge of JTCLK and is used to place
JTMS Ipu
the test access port into the various defined IEEE 1149.1 states. This pin has
a 10k pullup resistor.
JTAG Test Clock
JTCLK I JTCLK: This signal is used to shift data into JTDI on the rising edge and out
of JTDO on the falling edge..
JTAG Test Data In
JTDI Ipu JTDI: Test instructions and data are clocked into this pin on the rising edge of
JTCLK. This pin has a 10k pullup resistor.
JTAG Test Data Out
Oz
JTDO JTDO: Test instructions and data are clocked out of this pin on the falling
8mA
edge of JTCLK. If not used, this pin should be left unconnected.
JTAG Test Reset
JTRST_N: JTRST_N is used to asynchronously reset the test access port
controller. After power-up, JTRST_N must be toggled from low to high. This
JTRST_N Ipu action sets the device into the JTAG DEVICE ID mode. Pulling JTRST_N low
restores normal device operation. JTRST_N is pulled high internally via a
10k resistor operation. If boundary scan is not used, this pin should be held
low. This pin has an internal 10k pullup resistor.
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NAME TYPE FUNCTION
TEST PINS
SCEN I Used during factory test. Connect to DVSS.
STMD I Used during factory test. Connect to DVSS.
High-Impedance Test Enable (Active Low)
HIZ_N: This signal is used to enable testing. When this signal is low while
HIZ_N I JTRST_N is low, all the digital output and bidirectional pins are placed in the
high-impedance state. For normal operation this signal is high. This is an
asynchronous input.
MBIST_EN I Used during factory test. Connect to DVSS.
MBIST_DONE O Used during factory test. This pin should be a No Connection.
MBIST_FAIL O Used during factory test. This pin should be a No Connection.
TEST_CLK O Used during factory test. This pin should be a No Connection.
POWER PINS
DVSS Digital Ground for TDM-over-Packet
DVDDC 1.8V Core Supply Voltage for TDM-over-Packet
DVDDIO 3.3V Supply Voltage for I/O
ACVDD2 1.8V Analog CLAD Power Supply 2 used for CLK_HIGH Adaption
ACVDD1 1.8V Analog CLAD Power Supply 1
ACVSS2 Analog CLAD GND2 used for CLK_HIGH Adaption
ACVSS1 Analog CLAD GND1
Note: Pins with names ending with _N are active low.
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10 JTAG Information
For the latest JTAG model, go to: www.maxim-ic.com/tools/BSDL.
10.1 JTAG Description
The DS34S108 supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional
public instructions included are HIGHZ, CLAMP, and IDCODE. See Figure 10-1 for a block diagram. The
DS34S108 contains the following items, which meet the requirements set by the IEEE 1149.1 Standard Test
Access Port and Boundary Scan Architecture:
Test Access Port (TAP) TAP Controller
Instruction Register Bypass Register
Boundary Scan Register Device Identification Register
The Test Access Port has the necessary interface pins, namely JTCLK, JTRST_N, JTDI, JTDO, and JTMS. Details
on these pins can be found in Section 9.2. Details on the Boundary Scan Architecture and the Test Access Port
can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 10-1. JTAG Block Diagram
BOUNDRY SCAN
REGISTER
IDENTIFICATION
REGISTER
MUX
BYPASS REGISTER
INSTRUCTION
REGISTER
TEST ACCESS PORT SELECT

CONTROLLER
OUTPUT ENABLE
VDD VDD VDD
10k 10k 10k
JTDI JTMS JTCLK JTRST_N JTDO
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10.2 JTAG TAP Controller State Machine Description
This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. See
Figure 10-2 for details on each of the states described below. The TAP controller is a finite state machine that
responds to the logic level at JTMS on the rising edge of JTCLK.
Figure 10-2. JTAG TAP Controller State Machine
Test-Logic-Reset
1
0
Select 1 Select 1
1
Run-Test/Idle
DR-Scan IR-Scan
0
0 0
1 1
Capture-DR Capture-IR
0 0
Shift-DR Shift-IR
0 0
1 1
Exit1- DR 1 1
Exit1-IR
0 0
Pause-DR Pause-IR
0 0
1 1
0 Exit2-DR 0
Exit2-IR
1 1
Update-DR Update-IR
1 0 1 0
Test-Logic-Reset. Upon power-up of the device, the TAP controller starts in the Test-Logic-Reset state. The
instruction register contains the IDCODE instruction. All system logic on the device operates normally.
Run-Test-Idle. Run-Test-Idle is used between scan operations or during specific tests. The instruction register and
test register remain idle.
Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the
controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the controller to the Select-
IR-SCAN state.
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Capture-DR. Data may be parallel loaded into the test data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register
remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low or
it to the Exit1-DR state if JTMS is high.
Shift-DR. The test data register selected by the current instruction is connected between JTDI and JTDO and shifts
data one stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current
instruction is not placed in the serial path, it maintains its previous state.
Exit1-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state,
which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Pause-DR
state.
Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction retain their previous state. The controller remains in this state while JTMS is low. A rising edge on
JTCLK with JTMS high puts the controller in the Exit2-DR state.
Exit2-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state
and terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Shift-DR
state.
Update-DR. A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of
the Test registers into the data output latches. This prevents changes at the parallel output due to changes in the
shift register. A rising edge on JTCLK with JTMS low, puts the controller in the Run-Test-Idle state. With JTMS
high, the controller enters the Select-DR-Scan state.
Select-IR-Scan. All test registers retain their previous state. The instruction register remains unchanged during this
state. With JTMS low, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan
sequence for the instruction register. JTMS high during a rising edge on JTCLK puts the controller back into the
Test-Logic-Reset state.
Capture-IR. The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This
value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller enters the
Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller enters the Shift-IR state.
Shift-IR. In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts
data one stage for every rising edge of JTCLK towards the serial output. The parallel register, as well as all test
registers, remain at their previous states. A rising edge on JTCLK with JTMS high moves the controller to the Exit1-
IR state. A rising edge on JTCLK with JTMS low keeps the controller in the Shift-IR state while moving data one
stage through the Instruction shift register.
Exit1-IR. A rising edge on JTCLK with JTMS low puts the controller in the Pause-IR state. If JTMS is high on the
rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process.
Pause-IR. Shifting of the instruction register is halted temporarily. With JTMS high, a rising edge on JTCLK puts
the controller in the Exit2-IR state. The controller remains in the Pause-IR state if JTMS is low during a rising edge
on JTCLK.
Exit2-IR. A rising edge on JTCLK with JTMS high put the controller in the Update-IR state. The controller loops
back to the Shift-IR state if JTMS is low during a rising edge of JTCLK in this state.
Update-IR. The instruction shifted into the instruction shift register is latched into the parallel output on the falling
edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A
rising edge on JTCLK with JTMS low, puts the controller in the Run-Test-Idle state. With JTMS high, the controller
enters the Select-DR-Scan state.
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10.3 JTAG Instruction Register and Instructions
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the
TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in
the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one stage towards the serial output at JTDO.
A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high moves the controller to the
Update-IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the
instruction parallel output. Instructions supported by the DS34S108 and their respective operational binary codes
are shown in Table 10-1.
Table 10-1. JTAG Instruction Codes

INSTRUCTIONS SELECTED REGISTER INSTRUCTION CODES
SAMPLE/PRELOAD Boundary Scan 010
BYPASS Bypass 111
EXTEST Boundary Scan 000
CLAMP Bypass 011
HIGHZ Bypass 100
IDCODE Device Identification 001
10.3.1 SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os
of the device can be sampled at the boundary scan register without interfering with the normal operation of the
device by using the Capture-DR state. SAMPLE/PRELOAD also allows the DS34S108 to shift data into the
boundary scan register via JTDI using the Shift-DR state.
10.3.2 EXTEST
EXTEST allows testing of all interconnections to the device. When the EXTEST instruction is latched in the
instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all
digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The Capture-DR
samples all digital inputs into the boundary scan register.
10.3.3 BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the
one-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the devices normal
operation.
10.3.4 IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test register is
selected. The device identification code is loaded into the Identification register on the rising edge of JTCLK
following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via
JTDO. During Test-Logic-Reset, the identification code is forced into the instruction registers parallel output. The
device ID code always has a one in the LSB position. The device ID codes are listed in Table 10-2.
10.3.5 HIGHZ
All digital outputs are placed into a high-impedance state. The bypass register is connected between JTDI and
JTDO.
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10.3.6 CLAMP
All digital outputs pins output data from the boundary scan parallel output while connecting the bypass register
between JTDI and JTDO. The outputs do not change during the CLAMP instruction.
Table 10-2. JTAG ID Code

ID CODE (hex)
DEVICE
Rev[31:28] Device ID [27:12] Manu[11:0]
DS34S108 0 009B 143
DS34S104 0 009A 143
DS34S102 0 0099 143
DS34S101 0 0098 143
10.4 JTAG Test Registers
IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An
optional test register has been included in the device design. This test register is the identification register and is
used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
10.4.1 Bypass Register
The bypass register is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions, providing a short path between JTDI and JTDO.
10.4.2 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
10.4.3 Boundary Scan Register
The boundary scan register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is 32 bits in length. The BSDL file found at www.maxim-ic.com/tools/bsdl shows the entire
cell bit locations and definitions.
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11 DC Electrical Characteristics
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Input, Bidirectional or Open Drain
Output Lead with Respect to DVSS ...................................................................................................-0.5V to +5.5V
Supply Voltage Range (VDDIO) with Respect to DVSS.........................................................................-0.5V to +3.6V
Supply Voltage Range (DVDDC) with Respect to DVSS .......................................................................-0.5V to +2.0V
Ambient Operating Temperature Range ..............................................................................................-40C to +85C
Junction Operating Temperature Range ........................................................................................... -40C to +125C
Storage Temperature Range ............................................................................................................. -55C to +125C
Soldering Temperature .................................................................. Refer to the IPC/JEDEC J-STD-020 Specification.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods can affect reliability. Ambient
Operating Temperature Range is assuming the device is mounted on a JEDEC standard test board in a convection cooled JEDEC test
enclosure.
Note: The typical values listed in the tables are not production tested.
Table 11-1. Recommended DC Operating Conditions

(TJ = -40C to +85C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Logic 1 VIH 2.4 3.465 V
Output Logic 0 VIL -0.3 +0.8 V
DVDDIO 3.135 3.300 3.465 V
Supply 5%
DVDDC 1.71 1.8 1.89 V
Table 11-2. DC Electrical Characteristics
(TJ = -40C to +85C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
3.3V Supply Current
IDDIO (Note 1) 50 65 mA
(DVDDIO = 3.465V)
1.8V Supply Current
IDDC (Note 1) 225 280 mA
(DVDDC = 1.89V)
Lead Capacitance CIO 7 pF
Input Leakage IIL -10 +10 A
Input Leakage IILP -100 -10 A
Output Leakage (when High-Z) ILO -10 +10 A
Output Voltage (IOH = -4.0mA) VOH 4mA output 2.4 V
Output Voltage (IOL = +4.0mA) VOL 4mA output 0.4 V
Output Voltage (IOL = -8.0mA) VOL 8mA output 0.4 V
Output Voltage (IOL = +12.0mA) VOL 12mA output 0.4 V
Input Voltage Logic 0 VIL 0.8 V
Input Voltage Logic 1 VIH 2.0 V
Note 1: All outputs loaded with rated capacitance; all inputs between DVDDIO and DVSS; inputs with pullups connected to DVDDIO.
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12 AC Timing Characteristics
Refer to the full data sheet for this information.
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13 Application Interfaces
13.1 Connecting a Serial Interface Transceiver
Figure 13-1 shows the connection of the chip to a serial interface transceiver such as V.35 or RS-530. The figure
shows the first port in a DCE (Data Communications Equipment) application. All other ports can be connected in
the same way.
Each direction (Tx and Rx) has its own clock. However, TDM1_RCLK is optional, as the TDM-over-Packet chip can
work in single clock mode (two_clocks = 0) in which both directions are clocked by TDM1_TCLK. The clock source
of TDM1_RCLK or TDM1_TCLK can be either:
Internal (from the local oscillator)

External
Recovered from the packet network (provided by the DS34S108)
The control input signal TDM1_RSIG_RTS does not affect the data reception.
The TDM1_TSIG_CTS and TDM1_TX_MF_CD outputs are set by software.
The TDM1_RSIG_RTS value can be read by software.
A maskable interrupt can be asserted when RTS value changes.
Figure 13-1. Connecting the First Port to a Serial Transceiver
Tx TDM 1_ TX
Rx TDM 1_ RX DS34S108
SERIAL INTERFACE TCLK TDM 1_ TCLK

TRANSCEIVER
(DCE MODE) RCLK TDM 1_ RCLK
CTS TDM 1_ TSIG _ CTS
RTS TDM 1_ RSIG _ RTS
CD TDM 1_ TX_ MF _ CD
TDM 1_ ACLK
EXTERNAL INTERNAL
CLOCK CLOCK
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13.2 Connecting an External E1/T1 Framer
Figure 13-2, Figure 13-3, Figure 13-4, and Figure 13-5 show the connection of the first port of a DS34S108 to an
E1/T1 framer. All other ports can be connected in the same way.
In single-clock mode (two_clocks = 0) both Tx and Rx directions are clocked by TDM1_TCLK. Thus the framers
receive elastic buffer must be enabled.
The clock source of TDM1_TCLK can be either:
Internal (from the local oscillator)

External
Recovered from the packet network (provided by the DS34S108)
RCLK (from the LIU)
In two-clock mode (two_clocks = 1) Tx direction is clocked by TDM1_TCLK and Rx direction is clocked by
TDM1_RCLK. The clock source of TDM1_TCLK is the same as single-clock mode, and TDM1_RCLK should be
connected to the LIUs RCLK. This disables the receive elastic buffer of the framer.
Any of the SYNC or multiframe SYNC inputs can be left unconnected or connected to ground if the framer cannot
drive them. The chip has an internal free-running counter that generates these signals internally when not driven by
an external source. These internally generated sync signals are synchronized to the sync input pulse when one
exists.
Figure 13-2. External E1/T1 Framer in Applications with CAS (Single-Clock Mode)
Tx TDM 1_ TX
DS34S108
Rx TDM 1_ RX
RSYSCLK
E1/T1
FRAMER TCLK TDM 1_ TCLK
TX_SYNC TDM 1_ TX_SYNC
TSIG TDM 1_ TSIG _ CTS
RSIG TDM 1_ RSIG _ RTS
TDM 1_ TX_ MF _ CD
RX_SYNC TDM 1_ RX _ SYNC
LIU _ RCLK TDM 1_ ACLK
EXTERNAL CLOCK INTERNAL CLOCK
Framer TX_SYNC and RX_SYNC are asserted for one clock cycle every 1.5ms, 2ms, or 3ms for T1-SF, E1-MF, or
T1-ESF, respectively.
Framer RSYSCLK is the receive elastic buffer clock used to sample the Rx framer output. DS34S108 TDM1_RCLK
is not used in the single-clock mode.
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_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
Figure 13-3. External E1/T1 Framer in Applications without CAS (Single-Clock Mode)
Tx TDM 1_ TX
DS34S108
Rx TDM 1_ RX
RSYSCLK
TCLK TDM 1_ TCLK

TX_SYNC TDM 1_ TX_SYNC
x TDM 1_ TSIG _ CTS
RX_SYNC
TDM 1_ RSIG _ RTS
E1/T1 TDM 1_ TX_ MF _ CD
FRAMER
TDM 1_ RX_ SYNC
LIU _ RCLK TDM 1_ ACLK
Framer TX_SYNC is asserted for one clock cycle every N 125s.
Framer RSYSCLK is the receive elastic buffer clock used to sample the Rx framer output. DS34S108 TDM1_RCLK
and TDM1_RX_SYNC are not used for this application.
Figure 13-4. External E1/T1 Framer in Applications with CAS (Two-Clock Mode)
E1/T1 Tx TDM1_TX
FRAMER DS34S108
Rx TDM1_RX
TCLK TDM1_TCLK
TDM1_RCLK
RX_SYNC TDM1_RX_SYNC
TX_SYNC TDM1_TX_SYNC
TDM1_TX_MF_CD
TSIG TDM1_TSIG_RTS
RSIG TDM1_RSIG_RTS
LIU_RCLK
TDM1_ACLK
Framer TX_SYNC and RX_SYNC are asserted for one clock cycle every 1.5ms, 2ms, or 3ms for T1-SF, E1-MF, or
T1-ESF, respectively.
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_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
Figure 13-5. External E1/T1 Framer in Applications WO/CAS (Two-Clock Mode)
Tx TDM1_TX
E1/T1 DS34S108
Rx TDM1_RX
FRAMER
TCLK TDM1_TCLK
TDM1_RCLK
RX_SYNC TDM1_RX_SYNC
TX_SYNC TDM1_TX_SYNC
LIU_RCLK
TDM1_ACLK
Framer TX_SYNC and RX_SYNC are asserted for one clock cycle every N 125s.
13.3 Connecting an Ethernet MAC or PHY
Figure 13-6, Figure 13-7, Figure 13-8, Figure 13-9, Figure 13-10, and Figure 13-11 show the connection of the
DS34S108s Ethernet port to a MAC or PHY device in MII, RMII, and SSMII modes.
In SSMII mode there are two clock signals, one for each direction (Rx and Tx), routed together with the sync and
data signals. As the delay between the clock and these signals is lower, the designer can apply a longer trace
delay in this mode.
Figure 13-6. Connecting the Ethernet Port to a PHY in MII Mode
MII_TXD[3:0] TXD[3:0]
PHY
DS34S108 MII_RXD[3:0] RXD[3:0]
MII_TX_EN TX_EN
MII_RX_DV RX_DV
MII_TX_ERR TX_ERR
MII_RX_ERR RX_ERR
MII_COL COL
MII_CRS CRS
CLK_MII_TX CLK_TX
CLK_MII_RX CLK_RX
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_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
Figure 13-7. Connecting the Ethernet Port to a MAC in MII Mode
MAC
MII_RXD[3:0] RXD[3:0]
MII_TX_EN TX_EN
DS34S108 MII_RX_DV RX_DV
MII_TX_ERR x x TX_ERR
MII_RX_ERR RX_ERR
MII_COL COL
MII_CRS CRS
CLK_MII_TX CLK_TX
CLK_MII_RX CLK_RX
25MHz
OSC
Figure 13-8. Connecting the Ethernet Port to a PHY in RMII Mode
PHY
MII_TX_EN TX_EN
MII_RX_DV RX_DV
DS34S108
MII_RX_ERR RX_ERR
CLK_MII_TX CLK
Figure 13-9. Connecting the Ethernet Port to a MAC in RMII Mode
MAC
MII_TX_EN TX_EN
MII_RX_DV RX_DV
DS34S108
MII_RX_ERR RX_ERR
CLK_MII_TX CLK
50MHz
OSC
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_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
Figure 13-10. Connecting the Ethernet Port to a PHY in SSMII Mode
MII_TXD[0] TXD
PHY
MII_TXD[1] TXSYNC
MII_RXD[0] RXD
MII_RXD[1] RXSYNC
DS34S108
CLK_SSMII_TX CLK_TX
CLK_MII_RX CLK_RX
CLK_MII_TX CLK_REF
125MHz
OSC
Figure 13-11. Connecting the Ethernet Port to a MAC in SSMII Mode
MII_TXD[0] TXD
MAC
MII_TXD[1] TXSYNC
MII_RXD[0] RXD
MII_RXD[1] RXSYNC
DS34S108
CLK_SSMII_TX CLK_TX
CLK_MII_RX CLK_RX
CLK_MII_TX CLK_REF
125MHz
OSC
For the above applications, apply the following layout considerations:

Provide termination on all high-speed interface signals and clock lines.
Provide impedance matching on long traces to prevent reflections.
Keep the clock traces away from all other signals to minimize mutual interference.
In RMII mode, a very low skew clock buffer/driver is recommended to maximize the timing budget. In this mode
it is recommended to keep all traces as short as possible.
In SSMII mode, keep data/sync traces and clock traces at the same length to maximize the timing budget.
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_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
13.4 Implementing Clock Recovery in High-Speed Applications
For the high-speed interface (up to 51.84MHz), an external clock multiplier and jitter attenuator are needed. Clock
recovery in high-speed applications is depicted in Figure 13-12.
Figure 13-12. External Frequency Synthesis
LIU (WITH JITTER CLOCK MULTIPLIER

ATTENUATOR) DS34S108
Tx CLK OUT IN A CLK
The clock multiplier converts the low-speed clock at ACLK to a high-speed clock. It multiplies the input by 12 for E3
and T3 interfaces and by 10 for the STS-1 interface. The clock multiplier should be tuned to add minimum jitter.
The jitter attenuator can be part of the LIU or an independent part.
13.5 Connecting a Motorola MPC860 Host
The DS34S108 can be easily connected to a Motorola MPC860 host by means of the MPC860 GPCM (General-
Purpose Chip-Select Machine) module.
13.5.1 Connecting the Bus Signals
Because the MPC860 bus MSB is always 0, whereas the DS34S108 LSB is always 0, the signal order should be
switched as depicted in Figure 13-13 and Figure 13-14.
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_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
Figure 13-13. 32-Bit CPU Bus Connections
A[0:6]
MSB A7 H_AD24 MSB
A8 H_AD23
A9 H_AD22
A10 H_AD21
A11 H_AD20
A12 H_AD19
A13 H_AD18
A14 H_AD17
A15 H_AD16
A16 H_AD15
A17 H_AD14
A18 H_AD13
A19 H_AD12
A20 H_AD11
A21 H_AD10
A22 H_AD9
A23 H_AD8
A24 H_AD7
A25 H_AD6
A26 H_AD5
A27 H_AD4
A28 H_AD3
A29 H_AD2
A30 H_AD1
LSB A31 GND LSB
MSB D0 H_D31 MSB
D1 H_D30
D2 H_D29
D3 H_D28
D4 H_D27
MPC860 D5 H_D26
D6 H_D25
D7 H_D24 DS34S108
D8 H_D23
D9 H_D22
D10 H_D21
D11 H_D20
D12 H_D19
D13 H_D18
D14 H_D17
D15 H_D16
D16 H_D15
D17 H_D14
D18 H_D13
D19 H_D12
D20 H_D11
D21 H_D10
D22 H_D9
D23 H_D8
D24 H_D7
D25 H_D6
D26 H_D5
D27 H_D4
D28 H_D3
D29 H_D2
D30 H_D1
LSB D31 H_D0 LSB
BE0 H_WR_BE3_N
BE1 H_WR_BE2_N
BE2 H_WR_BE1_N
BE3 H_WR_BE0_N
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_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
Figure 13-14. 16-Bit CPU Bus Connections
A[6:0]
MSB A7 H_AD24 MSB
A8 H_AD23
A9 H_AD22
A10 H_AD21
A11 H_AD20
A12 H_AD19
A13 H_AD18
A14 H_AD17
A15 H_AD16
A16 H_AD15
A17 H_AD14
A18 H_AD13
A19 H_AD12
A20 H_AD11
A21 H_AD10
A22 H_AD9
A23 H_AD8
A24 H_AD7
A25 H_AD6
A26 H_AD5
A27 H_AD4
A28 H_AD3
A29 H_AD2
A30 H_AD1
LSB A31 LSB
VCC
H_D31
H_D30
H_D29
H_D28
H_D27
MC860 H_D26
H_D25
H_D24 DS34S108
H_D23
H_D22
H_D21
H_D20
H_D19
H_D18
H_D17
H_D16
MSB D0 H_D15 MSB
D1 H_D14
D2 H_D13
D3 H_D12
D4 H_D11
D5 H_D10
D6 H_D9
D7 H_D8
D8 H_D7
D9 H_D6
D10 H_D5
D11 H_D4
D12 H_D3
D13 H_D2
D14 H_D1
LSB D15 H_D0 LSB
VCC VCC
H_WR_BE3_N
H_WR_BE2_N
BE0 H_WR_BE1_N
BE1 H_WR_BE0_N
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_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
Unused data bus pins (H_D[31:16]) on the DS34S108 should be pulled up by using external resistors.
H_WR_BE2_N and H_WR_BE3_N should be pulled up (can be connected to VCC directly).
13.5.2 Connecting the H_READY_N Signal
The DS34S108 H_READY_N output should be connected to the MPC860 TA input. The CPU bus operates
asynchronously. The TA of the MPC860 is a synchronous input (i.e., needs to meet Tsu/Th). The designer should
synchronize H_READY_N to the MPC860 clock by means of a CPLD, which uses the MPC860 reference clock.
The internal logic in the CPLD also uses the MPC860 CS output. Both H_READY_N output and MPC860 TA input
should have a 1k pullup resistor.
Figure 13-15. Asynchronous ModeConnection of H_READY_N to MPC860 TA
VCC
VCC
MPC860
1k
DS34S108
TA 1k
CLKOUT CPLD H_READY_N
CS
H_CS_N
R/W H_R_W_N
Figure 13-16. CPLD Logic, Synchronizing H_READY_N to the MPC860 Clock
Another alternative for connecting the H_READY_N asynchronous is using the MPC860 UPM. In this option, the
H_READY_N output should be connected to the MPC860 UPWAIT (GPL4) signal, and no external timing
adjustment is needed. The H_READY_N output should have a 1k pullup resistor.
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_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
13.6 Working in SPI Mode
Table 13-1 illustrates the I/O connections for the DS34S108 operating in SPI mode.
Table 13-1. SPI Mode I/O Connections

SIGNAL NAME CONNECT TO COMMENTS
H_CPU_SPI_N 0 Selects SPI mode
DAT_32_16_N 1
H_CS_N 1
Known logical value
H_AD[24:1]
(either 1 or 0)
Known logical value
H_D[31:1]
(either 0 or 1)
H_D (0)/SPI_MISO Master MISO
H_WR_BE0_N/SPI_CLK Master SPI clock
H_WR_BE1_N/SPI_MOSI Master MOSI
H_WR_BE2_N/SPI_SEL_N Master SPI select
H_WR_BE3_N/SPI_CI Either 1 or 0 According to required SPI mode
H_R_W_N/SPI_CP Either 1 or 0 According to required SPI mode
13.7 Connecting SDRAM Devices
Table 13-2 lists suggested SDRAM devices to use in conjunction with the DS34S108.
Table 13-2. List of Suggested SDRAM Devices

VENDOR 64Mb DEVICE 128Mb DEVICE
Micron MT48LC2M32B2TG-6 MT48LC4M32B2TG-6
Samsung K4S643232H-TC/L60 K4S283232E-TC/L60
HY57V653220BTC-6 or
Hynix HY57V283220T-6
HY57V643220CT-6
Elpida N/A EDS1232AATA-60
Winbond W986432DH-6 N/A
IC42S32200/L-6T or
ICSI N/A
IC42S32200/L-6TI
ISSI IS42S32200C1-6T IS42S32400B-6T
When connecting the DS34S108 to an external SDRAM, it is advised to connect SD_CLK through a serial
termination resistor.
When connecting the DS34S108 to a 64Mb external SDRAM, it is advised to connect SD_A[11] through a serial
resistor to the SDRAM NC pin, that is A11 in a 128Mb SDRAM. In this way, a 128Mb SDRAM can be used on the
same board, if needed.
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_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
14 Pin Assignment
14.1 Board Design for the DS34S108 Family of Products
The DS34S108 is in a 484-ball TEBGA package. The DS34S104, S102, and S101 are all in a 256-ball TECSBGA
package. These three devices require the same footprint on the board.
The following information pertains only to the DS34S104, DS34S102, and DS34S101 devices. See Section 14.2
for DS34S108 pin assignments.
It is recommended that users design their board in such a way that it supports the stuffing of higher port-count
devices into a lower port-count socket. If lower port-count designs are to be potentially stuffed with higher port-
count devices, consideration must be taken during board design to bias the unused inputs, input/outputs, and
outputs appropriately. Generally, unused inputs are connected directly to the ground plane, unused outputs are not
connected, and unused input/outputs are connected to ground through a 10k resistor. Unused inputs with internal
pullups or pulldowns are not connected. Table 14-1 designates how each ball on the package should be connected
to implement a common board design. Shading indicates balls for the unused inputs, input/outputs, and outputs of
higher port-count devices.
When a user does stuff a socket with a higher port-count device, he/she will need a slightly modified BSDL file,
available from the factory upon request.
In this case, a higher port-count device includes only the DS34S102 and the DS34S104. Because the DS34S108
is in a different package, it cannot be stuffed on a 256-ball footprint.
The user may decide to not implement a common board design. In that event, the balls for the unused inputs,
input/outputs, and outputs need not be connected, and the stuffing of higher port-count devices into a lower port-
count socket is not recommended.
Table 14-1. Common Board Design Connections

BALL DS34S104 SOCKET DS34S102 SOCKET DS34S101 SOCKET
R8 ACVDD1 ACVDD1 ACVDD1
T8 ACVDD2 ACVDD2 ACVDD2
P8 ACVSS1 ACVSS1 ACVSS1
T9 ACVSS2 ACVSS2 ACVSS2
M14 CLK_CMN CLK_CMN CLK_CMN
P9 CLK_HIGH CLK_HIGH CLK_HIGH
A16 CLK_MII_RX CLK_MII_RX CLK_MII_RX
D15 CLK_MII_TX CLK_MII_TX CLK_MII_TX
E15 CLK_SSMII_TX CLK_SSMII_TX CLK_SSMII_TX
T12 CLK_SYS CLK_SYS/SCCLK CLK_SYS/SCCLK
R9 CLK_SYS_S CLK_SYS_S CLK_SYS_S
M4 DAT_32_16_N DAT_32_16_N DAT_32_16_N
F10 DVDDC DVDDC DVDDC
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_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
M10 DVDDC DVDDC DVDDC
G12 DVDDIO DVDDIO DVDDIO
H12 DVDDIO DVDDIO DVDDIO
J12 DVDDIO DVDDIO DVDDIO
J5 DVDDIO DVDDIO DVDDIO
K12 DVDDIO DVDDIO DVDDIO
K5 DVDDIO DVDDIO DVDDIO
L12 DVDDIO DVDDIO DVDDIO
L5 DVDDIO DVDDIO DVDDIO
M5 DVDDIO DVDDIO DVDDIO
N10 DVDDIO DVDDIO DVDDIO
G10 DVSS DVSS DVSS
G11 DVSS DVSS DVSS
G6 DVSS DVSS DVSS
G7 DVSS DVSS DVSS
G8 DVSS DVSS DVSS
G9 DVSS DVSS DVSS
H10 DVSS DVSS DVSS
H11 DVSS DVSS DVSS
H5 DVSS DVSS DVSS
H6 DVSS DVSS DVSS
H7 DVSS DVSS DVSS
H8 DVSS DVSS DVSS
H9 DVSS DVSS DVSS
J10 DVSS DVSS DVSS
J11 DVSS DVSS DVSS
J6 DVSS DVSS DVSS
J7 DVSS DVSS DVSS
J8 DVSS DVSS DVSS
J9 DVSS DVSS DVSS
K10 DVSS DVSS DVSS
K11 DVSS DVSS DVSS
K6 DVSS DVSS DVSS
K7 DVSS DVSS DVSS
K8 DVSS DVSS DVSS
K9 DVSS DVSS DVSS
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_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
L10 DVSS DVSS DVSS
L11 DVSS DVSS DVSS
L6 DVSS DVSS DVSS
L7 DVSS DVSS DVSS
L8 DVSS DVSS DVSS
L9 DVSS DVSS DVSS
R13 H_AD[1] H_AD[1] H_AD[1]
C10 H_AD[10] H_AD[10] H_AD[10]
E12 H_AD[11] H_AD[11] H_AD[11]
A12 H_AD[12] H_AD[12] H_AD[12]
T15 H_AD[13] H_AD[13] H_AD[13]
C12 H_AD[14] H_AD[14] H_AD[14]
D12 H_AD[15] H_AD[15] H_AD[15]
T16 H_AD[16] H_AD[16] H_AD[16]
B13 H_AD[17] H_AD[17] H_AD[17]
R14 H_AD[18] H_AD[18] H_AD[18]
B10 H_AD[19] H_AD[19] H_AD[19]
D13 H_AD[2] H_AD[2] H_AD[2]
P14 H_AD[20] H_AD[20] H_AD[20]
A10 H_AD[21] H_AD[21] H_AD[21]
B11 H_AD[22] H_AD[22] H_AD[22]
N14 H_AD[23] H_AD[23] H_AD[23]
A11 H_AD[24] H_AD[24] H_AD[24]
P13 H_AD[3] H_AD[3] H_AD[3]
D10 H_AD[4] H_AD[4] H_AD[4]
E13 H_AD[5] H_AD[5] H_AD[5]
D11 H_AD[6] H_AD[6] H_AD[6]
N13 H_AD[7] H_AD[7] H_AD[7]
A13 H_AD[8] H_AD[8] H_AD[8]
T14 H_AD[9] H_AD[9] H_AD[9]
L4 H_CPU_SPI_N H_CPU_SPI_N H_CPU_SPI_N
E11 H_CS_N H_CS_N H_CS_N
K13 H_D[0]/SPI_MISO H_D[0]/SPI_MISO H_D[0]/SPI_MISO
M12 H_D[1] H_D[1] H_D[1]
M13 H_D[10] H_D[10] H_D[10]
P16 H_D[11] H_D[11] H_D[11]
K14 H_D[12] H_D[12] H_D[12]
M15 H_D[13] H_D[13] H_D[13]
J14 H_D[14] H_D[14] H_D[14]
M16 H_D[15] H_D[15] H_D[15]
L14 H_D[16] H_D[16] H_D[16]
L16 H_D[17] H_D[17] H_D[17]
J15 H_D[18] H_D[18] H_D[18]
K16 H_D[19] H_D[19] H_D[19]
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_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
R15 H_D[2] H_D[2] H_D[2]
N16 H_D[20] H_D[20] H_D[20]
B12 H_D[21] H_D[21] H_D[21]
J16 H_D[22] H_D[22] H_D[22]
F12 H_D[23] H_D[23] H_D[23]
F13 H_D[24] H_D[24] H_D[24]
G13 H_D[25] H_D[25] H_D[25]
H13 H_D[26] H_D[26] H_D[26]
F14 H_D[27] H_D[27] H_D[27]
G14 H_D[28] H_D[28] H_D[28]
H14 H_D[29] H_D[29] H_D[29]
L13 H_D[3] H_D[3] H_D[3]
H16 H_D[30] H_D[30] H_D[30]
H15 H_D[31] H_D[31] H_D[31]
K15 H_D[4] H_D[4] H_D[4]
P15 H_D[5] H_D[5] H_D[5]
J13 H_D[6] H_D[6] H_D[6]
N15 H_D[7] H_D[7] H_D[7]
L15 H_D[8] H_D[8] H_D[8]
R16 H_D[9] H_D[9] H_D[9]
T13 H_INT[0] H_INT[0] H_INT[0]
N12 H_R_W_N/SPI_CP H_R_W_N/SPI_CP H_R_W_N/SPI_CP
R12 H_READY_N H_READY_N H_READY_N
C13 H_WR_BE0_N/SPI_CLK H_WR_BE0_N/SPI_CLK H_WR_BE0_N/SPI_CLK
P12 H_WR_BE1_N/SPI_MOSI H_WR_BE1_N/SPI_MOSI H_WR_BE1_N/SPI_MOSI
E10 H_WR_BE2_N/SPI_SEL_N H_WR_BE2_N/SPI_SEL_N H_WR_BE2_N/SPI_SEL_N
C11 H_WR_BE3_N/SPI_CI H_WR_BE3_N/SPI_CI H_WR_BE3_N/SPI_CI
N11 HIZ_N HIZ_N HIZ_N
R10 JTCLK JTCLK JTCLK
P10 JTDI JTDI JTDI
P11 JTDO JTDO JTDO
T10 JTMS JTMS JTMS
T11 JTRST_N JTRST_N JTRST_N
N5 MBIST_DONE MBIST_DONE MBIST_DONE
N6 MBIST_EN MBIST_EN MBIST_EN
R4 MBIST_FAIL MBIST_FAIL MBIST_FAIL
G16 MDC MDC MDC
G15 MDIO MDIO MDIO
B15 MII_COL MII_COL MII_COL
C15 MII_CRS MII_CRS MII_CRS
F16 MII_RX_DV MII_RX_DV MII_RX_DV
A15 MII_RX_ERR MII_RX_ERR MII_RX_ERR
B16 MII_RXD[0] MII_RXD[0] MII_RXD[0]
C16 MII_RXD[1] MII_RXD[1] MII_RXD[1]
Rev: 040108 55 of 69
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_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
D16 MII_RXD[2] MII_RXD[2] MII_RXD[2]
E16 MII_RXD[3] MII_RXD[3] MII_RXD[3]
D14 MII_TX_EN MII_TX_EN MII_TX_EN
E14 MII_TX_ERR MII_TX_ERR MII_TX_ERR
F15 MII_TXD[0] MII_TXD[0] MII_TXD[0]
A14 MII_TXD[1] MII_TXD[1] MII_TXD[1]
B14 MII_TXD[2] MII_TXD[2] MII_TXD[2]
C14 MII_TXD[3] MII_TXD[3] MII_TXD[3]
R11 RST_SYS_N RST_SYS_N RST_SYS_N
J4 SCEN SCEN SCEN
D2 SD_A[0] SD_A[0] SD_A[0]
C3 SD_A[1] SD_A[1] SD_A[1]
A4 SD_A[10] SD_A[10] SD_A[10]
F2 SD_A[11] SD_A[11] SD_A[11]
E1 SD_A[2] SD_A[2] SD_A[2]
A3 SD_A[3] SD_A[3] SD_A[3]
E2 SD_A[4] SD_A[4] SD_A[4]
B3 SD_A[5] SD_A[5] SD_A[5]
E3 SD_A[6] SD_A[6] SD_A[6]
C4 SD_A[7] SD_A[7] SD_A[7]
B4 SD_A[8] SD_A[8] SD_A[8]
D3 SD_A[9] SD_A[9] SD_A[9]
D1 SD_BA[0] SD_BA[0] SD_BA[0]
A2 SD_BA[1] SD_BA[1] SD_BA[1]
C1 SD_CAS_N SD_CAS_N SD_CAS_N
B2 SD_CLK SD_CLK SD_CLK
C2 SD_CS_N SD_CS_N SD_CS_N
E4 SD_D[0] SD_D[0] SD_D[0]
B5 SD_D[1] SD_D[1] SD_D[1]
B6 SD_D[10] SD_D[10] SD_D[10]
F3 SD_D[11] SD_D[11] SD_D[11]
A6 SD_D[12] SD_D[12] SD_D[12]
F4 SD_D[13] SD_D[13] SD_D[13]
B8 SD_D[14] SD_D[14] SD_D[14]
D7 SD_D[15] SD_D[15] SD_D[15]
F5 SD_D[16] SD_D[16] SD_D[16]
C7 SD_D[17] SD_D[17] SD_D[17]
A7 SD_D[18] SD_D[18] SD_D[18]
D8 SD_D[19] SD_D[19] SD_D[19]
F1 SD_D[2] SD_D[2] SD_D[2]
G2 SD_D[20] SD_D[20] SD_D[20]
E8 SD_D[21] SD_D[21] SD_D[21]
G3 SD_D[22] SD_D[22] SD_D[22]
A8 SD_D[23] SD_D[23] SD_D[23]
Rev: 040108 56 of 69
ABRIDGED DATA SHEET
_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
B9 SD_D[24] SD_D[24] SD_D[24]
G4 SD_D[25] SD_D[25] SD_D[25]
E9 SD_D[26] SD_D[26] SD_D[26]
G5 SD_D[27] SD_D[27] SD_D[27]
A9 SD_D[28] SD_D[28] SD_D[28]
D9 SD_D[29] SD_D[29] SD_D[29]
C6 SD_D[3] SD_D[3] SD_D[3]
C9 SD_D[30] SD_D[30] SD_D[30]
C8 SD_D[31] SD_D[31] SD_D[31]
G1 SD_D[4] SD_D[4] SD_D[4]
B7 SD_D[5] SD_D[5] SD_D[5]
D5 SD_D[6] SD_D[6] SD_D[6]
D6 SD_D[7] SD_D[7] SD_D[7]
E7 SD_D[8] SD_D[8] SD_D[8]
E5 SD_D[9] SD_D[9] SD_D[9]
C5 SD_DQM[0] SD_DQM[0] SD_DQM[0]
D4 SD_DQM[1] SD_DQM[1] SD_DQM[1]
E6 SD_DQM[2] SD_DQM[2] SD_DQM[2]
A5 SD_DQM[3] SD_DQM[3] SD_DQM[3]
A1 SD_RAS_N SD_RAS_N SD_RAS_N
B1 SD_WE_N SD_WE_N SD_WE_N
H4 STMD STMD STMD
R5 TDM1_ACLK TDM1_ACLK TDM1_ACLK
T7 TDM1_RCLK TDM1_RCLK TDM1_RCLK
P7 TDM1_RSIG_RTS TDM1_RSIG_RTS TDM1_RSIG_RTS
T5 TDM1_RX TDM1_RX TDM1_RX
P5 TDM1_RX_SYNC TDM1_RX_SYNC TDM1_RX_SYNC
T6 TDM1_TCLK TDM1_TCLK TDM1_TCLK
P6 TDM1_TSIG_CTS TDM1_TSIG_CTS TDM1_TSIG_CTS
T4 TDM1_TX TDM1_TX TDM1_TX
R7 TDM1_TX_MF_CD TDM1_TX_MF_CD TDM1_TX_MF_CD
R6 TDM1_TX_SYNC TDM1_TX_SYNC TDM1_TX_SYNC
R1 TDM2_ACLK TDM2_ACLK NC
P4 TDM2_RCLK TDM2_RCLK NC
T3 TDM2_RSIG_RTS TDM2_RSIG_RTS NC
P2 TDM2_RX TDM2_RX NC
T1 TDM2_RX_SYNC TDM2_RX_SYNC NC
P3 TDM2_TCLK TDM2_TCLK NC
T2 TDM2_TSIG_CTS TDM2_TSIG_CTS NC
P1 TDM2_TX TDM2_TX NC
R3 TDM2_TX_MF_CD TDM2_TX_MF_CD NC
R2 TDM2_TX_SYNC TDM2_TX_SYNC NC
M2 TDM3_ACLK NC NC
M1 TDM3_RCLK NC NC
Rev: 040108 57 of 69
ABRIDGED DATA SHEET
_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
N4 TDM3_RSIG_RTS NC NC
L2 TDM3_RX NC NC
N2 TDM3_RX_SYNC NC NC
L3 TDM3_TCLK NC NC
N3 TDM3_TSIG_CTS NC NC
L1 TDM3_TX NC NC
N1 TDM3_TX_MF_CD NC NC
M3 TDM3_TX_SYNC NC NC
J2 TDM4_ACLK NC NC
J1 TDM4_RCLK NC NC
K4 TDM4_RSIG_RTS NC NC
H2 TDM4_RX NC NC
K2 TDM4_RX_SYNC NC NC
H3 TDM4_TCLK NC NC
K3 TDM4_TSIG_CTS NC NC
H1 TDM4_TX NC NC
K1 TDM4_TX_MF_CD NC NC
J3 TDM4_TX_SYNC NC NC
Rev: 040108 58 of 69
ABRIDGED DATA SHEET
_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
14.2 DS34S108 Pin Assignment
Table 14-2. DS34S108 Pin Assignment (Sorted by Signal Name)

SIGNAL NAME BALL SIGNAL NAME BALL SIGNAL NAME BALL SIGNAL NAME BALL
ACVDD1 M2 H_AD[18] M19 NC C1 SD_D[1] F21
ACVDD2 K2 H_AD[19] N21 NC C10 SD_D[10] B22
ACVSS1 M1 H_AD[2] M21 NC C2 SD_D[11] H20
ACVSS2 K1 H_AD[20] M17 NC C5 SD_D[12] C21
CLK_CMN P1 H_AD[21] P20 NC C6 SD_D[13] H18
CLK_HIGH L1 H_AD[22] R22 NC C7 SD_D[14] C22
CLK_MII_RX V16 H_AD[23] N17 NC C8 SD_D[15] D21
CLK_MII_TX AA18 H_AD[24] T21 NC C9 SD_D[16] G20
CLK_SSMII_TX Y19 H_AD[3] K16 NC D3 SD_D[17] D22
CLK_SYS/SCCLK J1 H_AD[4] M22 NC D5 SD_D[18] J20
CLK_SYS_S J2 H_AD[5] T20 NC D6 SD_D[19] G21
DAT_32_16_N L21 H_AD[6] M18 NC D7 SD_D[2] G19
DVDDC A12 H_AD[7] M16 NC D8 SD_D[20] J21
DVDDC B11 H_AD[8] M20 NC D9 SD_D[21] E22
DVDDC C20 H_AD[9] L16 NC E1 SD_D[22] J19
DVDDC C4 H_CPU_SPI_N K19 NC E2 SD_D[23] H21
DVDDC E18 H_CS_N L17 NC E4 SD_D[24] F22
DVDDC E20 H_D[0]/SPI_MISO T22 NC E6 SD_D[25] K21
DVDDC E5 H_D[1] U21 NC E7 SD_D[26] G22
DVDDC G18 H_D[10] V22 NC E8 SD_D[27] K20
DVDDC G5 H_D[11] P18 NC F3 SD_D[28] H22
DVDDC L2 H_D[12] W22 NC F4 SD_D[29] G16
DVDDC T18 H_D[13] Y21 NC F5 SD_D[3] A21
DVDDC T5 H_D[14] P19 NC F7 SD_D[30] K22
DVDDC V18 H_D[15] Y22 NC F8 SD_D[31] J22
DVDDC V20 H_D[16] AA21 NC G1 SD_D[4] C16
DVDDC V5 H_D[17] AA22 NC G2 SD_D[5] A22
DVDDC Y10 H_D[18] AB21 NC G4 SD_D[6] A18
DVDDC Y20 H_D[19] U20 NC G6 SD_D[7] B21
DVDDIO AA11 H_D[2] N18 NC G7 SD_D[8] E21
DVDDIO AA13 H_D[20] R19 NC G8 SD_D[9] H19
DVDDIO AA15 H_D[21] AB22 NC H4 SD_DQM[0] A20
DVDDIO AA2 H_D[22] P17 NC H5 SD_DQM[1] E19
DVDDIO AA9 H_D[23] V21 NC H6 SD_DQM[2] B20
DVDDIO B10 H_D[24] R17 NC H7 SD_DQM[3] D20
DVDDIO B14 H_D[25] V19 NC J4 SD_RAS_N D16
DVDDIO B16 H_D[26] T19 NC J5 SD_WE_N C17
DVDDIO B2 H_D[27] W21 NC J6 STMD K15
DVDDIO B8 H_D[28] U16 NC J7 TDM1_ACLK E10
DVDDIO C3 H_D[29] R18 NC J8 TDM1_RCLK D12
DVDDIO D1 H_D[3] R20 NC K4 TDM1_RSIG_RTS C11
DVDDIO F2 H_D[30] W20 NC K5 TDM1_RX D10
DVDDIO H2 H_D[31] U19 NC K6 TDM1_RX_SYNC D11
Rev: 040108 59 of 69
ABRIDGED DATA SHEET
_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
DVDDIO J10 H_D[4] T17 NC K7 TDM1_TCLK F12
DVDDIO J11 H_D[5] P16 NC K8 TDM1_TSIG_CTS E11
DVDDIO J12 H_D[6] U18 NC L22 TDM1_TX C12
DVDDIO J13 H_D[7] R16 NC L4 TDM1_TX_MF_CD F13
DVDDIO K14 H_D[8] U22 NC L5 TDM1_TX_SYNC E13
DVDDIO K9 H_D[9] T16 NC L6 TDM2_ACLK E9
DVDDIO L14 H_INT[0] J17 NC L7 TDM2_RCLK E12
DVDDIO L9 H_R_W_N/SPI_CP K17 NC L8 TDM2_RSIG_RTS C14
DVDDIO M14 H_READY_N K18 NC M4 TDM2_RX D13
H_WR_BE0_N/
DVDDIO M9 L19 NC M5 TDM2_RX_SYNC C13
SPI_CLK
H_WR_BE1_N/
DVDDIO N14 J16 NC M6 TDM2_TCLK G10
SPI_MOSI
H_WR_BE2_N/
DVDDIO N9 J18 NC M7 TDM2_TSIG_CTS F11
SPI_SEL_N
H_WR_BE3_N/
DVDDIO P10 L20 NC M8 TDM2_TX G11
SPI_CI
DVDDIO P11 HiZ_N T3 NC N4 TDM2_TX_MF_CD F10
DVDDIO P12 JTCLK L3 NC N5 TDM2_TX_SYNC E14
DVDDIO P13 JTDI M3 NC N6 TDM3_ACLK G14
DVDDIO R2 JTDO N3 NC N7 TDM3_RCLK C15
DVDDIO U2 JTMS K3 NC N8 TDM3_RSIG_RTS G13
DVDDIO V3 JTRST_N P3 NC P4 TDM3_RX D15
DVDDIO W1 MBIST_DONE M15 NC P5 TDM3_RX_SYNC D14
DVSS A10 MBIST_EN P15 NC P6 TDM3_TCLK G9
DVSS A14 MBIST_FAIL N15 NC P7 TDM3_TSIG_CTS G12
DVSS A16 MCLK N1 NC P8 TDM3_TX E15
DVSS A8 MDC AB17 NC P9 TDM3_TX_MF_CD F9
DVSS AA1 MDIO AA20 NC R3 TDM3_TX_SYNC F14
DVSS AB11 MII_COL AA17 NC R4 TDM4_ACLK H12
DVSS AB13 MII_CRS Y18 NC R5 TDM4_RCLK J14
DVSS AB15 MII_RX_DV Y17 NC R6 TDM4_RSIG_RTS F15
DVSS AB9 MII_RX_ERR V17 NC R7 TDM4_RX H9
DVSS B1 MII_RXD[0] AA16 NC T1 TDM4_RX_SYNC H14
DVSS B12 MII_RXD[1] W16 NC T2 TDM4_TCLK H11
DVSS D19 MII_RXD[2] AB16 NC T4 TDM4_TSIG_CTS G15
DVSS D2 MII_RXD[3] Y16 NC T6 TDM4_TX J9
DVSS D4 MII_TX_EN W17 NC T7 TDM4_TX_MF_CD H13
DVSS E3 MII_TX_ERR AB20 NC T8 TDM4_TX_SYNC H10
DVSS F1 MII_TXD[0] AB18 NC U3 TDM5_ACLK V11
DVSS F17 MII_TXD[1] W18 NC U4 TDM5_RCLK V9
DVSS F6 MII_TXD[2] AA19 NC U5 TDM5_RSIG_RTS T9
DVSS H1 MII_TXD[3] AB19 NC U7 TDM5_RX R11
DVSS H15 NC A1 NC U8 TDM5_RX_SYNC U14
DVSS H8 NC A11 NC V1 TDM5_TCLK T13
DVSS K10 NC A13 NC V2 TDM5_TSIG_CTS P14
DVSS K11 NC A15 NC V4 TDM5_TX R12
DVSS K12 NC A2 NC V6 TDM5_TX_MF_CD R10
DVSS K13 NC A3 NC V7 TDM5_TX_SYNC R14
Rev: 040108 60 of 69
ABRIDGED DATA SHEET
_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
DVSS L10 NC A4 NC V8 TDM6_ACLK W14
DVSS L11 NC A5 NC W3 TDM6_RCLK T12
DVSS L12 NC A6 NC W5 TDM6_RSIG_RTS R9
DVSS L13 NC A7 NC W6 TDM6_RX V12
DVSS M10 NC A9 NC W7 TDM6_RX_SYNC T15
DVSS M11 NC AA10 NC W8 TDM6_TCLK V15
DVSS M12 NC AA12 NC Y1 TDM6_TSIG_CTS V13
DVSS M13 NC AA14 NC Y2 TDM6_TX W15
DVSS N10 NC AA3 NC Y4 TDM6_TX_MF_CD U15
DVSS N11 NC AA4 NC Y5 TDM6_TX_SYNC T10
DVSS N12 NC AA5 NC Y6 TDM7_ACLK V14
DVSS N13 NC AA6 NC Y7 TDM7_RCLK U13
DVSS N2 NC AA7 NC Y8 TDM7_RSIG_RTS T14
DVSS R1 NC AA8 RST_SYS_N P2 TDM7_RX U12
DVSS R15 NC AB1 SCEN J15 TDM7_RX_SYNC R13
DVSS R8 NC AB10 SD_A[0] A17 TDM7_TCLK Y11
DVSS U1 NC AB12 SD_A[1] F18 TDM7_TSIG_CTS W9
DVSS U17 NC AB14 SD_A[10] B19 TDM7_TX W12
DVSS U6 NC AB2 SD_A[11] D17 TDM7_TX_MF_CD Y15
DVSS W19 NC AB3 SD_A[2] F16 TDM7_TX_SYNC U11
DVSS W2 NC AB4 SD_A[3] B18 TDM8_ACLK Y13
DVSS W4 NC AB5 SD_A[4] E17 TDM8_RCLK U9
DVSS Y12 NC AB6 SD_A[5] A19 TDM8_RSIG_RTS Y9
DVSS Y3 NC AB7 SD_A[6] H17 TDM8_RX V10
H_AD[1] L18 NC AB8 SD_A[7] F19 TDM8_RX_SYNC T11
H_AD[10] N22 NC B13 SD_A[8] F20 TDM8_TCLK Y14
H_AD[11] L15 NC B15 SD_A[9] D18 TDM8_TSIG_CTS W11
H_AD[12] P21 NC B3 SD_BA[0] G17 TDM8_TX W10
H_AD[13] N16 NC B4 SD_BA[1] C19 TDM8_TX_MF_CD W13
H_AD[14] N20 NC B5 SD_CAS_N E16 TDM8_TX_SYNC U10
H_AD[15] P22 NC B6 SD_CLK H16 TEST_CLK J3
H_AD[16] N19 NC B7 SD_CS_N B17 TST_CLD G3
H_AD[17] R21 NC B9 SD_D[0] C18 NC H3
Rev: 040108 61 of 69
ABRIDGED DATA SHEET
_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
Figure 14-1. DS34S108 Pin Assignment (TEBGA Package)
1 2 3 4 5 6 7 8 9 10 11
NC NC NC NC NC NC NC DVSS NC DVSS NC
A
DVSS DVDDIO NC NC NC NC NC DVDDIO NC DVDDIO DVDDC
B
NC NC DVDDIO DVDDC NC NC NC NC NC NC TDM1_RSIG_RTS
C
DVDDIO DVSS NC DVSS NC NC NC NC NC TDM1_RX TDM1_RX_SYNC
D
NC NC DVSS NC DVDDC NC NC NC TDM2_ACLK TDM1_ACLK TDM1_TSIG_CTS
E
DVSS DVDDIO NC NC NC DVSS NC NC TDM3_TX_MF_CD TDM2_TX_MF_CD TDM2_TSIG_CTS
F
NC NC TST_CLD NC DVDDC NC NC NC TDM3_TCLK TDM2_TCLK TDM2_TX
G
DVSS DVDDIO NC NC NC NC NC DVSS TDM4_RX TDM4_TX_SYNC TDM4_TCLK
H
CLK_SYS/SCCLK CLK_SYS_S TEST_CLK NC NC NC NC NC TDM4_TX DVDDIO DVDDIO
J
ACVSS2 ACVDD2 JTMS NC NC NC NC NC DVDDIO DVSS DVSS
K
CLK_HIGH DVDDC JTCLK NC NC NC NC NC DVDDIO DVSS DVSS
L
ACVSS1 ACVDD1 JTDI NC NC NC NC NC DVDDIO DVSS DVSS
M
MCLK DVSS JTDO NC NC NC NC NC DVDDIO DVSS DVSS
N
CLK_CMN RST_SYS_N JTRST_N NC NC NC NC NC NC DVDDIO DVDDIO
P
DVSS DVDDIO NC NC NC NC NC DVSS TDM6_RSIG_RTS TDM5_TX_MF_CD TDM5_RX
R
NC NC HiZ_N NC DVDDC NC NC NC TDM5_RSIG_RTS TDM6_TX_SYNC TDM8_RX_SYNC
T
DVSS DVDDIO NC NC NC DVSS NC NC TDM8_RCLK TDM8_TX_SYNC TDM7_TX_SYNC
U
NC NC DVDDIO NC DVDDC NC NC NC TDM5_RCLK TDM8_RX TDM5_ACLK
V
DVDDIO DVSS NC DVSS NC NC NC NC TDM7_TSIG_CTS TDM8_TX TDM8_TSIG_CTS
W
NC NC DVSS NC NC NC NC NC TDM8_RSIG_RTS DVDDC TDM7_TCLK
Y
DVSS DVDDIO NC NC NC NC NC NC DVDDIO NC DVDDIO
AA
AB NC NC NC NC NC NC NC NC DVSS NC DVSS
1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19 20 21 22
DVDDC NC DVSS NC DVSS SD_A[ 0] SD_D[6] SD_A[5] SD_DQM [0] SD_D[ 3] SD_D[ 5]
A
DVSS NC DVDDIO NC DVDDIO SD_CS_N SD_A[3] SD_A[10] SD_DQM [2] SD_D[7] SD_D[ 10]
B
TDM 1_TX TDM 2_RX_SYNC TDM 2_RSIG_RTS TDM 3_RCLK SD_D[ 4] SD_WE_N SD_D[0] SD_BA[ 1] DVDDC SD_D[ 12] SD_D[ 14]
C
TDM 1_RCLK TDM 2_RX TDM 3_RX_SYNC TDM 3_RX SD_RAS_N SD_A[ 11] SD_A[9] DVSS SD_DQM [3] SD_D[ 15] SD_D[ 17]
D
TDM 2_RCLK TDM 1_TX_SYNC TDM 2_TX_SYNC TDM 3_TX SD_CAS_N SD_A[ 4] DVDDC SD_DQM [1] DVDDC SD_D[ 8] SD_D[ 21]
E
TDM 1_TCLK TDM 1_TX_M F_CD TDM 3_TX_SYNC TDM 4_RSIG_RTS SD_A[ 2] DVSS SD_A[ 1] SD_A[7] SD_A[8] SD_D[1] SD_D[24]
F
TDM 3_TSIG_CTS TDM 3_RSIG_RTS TDM 3_ACLK TDM 4_TSIG_CTS SD_D[29] SD_BA[0] DVDDC SD_D[2] SD_D[ 16] SD_D[ 19] SD_D[26]
G
TDM 4_ACLK TDM 4_TX_M F_CD TDM 4_RX_SYNC DVSS SD_CLK SD_A[ 6] SD_D[13] SD_D[9] SD_D[11] SD_D[ 23] SD_D[28]
H
DVDDIO DVDDIO TDM 4_RCLK SCEN H_WR_BE1_N/ SPI_M OS H_INT[ 0] _WR_BE2_N/SPI_SEL_ SD_D[ 22] SD_D[ 18] SD_D[ 20] SD_D[ 31]
J
DVSS DVSS DVDDIO STM D H_AD[ 3] H_R_W_N/SPI_CP H_READY_N H_CPU_SPI_N SD_D[ 27] SD_D[ 25] SD_D[30]
K
DVSS DVSS DVDDIO H_AD[ 11] H_AD[ 9] H_CS_N H_AD[ 1] H_WR_BE0_N/SPI_CLKH_WR_BE3_N/ SPI_CI DAT_32_16_N NC
L
DVSS DVSS DVDDIO M BIST_DONE H_AD[ 7] H_AD[20] H_AD[6] H_AD[18] H_AD[8] H_AD[ 2] H_AD[ 4]
M
DVSS DVSS DVDDIO M BIST_FAIL H_AD[ 13] H_AD[23] H_D[ 2] H_AD[16] H_AD[ 14] H_AD[ 19] H_AD[ 10]
N
DVDDIO DVDDIO TDM 5_TSIG_CTS M BIST_EN H_D[5] H_D[ 22] H_D[ 11] H_D[ 14] H_AD[ 21] H_AD[ 12] H_AD[ 15]
P
TDM 5_TX TDM 7_RX_SYNC TDM 5_TX_SYNC DVSS H_D[7] H_D[ 24] H_D[ 29] H_D[20] H_D[ 3] H_AD[ 17] H_AD[22]
R
TDM 6_RCLK TDM 5_TCLK TDM 7_RSIG_RTS TDM 6_RX_SYNC H_D[9] H_D[4] DVDDC H_D[26] H_AD[5] H_AD[ 24] H_D[0]/ SPI_M ISO
T
TDM 7_RX TDM 7_RCLK TDM 5_RX_SYNC TDM 6_TX_M F_CD H_D[ 28] DVSS H_D[ 6] H_D[ 31] H_D[19] H_D[ 1] H_D[8]
U
TDM 6_RX TDM 6_TSIG_CTS TDM 7_ACLK TDM 6_TCLK CLK_M II_RX M II_RX_ERR DVDDC H_D[25] DVDDC H_D[23] H_D[10]
V
TDM 7_TX TDM 8_TX_M F_CD TDM 6_ACLK TDM 6_TX M II_RXD[1] M II_TX_EN M II_TXD[ 1] DVSS H_D[30] H_D[27] H_D[12]
W
DVSS TDM 8_ACLK TDM 8_TCLK TDM 7_TX_M F_CD M II_RXD[ 3] M II_RX_DV M II_CRS CLK_SSM II_TX DVDDC H_D[13] H_D[15]
Y
NC DVDDIO NC DVDDIO M II_RXD[ 0] M II_COL CLK_M II_TX M II_TXD[2] M DIO H_D[16] H_D[17]
AA
NC DVSS NC DVSS M II_RXD[ 2] M DC M II_TXD[0] M II_TXD[3] M II_TX_ERR H_D[18] H_D[21] AB
12 13 14 15 16 17 18 19 20 21 22
Rev: 040108 62 of 69
ABRIDGED DATA SHEET
_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
Figure 14-2. DS34S104 Pin Assignment (TECSBGA Package)

1 2 3 4 5 6 7 8
SD_RAS_N SD_BA[1] SD_A[3] SD_A[10] SD_DQM[3] SD_D[12] SD_D[18] SD_D[23]
A
SD_WE_N SD_CLK SD_A[5] SD_A[8] SD_D[1] SD_D[10] SD_D[5] SD_D[14]
B
SD_CAS_N SD_CS_N SD_A[1] SD_A[7] SD_DQM[0] SD_D[3] SD_D[17] SD_D[31]
C
SD_BA[0] SD_A[0] SD_A[9] SD_DQM[1] SD_D[6] SD_D[7] SD_D[15] SD_D[19]
D
SD_A[2] SD_A[4] SD_A[6] SD_D[0] SD_D[9] SD_DQM[2] SD_D[8] SD_D[21]
E
SD_D[2] SD_A[11] SD_D[11] SD_D[13] SD_D[16] DVDDC DVDDC DVDDC
F
SD_D[4] SD_D[20] SD_D[22] SD_D[25] SD_D[27] DVSS DVSS DVSS
G
TDM4_TX TDM4_RX TDM4_TCLK STMD DVSS DVSS DVSS DVSS
H
TDM4_RCLK TDM4_ACLK TDM4_TX_SYNC SCAN_EN DVDDIO DVSS DVSS DVSS
J
TDM4_TX_MF_CD TDM4_RX_SYNC TDM4_TSIG_CTS TDM4_RSIG_RTS DVDDIO DVSS DVSS DVSS
K
TDM3_TX TDM3_RX TDM3_TCLK H_CPU_SPI_N DVDDIO DVSS DVSS DVSS
L
TDM3_RCLK TDM3_ACLK TDM3_TX_SYNC DAT_32_16_N DVDDIO DVDDC DVDDC DVDDC
M
TDM3_TX_MF_CD TDM3_RX_SYNC TDM3_TSIG_CTS TDM3_RSIG_RTS MBIST_DONE MBIST_EN DVDDIO DVDDIO
N
TDM2_TX TDM2_RX TDM2_TCLK TDM2_RCLK TDM1_RX_SYNC TDM1_TSIG_CTS TDM1_RSIG_RTS ACVSS1
P
TDM2_ACLK TDM2_TX_SYNC TDM2_TX_MF_CD MBIST_FAIL TDM1_ACLK TDM1_TX_SYNC TDM1_TX_MF_CD ACVDD1
R
T TDM2_RX_SYNC TDM2_TSIG_CTS TDM2_RSIG_RTS TDM1_TX TDM1_RX TDM1_TCLK TDM1_RCLK ACVDD2
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16
SD_D[28] H_AD[21] H_AD[24] H_AD[12] H_AD[8] MII_TXD[1] MII_RX_ERR CLK_MII_RX
A
SD_D[24] H_AD[19] H_AD[22] H_D[21] H_AD[17] MII_TXD[2] MII_COL MII_RXD[0]
B
SD_D[30] H_AD[10] H_WR_BE3_N/SPI_CI H_AD[14] H_WR_BE0_N/SPI_CLK MII_TXD[3] MII_CRS MII_RXD[1]
C
SD_D[29] H_AD[4] H_AD[6] H_AD[15] H_AD[2] MII_TX_EN CLK_MII_TX MII_RXD[2]
D
SD_D[26] H_WR_BE2_N/SPI_SEL_N H_CS_N H_AD[11] H_AD[5] MII_TX_ERR CLK_SSMII_TX MII_RXD[3]
E
DVDDC DVDDC DVDDC H_D[23] H_D[24] H_D[27] MII_TXD[0] MII_RX_DV
F
DVSS DVSS DVSS DVDDIO H_D[25] H_D[28] MDIO MDC
G
DVSS DVSS DVSS DVDDIO H_D[26] H_D[29] H_D[31] H_D[30]
H
J
DVSS DVSS DVSS DVDDIO H_D[0]/SPI_MISO H_D[12] H_D[4] H_D[19]
K
L
DVDDC DVDDC DVDDC H_D[1] H_D[10] CLK_CMN H_D[13] H_D[15]
M
DVDDIO DVDDIO HiZ_N H_R_W_N/SPI_CP H_AD[7] H_AD[23] H_D[7] H_D[20]
N
CLK_HIGH JTDI JTDO H_WR_BE1_N/SPI_MOSI H_AD[3] H_AD[20] H_D[5] H_D[11]
P
CLK_SYS_S JTCLK RST_SYS_N H_READY_N H_AD[1] H_AD[18] H_D[2] H_D[9]
R
ACVSS2 JTMS JTRST_N CLK_SYS/SCCLK H_INT[0] H_AD[9] H_AD[13] H_AD[16] T
9 10 11 12 13 14 15 16
Rev: 040108 63 of 69
ABRIDGED DATA SHEET
_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
1 2 3 4 5 6 7 8
SD_RAS_N SD_BA[1] SD_A[3] SD_A[10] SD_DQM[3] SD_D[12] SD_D[18] SD_D[23]
A
SD_WE_N SD_CLK SD_A[5] SD_A[8] SD_D[1] SD_D[10] SD_D[5] SD_D[14]
B
SD_CAS_N SD_CS_N SD_A[1] SD_A[7] SD_DQM[0] SD_D[3] SD_D[17] SD_D[31]
C
SD_BA[0] SD_A[0] SD_A[9] SD_DQM[1] SD_D[6] SD_D[7] SD_D[15] SD_D[19]
D
SD_A[2] SD_A[4] SD_A[6] SD_D[0] SD_D[9] SD_DQM[2] SD_D[8] SD_D[21]
E
SD_D[2] SD_A[11] SD_D[11] SD_D[13] SD_D[16] DVDDC DVDDC DVDDC
F
SD_D[4] SD_D[20] SD_D[22] SD_D[25] SD_D[27] DVSS DVSS DVSS
G
NC NC NC STMD DVSS DVSS DVSS DVSS
H
NC NC NC SCAN_EN DVDDIO DVSS DVSS DVSS
J
NC NC NC NC DVDDIO DVSS DVSS DVSS
K
NC NC NC H_CPU_SPI_N DVDDIO DVSS DVSS DVSS
L
NC NC NC DAT_32_16_N DVDDIO DVDDC DVDDC DVDDC
M
NC NC NC NC MBIST_DONE MBIST_EN DVDDIO DVDDIO
N
TDM2_TX TDM2_RX TDM2_TCLK TDM2_RCLK TDM1_RX_SYNC TDM1_TSIG_CTS TDM1_RSIG_RTS ACVSS1
P
TDM2_ACLK TDM2_TX_SYNC TDM2_TX_MF_CD MBIST_FAIL TDM1_ACLK TDM1_TX_SYNC TDM1_TX_MF_CD ACVDD1
R
T TDM2_RX_SYNC TDM2_TSIG_CTS TDM2_RSIG_RTS TDM1_TX TDM1_RX TDM1_TCLK TDM1_RCLK ACVDD2
9 10 11 12 13 14 15 16
SD_D[28] H_AD[21] H_AD[24] H_AD[12] H_AD[8] MII_TXD[1] MII_RX_ERR CLK_MII_RX
A
SD_D[24] H_AD[19] H_AD[22] H_D[21] H_AD[17] MII_TXD[2] MII_COL MII_RXD[0]
B
SD_D[30] H_AD[10] H_WR_BE3_N/SPI_CI H_AD[14] H_WR_BE0_N/SPI_CLK MII_TXD[3] MII_CRS MII_RXD[1]
C
SD_D[29] H_AD[4] H_AD[6] H_AD[15] H_AD[2] MII_TX_EN CLK_MII_TX MII_RXD[2]
D
SD_D[26] H_WR_BE2_N/SPI_SEL_N H_CS_N H_AD[11] H_AD[5] MII_TX_ERR CLK_SSMII_TX MII_RXD[3]
E
DVDDC DVDDC DVDDC H_D[23] H_D[24] H_D[27] MII_TXD[0] MII_RX_DV
F
DVSS DVSS DVSS DVDDIO H_D[25] H_D[28] MDIO MDC
G
H
J
DVSS DVSS DVSS DVDDIO H_D[0]/SPI_MISO H_D[12] H_D[4] H_D[19]
K
L
DVDDC DVDDC DVDDC H_D[1] H_D[10] CLK_CMN H_D[13] H_D[15]
M
DVDDIO DVDDIO HiZ_N H_R_W_N/SPI_CP H_AD[7] H_AD[23] H_D[7] H_D[20]
N
CLK_HIGH JTDI JTDO H_WR_BE1_N/SPI_MOSI H_AD[3] H_AD[20] H_D[5] H_D[11]
P
CLK_SYS_S JTCLK RST_SYS_N H_READY_N H_AD[1] H_AD[18] H_D[2] H_D[9]
R
9 10 11 12 13 14 15 16
Rev: 040108 64 of 69
ABRIDGED DATA SHEET
_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
1 2 3 4 5 6 7 8
A SD_RAS_N SD_BA[1] SD_A[3] SD_A[10] SD_DQM[3] SD_D[12] SD_D[18] SD_D[23]
B SD_WE_N SD_CLK SD_A[5] SD_A[8] SD_D[1] SD_D[10] SD_D[5] SD_D[14]
C SD_CAS_N SD_CS_N SD_A[1] SD_A[7] SD_DQM[0] SD_D[3] SD_D[17] SD_D[31]
D SD_BA[0] SD_A[0] SD_A[9] SD_DQM[1] SD_D[6] SD_D[7] SD_D[15] SD_D[19]
E SD_A[2] SD_A[4] SD_A[6] SD_D[0] SD_D[9] SD_DQM[2] SD_D[8] SD_D[21]
F SD_D[2] SD_A[11] SD_D[11] SD_D[13] SD_D[16] DVDDC DVDDC DVDDC
G SD_D[4] SD_D[20] SD_D[22] SD_D[25] SD_D[27] DVSS DVSS DVSS
H NC NC NC STMD DVSS DVSS DVSS DVSS
J NC NC NC SCAN_EN DVDDIO DVSS DVSS DVSS
K NC NC NC NC DVDDIO DVSS DVSS DVSS
L NC NC NC H_CPU_SPI_N DVDDIO DVSS DVSS DVSS
M NC NC NC DAT_32_16_N DVDDIO DVDDC DVDDC DVDDC
N NC NC NC NC MBIST_DONE MBIST_EN DVDDIO DVDDIO
P NC NC NC NC TDM1_RX_SYNC TDM1_TSIG_CTS TDM1_RSIG_RTS ACVSS1
R NC NC NC MBIST_FAIL TDM1_ACLK TDM1_TX_SYNC TDM1_TX_MF_CD ACVDD1
T NC NC NC TDM1_TX TDM1_RX TDM1_TCLK TDM1_RCLK ACVDD2
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16
SD_D[28] H_AD[21] H_AD[24] H_AD[12] H_AD[8] MII_TXD[1] MII_RX_ERR CLK_MII_RX A
SD_D[24] H_AD[19] H_AD[22] H_D[21] H_AD[17] MII_TXD[2] MII_COL MII_RXD[0] B
SD_D[30] H_AD[10] H_WR_BE3_N/SPI_C H_AD[14] H_WR_BE0_N/SPI_CL MII_TXD[3] MII_CRS MII_RXD[1] C
SD_D[29] H_AD[4] H_AD[6] H_AD[15] H_AD[2] MII_TX_EN CLK_MII_TX MII_RXD[2] D
SD_D[26] _WR_BE2_N/SPI_SEL H_CS_N H_AD[11] H_AD[5] MII_TX_ERR CLK_SSMII_TX MII_RXD[3] E
DVDDC DVDDC DVDDC H_D[23] H_D[24] H_D[27] MII_TXD[0] MII_RX_DV F
DVSS DVSS DVSS DVDDIO H_D[25] H_D[28] MDIO MDC G
DVSS DVSS DVSS DVDDIO H_D[26] H_D[29] H_D[31] H_D[30] H
DVSS DVSS DVSS DVDDIO H_D[6] H_D[14] H_D[18] H_D[22] J
DVSS DVSS DVSS DVDDIO H_D[0]/SPI_MISO H_D[12] H_D[4] H_D[19] K
DVSS DVSS DVSS DVDDIO H_D[3] H_D[16] H_D[8] H_D[17] L
DVDDC DVDDC DVDDC H_D[1] H_D[10] CLK_CMN H_D[13] H_D[15] M
DVDDIO DVDDIO HiZ_N H_R_W_N/SPI_CP H_AD[7] H_AD[23] H_D[7] H_D[20] N
CLK_HIGH JTDI JTDO _WR_BE1_N/SPI_MO H_AD[3] H_AD[20] H_D[5] H_D[11] P
CLK_SYS_S JTCLK RST_SYS_N H_READY_N H_AD[1] H_AD[18] H_D[2] H_D[9] R
9 10 11 12 13 14 15 16
Rev: 040108 65 of 69
ABRIDGED DATA SHEET
_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
15 Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a
link to the latest package outline information.)
15.1 484-Ball TEBGA (56-G6038-001)
Rev: 040108 66 of 69
ABRIDGED DATA SHEET
_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
15.2 256-Ball TECSBGA (56-G6028-001)
Rev: 040108 67 of 69
ABRIDGED DATA SHEET
_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
16 Thermal Information
VALUE
PARAMETER
TEBGA TECSBGA
Target Ambient Temperature Range -40C to +85C -40C to +85C
Die Junction Temperature Range -40C to +125C -40C to +125C
Theta-JC (Junction to Top of Case) 4.5C/W 3.7C/W
Theta-JB (Junction to Bottom Pins) 7.1C/W 13.1C/W
Still Air 15.0C/W 26.2C/W
Theta-JA Moving Air: 1m/s 12.7C/W
(Note 1) Moving Air: 2m/s 11.5C/W
Moving Air: 2.5m/s 11.1C/W
Note 1: Theta-JA values are estimates using JEDEC-standard PCB and enclosure dimensions.
Rev: 040108 68 of 69
ABRIDGED DATA SHEET
_____________________________________________ DS34S101/DS34S102/DS34S104/DS34S108
17 Document Revision History

REVISION PAGES
DESCRIPTION
DATE CHANGED
091407 Preliminary release.
Initial data sheet release. See below for changes made to the data sheet since the 091407
preliminary release version.
Removed future status from DS34S104 in the Ordering Information table. 1
Updated status of IETF PWE3 standards for CESoPSN and TDMoIP. 1, 6, 10, 15
In Table 9-1 and Table 9-2, corrected the pin type (from Ipd to I) and changed pin
description to tell users to connect inputs SCEN and STMD to DVSS. These inputs 25, 33
do not have internal pulldowns.
In Section 7.1: Global Features, clarified product and package type relationships for
040108 14
the TEBGA and TECSBGA packages.
In Table 9-2, clarified the pin description for input CLK_HIGH, added information for
30
the unused input MCLK.
In Table 9-2, changed the output type for H_READY_N to three-stateable (from Opu
32
to Oz). This output does not have an internal pullup.
In Table 9-2, simplified the pin descriptions for signals only used in factory
33
(TEST_CLK, SCEN, STMD).
In Section 16: Thermal Information, updated the thermal Information for the TEBGA
68
package. Added Theta-JA values for TEBGA deployments with forced air flow.
Rev: 040108 69 of 69
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses
are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

DS34S101//DS34S102/DS34S104/DS34S108: Single/Dual/Quad/Octal TDM-Over-Packet Transport Devices

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DS34S101//DS34S102/DS34S104/DS34S108: Single/Dual/Quad/Octal TDM-Over-Packet Transport Devices

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ABRIDGED DATA SHEET

2 Acronyms and Glossary

Table 3-1. TDM-Over-Packet Related Specifications

Figure 5-1. Metropolitan Legacy Service Over Packet-Switched Network

Figure 5-2. Cellular 2/3G Backhaul Over Packet-Switched Networks

5.1 Other Possible Applications

5.1.1 Point-to-Multipoint TDM Connectivity over IP/Ethernet

5.1.2 HDLC Transport over IP/MPLS

5.1.3 Using a Packet Backplane for Multiservice Concentrators

Figure 6-1. DS34S108 Functional Block Diagram

Byte Enable Mask

7.1 Global Features

7.2 Clock Synthesizer

7.3 TDM-over-Packet Engine

SAToP (Structure-Agnostic TDM over Packet)

7.3.1 TDM-over-Packet User Interfaces

For the E3/T3/STS-1 option, the AAL1 or SAToP method is used.

UnframedE1/T1 pass-through mode (AAL1, SAToP, or HDLC payload type method).

7.3.2 Network Port

Transmit and receive queues

7.3.4 Clock Recovery

TDM-over-Packet supports the following clock recovery modes:

Adaptive clock recovery

7.3.5 Delay Variation Compensation

7.3.6 CAS Support

7.4 Test and Diagnostics

7.5 Control Port

32- or 16-bit parallel control port

8 Functional Description and Device Registers

9.1 Short Pin Descriptions

Table 9-1. DS34S108 Short Pin Descriptions

9.2 Detailed Pin Descriptions

10.1 JTAG Description

Figure 10-1. JTAG Block Diagram

TEST ACCESS PORT SELECT

10k 10k 10k

JTDI JTMS JTCLK JTRST_N JTDO

10.2 JTAG TAP Controller State Machine Description

Figure 10-2. JTAG TAP Controller State Machine

Table 10-1. JTAG Instruction Codes

Table 10-2. JTAG ID Code

10.4 JTAG Test Registers

10.4.1 Bypass Register

10.4.2 Identification Register

10.4.3 Boundary Scan Register

Table 11-1. Recommended DC Operating Conditions

13.1 Connecting a Serial Interface Transceiver

Internal (from the local oscillator)

The TDM1_TSIG_CTS and TDM1_TX_MF_CD outputs are set by software.

The TDM1_RSIG_RTS value can be read by software.

A maskable interrupt can be asserted when RTS value changes.

Figure 13-1. Connecting the First Port to a Serial Transceiver

SERIAL INTERFACE TCLK TDM 1_ TCLK

13.2 Connecting an External E1/T1 Framer

The clock source of TDM1_TCLK can be either:

Internal (from the local oscillator)

LIU _ RCLK TDM 1_ ACLK

EXTERNAL CLOCK INTERNAL CLOCK

TCLK TDM 1_ TCLK

LIU _ RCLK TDM 1_ ACLK

EXTERNAL CLOCK INTERNAL CLOCK

Framer TX_SYNC is asserted for one clock cycle every N 125s.

EXTERNAL CLOCK INTERNAL CLOCK