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An Overview of Microprocessor
The first question comes in a mind "What is a
microprocessor?. Let us start with a more familiar term computer. A
digital computer is an electronic machine capable of quickly
performing a wide variety of tasks. They can be used to compile,
correlate, sort, merge and store data as well as perform calculations.
A digital computer is different from a general purpose calculator
in that it is capable of operating according to the instructions that are
stored within the computer whereas a calculator must be given
instructions on a step by step basis. By the definition a programmable
calculator is a computer.
Historically, digital computers have been categorized according
to the size using the words large, medium, minicomputer and
microcomputer. In the early years of development, the emphasis was
on large and more powerful computers. Large and medium sized
computers were designed to store complex scientific and engineering
problems. These computers were accessible and affordable only to
large corporations, big universities and government agencies. In the
1960s computers were accessible & affordable only to large
corporations, big universities & government agencies, In late 1960s,
minicomputers were available for use in a office, small collage,
medium size business organization, small factory etc. As the
technology has advanced from SSI to VLSI & SLSI (very large scale
integration & super large scale integration) the face of the computer
has changed. It has now become possible to build the control
processing unit (CPU) with its related timing functions on a single
chip known as microprocessor. A microprocessor combined with
memory and input/output devices forms a microcomputer. As for as
the computing power is concerned the 32- bit microcomputers are as
powerful as traditional mainframe computers.
The microcomputer is making an impact on every activity of
mankind. It is being used in almost all control applications. For
example analytical and scientific instruments, data communication,
character recognition, musical instruments, household items, defence
equipments, medical equipments etc.
Computers communicate and operate in binary numbers 0 and
1 also known as bits. It is the abbreviation for the term binary digit.
The bit size of a microprocessor refers to the number of bit which can
be processed simultaneously by the arithmetic circuit of the
microprocessor. A number of bits taken as a group are this manner is
called word. For example, the first commercial microprocessor the
Intel 4004 which was introduced in 1971 is a 4-bit machine and is
said to process a 4-bit word. A 4-bit word is commonly known as
nibble and an 8-bit word is commonly known as byte. Intel 8085 is an
8-bit microprocessor. It should be noted that a processor can perform
calculations involving more than its bit size but takes more time to
complete the operation. The short word length requires few circuitry
and interconnection in the CPU.
Microcomputers:
In a very general a microcomputer is best regard as a system
incorporating a CPU and assisted hardware whose purpose is to
manipulate data in same fashion. This is exactly what any digital
circuit designed using SSIs and MSIs will also do therefore,
microcomputer should be regard as a general purpose logic device.
In contrast to standard SSIs and MSIs where the manufacturer
decides what the device will do, with microcomputer it is the user who
decides what the device should do by asking it to execute a proper
set of instructions. A microcomputer, from this point of view is merely
an assembly of devices whose sole task is to ensure that the
instruction desire are indeed carried out properly and to allow the
microprocessor to communicate with the real world, i.e. the user
environment. The power of the microcomputer lies in the fact that if
the application change, the same system can still used by
appropriately modifying the instruction to be executed and if
necessary some changes in the hardware. In contrast, a digit circuit
designed using SSIs and MSIs for same application will need to be
completely redesigned if the application changes significantly.
The objective of a microcomputer is to manipulate data in a
certain fashion specified by the system designer. A typical
microcomputer achieves their objective by getting its CPO (p) to
execute a number of instructions in the proper sequence. This
sequence of instruction comprises the program that is executed by
the micro computer.
A microcomputer which does nothing other than manipulate
data present within itself, Will not be of much use to anybody. In order
to do something meaningful, data being manipulated should depend
on same fashion on input provided to the microprocessor would be
completely senseless unless the results of these manipulations
affects things outside the c itself. A c should on its input, the which
in same way, depends on its input, the way input and output are
related is decided by the program that gets executed.
Therefore, a c is an assembly of devices including a CPU,
which manipulate data depending on one or more inputs and
according to a program, in order to generate one or more output.
Microcontrollers
A P does not have enough memory for program and data
storage, neither does it has any input and output devices. Thus when
a P is used to design a system, several other chips are also used to
make up a complete system. For many applications, these extra
chips imply additional cost and increased size of the product. For
example, when used inside a toy, a designer would like to minimize
the size and cost of the electronic equipment inside the toy.
Therefore, in such applications a microcontroller is used more often
than a microprocessor.
A microcontroller is a chip consisting of a microprocessor,
memory and an input/output device. There are 4 bit as well as 32 bit
microcontrollers.
Lass 4-bit 8 8 16 32
Lecture-3
MEMORY:
It is a storage device. It stores program data and the results.
There are two kind of memories; semiconductor memories &
magnetic memories. Semiconductor memories are faster, smaller,
and lighter and consume less power. Semiconductor memories are
used as the main memory of a computer. Magnetic memories are
slow but they are cheaper than semiconductor memories. Magnetic
memories are used as the secondary memories of a computer for
bulk storage of data and informations. With the development in
technology, semiconductor memories are used everywhere.
Let us see how semiconductor memories are developed.
Development of Memory:
The smallest unit of information a digital system can store in a
binary digit which has a logic value of 0 or 1. A bit of data is stored in
electronics devices called a flip flop or a 1-bit register. A flip flop is
a general memory and has two stable states in which it can remain
indefinitely as long as the operating power is not interrupted. The
output can be changed only if the input signals allow for it. A very
simple type of flip flop is D- type flip- flop as shown in fig.
D Q
PR
CLK
CLR
It has a single data input D and two input, Q and . Output Q
represents the state of flip- flop; represent the complement of the
flip- flops state. The logic value at a flip- flops D input when a clock
signal, CLK occurs is stored in the flip- flop. If the store value is equal
to 1 (Q = 1) the flip flop is set. If the stored value is equal to 0 (Q =
0) the flip flop is clear.
The logical operation of a D type flip flop is expressed by the
characteristic equation Qn+1 = Dn. This equation indicates that the
output of a D- type flip flop after the accordance of a clock pulse,
Qn+1 is equal to the logic value of the D input before the accordance
of the clock pulse Dn. But D type flip-flop differ with regard to the
praise time at which the clock pulse causes the input data to be
accepted, the output to change in accordance with the input, and the
output to be held or latched.
Two clock pulse or strokes are shown in fig positive clock pulse.
This signal is logic 0 in its quiescent state, makes a transition to logic
1 remains at logic 1 momentarily, and then returns to logic 0. The
leading edge of the pulse is a 0 to 1 or positive transition and the
trailing edge is a 1 to 0 or negative transition. The clock pulse shown
is a negative clock pulse, its quiescent value is logic 1 and it makes a
momentary negative transition to logic 0 followed by a positive
transition back to logic 1. A positive transition is also referred to as a
using edge, and a negative transition is also referred as the following
edge.
Leadingedge
Trailingedge
1 Trailingedge
1
0 0
Leadingedge
(a)
(b)
D Q
CLK
>CLK
(+veedge)
D
D Q Q
>CLK ( veedge)
7475
D Q CLK
>CLK D
D Q
>CLK Q
(+ve)
Q
( ve)
Function table:
Lecture-5
Development of Memory Chip:
Let us consider a memory of 16 words, each of 8 bits is to be
stored. 16 words can be stored in 16 memory locations, each having
a unique 4 bit memory address (0000 to 1111) and each location
being capable of containing 8 bits of data.
To set up this memory system using ICs, 16 bit flip-flop
registers are required. To identify the correct address a 4 line-16 line
decoder can be used to decode the 4 bit location address to select
the appropriate data register (1 to 16) for input/output. Figure shows
the circuit used to implement the memory system.
The 74LS374s are octal D flip flops with three state of outputs.
To store data in them, 8 bits of data are put on the D0 to D7 data
inputs via the data bus. Then the low to high edge on the clock input
will cause the data a D0 to D7 to be latched into each flip-flop. the
stored value in the D flip-flopis observed at the outputs Q0 to Q7 by
making the output enable pin low
To select the appropriate memory location, a 4 bit address is
input to 74154 (4 Line to 16 Line decoder), which outputs a low pulse
on one of the output lines when the is pulsed low. The timing
of setting up the address bus, data bus and pulsing the line
is critical. The following figure shows standard timing diagram bus
driven devices. Rather than showing all four address lines and all
data lines, they are grouped and X is used to show where any or all
of the lines are allowed to change digital levels.
The address and the data lines must be set up some time (ts)
before the low to high edge of . In other words the address
and the data lines must be valid some period of time (ts) before the
low to high edge of in order for the74374 to interpret them
correctly.
When the line is pulsed, the decoder outputs a low
pulse on one of its 16 outputs which clocks the appropriate memory
location to receive data from the data bus. After the propagation
delay, (tp) the data output at Q0 to Q7 will be the new data just
entered into the D flip-flop. Then the tp will include the propagation
delay of decoder and of the D flip-flop.
In the figure all the three state outputs are continuously enabled
so that their Q outputs always active. To reduce the number of lines
the 8 outputs Q0 to Q7 of all 16 memory locations back to the data
bus. The enables of the 16 memory locations have to be
individually selected at the appropriate time to avoid a conflict on the
data bus, called bus contention. Bus contention occurs when two or
more devices are trying to send their digital levels to the shared data
bus at the same time. To individually select each group of Q outputs,
the grounds on the enables would be removed and instead be
connected to the output of another 74154 1 of 16 decoder.
Commercially available memory chips combine all the decoding
and the storage elements in a single package.
MEMORY:
If a memory stores N- words of information each word being of
m bits, we say it is a Nxm memory. e.g. 8x4 memory means there are
8 words 4 each word containing 4- bit of information (called nibble). 8
words are stored at 8-memory locations and these memory locations
are clearly identified by addresses. Addresses are formulated by bit
combinations available in wires known as address lines. To identify 8
memory locations we require 3 address lines designed A2A1A0. The
memory locations identify and the corresponding content stored is
shown in table.
A2 A1 A0 Decimal Memory Contents of the
Equivalent Location memory location
0 0 0 0 0 M(0)
0 0 1 1 1 M(1)
0 1 0 2 2 M(2)
0 1 1 3 2 M(3)
1 0 0 4 3 M(4)
1 0 1 5 5 M(5)
1 1 0 6 6 M(6)
1 1 1 7 7 M(7)
Classification of Memory:
In general, semiconductor memories can be clarified in two
main groups random access memories (RAM) and sequential access
memories (SAM).
RAM can be classified in three main groups as shown below.
ROMS:
The type of memory means the content of an address location
can only be read and cannot be written into. The contents of the
memory location are not destroyed whether the power is ON or OFF.
Such a memory is known as non volatile memory. ROMs are used to
store data on permanent basis. They are random access memories
and this makes them very useful for the storage of computer
operating systems, software language computers, look-up tables and
programs for dedicated microprocessor applications. ROMs can only
be read are not written into.
MASK ROMs:
Mask ROMs are programmed by a masking operation
performed on the chip during the manufacturing process. The
contents of a ROM are decided by the manufacture. These contents
are permanently stored in a ROM at the time of manufacturing. The
contents of MROMs cannot be changed by the user. Most desktop
computers use MROMs to contain there operating system and for
execution fixed procedures, such as decoding the keyboard and the
generation of characters for the CRT.
PROMs:
If user needs relatively few ROMs, there is a variation, which
cost more per devices but allows the user to in rest the information.
To avoid the high one-time cost of producing custom mask ROMs, IC
manufacturing provides user programmable ROMs. This device is
called programmable Read only memory. Using special equipments,
called PROM programmers, user can program a PROM- once.
Subsequently one can read the information out of PROM as often as
one wish, but one can never write into it again. Therefore once the
PROM is programmed with correct information it can be used as a
ROM only in microcomputer. If one needs to change or correct the
information stored in the PROM, one must pull it out, throw it away
and replace is with a fresh unused PROM, writing the new on
corrected information into this in used devices. The PROM will hold
its contents indefinitely.
These PROMs are provided with fusible links which are burned
during the programming. Once the data are permanently stored in the
PROMs, it can be read again and again by just accessing the correct
memory location.
EPROMs:
If a mistake is done in programming ROM and PROMs, the
correction cannot be made. The solution of this problem is erasable
PROM (EPROM). An EPROM is an erasable PROM. The contents
are erased by ultra violet light. Therefore, they are also called
UVEPROM. The user can not erase the content of a single memory
location, the entire contents are erased.
EPROMs can be reprogrammed using EPROM programmer.
Once programmed, it can be used as ROM in microcomputer. Later,
if one needs to correct the information stored, it is taken out from the
system, erase the program written, write new program into it and use
it.
The EPROM is erased by exposing an open window in the IC to
an ultraviolet light source for a specified length of time, typical erase
time vary between two and 30 minutes, the EPROM programmed and
providing proper addresses.
An EPROM also holds the information indefinitely once it has
been programmed. One can read the contents of an EPROM as often
as one like.
RMMs:
They are read mostly memories, since they have much slower
write time then read time, there memories are usually suited for
operation where mostly reading rather than, sorting will be performed.
E2PROMs:
E2PROM are electrically erasable PROM. They need not to be
removed from a microcomputer board for erasing. Erasing &
programming E2PROM is much easier as the ultraviolet sources are
not required. The stored information can be erased by applying a high
voltage of about 21V, a singly byte or the entire chip can be erased
in10 mille sec. This is faster than UV erasing and it can be done
easily while the chip is still in circuit, It is also known as EAPROM
(electrically alterable PROM). One can write into at any time without
erasing prior contents. The problems with EAROM are that
electronically they are relatively difficult to use also, they slowly lose
their information.
One application of the E2PROM is in the tuner of a morden TV
set. The E2PROM remember (i) the channel, you were watching
when your tuned off the set (2) the volume setting of the audio
amplifier.
RWMS:
In this type of memory one can either read the contents of an
addressed location in a MEMORY READ operation or one can write a
m bit of data in the addressed memory location in a MEMORY
WRITE operation. It is a volatile memory. It is normally known as
RANDOM ACCESS MEMORY (RAM). The content of RWM shall be
destroyed when the power is OFF. During of MEMORY REALD
operation the content of the addressed location is not destroyed. It is
only read onto the external data bus. During a MEMORY WRITE
operation, however, the original content of the addressed location is
destroyed and the new content takes it placed which is just now
written.
Read/write memories are used for temporary storage of data
and program instruction in a up based septum there are also RAMs,
RWMs are generally called RAMs, RAMMs a specific terms it tells
that the data can be read on written to any memory location,
RAM is classified as either static on dynamic, static RAMs
(SRAMs) flip flops as basic storage elements; whereas the dynamic
RAMs (DRAMs) use internal capacitor as basic storage elements,
additional refresh circuitry is needed to maintain the charge on the
internal capacitor of a dynamic RAM; they have more packing
density, there it has more storage capacity per unit area team a
static RAM, the cast per bit of dynamic RAMs is also much less than
that of the static RAMs.
Non-volatile RAM:
A Non-volatile RAM combines a static RAM and E2PROM into
the same chip. Such a device operates as a normal RAM. If power
supply fails the entire content of RAM are stored in E2PROM by a
single signal . A signal can transfer data from
E2PROM back into the RAM. E.g. x2201 is a non-volatile RAM of 1K
bit. The transfer time is 4msec.
Lecture-7
The symbolic diagram of a static RAM and ROM are shown below:
Figure (a)
The pin details are given below:
GND = +5V and Ground
- address lines
data lines
Programming voltage
= output enables (to enable the output data buffer)
/PROG= dual function pin. While programming HIGH pulse is
applied at this pin and during read operation the chip is selected
enabled by making pin low.
The above procedure is repeated for all location to programme all the
2K memory location. One can programme 2716 partly as required. All
the above actions are carried out in separate unit known as EPROM
programmer. It requires only 100sec to programme all the memory
locations.
Once the programme is written down in memory chip, it cannot be
erased. If we want to change it we put it in UV eraser and erase it and
then programme it again.
The wave forms of the chip show that the data out puts became valid
after a delay for setting up the addresses on enable the chip on
inability the output whichever is completed last.
Fig (b)
The truth table for control signals are as follows:
Operation REMARKS
The data available on the data bus shall
0 0 X WRITE be written on the addressed location. The
original contents are lost. The new labes
it place
The content of the addressed location is
0 1 0 READ READ on to the output data line 0-00. The
content other addressed location is not
destroyed.
No
0 1 1 operation Output is Tri state.
*tri stated
No
1 * * operation Output is Tri state.
tri stated
The two chips 2716 and 6116 are pin by pin compatible and can be
used in place of other. The pin by pin compatibility of 6116 with 2716
has a advantage. In the initial stage of a programme development we
fix up 6116 in the 24 pin socket provided on the microcomputer and
develop the programme. After a lot of effort we are ready with a
permanent programme. Once the programme is completely tested
and satisfactory then using a PROM programmer the programme can
be transferred to 2716 ROM for permanent storage. Thereafter, 2716
can be put directly to the same socket occupied by 6116. A simple
jumper should be provided for pin no 21. This is shown in figure
below.
Lecture-8
Dynamic RAM chip:
A dynamic RAM comprises storage cells that may be thought of
eclectically as capacitors there are many thousands of these
capacitors, or storage cells on a dynamic RAM chip, each all is
capable of storing one bit of information.
The capacitor that makes this storage cell is not ideal. That is,
change placed on this capacitor will leak off given enough time. In a
DRAM, the change on the capacitor represents the stored data.
Therefore, the data stored in the cell can be lost. A more accurate
model of the storage cell is a capacitor in parallel with a resistor.
: When the up has output the col address on the A5-A0 lines, the
line is assented internally.
DIN: Data is stored in the cap cell by making this line o or 1. After
the row & ecol address are latched internally, the up writer to the cell
by places data on this line.
DOUT: Data is read from the RAM chip their line, after the row & col,
address are latched internally, the selected cell entreats are output to
the line.
Lecture 2
Microcomputer Organization:
The basic components of a microcomputer are:
1) CPU
2) Program memory
3) Data memory
4) Output ports
5) Input ports
6) Clock generator.
These components are shown in figure below:
Program Memory:
The basic task of a microcomputer system into ensure that its
CPU executes the desired instruction sequence is the program
properly. The instruction sequence is stared in the program memory
on initialization- usually a power up and manual reset the processor
starts by executing the instruction in a predetermined location in
program memory. The first instruction of the program should
therefore be in this location in typical p basic system, the program to
be executed is fixed one which does not change. Therefore p
program are store on ROM, or PROM, EPROM, EEPROM.
In the trainer kit, ROM contains only the monitor program. The
user program is not stored in ROM because it needs not to be stored
permanently.
Data Memory:
A microcomputer manipulates data according to the algorithm
given by the instruction in the program in the program memory.
These instruction may require intermediate results to be stored, the
functional block in c have same internal reg. which can also be used
if available for such storage external data memory is needed if the
storage requirements is more.
Apart from intermediate storage, the data memory may also be
used to provide data needed by the program, to store some of the
results of the program. Data memory is used for all storage purposes
other than storage of program. Therefore, they must have head write
capability RWM or RAM.
It stores both the instructions to be executed (i.e. program) and
the data involved. It usually contains ROM (Read memory). The ROM
can only read and cannot be written into and is non volatile that is, it
retains its contents when the power is turned off. A ROM is typically
used to store instructions and data that do not change. For example,
it stores the monitor program if a microcomputer.
One can either read from or write into a RWM. The RWM is
volatile, that is it does not retain its contents when the power is turned
off. It is used to store user programmes & data which are temporary
might change during the course of executing a program. Both ROM &
RWM are RAM (Random access memory). RWM is respectively.
During a memory read operation, the content of the addressed
location is not destroyed. During a unit operation, the original content
of the addressed location is destroyed.
Both ROM & RWM are arranged into words, each of which has
a unique address. The address of a word is memory location and it is
placed in parentheses. Therefore, X is an address and (X) is the
content of that address X.
The address decodes taken an address and from the control
unit and select the proper memory location and obtaining its content
takes a certain amount of time, this times is the access time of the
memory. The access time affects the speed of the computer, pins,
and the computer must obtain the instruction and data from the
memory. Computer memory as usually RAM so that all memory
location have the same access time. The computer must wait shiner
of units memory, typical memory access time range from several
uses. Memory sections often subdivided into units called pages. The
entire memory section may involve million of cords, when a page
contains between 256 & 4k warts. The computer may access a
memory location by first decreasing a particular page and then
accessing a location on that page. The advantage of paging is that
the computer can reach several locations on the same page with just
the address in the page. The process is like describing street address
by first specifying aspect and them listing the have numbers. The
control section transfers data to or from memory as follows.
1. The control section reads an address to the memory.
2. The control section sends a read and write signal to the
memory to indicate, the direction of the transform.
3. The control section waits until transfer has been completed .this
delay precedes the actual datas transfer in the input case and
follows it in the output case.
Input/Output Ports:
The input & output ports provide the microcomputer the
capability to communicate with the outside world. The input ports
allow data to pass from the outside world to the c data which will be
used in the data manipulation being done by the microcomputer to
send data to output devices
The user can enter instruction (i.e. program) and data in
memory through input devices such as keyboard, or simple switches,
CRT, disk devices, tape or card readers. Computers are also used to
measure and control physical quantities like temperature, pressure,
speed etc. For these purposes, transducers are used to convent
physical quantise into proportional electrical signals A/D computers
are used to convert electrical signals into digital signals which are
sent to the compute.
The computer sends the results of the computation to the
output devices e.g. LED, CRT, D/A converters, printers etc.. These
I/O devices allow the computer to communicate with the outside
world I/O devices are called peripherals.
Clock Generator:
Operations inside the p as well as in other parts of the c,
are usually synchronous by nature. The clock generator generates
the appropriate clock periods during which instruction executions are
carried out by the microprocessor. This condition ensures that events
in different path of the systems can proceed in a systematic fashion.
Some of the microprocessors have an internal clock generator
circuit to generate a clock signal. These microprocessors require an
external crystal or RC network to be connected at the appropriate
pins for deciding the operating frequency (e.g. 8085). Some
microprocessors require an external clock generator (e.g.
8086).These microprocessors also provides an output clock signal
which can be used by other devices in the microcomputer system for
their can timing and synchronizing.
Lecture-9
Intel 8085 Microprocessor
It is a 40-pin DIP(Dual in package) chip, base on NMOS technology,
on a single chip of silicon. It requires a single +5v supply between
Vcc at pin no 40 and GND at pin no 20. It can address directly 216
memory locations or 6536 memory locations or 64k memory locations
using 16 address line (A15-A0).
Pin no 28 to 21 gives as the higher order 8 bits of the address (A15-
A8).these 8- address lines are uni-directional tri-state address lines
these address lines becomes tri-state under three conditions namely.
(a) During DMA (direct memory access )operation
(b) When a HALT instruction is executed
(c) When is being RESET.
A15-A8 at pin no 19 to pin no 12 pin no 19 to pin no 12, marked A7-
A0 is used for dual purpose. The during it operation shall move
from one state to the other. There are ten (10) different states for the
R7.5 FLIP-FLOP
The RST 7.5 control signal input is a LOW to HIGH transition
active interrupt control signal input. The LOW to HIGH transition of
the signal is registered in R7.5 FLIP-FLOP. Whenever M7.5 FLIP-
FLOP is CLEAR, the output of R7.5 is sensed and recognized as an
interrupt by the R7.5 FLIP-FLOP can be CLEAR through the
same SIM instruction. It is for the user to make use of these facilities.
With the above explanation, we can write the logic expression for the
logic variable, VALID INT.
VALID INT = 0 when none of the interrupt control signal input are
interrupting the microprocessor and VALID INT = 1 when any of the
interrupt control signal is active. Thus
VALID INT= TRAP+ INTE [INTR+R7.5 + RST 6.5 + RST
5.5 ]
These control signal are normally HIGH and becomes active LOW
during T2 state and goes back to HIGH during T3 state. In between T2
& T3 states any no of WAIT states Tw can be inserted.
Buses:
Bus is a group of parallel lines that connect two or more
devices. It carriers information in bits (When the microprocessor
needs to access a circuit memory location or I/O devices) in another
part of the c; it does so by setting up signals on the address bus to
identify the appropriate circuit. Data may be transferred by means of
data bus, in required direction between the circuit and the processor.
Signals on the control bus server a number of purpose such as
control the transfer of data direction.
Data Bus:
A set of data lines (8) referred to as the data bus is shared by
number of devices to transfer data between p and peripherals.
Case must be taken that at a time only. One device should output
data on the data bus, the other devices data on the data bus, the
other devices which can output data meet be in high 7 condition. The
data can flow in both directions that is to or from the p. Therefore,
this is a bidirectional bus. (BDB) In some microprocessors, the data
pins are also used to send other information such as address bits in
addition to data. This means that the data pins are time shared or
multiplexed. The Intel SDK-85 microcomputer, is a example where
the lower 8 bits of the address are multiplexed on the data bus,
Control Bus:
This bus consists of a number of signals that are used to
synchronize the operation of the individual microcomputer elements
The p uses these signals for every operation it performs (like
reading or writing a memory location on device). These signals are
also used to identify memory or I/O devices etc. e.g., RD, WR, IO/M ..
The microprocessor sends some of these control signals to the other
elements to indicate the type of operation being performed. The
bussed architecture of microprocessor is shown.
Applications of Microprocessors:
The application of microprocessors is increasing day by day.
There are memories applications few are:
1) Analytical scientific instruments
2) Smart terminals
3) Stacker crane controls
4) Conveyor controls
5) Word processor
6) Point of scale systems
7) Standalone electronics cash system
8) Electronic games
9) Vending and dispensing machines
10) Market scales
11) Traffic light controls
12) Home heating and lighting controls
13) Security & fire alarm system
14) Home appliances
15) Computer aided instruction
16) On line control of lab instrumentation
17) Desktop computers
18) Check processor
19) Payroll system
20) Inventory control
21) Automatic type setting
22) Compact business machines
23) Medical instrumentation
24) Automobile diagnostics
25) Data communication processing
26) Optical character recognition
27) I/O terminal for computers.
Lecture-12
INTERNAL ARCHITECTURE OF INTEL 8085: The Functional Block
Diagram Of 8085 Is Shown In Fig 16.
The three crossed bits are redundant bits and not used. They can be either 0
or 1. It is immaterial but normally forced to be zero. These five bits are
affected as a result of execution of an instruction. All instruction execution
do not affected the flags e.g. data transferring operation do not affect these
flags the arithmetic operation effect all these flags the meaning & the effect
of the fleegs are as follow;
CY CARRY FLAG BIT: this particular bit is SET if there is a carry from the
MSB position during an addition operation or if there is a borrow during the
subtraction operation, otherwise this flag is RESET.
AC- AOXILIARY CARRY FLAG BIT: This bit is SET if there is a carry
from A3 bit to A4 bit of the accumulator during the process of executing
operation connected with an accumulator otherwise it is RESET. The AE
flag is useful for arithmetic & is used in a particular instruction known as
DAA (Decimal adjust accumulates).
Z-ZERO FLAG: Zero flag bit is SET if the result of an operation is zero,
otherwise it is RESET.
S-SIGN FLAG: This flag is SET if the MSB of the result is a 1 otherwise it
is RESET. As an example, let us consider the execution of the instruction
ADDB. ADD is the mnemonic for addition B is the second operand. The
first operand is known to exist as the content of the accumulator. The
meaning of the instruction is add the content of the B register to the content
of A register and store the result back in the accumulator, symbolically, we
write the macro RTL complemented.
A B 1 0100 0000 A
cy 1111 1111 AC
C C 1 C C
Let us suppose C contains (C) =D2H before the execution of the instruction
after the instruction, C shall contains D1H and therefore in not zero.
Therefore the flag register will be affected as follows.
S Z X AC X P X CY
FR = 1 0 0 0 010 0
On the other hand, if a contains 01H just before the execution if the
instruction, C shall contain 00H. Since the result of the operation is 0 the
zero flag shall now be SET to 1. Other flag will be affected in the normal
way.
These flag bits are utilized in many instructions for branding operations
during the execution of a programme normally one of these bits are tested
for TRUE or FALSE condition depending upon the condition the
programme branches. This is shown in fig 18.
REGISTER SECTION:
There are 6-8 bit register designed B, C, D, E, H, & L. all are accessible to
the user. In an instruction these six 8bit register along with the accumulator
A shall be identified by a 8 bit code designated either SSS or DDD.
Whenever SSS is used, it corresponds to service register. Whenever, DDD is
used, it corresponds to destination register. The code used as follows,
SSS or DDD
000 ----- B
001 ----- C
010 ----- D
011 ----- E
100 ----- H
101 ----- L
111 ----- A
Note in the above code 110 is not used. Whenever 110 is used for SSS or
DDD, it means a specific register pair (H,L), together to from 16 bit register
known as memory address register (MAR) or M- pointer.
This is an ALP statement, MOV is the mnemonic for move, and V1, v2 are
the operand register, in the statement, V2 is the source register and V1 is the
destination register. The meaning of the instruction is MOVE the contents of
v2 register into V1 register5. Symbolically this basic operation can be
described by a basic RTL statement (V1) ---- (V2).
This is a single byte instruction. The single byte being the operation code.
The arrangement of the op code single byte is shown in fig 19.
V1 code V2 code
0 1 D D D S S S
Fig 19 (a) gives the example of MOV A, H code for this statement is,
0 1 1 1 1 1 0 0
For move fig 19 (a).
The opcode is read is together 0111 1100 B = 7CH. when the instruction7CH
is executed content of H register shall be transferred to A register. Note
that content of H register is not destroyed. However, the original content of
A register is lost. Let us take another example for the use of code 110.
RP
00 ----- (B, C)
01 ----- (D, E)
10 ----- (H, L)
11 ----- SP --------- (SPH, SPL)
Lecture-13
PROGRAM COUNTER:
Note: If the address information for PC has not been sent out during
T state to the external world, them the PC will not be incremented
using T2 state.
Since the contents of (B, C) & (D, E) reg. pairs are stored at the
top of the stack, these registers are now available for further
computation in the subroutine. At a later stage of execution of the
program after utilizing B, C, D, E registers, there may be a need to
restore the original contents to the respective registers. E.g. at the
end of the subroutine, the data is restored to the proper register.
When POP D is executed the data from the top of the stack is copied
to reg. E, data pointer is incremented by 1, then the next byte of the
saved data is copied from the stack to the reg. D, and SP is further
incremented by 1.
This is similar to previous one but now some data has been
stored in the stack area but these are irrelevant anyway. They will be
destroyed during the next PUSH operation on the stack.
From the above discussion, following points emerge:
1. The stack pointer always points to the top of the stack up to
which it is full with relevant data.
2. Storing or saving the data on stack is known as PUSH
operation.
3. The restoring or reading data from the stack onto certain
internal registers are known as POP instructions.
4. The stack operates on Last in first out basis.
5. The stack pointer can be initialized to the bottom of the stack
but bottom of the stack cannot be utilized to store any useful
data.
6. It is for the user to see that the program area does not overlap
with stack area.
Lecture-14
W-Z:
When a 3-byte instruction containing 2 byte address is to be
executed by the , the first byte is the (op-code) which is fetched
and then decoded by the decoder. Then two memories read m/c
cycles are executed to read the two byte address one in each m/c
cycle and placed in W-Z register. During instruction execution, (in
next m/c cycle), the addr in W-Z register pair is transferred to the
address latch to address memory or I/O for data transfer.
Interrupt Control Section:
Sometimes it is necessary to interrupt the execution of the main
program to answer a request from an I/O device. For instance, an I/O
device may send an interrupt signal to interrupt control unit to indicate
that data is ready for input. The temporarily stops what it is doing,
inputs the data and then returns to what it was doing.
Serial I/O Control:
Sometimes, I/O devices work with serial data rather than
parallel. In this case, the serial data stream from an input device must
be converted to 8-bit parallel data before the computer can use it.
Likewise the 8-bit data out of a computer must be converted to serial
form before a serial output device can use it.
The SID input is where serial data enters the 8085. The SOD
output is where the serial data leaves the 8085. Two instructions
known as SIM & RIM allow the user to perform the serial parallel
conversion needed for serial I/O device.
Timing and control section:
The timing and control section supervise the complete
operation of the . The on chip clock oscillator which produces the
internal clock is a part of this section. The timing and control section
also has a state generator to generate 10 different states namely
state generator is a multi
mode counter. The next state of the state generator from the present
state is decided by the many control signals like READ, HALI, INTR,
HOLD etc in each states then section of generator many control
signals for executing the instruction fetched.
The operation of the is cyclic in natural. During the normal
operation from the ward Go, sequentially and executes one
instruction after another until a HALT instruction is executed. The
fetching and execution of a single instruction constitutes an
instruction cycle. The instruction cycle consists of one or more read
or write operation to memory or an I/O device each memory I/O
reference requires a mechanic cycle. In other words every time a byte
of data is more from CPU to I/O or memory or from memory I/O to
cpu , a machine cycle is required.
There are seven different kinds of m/c cycles in the 8085 A:
1. OPCODE FETCH
2. MEMORY READ
3. MEMORY WRITE
4. I/O READ
5. I/O WRITE
6. INTEROPT ACKNOLEDGE
7. BUS IDLE
Three status signals IO/ generated at the beginning of
each m/c cycle (and generated during state of
the M/C cycle) identify each type of the m/c cycle the station signals
remain valid for the duration of the cycle. The instruction fetch portion
of an instruction cycle requires a machine cycle for each byte of the
instruction to be fetched since instruction consist of 1 to 8 bytes (1,2
or 3), the instruction fetch Is one to three machine cycles in duration.
The first m/c cycle in an instruction cycle is always an OPCODE
fetch m/c cycle which is always single by long and the 8 bits obtained
during an OPCODE FETCH are always interpreted as an OPCODE
of an instruction. Note that to fetch an instruction is to transfer an
entire instruction from memory to the necessitates an OPCODE
FETCH m/c cycle. However, one or two memory read m/c cycles are
also needed to complete the fetch for 2&3 byte instruction
respectively.
The number of m/c cycles required to execute the instruction
depends on the particular instruction. Some instruction require no
addition m/c cycles after the instruction fetch is complete, other
requires additional m/c cycles to write or read data to or from memory
or I/O devices from one to five. Around 50% of the instruction
requires only one m/c cycle for fetching and executing the instruction,
no instruction requires more than five m/c cycles M/C cycles like the
memory read or memory write may occur more than once a single
instruction cycle.
MC-i (i=2,3,4,5)
Thus one complete transition from state through the state
diagram and back to constitutes a complete m/c cycle the partial
state transition diagram is shown below assuming READY=1 is no
wait.
The shaded portion above that these state may be neede in
same instructions. Instruction cycles for various 8085A instruction
required to execute an instruction will depend on the READY & HOLD
signal inputs.
For example consider the 3 byte instruction STA ADDR, STA stands
for store accumulator direct the meaning of the instruction is transfer
the content of the accumulator to an external memory location whose
address is specified in the instruction is ADDR since. The location
can be anywhere in the 64k memory space that the 8085A can
directly address, 16k are required for the address thus the STA
instruction contain 8bytes; a 1 byte op-code and 2-byte address. The
instruction is stored in the memory as follows.
OP CODE BYTE 1
LOWER ADDR 2
HIGHER ADDR 3
Three m/c cycles are required o fetch this
instruction. In MC-1 is op code fetch M/C ,the opcode is transferred
from memory to the instruction register during states and then
during state it is interpreted , at this point the cpu knows that it
must do more m/c cycles two RMC to fetch the complete instruction
in MC-2 the lower addresses transferred from the memory to the
temporary register Z. in MC-3 the third byte i.e. the higher address is
transferred from the memory to the temporary register W. when the
entire instruction is in the it is executed. Execution means a data
transfer from the to memory. The contents of the accumulators
are transferred to the memory location, whose address was
previously transferred to the by the proceeding two memory read
m/c cycles the address of the memory location to be written is
generated as follows the high order address byte is temp reg. W is
transferred to the address latch and the low order address byte in Z
reg. is transferred to address/data latch. The content of the A is then
placed on the data bus. This data transfer is affected by a MWRMC
thus 3 byte STA instruction has four m/c cycles in its instruction
cycles.
Mnemonic Instruction byte
STA op code OP CODE
FETCH
LO addr MRMC
Hi addr MRMC
MWRMC
This STA has a total of 13 states. If the 8085A is operating at
325.5ns time, the STA instruction cycle is executed in 4.23 . This
time period is the instruction execution time, although it actually
includes both the instruction fetch and the execution time.
Lecture-15
MACHINE CYCLES
comes out of Twout state and enters into state and cycle
continues wait states continues to be inserted as long as READY is
low.
The effect of entering a wait states is to hold all external signals
from the in the same state they were on at the end of state . Is
the content of address bus, data bus, and control bus are all hold
constant. This stretches the duration of address pulse, so
devices with access time greaten than 575ns can be read. If N wait
states are introduced into the cycle, the required access time is
[( T-225] ns.
Fig shows a single WAIT state or transition in OFMC. Sampling
of the READY line in state and the transition into the WAIT state
Fig shows the 8085A state transition diagram this is compact way of
showing when during an instruction cycle the 8085A will enter a halt
state, insert a wait state, res to HOLD input or respond to an interrupt
input.
Note that the does not check whether a valid intercept request
is present until the end of the unidirectional cycle .this is necessarily
so that the address if the next instruction can be pushed into the
stack.
MOV r1, r2: This is an ALP statement, MOV is the mnemonic for
move. r2 is the source register. r1 is the destination register in the offer
and fields the meaning of the instruction is move the contents of the
register r2 into r1. The content of r2 is not destroyed .content of r1os
destroyed and new value form r2 takes it place. The macro RTL
implemented is
(r1) (r2)
Thus the instruction cycle for MOV r1,r2 takes only L1 clock
states (& not six) after the executions PC point to next address.
MC- 1.
Mc 2
FEO T1 : AD7- AD0 (PCL) , A15 A5= (PCH), ALE
(r1) (z) T2 :: = 0, (PC) (PC ) + 1, AD1- AD0 M(AB)
This Operation Require Only Single M/C Cycle of OFMC & needs
only four state.
MC -1 OFMC
T1 T2 T3 T4
INSTRUCTION CYCLE
Now after execution of this instruction pointer goes to T1 state & PC
points to next address.
C2
OFMC T1:AD7 AD0 (L), A15 A8 (H) , ALE
IO / M 0 T2: RD 0, AD7 AD0 M (AB)
S1 1 T3:RD 1, , (R) (AD7 AD0 )
S0 0
This Operation requires only two m/c cycle OFMC & MRMC and total
7 states. It requires 3.5 sec using 2 MHz clock
INSTRUCTION CYCLE
OFMC MRMC
T1 T2 T3 T4 T1 T2 T3
Fig.7
The addressing mode is register indirect addressing mode fig 7
illustrates the operation cycle.
01 110 SSS N
It has seven variations SSS cannot be 110.
MC 2
MWRMC T1:AD 7 AD0 (L), A15 A8 (H),ALE
IO / M 0 T2: WR 0, AD7 AD 0 M (v)
S1 0 T3:WR 1, , M(AB) (AD 7 AD0 )
S0 1
The Operation requires only Two m/c cycles- OFMC & MWRMC and
total no of 7 states. It requires 3.5 p using 2 MHZ internal clocks. It
is register indirect addressing mode.
INSTRUCTION CYCLE
OFMC MWRMC
T1 T2 T3 T4 T1 T2 T3
MVI r, DATA:
00 DDD 110 N
<B2> N+1
(v) B2
The micro RTL flow is
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC)(PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,,(IR)(AD7 AD0)
S1 1
T4:MVI V1
S0 1
MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0,(PC)(PC) 1, AD7 AD0 M(AB)
S1 1 T3:RD1,,(v)(AD7 AD0)
S0 0
It require only two m/c cycles OFMC & MRMC and 7 states. It
requires 3.5 using 2 MHz internal clock.
.
Figure. 9
Lecture-19
Instruction Set
MVI M, DATA:
This is an ALP statement DATA is symbolic name given to the
nd
2 byte of the instruction MVI is the mnemonic for move immediate. M
in the operand field stands for memory pointer. The meaning of the
instruction is 8 bit data available as a 2nd byte of the instruction should
be moved to the memory location whose address is available in m
pointer namely (H, L) register pair. The macro RTL implement should
be.
M (H, L) B2
00 110 110 N
<B2> N+1
MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0,(PC) (PC) 1, AD7 AD0 M (AB)
S1 1 T3:RD1,,(Z) (AD7 AD0 )
S0 0
MC 3
MWRMC T1:AD 7 AD0 (L), A15 A8 (H),ALE
IO / M 0 T2: WR 0, AD7 AD 0 (Z)
S1 0 T3:WR 1, , M(AB) (AD7 AD 0 )
S0 1
(rpL) B2
(rpH) B3
The instruction format is
00 RPO 001 N
<B2> N+1
<B3>
N+2
RP = 00 LXI B, DDATA
RP = 01 LXI D, DDATA
RP = 10 LXI H, DDATA
RP = 11 LXI SP, DDATA
The micro RTL flow is
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0, (PC)(PC) 1 AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:LXIrp 1
S0 1
MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0, (PC) (PC) 1 AD7 AD0 M(AB)
S1 1 T3:RD1,, (rp) (AD7 AD0 )
S0 0
MC 3
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0, (PC) (PC) 1 AD7 AD0 M(AB)
S1 1 T3:RD1,, (rpH) (AD7 AD0 )
S0 0
It requires three m/c cycle OFMC & two MRMC. And total no of 10
states. It needs 5sec using 2 MHz internal clock. It is immediate
addressing mode.
LDA ADDR:
00 111 010 N
<B2> N+1
<B3>
N+2
(A) M(B3 , B2 )
MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0, (PC)(PC) 1 AD7 AD0 M(AB)
S1 1 T3:RD1,, (Z) (AD7 AD0 )
S0 0
MC 3
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0, (PC)(PC) 1 AD7 AD0 M(AB)
S1 1 T3:RD1,, (W)(AD7 AD0)
S0 0
MC 4
MRMC T1:AD7 AD0 (Z), A15 A8 (W),ALE
IO / M 0 T2: RD 0, AD7 AD0 M(AB)
S1 1 T3:RD 1, , (A) M(AD7 AD0 )
S0 0
STA ADDR:
00 110 010
<B2>
<B3> N
N+1
N+2
M(B2 , B3 ) (A)
This has no variations this is. This is direct addressing mode. The
micro RTL flow is:
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0, (PC)(PC) 1 AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR)(AD7 AD0)
S1 1
T4:STA 1
S0 1
MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0, (PC)(PC) 1 AD7 AD0 M(AB)
S1 1 T3:RD1,, (Z)(AD7 AD0)
S0 0
MC 3
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0, (PC)(PC) 1 AD7 AD0 M(AB)
S1 1 T3:RD1,, (W)(AD7 AD0)
S0 0
MC 4
MWRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:WR0, AD7 AD0 (A)
S1 0 T3:WR1,, M(AB) (AD7 AD0 )
S0 1
It requires 4 machine cycle OFMC & 2 MRMC & one MWRMC and
13 states. It need 6.5sec using 2 MHz internal clock.
00 101 010 N
<B2> N+1
<B3>
N+2
MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
S1 1 T3:RD1,, (Z) (AD7 AD0 )
S0 0
MC 3
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
S1 1 T3:RD1,, (W) (AD7 AD0 )
S0 0
MC 4
MRMC T1:AD 7 AD 0 (Z), A15 A8 (W), ALE
IO / M 0 T2: RD 0, AD 7 AD 0 M(AB)
S1 1 T3:RD 1, , (L) (AD 7 AD 0 )
S0 0
MC 5
MRMC T1:AD7 AD0 (Z 1), A15 A8 (W),ALE
IO / M 0 T2: RD 0, AD7 AD0 M(AB)
S1 1 T3:RD 1, , (H) (AD7 AD0 )
S0 0
This instruction requires 5m/c cycles OFMC & 4 MRMC and total 16
states. It needs 8s using 2 MHz clock. This instruction has no
variations. It is direct addressing mode.
00 100 010 N
<B2> N+1
<B3>
N+2
MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
S1 1 T3:RD1,, (Z) (AD7 AD0 )
S0 0
MC 3
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
S1 1 T3:RD1,, (W) (AD7 AD0 )
S0 0
MC 4
MWRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:WR 0, AD7 AD0 (A)
S1 0 T3:WR 1,, M(AB) (AD7 AD0 )
S0 1
MC 5
MWRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:WR0, AD7 AD0 (A)
S1 0 T3:WR1,, M(AB)(AD7 AD0 )
S0 1
00 RP1 010 N
There are two variations in this instruction RP =00 for (B, C) pair and
RP= 0 form DE pair note that RP=10 and 11 are not allowed in this
instruction. The micro RTL is
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:LDAXrp 1
S0 1
MC 2
MRMC T1:AD7 AD0 (rpL), A15 A8 (rpH),ALE
IO / M 0 T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
S1 1 T3:RD1,, (A) (AD7 AD0 )
S0 0
This instruction requires 2 m/c cycles OFMC & MRMC and 7 states. It
needs 3.5 sec using 2MHz clock. The addressing mode is register
indirect addressing mode.
(12) STAX rp: This is an mnemonic for STAX accumulator indirectly
using register indirect addressing mode. The meaning of the
instruction is the content of the accumulator should be moved to the
memory location whose address is available in register pair. The
macro RTL implemented shall be
00 RP0 010 N
Here also only two variations RP=00 and 01 are allowed. The micro
RTL flow is
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:STAX rp 1
S0 1
MC 2
MWRMC T1:AD7 AD0 (rpL), A15 A8 (rpH),ALE
IO / M 0 T2: WR 0, AD7 AD0 (A)
S1 0 T3:WR 1, , M(AB) (AD7 AD0 )
S0 1
It requires only 2 m/c cycles OFMC & MWRMC and 7 states. It needs
3.5sec using 2MHz clock.
11 011 011 N
<B2> N+1
The data generated by an i9nput device is stored temporarily in
some register which can be used by the MP when necessary 2n
order to place the contents of the input register and the MP system
bus, the outputs the connected to the data bus through a three, state
input instructions places an Q- bit devices address at the address
bus, where it is duplicated an higher & lower order bus An external
decoder decodes the device address, the IO/ , & the pulse in
order to generate an input device select pulse state buffer, the
addressed input parts three state buffer, thus placing the input ports
data an the data bus.
The IN port is a2- byte instructions, the first byte is the OP code
and the second byte is the 8-bit input device address. The address
may be any varying from 00 to FF. Thus , a total of 256 input devices
can be connected directly, through updated I/O structure, where the
source register to identified by an explicit 8-bit address, the
corresponding I/O structure is shown by the map.
The micro RTL flow for executing this instruction is as follows:
MC- 1 OFMC T1 : AD,- AD (PCL) , A15 A8 (PCH), ALE =
IO/ = 0 T2 : = 0, (PC) (PC ) + 1, AD1- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : IN = 1
Mc 2 MRMC
IO/ =0 T1 : AD1- AD0 (PCL), D5 A8 (PCH),ALE =
S1 = 1 T2 : = 0, (PC) (PC ) + 1, AD1- AD0 M(AB)
S0 = 1 T3 : = 1, (W) (AD7- AD0) (Z) (AD7- AD0)
00H
FFH
IO / M 1
S1 1`
S0 0
RD 0
110 100 11 N
<B2> N+1
MC 2
MRMC T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0 T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
S1 1 T3:RD1,, (Z)(AD7 AD0)&(W) (AD7 AD0)
S0 0
Thus it requires 3m/c cycles OFMC, MRMC & IOWRMC and total 10
states. It needs 5sec using 2 MHz internal clock. If the output device
is interfaced for communications using this instruction then the
structure is known as isolated I/O structure I/O structure or I/O map
I/O structure. We can address directly 256 output devices addressed
from 00H to FFH. Shown in fig19a.
00H
FFH
IO / M 0
WB 0
fig 14 a output I/O space
(AB) (B0 ,B1 )H
(Y1Y0 Y1Y0 )H
11 10 10 N
11
The micro RTL flow is
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:XCHG 1, (H,L) (D,E)
S0 1
Lecture-21
2) ARITHMETIC GROUP: This group perform the arithmetic operation on
the operands normally the operands are necessary for any arithmetic
operation one of the operand is always seen in the accumulator the other
operand can be seen in one of the three positions.(a) an internal general
purpose register (r) .
All of the flags are effected as per standard rule. The format of the operation
code is shown in fig 15.
This is a single byte instruction. The meaning is add the content of register
(v) to the content of accumulator and store it back to the accumulator. The
operation code is 10 000 SSS. It has 7 variations. The micro RTL flow is
given below:
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:(A) (A) (v)
S0 1
This is a single byte instruction. The meaning is add the content of memory
location whose address is in (H, L) pair to the content of accumulator and
store it back to the accumulator. The operation code is 10 000 110 or 86H. It
has no variations. It is register indirect addressing mode. The micro indirect
addressing mode. The micro RTL flow is given below,
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR)(AD7 AD0 )
S1 1
T4:ADD M 1
S0 1
MC 2
MRMC
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
IO / M 0
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
S1 1
T3:RD1,, (TEMP)(AD7 AD0),(A)(A) (TEMP)FEO
S0 0
FEO
IT requires two m/c cycle OFMC, MRMC, and 7 state.
(3) ADI DATA: It is a two byte instruction. The second operand is seen in
the instruction itself. The operation code is
11 000 110 N
<B2> N+1
(A) (A) B2
The meaning of the instruction is add the content available as the second
byte of the instruction to the content of accumulation and store the result
back to the accumulator. It has no variations and it is immediate addressing
mode. The micro RTL flow is,
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:ADIDATA M 1
S0 1
(4) ADC v: The meaning of the instruction is add the content of register (v)
to the content of accumulator with carry. The macro RTL implemented is
(A) (A) (v) (cy)
It is a single byte instruction. The opcode is 10 001 SSS. It has 7 variations.
It is register addressing mode. The micro RTL flow is
(5) ADC M: The meaning of the instruction is add the contents of memory
location whose address is in (H, L) pair to the contents of accumulator with
carry, the macro RTL implemented is
(A) (A) M(H,L) (cy)
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:ADC M M 1
S0 1
(6) ACI DATA: The meaning of the instruction is add the content available
the second byte of instruction itself to the content to accumulator with carry
and store the result back to the accumulator. It is a two byte instruction. The
opcode is
11 001 110 N
<B2> N+1
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2:RD0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (IR) (AD7 AD0 )
S1 1
T4:ACIDATA 1
S0 1
(7) SUB v: The meaning of the instruction is subtract the content of register
from the content of accumulator and stored the result back into accumulator.
The macro RTL implemented is
(A) (A) (v)
(8) SUB M: The meaning of the instruction is subtract the content of the
memory location. Whose address is in (H, L) pair from the content of
accumulator and store the result back in the accumulator. The macro RTL
flow is
(A) (A) M(H,L)
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:SUB M 1
S0 1
MC 2
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
MRMC
T2:RD0, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (TEMP)(AD7 AD0) (A) (A) (TEMP)
S1 1
FEO
S0 1
(9) SUI DATA: The meaning of the instruction is subtraction the content
available as a second byte of instruction from the content of accumulator and
store the result back in the accumulator. It is a two byte instruction. The
operation code is
11 010 110 N
<B2> N+1
(A) (A) B2
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:SUI DATA 1
S0 1
MC 2
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
MRMC
T2:RD0, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (TEMP) (AD7 AD0 ) (A) (A) (TEMP)
S1 1
FEO
S0 0
(10) SBB v: The meaning of the instruction is subtract the content of register
from the content of accumulator with borrow and store the result back in the
accumulator. The macro RTL implemented is
(A) (A) (v) (cy)
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:SBB M 1
S0 1
MC 2
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
MRMC
T2:RD0, AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (TEMPR)(AD7 AD0)(A) (A) (TEMP)
S1 1
FEO
S0 0
(12) SBI DATA: The meaning of the instruction is subtract the content
available as a second byte of the instruction from from content of
accumulator with barrow and store the result back in accumulator. It is a two
byte instruction. The operation code is
11 011 110 N
<B2> N+1
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:SBI DATA 1
S0 1
MC 2
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
MRMC
T2:RD0, (PC) (PC) 1,AD7 AD0 M(AB)
IO / M 0
T3:RD1,, (TEMPR)(AD7 AD0)(A) (A) (TEMP) (cy)
S1 1
FEO
S0 0
Note: In all these above instruction all the flow are affected as per rule.
Lecture-22
(13) INR v: The meaning of the instruction is incremented the content of
register v by 1 and store it back to the register r. the macro RTL
implemented is
(v) (v) 1
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:INRv 1 (TEMP) v, (v) (TEMPp)a
S0 1
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:INR M 1
S0 1
MC 2
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
MRMC
T2:RD0,AD7 AD0 M(AB)
IO / M 0
S1 1 T3:RD1,, (TEMP)(AD7 AD0), (ALU) (TEMP) 1
S0 0
MC 3
MWRMC3 T1:AD 7 AD 0 (L), A15 A 8 (H), ALE
IO / M 0 T2: WR 0, AD 7 AD 0 (A)
S1 0 T3:WR 1, , M(AB) (AD 7 AD 0 )
S0 1
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:DCR v 1,(v) (v) 1
S0 1
MC 1
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC
T2: RD 0,(PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:DCR M 1
S0 1
MC 2
MRMC T1:AD7 AD0 (L), A15 A8 (H),ALE
IO / M 0 T2:RD0,AD7 AD0 M(AB)
S1 1 T3:RD1,, (TEMP) (AD7 AD0 ), (ALU) (TEMP) 1
S0 0
MC 3
MWRMC T1:AD 7 AD 0 (L), A 15 A 8 (H) , ALE
IO / M 0 T 2: WR 0, AD 7 AD 0 (A )
S1 0 T3:WR 1, , M (AB) (AD 7 AD 0 )
S0 1
(17) INX rp: The meaning of the instruction is incremented the register pair
(rp) implemented is
(rp) (rp) 1
(18) DCX rp: The meaning of the instruction is decrement the register pair
(rp) together by1. The macro RTL implemented is
(rp) (rp) 1
It requires one m/c cycle OFMC and 6 states. In above two instructions no
flag is affected.
(19) DAD rp: The meaning is double precision addition is add the content of
(H,L) pair to the content of register pair (rp) and store the result back is in
the (H,L) pair. The macro RTL implemented in
(H,L) (H,L) (rpH, rpL)
Only the CY flag is effected as per rule. It is a single byte instruction. The
operation code is 00 RP 1001. It has memory is needed, if the opcode is read
from the memory therefore it goes into bus m/c cycle because to requires 10
states even single byte instruction. The micro RTL flow
MC 1
T1:AD7 AD0 (Z 1), A15 A8 (W),ALE
OFMC
T2: RD 0, (PC) (PC) 1, AD7 AD0 M(AB)
IO / M 0
T3:RD 1, , (IR) (AD7 AD0 )
S1 1
T4:DAD rp 1
S0 0
MC 2
T 1: ( W ) ( A ) , ( Z ) ( P R )
BIMC
T 2 : ( A ) ( rp L ), (T E M P ) ( rp L )
IO / M 0
T 3 :( L ) ( L ) ( rp L )
S1 0
( c y f la g i s S E T o r R E S E T )
S0 1
MC 3
BIMC
T1: ( A ) ( rp H ), (T Y R ) ( rp H )
IO / M 0
T 2 : ( H ) ( H ) 1, ( r p H ) C Y
S1 0
T 3 : ( A ) ( W ) ( P R ) (S , Z A C , P )
S0 1
RD 1
S0 1 FEO
AdjustA & flags
Lecture-23
LOGICAL GROUP:
Fig 17
Fig 17 gives the operation code format for logical group. It consists of
19 basic instructions. There are three basic logic operation AND XOR
& OR logical operation takes place bit by. The operand is assumed to
be in the accumulator. The second operand is seen either in the
internal general purpose register, in the memory location pointed to
the M- pointer or as the second byte logical operation is stored back
in the accumulator.
10 100 N
SSS
It has 7 variations. The micro RTL flow is
given below. The cy flag is cleared and AC is set.
T1:AD7 AD0 (PCL), A15 A8 (PCH),ALE
OFMC T2: RD 0, (PC) (PC)H,AD7 AD0 M(AB)
IO / M 0 T3:RD 1, , (IR) (AD7 AD0 )
S1 0 T4 : (A) (A) (r)
S0 1 FEO
ANA M:
10 100 110
N
(A) (A) B2
11 011 110
<B2>
MRMC
T1:AD7 AD0 (PCL), A15 A8 (H),ALE
IO / M 0
T2: RD 0, (PC) ,(AD7 AD0 ) M(H,L)
S1 1
T3:RD 1, , (Temp) (AD7 AD0 ),(A) (A) (Temp)
S0 0
10 1 0 1 S S S N
1 0 1 0 1 110 N
Note 1: In all exclusive OR ALP is all the flags are affected as per
standard rule expect AC & CY flags are cleared.
2. There is no explicit instruction to clear the accumulator to
zero however it is implicit is the statement XRAA. This means (A)
(A) + (A) ,the result will be 0000 0000 is the accumulator along with
dealing AC & CY flags.
7) ORA r (OR Register), this is an ALP statement. The macro RTL
implemented is,
(A) (A) U (r)
If is a single byte instruction the contend of the register r is
inclusive ORed with the contents of accumulator bit by bit and the
result is stored back into accumulator the operation code is,
10 110 S S S N
10 1 1 0 110 N
11 110 1 1 0
< B2 >
ANI 40
10 1 1 0 110 N
11 110 1 1 0
< B2 >
2f has no variations. The addressing mode is immediate
addressing. It requires too M/C cycle OFMC and MRMC of seven
states.
Lecture-24
13) RLC: This is an ALP statement. The macro RTL implemented is,
(A0+ 1) (A1) 0 = 0 to 6
(A0) (A7)
(CY) (A7)
The meaning of the instruction is not the left the content of the
accumulator by one bit the lower order bit & the CY flag are both set to the
value shifted out the high order bit position. Only the CY flag is affected.
The operation code is,
10 1 0 1 S S S N 074
The content of the accumulator is rotate right by one bit position as shown
In fig
A2 A0
CY
The high order bit & the Cy flag can both set to the value of shifted out
of the low order bit position only the Cy flag is affected the operation is
10 1 0 1 11 1 N is O Fm
(Ai + 1 ) (Ai) i = 0 to 6
(CY) (A7),
(A0) (CY)
The content of the accumulator is rotate left one position through the
CY flag. The low order bit is set equal to the CY flag. The CY flag is set to
the value shifted out of the A7 bit as shown in fig
CY A7 A0
Only the CY flag is affected the operation code is
10 1 0 1 11 1 N = 17H
If has no variations, the addressing mode is implied addressing mode.
Only one M/C cycle OFMC of 4 states is required.
16) RAR: (Rotate accumulator right through carry), this is an ALP statement
the macro RTL implemented is,
(Ai) (Ai + 1) i = 0 to 6
(CY) (A0),
(A7) (CY)
The content of the accumulator is rotate right one bit position through
the CY flag. The high order bit is set equal to the CY flag and The CY flag
is set to the value shift10 out of the A0 only the flag is affected.
CY A7 A0
The operation code is,
000 1 11 11 = (IF)H
This is a single byte instruction. The M/C cycles required is only one
OFMC- 4 the addressing mode is implied addressing mode.
000 1 11 11 N= 2FH
It is a single byte instruction & no variation. The addressing mode is
implied addressing mode requires one M/C- 4.
18) CMC: (complement carry), this is an ALP statement, and the macro RTL
implemented is,
(CY) ( )
00 11 11 11 = (3F)H
The carry flag is set to 1 and no others flags are affected, the operation
code is,
00 11 01 11 N= 3T4
JMP DDR:
This is an ALP statement DDR is the symbolic name given to the
16- bit address data available as the second & the third byte of the
instruction. JMP is the mnemonic for jump the meaning of the instruction is
load the PC with the 16- bit data available in the instruction itself so that he
next instruction is fetched cycle. This is a 3 byte instruction the instruction
formed being.
The macro
RTL implemented is
(PCH) < B3 >
(PCL) < B2 >
Conditions before & after the execution of JM addr instruction are
shown below.
The macro RTL flow is as shown below.
MC - 1
OFMC T1 : AD1 AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : instruction is decoded JMP = 1
MC - 2
MRMC T1 : AD1 AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (Z) (AD7- AD0)
S0 = 1
MC - 3
MRMC T1 : AD1 AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ =0 T2 : = 0, (PC) (Z ), (AD7- AD0) M(AB)
S1 = 1 T3 : = 1, (PCH) (AD7- AD0)
S0 = 1 W FEO =WZ+1 Wz pc wt
Thus, it requires three machine cycle OFMC, MRMC & MRMC and
total 10 states using a 2 MH3 internal clock it requires 5 sec. No variation
in this instruction. The addressing the mode in their case is immediate
addressing mode because the 16 bit address data is immediately in the
instruction itself to be loaded into the PC.
2. J cend ADDR: There are 8 variations for this instructions depending upon
the conditions to be tested. They are JNZ, JZ, JNC, JC, JPO, JPF, JP, and
JM. This is also an ALP statement. This is a 3 byte instruction the operation
code format is,
11 000 011 N
< B2 > N+1
N+2
< B3 >
The meaning of the instruction is illustrated in the flow chart
Y3Y2 N+2
X3X2X1X0
PC
Fig shows the condition existing just before the stand of instruction
cycle J cend ADDR the IC, b address in the PC just often the end of the
instruction cycle depends upon the condition to be tested PC will be loaded
with B3B2 if the given condition is TRUE, otherwise (PC) will go to (PC)
where (PC) shall be the address X3X2X1X0 which points to the operation
code 11 CCC 010. The micro RTL flow given below.
MC - 1
OFMC T1 : AD1 AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : J cond = 1
MC - 2
MRMC T1 : AD1 AD0 (PCL) , A15 A8 (PCH) , ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (Z) (AD7- AD0)
S0 = 1 if condition = true, go to MC-3 else (PC) (PC) + 1
MC - 3
MRMC T1 : AD1 AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 0 T2 : = 0, (PCL) (Z ), (AD7- AD0)
M(AB)
S1 = 1 T3 : = 1, (PCH) (AD7- AD0)
S0 = 1 W FEO =WZ+1 Wz pc wt
11 000 011 N = CD 4
< B2 > N+1
N+2
< B3 >
PC Z3Z2Z1Z0
Full
SP
The main RTL flow is
MC - 1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : CALL = 1
: (sp) (sp) - 1
MC - 2
MRMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (Z) (AD7- AD0)
S0 = 1
MC - 3
MRMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+ 1, (AD7- AD0)
M(AB)
S1 = 1 T3 : = 1, (W) (AD7- AD0)
S0 = 1
MC - 4
RMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, (AD7- AD0) (PCH),(SP) (SP)-1
S1 = 1 T3 : = 1, M(AB) (AD7- AD0) , (SP) (SP)-1
S0 = 1
MC - 5
NRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH), ALE =
IO/ =0 T2 : = 0, (AD7- AD0) (PCL),
S1 = 1 T3 : = 1, M(AB) (AD7- AD0) ,
S0 = 1
T1 : A15- A8 (W) , AD1 AD0 (Z) , ALE =
FEO T2 : = 0, 1 (PC) (WZ) +1,
11 CCC 10 0 N
N+1
< B2 > N+2
< B3 > N + 3 return address
MC - 4
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, (SP) (SP)-1 (AD7- AD0) (PCH),
S1 = 1 T3 : = 1, M(SP) (AD7- AD0) ,
S0 = 1
MC - 5
MWCMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, (AD7- AD0) (PCL),
S1 = 1 T3 : = 1, M(AB) (AD7- AD0) ,
S0 = 1
T1 : A15- A8 (W) , AD1 AD0 (Z) ,ALE
FEO T2 : (PC) (WZ) +1,
5) RET (Return):
This is an ALP statement, stands for RETURN. The meaning OS
return to the main program from the subroutine unconditionally, obviously
the instruction should be a part of the subroutine program. This is a single
byte instruction the operation code format is,
11 CCC 10 0 N = C9H
(PCL) M(SP)
(PCH) M[(sp) + 1]
(sp) (sp)+2
When this instruction is executed the 16 bit, address data available at
the top of the stack shall be loaded into the (PC) and stack print is
readjusted a that it again print to the top of the stack the content of the
memory location whose address is specified in register SP is moved to the
low order 8 bits of the memory location whose address is one more than the
content of register SP register is moved to the high order 8 bits of pc, the
content of the register SP is incremented by 2. 2f is for the used to set to it
that the proper RETURN ADDR is available correctly on the top of the stack
before asking the p to execute the RET instruction
MC - 2
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) , ALE =
IO/ = 0 T2 : = 0, (SP) (SP)+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (PCL) (AD7- AD0)
S0 = 1
MC - 3
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (PCH) ,ALE =
IO/ =0 T2 : = 0, (SP) (SP )+ 1, (AD7- AD0) M(AB)
S1 = 1 T3 : = 1, (CH) (AD7- AD0)
S0 = 1
Thus it requires 3m/c cycles and 10states, for 2MH3 internal clock the
time required is 5 sec, the address mode is register indirect.
MC - 1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : R cond = 1
MC - 3
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, (SP) (SP )+ 1, (AD7- AD0) M(AB)
S1 = 1 T3 : = 1, (PCH) (AD7- AD0)
S0 = 1
The high order 8 bits of the next instruction address are moved to the
memory location whose address is one less than the content of register SP.
The low order 8 bit of the next instruction address are moved to the memory
location whose the address is two less than the content of register SP. The
content of register sp is decremented by 2 control is transferred to the
instruction whose address is eight times the content of NNN.
MC - 1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 0 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : RST n = 1
MC - 2
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, (SP) (SP)+1, AD7- AD0 (PCH)
S1 = 1 T3 : = 1, M(A6) (AD7- AD0),(PCH) (00)
S0 = 1
MC - 3
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, AD7- AD0 (PCL)
S1 = 1 T3 : = 1, M(AB) (AD7- AD0),(PCL)(8 N)4
Thus 12 states are required for the execution of this instruction. One
important point while writing a subroutine program starting from the fixed
location as calculated.
Consider for example RST 5 & D 576.the corresponding starting
address of the subroutine are 0028 for RSTS, & 00304 for RST 6.recollect
that there is RST 5-5 interrupt control signal input at pin no 9 of the p this
also corresponding to an interrupt service routine starting from 00204. These
addresses are shown in fig.
The fig shows that there are only four bytes, possible for each
subroutine link and it is difficult to write subroutine here therefore, first byte
will be C3 (jump Instruction) and 2nd & 3rd bytes will be the address of same
memory locations which is the starting address of subroutine, this is known
as subroutine link address 4th byte is no operation.
8) PCHL: this is a single byte instruction the operation code is,
N=E94
11101001
There is no variation in this instruction. The macro RTL implemented is,
(PCL) (L) (PC) (H,L)
(PCH) (H)
The content of register (H) is merged to the (PCH) and content of
register (L)is merged to (PCL).the meaning of the instructions is jump to (H)
(L) location. Register indirect jump instruction. This is the only instruction
available in 8085 which allows the use to obtain a jump address from a
register. This instruction uses register addressing mode other jump
instruction use immediate reg indirect addressing mode.
This instruction is very useful in implanting select structure of the
software program. The means RTL flow is,
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 1 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : PCHL = 1
: (sp) (sp) -1
MC - 2
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH), ALE =
IO/ =0 T2 : = 0, (SP) (SP)-1, AD7- AD0 (rph)
S1 = 1 T3 : = 1, M(AB) (AD7- AD0)
S0 = 1
MC - 3
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) , ALE =
IO/ =0 T2 : = 0, AD7- AD0 (rpl)
S1 = 1 T3 : = 1, M(AB) (AD7- AD0)
Thus it required 12 states.
2. PUSH PSW (push processor status word):
The meaning of the instruction is save (push) the processor status
word on the top of the stack. The accumulator & flag register together form
a 16- bit word known as the processor status word (psw), ACC will occupy
the higher order 8 bits and flag register will occupy the lower order 8-bits in
PSW.
The operation code is
11110101N = (F5)H
The macro RTL implemented is
M (sp)-1 (A)
M (sp)-2 (PR)
(sp) (sp)-2
The content of the register A is moved to the memory location whose
address is one less than the register SP. The contents of flag register are
moved to the memory location whose address is two less than the content of
register SP. The content of the register SP is decremented by 2.2f requires 3-
M/C cycles and 12 states, the macro RTL flow is same as push rp the
addressing mode is register indirect.
3. The meaning of the instruction is pop (load) the content form the top of
the stack into register pair rp. The operation code is,
MC-1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 1 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : POP rp = 1
MC - 2
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, (SP) (SP)+1, AD7- AD0 M(AB)
S1 = 1 T3 : = 1, (rpl) M(AB)
S0 = 1
MC - 3
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH) ,ALE =
IO/ =0 T2 : = 0, (SP) (SP)+1, AD7- AD0 M(AB)
S1 = 1 T3 : = 1, (rpH) M(AB)
S0 = 1
It requires 3 m/c cycles and 10 states. The addressing mode is register
indirect addressing mode.
4) POP PSW: The meaning of the instruction is load the processor vector
word register from the top of the stack. The operation code format is,
1111 =F1H
0001
It has no variation. The macro RTL implemented is,
(FR) M (SP)
(A) M (SP+1)
(SP) (SP) +2
The content of the memory location pointed by SP is moved to the
flag register (i.e. to restore various condition flags). The content of the
memory location whose address is one move than the content of SP is
moved to register A. the content of SP is incremented by 2.
The micro RTL flow is same as Popup. It also requires 3 m/c cycles
and 10 states the addressing mode is register indirect. Flags affected are Z,
S, AC, P, and CY.
5) The meaning of the instruction is exchange the top of the stack with the
content of (H, L ) register pair. The macro RTL implemented is,
M (SP) (L)
M (SP+1) (H)
The content of register L is exchanged with the content of the memory
location whose address is specified by the content of SP. The content of
register H is exchanged with content the memory location whose address is
one more than the content of SP.
The operation code format is
11 100 011 =E3H
MC-1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) ,ALE =
IO/ = 1 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : XTHL = 1
MC - 2
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH), ALE =
IO/ =0 T2 : = 0, (SP) (SP)+1, AD7- AD0 M(AB)
S1 = 1 T3 : = 1, (Z) (AD7-AD0)
S0 = 1
MC - 3
MWRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH), ALE =
IO/ =0 T2 : = 0, AD7- AD0 (L), (SP) (SP)+1
S1 = 1 T3 : = 1, M(AB) (AD7-AD0),(L) (Z)
MC - 4
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH), ALE =
IO/ =0 T2 : = 0, AD7- AD0 M(AB)
S1 = 1 T3 : = 1, (Z) (AD7-AD0)
S0 = 0 or W
MC - 5
MRMC T1 : AD7- AD0 (SPL) , A15 A8 (SPH), ALE =
IO/ =0 T2 : = 0, (SP) (SP)-1, AD7- AD0 (H)
S1 = 0 T3 : = 1, M(AB) (AD7-AD0),(H) (Z),(SP)
(SP)-1
S0 = 1
Thus it requires 16 states and 5 m/c cycles flags affection.
(SPH) (L)
(SPH) (H)
The operation code format is
11 111 001 =E9H
MC-1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH), ALE =
IO/ = 1 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : SPHL = 1
T5 : (SPL) (L) (SPH) (H)
T5 : x
2f requires one m/c cycle and 6 states.
Lecture-27
M/C control instructions:
EI (Enable interrupts):
The interrupt system is enabled following the execution of the next
instruction when this instruction is executed, then INTE F/F is set so that all
the interrupts are enabled and 8083 A will recognize external interrupt
request except those that are masked.
The operation code format is
1111 1 0 11 =FBH
MC-1
OFMC T1 : AD7- AD0 (PCL) , A15 A8 (PCH) , ALE =
IO/ = 1 T2 : = 0, (PC) (PC )+1, AD7- AD0
M(AB)
S1 = 1 T3 : = 1, (IR) (AD7- AD0)
S0 = 1 T4 : EI = 1
When the SIM instruction is executed, the interrupt mask register not
changed.
(ii) RST 7.5 is edge sinister (LO). A pulse at the RST 7.5 always sets an
internal RST 7.45 F/F, even if the jump to the service routine is inhibited by
masking If interrupts are disabled at the time the RST 7.5 pulse occurs, this
input will still be recognized later since the RST 7.5 F/F has can be cleared
(or Reset) by keeping bit A4=1 when SIM is executed, this may be required
if we do not want to service an earlier RST 7.5 interrupted.
The RST 7.5 F/F is also cleared by a signal input or when the
CPU acknowledges a RST 7.5 interrupt. All three mask bit (A2, A1, A0) are
also set by its all vectored interrupt (except) are masked and therefore
disabled are masked and therefore disabled.
(iii) Load the SOD (serial output data) latch.
The SOD output of the 8085A shown the status of a 1-bit output port,
execution of the SIM instruction sets the output port content to that of A7
provided the serial output enable A6 is also
1. If SOE = A6=0, the contents of the output port is unaffected SOD is reset by
the input.
Using SOE & MSE properly one can use the SIM instruction is different
ways the format of Ace for SIM instruction is
Ace content before SIM
This instruction requires are m/c cycle of four states no flags affected.
E.g. (1) send a1 to the SOD output line. The following sequence of
instruction shall do the word.
MVI A, CO (1100 0000)
SIM:
(2) The following sequence of instruction shell unmask RST 6.5 interrupt
control signal input & mask all other after power on.
MVI A, OD (0000 1101)
SIM, EI:
RIM: (Read interrupt mask): Whenever their instruction is executed the
status of the mask F/F INTE F/F the SID input & if any interrupts are
pending is read into accumulation as follows.
The RIM instruction loads data into accumulation relating to
interrupts & the serial input. After RIM is executed the content of A are as
follows:
1) Current interrupt enables status for the RST 5.5, 6.5, 7.5 hardware interrupts
in A0 A1 & A2 bits (1= if mask disabled, 0 if they are enabled).
2) Current interrupt enable flag status in bit A3. (=1 interrupts enabled) except
immediately following a TRAP interrupt.
Following a TRAP interrupt (enables/ ) prior to the TRAP
interrupt.
This is useful to retrieve current interrupt since TRAP. This is important
since TRAP is a non mask able interrupt which can happen at any time.
3) Hardware interrupts pending. (Received but not serviced). On the RST 7.5,
6.5,& 5.5 line. A 1 at A6, A5, A4, respectively indicate that RST 7.5, 6.5 &
5.5 interrupts are pending.
4) Transfer the bit present at 8085s SID input to A7.
Apart from the CPU get the SID input, the RIM instruction is primarily used
to monitor interrupt status e.g.
a) Monitor whether or not an interrupt is pending without actually servicing it.
b) Check using IE properly if CPU is currently, servicing an interrupt.
c) By properly using RIM & SIM one can design any other prior structure. The
operation code is (20)4. 2f is a single byte instruction If requires 4 states.
MC 1 OFMC 4
MC 2 T1 = FEO
T2 = INTERRUPT MASK (A)
Lecture-28
UNSPECIFIED OP CODES OF THE 8085A
Examine the instruction set of 8085a, one finds that out of the 256
possible opcode with 2 bits, Intel announces only 246, there are no
announced instruction corresponding to the 10 missing opcode. User
have since reported that these missing opcode. The flags specified
by Intel are S, Z, AC, P, CY located in the flag register as
S Z X AC X P X CY
Users have reported that there are two more flag bits having same
useful meaning.
S Z X5 AC X P V CY
28 N
<B2> N+1
The meaning of the instruction in the contain of register pair (H, L) are
added to the immediate byte. The result is placed in register pair (D,
E) no condition flags are affected.
It requires three m/c cycles and 10 states. The addressing
mode is immediate & register addressing mode the second byte is
called offset.
5) LDSI: (Load (D, E) reg pain with SP flow immediately byte). The
macro RTL implements is
(D.E) (BP) + <B2>
This is a byte instruction the opcode format is
3S N
<B2> N+1
(SP)(SP)2
(PC)0040H
False is True
X5 = 0
(PC)(PC)f3 (PC1)<B>
(PCH)<B3>
IS
False X5=1 True
(PC)(PC)+3 (PCL)<B1>
(PCH)<B3>
1) Label field: The first field is the label field. A label is a symbol used to
represent an address that is not specified known on it is a name to be
field is usually ended with a colon.
2) Mnemonic field: This field contains the mnemonic for the instruction
to be performed sometimes mnemonics are referred to as operation
codes or opcode. It may consist of pseudo mnemonics.
3) Operand field: Operand field consists of operand and operands either
constants or variables with reference to the instruction in the
mnemonic field it may be any register, data, or address on which the
instruction is to be performed. Repenting upon the absent, may
contain one operand or two operands separated by a comma. A
comma is required between register initials or between register initial
and a data byte.
4) Comment field: A very important part of an any ALP in the comment
field. For most assemblers the comment field is started with a
semicolon. Comments do not become part of the machine program.
They are written for the reference of the user. If you write a program
without comment and set it aside for 6 months it may be very default
for you to understand the program again when you back to it. It may
even that someone else must have written it. Comments should be
written to explain in detail what each instruction or group of instruction
is doing. Comments should not just describe the mnemonic, but also
the function of the instruction in the particular routine. For best result,
write comments as if you trying to explain the program to someone
who initially knows nothing about the programs purpose. In addition
to the comments of a program or subroutine should start with a series
of comments describing what the program is supposed to do. The
staring comments should also include a list of parameter, registers
and memory location used.
given by
Fig(3)
Having written the macro RTL flow chart we can directly write ALP.
The preliminary ALP for fig -3 is shown in fig -4
NSUM: XRA A ; CLEAR ACCUMULATOR
MVI C, N ; INITIALIZE THE COUNTER WITH LAST NN
MOV B, A ; INITIALIZE N.N IN B TO ZEI
NEXT: INR B ; GENERATE NEXT N.N
ADD B ; OBTAIN RUNNING SOMINA
DCR C ; HAS ALL N.N ADDED?
JNZ NEXT ; NO, GO BACK TO GENERATE NEXT N.N
HLT ; YES
ORG 0100 H
At location 0100h [AL instruction]
END
EQU:
Symbolic names, which appear in assembly language programs as
labels, instructions mnemonics and operands are translated to binary
values by the assembles. As discussed in hand- assembly the labels
are assemblers location counter when entertained on the first pass of
the assembly. Instruction mnemonics have predefined values that the
assembler obtains from a table that is part of the assembler.
A symbolic operand can be a register name, an address or a data
constant. Register names have predefined values, all addresses
correspond to labels in
The program and their values are defined. Data constants, on the
other hand, are defined by the designer using an equate instruction
EQU defines symbolic used in the program. Equate assembler
directives usually appear as a group at the beginning of a program
and have the form.
Name EQU expression.
NAME stands for the symbolic name, the assemble evaluates the
expression and equates the symbolic name to it by placing the name
in its symbol table along with the value of the expression. Therefore,
whenever the name appears in the program, it is replaced by the
value the expression in the equate pseudo instruvtion.eg
COUNT EQU 0100 H
Note the symbolic name is not followed by a adan and is not a label
even though it appears in the label field. The symbolic name in are
equate statement cannot be used in another nor can it be used as the
label of another instruction. That is, the name in an equate directive
cannot be redefined. If its value is changed, the equate assemble
directive must be changed and the program reassembled.
4) SET: SET is simi8lar to EQU assemble directive this directive also
assigns a value to the name associated it. However, the same
symbol can be redefined by another SET statement late in the
program. Thus, mere that one SET instructio0ns can have the same
name the SET assembles directive has the form.
Name set expression.
5). DS: Another pheudo instructions, the define storage, reserves or
allocates read/write memory locations for storage of temporary data.
The first of the locations allocated can be referred to by an optional
symbolic label. The define storage instruction has the form
Opt label: DS expression.
A number of bytes of memory equal to the value of the expression
are reserved. However, no assumptions can be made above the
initial values of the data in these reserves locations.re the assembler
does not initialize the contents of these locations in anyway.
(e.g. BUFFER: DS 96 tells the assembler to reserve 96 memory
locations for storage when it assembles the program the address of
the first location is BU*FFER. (Buffer to BUFFER +96-1) such a
buffer is usually written and read sequentially using reg indirect
addressing. 2f has a symbolic name is used with the DS pseudo
instructions, it has the value of the address of the first reserved
location.eg to establish two byte storage registers in C/N memory
with the names TEMP 1 & TEMP 2,the instruction is written.
TEMP 1: DS 1
TEMP 2: DS 2
During the first pass, the assembler assigns the values of its location
counter to TEMP 1& TEMP 2,respectively and thus as address is
associated with each Label. Instructions in the program can read a
write these locations using memory reference instructions such as
STA TEMP 1or LDA TEMP 2.
A memory buffer is a collection of consecutive memory locations
also used to store data temporarily.
6). DB: When a table of foxed data values is required, memory must
also be allocated. However, unlike the DS, each memory l0ocations
must have a defined value that is assembled into it. The pseudo
instructions for this is define, DB.
Opt name: DB list
List refers either to one or more arithmetic or logic expressions that
evaluate to 8 bit data quantities or to strings of character enclosed in
quotes that the assembler replaces with their equivalent ASCII
representations. Assembled bytes of data are stored in successive
memory location until the list is exhausted.eg DB 07A H stores 7A H
in meaning location right after the preceding instruction. E.g. DB
JOMA stores 4A,4F,48 & 4E in the four successive memory
locations to represent the string of ASC II characters.
7) DW: Define war instruction is similar to define byte pseudo0
instruction.
Opt name: DW list
The only difference between the DB & DW is that expression in this
define ward list is evaluated to 16-bit quantity and stored as 2-bytes.2f
is stored with the low order bytesi9n the lower memory locations and
the high order byte in the next higher one .this is consistent with the
convention for storing 16- bit quantities in 8085 A systems.
Macros:
Sometimes it is required that same set of instructions are to be
repeated again & again. One way to simplify the problem is the care
of subroutine. The other way is the use of macros. The assemblers
which have the capability to process macro instructions are called
macro assemblers. The assemblers are designed such that the
programmer need to write set of instruction once and then refer it
many times as desired.
A macro instruction is a single instruction that the macro assemble
replaces with a group of instruction whenever it applies in an
assembly language program. The macro instruction and the
instruction that replace it are defined by the system design only once
in the program. Macros are useful when a small group of instruction
must be repeated several times in a program, with only minor or no
changes in each repetition.
The use of macro in ALP entails three groups:
1) The macro definition
2) The macro reference
3) The macro expansion.
The macro definition defines the group of instruction equivalent
reference is the use of the macro instruction as an instruction in the
program. A macro expansion is the replacement of the instruction
defined be its equivalent.
The first two steps are caused out by the system designer and the
third by the macro assembler.
The macro definition has the following format:
LABEL CODE (Mnemonic) OPERAND
Name MACRO List
[Macro body]
ENDM
Name stands for the name of the macro that appears in the label
field of the macro definition. A list of dummy parameters may be
specified as List, and, if so, these parameters also appear in the
macro body. The macro body is the sequence of assembly language
instructions the replace the macro reference into program when
assembled. The macro definition produces no object code
(hexadecimal number); it simply indicates to the assembler what
instructions are represented by the macro name.
Example:
Consider the use of a macro involving a large amount of indirect
addressing. An indirect addressing input capability is provided by the
two instructions:
LHLDaddr
MOV r, M
This sequence can be written as a macro named LDIND; with a
macro definition of
LDIND MACRO REG, ADDR
LHLD ADDR
MOV REG, M
ENDM
To have the macro body appear at any given point in the program
requires a macro reference. This format is identical to that of an
assembly language instruction.
Label code (Mnemonic) operand optional label name parameters list
Name is the label by which the macro is referenced or called.
The following macro instructions load reg c indirectly through the
address PRT
LDIND C, PTR
143D = 8FH.
So in FIG-11 the no N to be loaded in to the D register is off to
introduce m sec delay in the main pregame
Example 4: Modify examples -3 to introduce k m ser delay
One way to solve the problem of fig-16 is to repeat the flow chart of
fig-15 every time loading the (B.C) pain in the appropriate constant
k, this is empery and occupies reminder amount of memory space
unnecessarily , we can therefore write a subroutine program for k m
esc time delay starting from the symbolic address KDLEY, while
writing the subtracting it shall be assumed that values k is available in
the (B . c) register pain, this means that the value of k must be loaded
in to the (B.C) pain in the main programmed before calling the
subtraction this is known As the input to subtraction, or parameter
passing from the main programmed, the second point has to be
noted while written the subroutine , contents of all the register made.
Use of in the subtraction programmed should not be destroyed they
should be saved on the top of stack introduce the necessary delay
through software delay restore the contents of registers by pop
operations, and then RETURN to the main programmed the
subtraction is incorporation the above details is shown in fig-17.
KDLEY: PUSH B
PUSH D
PUSH PSW
MVI D, 8CH
DCR D
JNZ LPI
DCX B
MOV A, B
ORA C
JNZ LP2
POP RET
fig-17
Lecture-32
Problem 1:
An output port with an 8-bit register latch driver is interfaced
using isolated I/O PORT address 30H. This register latch driver o/p
driver o LED (0-0ff, 1-on) write a software programmed in MLP to
simulate a 8-bit ring counter as the PORT 30h. Ring counter
Must go from one state to the nest in 10 sec k m sec delay
subroutine programmed is available to you from the starting
address, 0430h, write your programmed from 0800h,
Note: For 1 T.T.T load when at is high current dram is 40 u amp
called sourcing currant when logical 0 wits then Io1 = -10ma (sinking
current) most of the J.C chip can take 10 T.T.L load,
CALLS : USMUL
DESTRCYS : (H, L)
Algorithm: SUM
POLSM: POSH PSW ; SAVE PROCESSOR STATOS
WORD
POSH D ; SAVE (D, E) PAIR
POSH B ; SAVE (B, C) PAIR
LXI D, 0000H; INITIALIZE RONNING SUM
IN PRTX ; INPUT X VALUE PROMPRTX IN
10ACC
NEXT: LHLD CLP ; LOAD (H, L) WITH CLP
MOV.C, M ; BRING CORRENT COEFF INTOC
INX H ; (H, L) POINTS TO NEXT COEFF.
SHLD CLP ; SAVE THE NEXT COFEE ADDR IN
CLP
MOV L, C ; BRING CURRENT COEFF IN (L)
MVI H, 004 ; EXTEND THE COEFF TO
RONNING
SUM, RUNNING SUM IS NOW IN
(H,L)
XCHG ; CURRENT MULTIPLICAND IS NOW
IN
PROPER POSITION
CALL USMUL; CURRENT PRODUCT IS IN (H,L)
PAIR
XCHG ; UPDATE THE RUNNING SUM IN
(DF)
DCR B ; ALL PONE
JNA NEXT ; NO
LHLD CLP ; (H, L) PAIR NOW POINTS TO ao
MOV L, M ; BRING ao TO (L)
MVI H, OOH ; EXTEND IT TO 16-BITS
DAD D ; (H, L) NOW CONTAINS TOTAL
SUM
POP B
POP D
POP PSW
RET
EXAMPLE; It is desired to divide a 16 bit number in locations 2000
and 2001 (HIGH BXTE IN 2001) by an 8-bit number is location 2002
using the division algorithm
a) Flowchart the problem
b) Convert the flowchart to an 8085 MLP
2000 DATA
2001 DATA
2002 DATA
2003 DATA
2004 MVI D, 00 ; INITIALIZE D= 00
2006 LIX H, 2000 ;( H,L) points to 20004
2009 MOV A, M, LOWER BYSE OF DIVIDEND IN
(A)
200A LXI 4, 2002 ; (4, U POINT TO
2002H
200D ANA A To CLEAR THE or
(Dividend L-
200F SBB M
Davison-L)
200F LXI M, 2000H same the serum of
subtract in 2000h
2012 MOV M, A
2013 LXI H, 2001H, (Dividend h-Divisor CY)
2016 MOV A, M save it is 200 TH
2019 LIX H, 2000H
201A SBBM
201 B LIX H, 2001H
201E MOV M,A
201F JP 2026
2022 LIX H, 2000 (A) (Dividend L)
2025 MOVA, M (M) (Divison L)
2026 LXI H, 2002 A (A)-1(M)
2029 ADD M
202A MOV D, A (E) A
202B HLT
202C INRD
202D JMP 2006 - increment D.
00001000/0000000101
0101 0001 0000
0011 000000011 0010
0010/0000 00100
0000
Lecture-33
INPUT/OUTPUT Techniques
Along with or
Or
Only the IN and OUT instructions provide data transfer for
isolated I/O IN and OUT each require three m/c cycles for execution
the first is of course, an OPCODE FETCH. The second is MEMORY
READ during which the 8-bit port address is transferred from memory
to the p and placed in both the W & Z temporary registers and the
third is either an I/O READ on I/O WRITE machine cycle during which
the actual data transfer from or to the I/O device occurs.
During the I/O READ and I/O WRITE m/c cycles, the 8-bit port
address, in W & Z is outputted from the 8085 A on address data bus
lines AD7-AD0 and on address lines AD15-AD8.the read and
write control strobes from the 8085 A specify the exact time at
which an input ports tri-state buffer is enabled to drive the data bus
or the exact time at which an output port the data placed on the data
bus by the p respectively.
For input ports, external decoding logic combines IO/ ,
and the port address and generates a unique input device select
pulse for each input port. The pulse occurs only during the I/O READ
m/c cycle of an in interaction that address the specific port. The input
device select pulse enables the input ports tri-state buffer.2f through
design or program error. The tri-state buffers of two or more ports or
a port and a memory device are simultaneously enabled both drive
the data bus and cause bus contention.
For output operation, external decoding logic combines ,
IO/ and the port address and generates a unique output device
select pulse occurs only during the I/O WRITE m/c cycle of an OUT
instruction that addresses the port and decks the output ports
register. Typically each output device select pulse checks a single
output port; however it is possible that more than one port are
selected simultaneously.
The design of device selection logic varies, depending on how
many I/O devices are required in a system. 2f only a single input port
and a single output port are required address decoding is
unnecessary. The I/ control signal is simply combined with to
inverted and NANDed with A4 and IO/ an active low device select
pulse is generated. This pulse is connected to the active
low enable of a tri-state buffer and determines when the buffer drive
the bus.2f the IC tri-state buffer has multiple inputs, the internal logic
of the tri-state buffer itself may be sufficient, and no external gates
are required.
Example 3:
In example 1 & 2 we have used SSI chips for obtaining the
PORT select signal, we can also use MSI chips to simplify the
decoding circuitry fig-9 gives the decoding circuitry for inputting 8-bit
data from 8-toggle switches involutes I/O, PORT address allocated
body AC to AF it with ACH as primary address and AF H as foil back
address, we have used 8205 (3 fine to 8-bit line decoder.
The advantage of fig-7 can be realized when we have more than one
port to select because a maxm of 8 chip select signals, can be
generated using the same decoding circuitry of fig-7.
Lecture-36
Memory Mapped I/O :
In this cases the I/O devices are not given separate addresses
other than memory i.e. 0000 to FFFF.(64k).but part of the space is
reserved for I/O devices. The advantage is any instruction that
references memory can also transfer data between an I/O device and
the ,as long as the I/O port is assigned to the memory address
space rather than to the I/O address space. The register associated
with the I/O port is simply treated as memory location register.
Consider an example in which address bit A15 designates
whether instructions reference memory or an I/O device.2f A15= 0, a
memory register is addressed; If A15= 1, than a memory mapped I/O
device is address .this assignment elevates the first 32kbytess of
memory address space to memory and second 32k to memory
mapped I/O devices. External logic generates devices select pulses
for memory mapped I/O only when = 0, the appropriate
address is on the address low and a or strobe occurs.
Input and output transfer using memory mapped I/O are not
limited to the accumulator. For example, same of 8085 A instructions
that can be used for input from memory mapped I/O ports.
MOV r, m move the connects of input port whose address is
available in (H,L) reg pair to any internal register.
LDA addr load the acc with the content of the input port whose
address is available as a second and third byte of the instruction.
Other instructions include, ANA M, ADD M, 1HD add (input from two
ports and store the contents is reg pair (L) and (H) ADD M and ANA
M provide input data transfer and computation in a single instruction.
same instruction that out the data from memory mapped ports are
MOV M,r
STA addr
MVI M, data
SHLD addr
LHLD and SHLD carry out 16- bit I/O transfers with single instructions
which reduce program executive time considerably. The price paid for
this added capability is a reduction in directly addressable main
memory and the necessity of decoding a 16- bit rather than an 8-bit
address.
When a microprocessor puts out an address and generates a
control strobe for a memory read, it has no way of determining
whether the device that responds with data is a memory device or an
I/O device; nor does it care. If only requires that the devices that
respond does so with in the allowable access time or uses the
READY line to request a sufficient number of WAIT states. The some
of true when a executives a write to memory.2f supplies an
address data, and a write strobe and continues its operations,
external logic determines whether memory, I/O or anything at all
receives the data transferred.
Example- 1:
In all the examples discussed in chapter 34, we have interfaced, an
I/O device using isolated I/O structure. Now let is interface the same
device using memory mapped I/O structure memory space allocated
for the memory location from A000 H to A0FF H has been allocated
to this device, the decoding circuitry using 8205 decoder and buffer is
shown in figure below:.
Example-2:
We shall now take up a problem which involves ROM, RWM; input
devices
Design a CPU, PCB for a process control application which requires
the following,
1) 8085 A CPU whit 8212 latch.
2) 8k byte ROM consisting of two 4k byte 2732 ROMs.
3) 4k RWM consisting of two 6116 (each K x 8)
4) Two input devices connected through input ports.
5) Two output devices connected through two output ports.
6) A minimum of 32k byte memory space must be open for
further explain.
Use memory mapped I/O structure to design interfacing circuitry. Use
Fold back principles to simplify device circuitry,
2732 4 k 8 ROM 8K 8
6116 2 k 8 RWR 8K 8
Two Input Devices 8K
Two Output Devices 8K
The memory map for this problem is shown in figure.
A15A14A13A12 A11---- A0 Control Signals Address
0 0 0 0 0------0 CSROM0 0000H to 0FFFH
0 0 0 0 1------1
0 0 0 1 0------0 CSROM1 1000H to 1FFFH
0 0 0 1 1------1
0 0 1 0 0------0 CSRAM0 2000H to 2FFFH
0 0 1 0 1------1
0 0 1 1 0------0 CSRAM1 3000H to 3FFFH
0 0 1 1 1------1
0 1 0 0 0------0 IDSP1 4000H to 4FFFH
0 1 0 0 1------1
0 1 0 1 0------0 IDSP2 5000H to 5FFFH
0 1 0 1 1------1
0 1 1 0 0------0 ODSP1 6000H to 6FFFH
0 1 1 0 1------1
0 1 1 1 0------0 ODSP2 7000H to 7FFFH
0 1 1 1 1------1
=160 the voltage drop across the LED and 7447 are not exactly
predicable and the exact current through the LED is not critical as
long as we dont exceed its maximum rating. Therefore a standard
value of 150 is reasonable.
The circuit designed is suitable for driving just one or two LED
digits. However there are problems it we want to display 6 digits. The
first problem is power consumption for worst case calculation,
assume all six digits are display 8 so all seven segment are lit. Seven
augment times 20mA per segment gives a current of 140mA per digit
multiplying these 6 diets given a total current do 840mA. For the
static approach is that each display digit required a separate 7447
decode each of which uses another 12Ma. Therefore, the current
required by the decoders and LED display might be several times the
current required by the rest of the circuitry in the instrument.
To solve this problem of static display approach, we use a
multiplexing technique. The circuit for six digit only one 7447 bias
used and the segment output of the 7447 are the digits. The chip
select of all six digits are connected to six PNP transistors. The PNP
transistor in series with common anode is driven from another port.
The p first output the BCD code for digit 1 to 7447. The 7447
output the corresponding seven segment code on the segment bus
lines. The transistor connect to digit 1 is then turned on by outputting
a low to that pit of port A (a low turns on a PNP transistor). All other
bits are made high so other digits are in off state. After few ms digit 1
is turned off by outputting all high to port A. The BCD code for digit 2
is then input to the 7447 on port B and a word to turn on digit 2 is
output on port A. this process is repeated until all of the digits have
last digit in the display bus been turned ON , the cycle is repeated
starting with first digit. Each digit is turned or ON refreshed at a
frequency called the refresh rate. If a digit is refreshed at higher rate
then it appears to the human eye to be constantly ON. The minimum
practical refresh rate is unusually 100Hz for N digits refreshed at the
max ON time tD for each digit is
=
Let the digits to be displayed are stored in memory location starting
from DIGDI5 5.
** LXIH, DIDIS 5
MVI Bxx011111
MVIC, 06(IFH)
* XRA A
CMA
OUT port A
MOV A,M
OUT port B
MOV A,B
OUT PORT A
RAR
MOV,A
DCR H
CALL MS DELAY
DCR C
JNZ *
JMP * *
A disadvantage of the software multi playing approach is that it puts
an additional burden an the CPU. Also, if CPU gets involved in doing
sane length task which cannot be interrupted to refresh the display,
only one digit of the display will be left on.
Lecture-38
CPU Initiated Conditional I/O Transfer
In conditional data transfer, execution of the I/O instruction
transferring the data is conditioned on the I/O device being ready for
the data transfer readiness is determined by an unconditional transfer
of information from the I/O device to the that proceeds state of the
I/O device hardware often 1 or 2 indicate the status of an I/O device.
A single bit of status information indicates when a single output port
has information available for input or when a single output port is
ready to receive information. The software that tests the status flag
increases the time associated with the I/O operation; the additional
time is the I/O overhead.
In the above discussions, we have interfaced the ADC directly & with
the bus. It is passable however to interface the ADC with the bus
through programmable peripheral interface support chip.
Lecture-39
INTERRUPT I/O TRANSFER
The time that elapses between the occurrence of the interrupt and the
beginning of the execution of the interrupt handling subroutine is the
response time, the sum of the times of steps (1) through (4)the
difference between the total time that the p is interrupted and the
service subroutine is referred to as overhead interrupt structures with
zero overhead allow greater throughput.
TRAP:
TRAP is a nonmaskable vectored interrupt.2f can interrupt the
p once the power is on. Most p interrupt input are level sensitive
however, some are edge sensitive and others are both edge and
level sensitive, the TRAP input is both edge sensitive and level
sensitive interrupt. 2f means that TRAP make a low to high trisection
and remain high until it is acknowledged. The positive edge of the
TRAP signal will set the D flip flop .because of the AND gate,
however the final TRAP also depends on a sustained high level
TRAP input. This is why the TRAP is both edge and level sensitive
this also avoids false triggering caused by noise and transients.
RST (internal)
M [(SP)-1] (PCH)
M [(SP)-2] (PCL)
(SP) (SP)-2
(PC) restart address
- Chip selected
- Read input
- Write input
A0 A1 Port Address
VCC - +5v
GND - Ground
The block diagram is shown below:
Functional Description:
This support chip is a general purpose I/O component to interface
peripheral equipment to the microcomputer system bus. It is
programmed by the system software so that normally no external
logic is necessary to interface peripheral devices or structures.
Chip Select:
A low on this input selects the chip and enables the communication
between the 8255 A & the CPU. It is connected to the output of
address decode circuitry to select the device when it (Read). A
low on this input enables the 8255 to send the data or status
information to the CPU on the data bus.
(Write):
A low on this input pin enables the CPU to write data or control words
into the 8255 A.
PORTs A, B and C:
The 8255A contains three 8-bit ports (A, B and C). All can be
configured in a variety of functional characteristic by the system
software.
PORTA:
One 8-bit data output latch/buffer and one 8-bit data input latch.
PORT B:
One 8-bit data output latch/buffer and one 8-bit data input buffer.
PORT C:
One 8-bit data output latch/buffer and one 8-bit data input buffer (no
latch for input). This port can be divided into two 4-bit ports under the
mode control. Each 4-bit port contains a 4-bit latch and it can be used
for the control signal outputs and status signals inputs in conjunction
with ports A and B.
Group A & Group B control:
The functional configuration of each port is programmed by the
system software. The control words outputted by the CPU configure
the associated ports of the each of the two groups. Each control block
accepts command from Read/Write content logic receives control
words from the internal data bus and issues proper commands to its
associated ports.
Control Group A Port A & Port C upper
Control Group B Port B & Port C lower
The control word register can only be written into No read operation if
the control word register is allowed.
Operation Description:
Mode selection:
There are three basic modes of operation that can be selected by the
system software.
Mode 0: Basic Input/output
Mode 1: Strobes Input/output
Mode 2: Bi-direction bus.
When the reset input goes HIGH all poets are set to mode0 as input
which means all 24 lines are in high impedance state and can be
used as normal input. After the reset is removed the 8255A remains
in the input mode with no additional initialization. During the execution
of the program any of the other modes may be selected using a
single output instruction.
The modes for PORT A & PORT B can be separately defined, while
PORT C is divided into two portions as required by the PORT A and
PORT B definitions. The ports are thus divided into two groups Group
A & Group B. All the output register, including the status flip-flop will
be reset whenever the mode is changed. Modes of the two group
may be combined for any desired I/O operation e.g. Group A in mode
1 and group B in mode 0.
The basic mode definitions with bus interface and the mode definition
format are given in fig (a) & (b),
Lecture-43
Intel 8255A: Programming and Operating Modes
Example:
Configure 8255 A in following I/O mode.
PORT A; Input; POET B: output
PCU output; PCL: Input
The control word with I/O modes as mode0 will be
1 00 1 00 012 = 91H
The control word will be outputted to control word register having add
03H.The relevant instruction will be follows:
MVI A, 91H
OUT 03H
For the above example, set bit PC0 High through bit set/reset. Note
PCU is configured in output mode. Only the bit of the PORT C,
configured in output mode can be set/reset. The relevant control word
will be 0XXX 110 1 = 0DH. The instructions to SET the port bit PC1
will be
MVI A, 0DH
OUT 03H
Operating Modes:
The output and input ports of the two systems, acting as data lines,
are connected. The OBF of system 1 is connected to STB of system
2. The IBF of system 2 is connected to ACK of system 1 through
inverter. The interrupt outputs are connected to any interrupt of the
system. Here, they are connected to RST7.5.
The flow charts for data transfer in this manner are given below:
The waveforms for during data transfer are shown in figure below:
Lecture-45
OUTPUT operation
PC7: output buffer full PORT A.
The output will go low to indicate that the CPU has written data
lim
out to specified port. The will be set by the rising edge of
input and reset by input being low.
PC7: Acknowledge port A
A low on this input informs the 8255, the data from port A has been
accepted. The difference between in mode 1& mode 2 is that
in mode 2 the output of the PORT A is normally in a tri-state
condition, so the signal enables the output buffer of PORT A in
addition to indicating that the external device has accepted the PORT
A data.
INTE F/F 1:
The interrupt enable INTE f/f associated with OBF. It is controlled by
bit set/reset of PC6.
Input operation:
PC4:
Input strobe for PORT A. A low on this input loads data into the input
latch.
PC5: IBFA
Input is full PORT A. A high in this output indicate that data has been
loaded into the input latch.
INTEL 2:
(The interrupt enable INTE f/f associated with IBF). It is controlled by
bit set/reset of PC4.
PC3 INTRA: Interrupt request port A
A high on this output can be used to interrupt the CPU for both input
output operations. When PC6 is set, this signal indicates that the data
written into port A by the CPU has been accepted by the external
device. When PC4 is set this signal indicates that the data has been
written into PORT A by an external device. By proper control of
PC4&PC6 bits an interrupt driven bidirectional 8-bit data bus between
the CPU& a peripheral device or even another CPU can be
established.
The timing diagram is shown below:
Special mode combination consideration:
There are several combinations of modes when not all of the
bits in port C are used foe control as status. The remaining bits can
be used as follows:
If programmed as inputs. All the input lines can be accessed
during a normal PORT C read. If programmed as outputs. Bits is
upper (PC3-PC0) must be individually accessed using the bit
set/reset function. Bits in a lower (PC3-PC0) can be accessed using
the bit set/reset function or accessed as a three some by writing into
PORT C.
Reading PORT C status:
In mode 0 port C transfers data to or from the peripheral
device. When the 8255 is programmed to function in mode 1 or 2,
ports C generates or accept handshaking signals with the peripheral
device. Reading the contents of PORT C allows the programmer to
test or verify the status of each peripheral device and change the
program flow accordingly. There is no special instruction to read the
status information from port C. A normal read operation of PORT C is
executed to perform this function.
Mode 1 Status word
Input configuration
I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB
Group A Group B
Output configuration
INTEA I/O I/O INTRA INTEB INTRB
Group A Group B
Group A Group B
Lecture-46
INTEL 8253: Programmable Timer
0 1 0 0 0 Load counter 0
0 1 0 0 1 Load counter 1
0 1 0 1 0 Load counter 2
0 1 0 1 1 Write mode word
0 0 1 0 0 Read TM0
0 0 1 0 1 Read TM1
0 0 1 1 0 Read TM2
0 0 1 1 1 No- operation 3- state
1 X X X X Disable -- state
0 1 1 X X No- operation 3- state
Control word register:
It is selected when A0 and A1 re 11. It the accepts information from
the data bus buffer and stores it in a register. The information stored
in then register controls the operation mode of each counter,
selection of binary or BCD counting and the loading of each counting
and the loading of each count register. This register can be written
into, no read operation of this content is available.
Counters:
Each of the times has three pins associated with it. These are CLK
(CLK) the gate (GATE) and the output (OUT).
CLK:
This clock input pin provides 16-bit times with the signal to causes the
times to decrement maxm clock input is 2.6MHz. Note that the
counters operate at the negative edge (H1 to L0) of this clock input. If
the signal on this pin is generated by a fixed fq oscillator then the
user has implemented a standard timer. If the input signal is a string
of randomly occurring pulses, then it is called implementation of a
counter.
GATE:
The gate input pin is used to initiate or enable counting. The exact
effect of the gate signal depends on which of the six modes of
operation is chosen.
OUTPUT:
The output pin provides an output from the timer. It actual use
depends on the mode of operation of the timer. The counter can be
read in the fly without inhibiting gate pulse or clock input.
Lecture-47
System Interface:
To interface 8253 with 8085, signal is to be generated.
Whenever , chip is selected and depending upon A1, A0 one of
the internal register is enabled. Since in isolated I/O mapped
interfacing, IN & OUT instructions are used, therefore address is
duplicated.
A15 - A8 = A7 - A0
Since A1 A0 select the internal register, these bits are not used to
generate . Again let us consider, A15 A11 be 000100. Therefore,
the address for timer 0 would be 0001x00 i.e either 10H or 14H
Similarly, counter 1 address = 11H or 15H
Counter 2 address = 12H or 16H
Command word register address = 13H or 17H
SC1 & SC0 These bits indicate whether the control word is
intended for counter , or .
SC1 SC0
0 0 Select counter 0
0 1 Select counter 1
1 0 Select counter 2
1 1 illegal
RL1, RL0:
Each of the 8253s counters has 16 bits. Since they are accessed via
a 8-bit data bus, two spate read or write operations are required to
completely access one counter. The 8253 allows the user a
substantial degree of freedom in this regard. The various choices are
decided by the values of RL1 and RL0 as shown below:
RL1 RL0
0 0 Counter latching operation
0 1 Read/ Load least significant byte only
1 0 Read/ Load most significant byte only
1 1 Read/ Load least significant byte first, then
most significant byte.
If RL1=RL0=0 is programmed, the four lower order bits ( M2, M1, M2,
BCD) are dont cares.
Modes of operation:
Each of the three counters of 8253 can be programmed to operate in
six modes of operation to produce the desired output. Each timer
requires a clock input. The counters are negative edge triggered
down counter is whenever there is H1 L0 transition at the CLK
input, the count value is decremented by 1. The down counting is
controlled by the gate. The output pin can be used as an interrupt
request signal in the interrupt related modes.
Counter Loading:
The counter register is not loaded until the output value written is
followed by a rising edge and a following edge of the clock input to
the counter.
Mode0: Interrupt on terminal count
The output of the counter will go low when mode 0 has been
programmed. After the count is loaded the counter will remain low. If
the gate is low the counting is disabled the counter will start down
counting as soon as both bytes have been loaded and the gate is
mode HIGH. The output remains zero until count value reaches 0.
When the terminal count is reached (count value =0) the output will
go high and remains high until the selected counter is reloaded with
the mode or a new count value the mode is loaded. After the counter
has reached zero it will continue to count down from FFFF value but
will not change the output signal.
Inputting GATE=0; disables the counter. The count value stays frozen
if GATE goes low during counting. i.e. the counter stops counting .
Counting resumes from the from frozen value. When GATE returns to
1.
A+B =4
The count value may be changed at any instant even when the
counting operation is going on. Loading a new count value essentially
restart the counter with this new value. Note that if the counter value
to be loaded is 8 bits the effect of loading the new count value is
immediately. If the count value to be loaded is 16- bits the counter
stops counting after the first byte is loaded and resumes counting
only after the second byte is loaded.
Expect for mode0 in all other modes:
i) Retriggering of gate will cause the counter to reset to full count
and start down counting.
ii) The output will be high initially.
Lecture-48
Mode1 programmable one shot:
In this mode, counter acts as a retrigger able, programmable one
shot programming this mode sets the output high. Whenever there is
a rising edge at the gate, the counter starts down counting. The
output of the counter goes low and remains low during down
counting. When terminal count is reached, the output goes high.
Therefore, the output is low for the no. Of clock pulses whose value is
loaded in counter.
If a new count value is lowed while the output is low, it will not affect
the period of one shot pulse until the succeeding trigger. The one
shot is retriggerable, hence the output will remain low for the full
count value after any rising edge of the gate input.
Mode 2 Rate generator or divide by N counter:
This mode of operation provides a device by N- counter of the
counter is loaded initially with N count value. After loading the counter
and triggering it, the output will be high till the last one period (i.e. the
output will be high for (N-1) clock pulses and then it will go low for
one cycle of input clock and then return HIGH and the count value
(W) is automatically reloaded into the counter. Once again, the OUT
stay high for (N-1) clock pulses before going low for one clock pulse.
Thus the period from one output pulse to the next equal the number
of input in the count register. If the count register is reloaded between
the output pulses the present period will not be affected but the
subsequent period will reflect the new value. The gate input can be
used to control the counter. If the gate is low, the output will be HIGH
and no counting will be performed. When GATE input goes L0 H1,
the counter will start counting from the initial value and GATE=1,
enables counting. Thus this gate can be used by external hardware to
synchronize the counting.
Example:
Configures timer / counter No.1 in mode 0 and load it with 2 msec
period at 1.5MHz clock frequency.
2ms at 1.5MHz = 3000 cycles
= 0BBS H
Therefore, CW will be
(01 11 00 00)2 = 70 H
The necessary instructions for loading the count value are
MVI A, 70
OUT 13
MVI A, 08
OUT 11
MVI A, 0B
OUT 11
Read the counter 1 on the fly and store the value in (B, C) pair
CW (01 00 XX XX) = 40H
The necessary statements are,
MVI A, 40H
OUT 13H
IN 11
MOV C. A
IN 11
MOV B, A
INTEL 8254:
This chip also consists of 3- 16-bit down counters. Each
counter is software in different modes. Each counter has a clock
input, a gate control input and an output. The maxm clock input is
10MHz. This chip is identified to 8253 in all respect (pin configuration
and modes of operation) except the read function.
All counter in an 8253/8254 have latches on their outputs.
Reading the counter means actually reading the data on the output of
these latches. These latches are normally enabled during counting so
that the latch outputs just follow the counter outputs. If we read, the
count value during counting, the count may change between reading
the LSB&MSb. There are three ways to read the count value.
The first is to stop the counting by inhibiting the clock signal or
making the gate input low with external hardware. The counting is
then stopped. There method has the disadvantages that it requires
external hardware.
The second way of reading a stable value from a counter is to
latch the current count with a counter latch command, and then read
the latched count. A counter is latched a control word to the control
register. A counter latch command is specified by making the RW1 &
RW0 bits both0. The SC1 & SC0 bits specify which counter we want
to latch. The lower 4 bits of the control word are dont cares. When a
counter latch command is sent, the latched count is held until it is
read. When the count is read from the latches, the counter outputs
return to following the counter outputs.
The third method of reading a stable count from a counter is to
latch the count with a read back command. This command is
available only in 8254, but not in 8253.
The read-back command allows the user to check the count
value, programmed mode, and current state of the out pin and Null
count flag of the selected counter. The command is written into the
control word register and has the format shown in fig,
D7 D6 D5 D4 D3 D2 D1 D0
1 1 CNT2 CNT1 CHT0 0
Lecture-50
Priority Interrupt Controller:
In general in any application the data transfer between CPU &
I/O devices is interrupt driven. The number of interrupts in any
application depends upon the requirement.
In reality, these interrupt are asynchronous, they do not occur
are at a time in an orderly fashion. Microprocessors have certain
priorities established for their various inputs. A priority interrupt
structure distinguishes among several devices simultaneously
requesting service and assures that the device with the highest
assigned priority is serviced first.
The five interrupt inputs have an internally established, fixed
multilevel priority structure. From highest to lowest they or TRAP,
RST7.5, RST6.5, RST5.5 and INTR. TRAP, since it is not mask able,
is usually reserved to handle catastrophic events such as power
failures. I/O devices are associated with the other four interrupt inputs
in such a way that the highest priority device is connected to RST7.5,
the next highest priority device to RST 6.5 and so on. Devices that
require the fastest response time or that interrupt the microprocessor
with greatest frequency are usually given the highest priority.
Once an interrupt occurs, the internal interrupt enable flip-flop,
INTE f/f, is automatically cleared, allowing no more interrupt until an
EI instruction is executed. However if for example, an RST7.5
interrupt occurs, and the service subroutine for that interrupt
subsequently enables the microprocessor interrupt features before its
completion, the microprocessor can be interrupted by a lower priority,
for instance, an RST5.5.
Several I/O devices can be connected to a single
microprocessor interrupt input by ORing their interrupt request occurs
at such an input, the particular device requesting an interrupt must be
identified. For INTR of the 8085A, identification and transfer of control
to the starting address if the service subroutine are done in a
vectored manner for as many as eight devices. Each of the eight is
assigned a different interrupt vector in the RST n instruction. The
appropriate RST n instruction op code is placed on the data bus in
response to
In fig, the restart instruction is generated with the aid of a
priority encoder that supplies the three bits, NNN of the interrupt
vector. An 8 line3 to 3 line priority encoder allows the highest priority
device with its interrupt request flag set, to generate NNN, and thus
be identified immediately.
An interrupt must be identified for INTR of the 8085A,
identification and transfer of control to the starting address of the
service subroutine are many in a vectored manner for as many eight
devices. Each of the eight is assigned a different interrupt vector in
the RST n instruction. The appropriate RST n instruction OP code is
placed on the data bus in response to , the I/O devices interrupt
request F/F outputs are ORed together and connected to the
interrupt input if fig. The restart instruction is generated with the aid of
priority encoder that supplies the three bits. NNN of the interrupt
vector. An 8 line to 3 line priority devices with its interrupt request flag
set-to generate NNN and thus be identified immediately.
The D-type positive level triggered latch allows the input to the
priority latch allows the input to the priority encoder to follow the Q
outputs of the interrupt flags until an occurs. The signal
forces the latch output to retain the values that existed at the leading
edge of the , and enables the three state buffer, placing an RST
instruction on the data bus. The input this instruction on the rising
edge of and control is transferred to the location association
with the RSTn instruction.
The priority encoder establishes priority among interrupt that
occur simultaneously. That is, if one device sets its interrupt request
flag, causing an interrupt, and another device sets its flag before the
interrupt acknowledge ( occurs). The serviced the one
connected to the highest number input of the priority encoder.
The instruction RST0 transfers control the first memory
location, the same location used when an external reset is applied to
the system. Thus, RSTo is usually not used for interrupts. The priority
encoder establishes priority among interrupt that occur
simultaneously. That is, if one device sets it interrupt request flag,
causing an interrupt, and another device also sets its flag before the
interrupt acknowledge occurs. The device serviced is the one
connected to the highest number input of the priority encoder.
The INA m/c cycle automatically disables the INTE F/F so that
no other interrupts can occur until the one being processed is
completed. The interrupt request F/F of the device being serviced
must be cleared. is gated with 1- out of 8 decoder to clear the
appropriate F/F however a programmed pulse generated by each
device is service subroutine would have the same effect. The next to
last instruction in the service subroutine enables the interrupt, the last
instruction transfers control back to the instruction following the one
that was interrupted. The lower priority of the two interrupt request will
then cause another INA m/c cycle to occur. The low priority interrupt
will then be serviced.
Lecture-51
INTEL 8259A Programmable Interrupt Controller
The 8259A is a programmable interrupt controller designed to work
with Intel microprocessor 8080 A, 8085, 8086, 8088. The 8259 A
interrupt controller can
1) Handle eight interrupt inputs. This is equivalent to providing
eight interrupt pins on the processor in place of one INTR/INT
pin.
2) Vector an interrupt request anywhere in the memory map.
However, all the eight interrupt are spaced at the interval of
either four or eight location. This eliminates the major
drawback, 8085 interrupt, in which all interrupts are vectored to
memory location on page 00H.
3) Resolve eight levels of interrupt priorities in a variety of modes.
4) Mask each interrupt request individually.
5) Read the status of pending interrupts, in service interrupts, and
masked interrupts.
6) Be set up to accept either the level triggered or edge triggered
interrupt request.
7) Mine 8259 as can be cascade in a master slave configuration to
handle 64 interrupt inputs.
: Chip select
To access this chip, is made low. A LOW on this pin
enables & communication between the CPU and the 8259A.
This pin is connected to address bus through the decoder logic
circuits. INTA functions are independent of .
:
A low on this pin. When is low enables the 8259 A to accept
command words from CPU.
:
A low on this pin when is low enables these 8259 A to release
status on to the data bus for the CPU. The status in dudes the
contents of IMR, ISR or TRR register or a priority level.
D7-D0:
Bidirectional data bus control status and interrupt in a this bus. This
bus is connected to BDB of 8085.
CAS0-CAS2:
Cascade lines: The CAS lines form a private 8259A bus to control a
multiple 8259A structure ie to identify a particular slave device. These
pins are outputs of a master 8259A and inputs for a slave 8259A.
/ : Salve program/enable buffer:
This is a dual function pin. It is used as an input to determine whether
the 8259A is to a master ( / = 1) or as a slave ( / = 0). It is
also used as an output to disable the data bus transceivers when
data are being transferred from the 8259A to the CPU. When in
buffered mode, it can be used as an output and when not in the
buffered mode it is used as an input.
INT:
This pin goes high whenever a valid interrupt request is asserted. It is
used to interrupt the CPU, thus it is connected to the CPUs interrupt
pin (INTR).
:
Interrupt: Acknowledge. This pin is used to enable 8259A interrupt
vector data on the data bus by a sequence of interrupt request pulses
issued by the CPU.
IR0-IR7:
Interrupt Requests: Asynchronous interrupt inputs. An interrupt
request is executed by raising an IR input (low to high), and holding it
high until it is acknowledged. (Edge triggered mode).or just by a high
level on an IR input (levels triggered mode).
A0:
A0 address line: This pin acts in conjunction with the , &
pins. It is used by the 8259A to send various command words from
the CPU and to read the status. If is connected to the CPU A0
address line. Two addresses must be reserved in the I/O address
space for each 8259 in the system.
Functional Description:
The 8259 A has eight interrupt request inputs, TR2 IR0. The 8259 A
uses its INT output to interrupt the 8085A via INTR pin. The 8259A
receives interrupt acknowledge pulses from the at its input.
Vector address used by the 8085 A to transfer control to the service
subroutine of the interrupting device, is provided by the 8259 A on the
data bus. The 8259A is a programmable device that must be
initialized by command words sent by the. After initialization the 8259
A mode of operation can be changed by operation command words
from the.
The descriptions of various blocks are,
IRR stores all the interrupt inputs that are requesting service.
Basically, it keeps track of which interrupt inputs are asking for
service. If an interrupt input is unmasked, and has an interrupt signal
on it, then the corresponding bit in the IRR will be set.
Priority Resolver:
This logic block determines the priorities of the set in the IRR. The
highest priority is selected and strobed into the corresponding bit of
the ISR during pulse.
Cascade buffer/comparator:
This function blocks stores and compare the IDS of all 8259As in the
reg. The associated 3-I/O pins (CAS0-CAS2) are outputs when
8259A is used a master. Master and are inputs when 8259A is used
as a slave. As a master, the 8259A sends the ID of the interrupting
slave device onto the cas2-cas0. The slave thus selected will send its
pre-programmed subroutine address on to the data bus during the
next one or two successive pulses.
Lecture-52
Interrupt sequence:
The powerful features of the 8259A in a system are its
programmability and the interrupt routine address capability. It allows
direct or indirect jumping to the specific interrupt routine requested
without any polling of the interrupting device.
Before considering the details of programming the 8259A, the
sequence of events that occur in response to an interrupt request at
one of the IR inputs of an initialized 8259A are considered. The
sequence of events during an interrupt depends on the type of CPO
being used. The events occur as follows in 8085 system.
1) One (or more) of the interrupt request lines (IR0-IR7) is one
mate logic1 by devices requesting service. The corresponding
bits in the interrupt request register (IRR) is set i.e. when an
interrupt request has been received, it is first latched into the
IRR.
2) The priority resolver and control logic use information from the
ISR and IMR to determine if the should be interrupted. If so,
INT becomes logic 1.
3) If the 8085As INTR interrupt is enabled, the completes the
execution of the current instruction and then executes an
interrupt acknowledge, INA machine cycle. During the INA the
8085A acknowledges the interrupt with an pulses.
4) In response to the the 8259A sets the highest priority ISR,
bit and reset the corresponding IRR bit. The 8259A also places
the CALL instruction op code CDH on the 8-bit data bus through
D7-D0 pins.
5) When the 8085A receives a CALL instruction OP code during
the INA m/c cycle, it generates two more INA m/c cycles.
During the second & a third are generated by the 8085A.
6) In response to the second pulses, the 8259A places the
low address of a pre-programmed subroutine address on the
data bus. The high address on the data bus in response to the
third pulses.
7) This completes the 3-byte CALL instruction released by the
8259A. If the 8259A is in AEOI (autocratic end of interrupt)
mode, the ISR bit is reset at the end of the third pulses.
Otherwise the ISR bit remains set until an appropriate EOI
command is issued by the 8085A at the end of interrupt service
subroutine.
8) The 8085A executes the CALL instruction by saving the PC
(return address) an the stack and transferring control to the pre-
programmed address.
If ICW=0, then all functions selected in ICW4 are set to zero. This
puts the 8259A in the 80/85 mode, with no AEOI (automatic end of
interrupt), and non buffered operation. No ICW4 would then be sent
in their initialization sequence. For an 8086/8088 system their bit
must always be set to 1.Bit 1 (SNGL) indicates whether or not. The
8259A is cascade with other 8259As. If SNGL=1, only one 8259A is
in the interrupt system. In this case no ICW3 is needed. Bit 2 (ADI)
(CALL address interval) is used in 8080/85 system only and not in
8086. In 80/85 system, the 8 interrupts will generates CALL to 8
locations equally spaced in memory. The separation interval between
the eight vector addresses may be 4 or 8 bytes. Thus the 8 interrupt
routines will occupy a page of 32 or 64 bytes, respectively. The
desired interval is selected by bit 2 of ICW1.
0 0 0 IR1
. . . .
. . . .
1 1 1 IR7
A10-A3 are ignored and ADI has no effected.
LTIM: If LTIM =1, then the 8259A will operate in the level interrupt
mode. If LTIM = 0, then the interrupt are edge triggered.
A15-A8 specify the higher byte addr of the interrupt for 80/85 system
only. For 8086, T7-T3 are used to specify the interrupt vector address.
Thus, an 8085A system using a single 8259A could be programmed
with only two ICWs; ICW1 & ICW2. eg. if
ICW1 = 0001 00102 and ICW2 = 0000 01002
with these initialization command words, the interrupt request inputs
are programmed for edge triggered mode. In addition, the 8259As
priority instruction would be operating in the fully rested mode i.e. IR0
having the highest priority.
Lecture-53
Initialization Control Word 3 ICW3:
This word is read only where there is mode than one 8259A in the
system and one cascading is used in which case SNGL=0. It will load
the 8-bit slave register.
The functions of this register are:
a) In the master mode (either when SP= 1 or in buffered mode
when M/S=1 in ICW4) a 1 is set for each slave in the system.
The master will then release byte 1 of the CALL sequence
(80/85 system only) and will enable the corresponding slave to
release bytes 2 and 3 through the address lines (In 86/88 only
two bytes). The format of ICW3 in this case is,
S7 S6 S5 S4 S3 S2 S1 S0
If Si =1, IR input has a slave and if Si=0, IR input does not have
a slave.
b) In the slave mode (either when = 0 or if BUF =1 and M/S =0
in ICW4) bits 2-0 identify the slave. The slave compares its
cascade input with these bits and if they are equal bytes 2&3 of
the CALL sequence are released by it on the data bus.
0 0 0 0 0 ID2 ID1 ID0
The three identification bits ID2, ID1, and ID0 tells the slave 8259A to
which master input, slave is connected.
Initialization Control Word 3 ICW4:
ICW4 is output to only if ICW4 in ICW1 is set to 1. Otherwise
the contents of ICW4 are cleared. The bits in ICW4 are defined as
follows:
M7 M6 M5 M4 M3 M2 M1 M0
R SL EOI 0 0 L2 L1 L0
R, SL and EOI stands for rotate, set level, and end of Interrupt and
the bit combination of these decides the manner in which ISR bit is
cleared. L2, L1, and L0 decides the interrupt level to be acted upon if
SL bit is made 1.
R SL EOI Interrupt Mode
0 0 1 Non-specified EOI command
End of Interrupt
0 1 1 specified EOI command
1 0 1 Rotates on non-specified EOI
1 0 0 Rotate in AEOI mode (set) Automatic rotation
0 0 0 Rotate in AEOI mode (clear)
1 1 1 Rotate on specific EOT command
specific rotation
1 1 0 Set priority command
0 1 0 No-Operation
0 0 ES MH SMH 0 1 P RR RIS
RR RIS Operation
0 0 No Action
0 1 No-Action
1 0 Read Interrupt Request Register on next RD pulse
1 1 Read In-service Register on next RD pulse
P Operation
0 No Poll Command
1 Poll Command
How the priority resolves the ISR set to allow service un interrupting
device .Will be clean by the following example.
Suppose IR2 and IR4 are unmasked and that an interrupt
signal comes in on the IR4 input .since IR4 is unmasked bit 4 of the
IRR will be sort. The priority resolves will detect that these bit is set
and seen. If any location needs to be taken. To do if checks the bits
in the in-service register (ISR) to see if a higher priority interrupt are
being serviced if a higher priority interrupt is being serviced if a higher
priority interrupt is being serviced. If a higher priority interrupt is being
serviced received as indicated by a being set for that input in the ISR,
then the priority resolves will take no action. If no higher priority
interrupt is being serviced. Then the priority resolve will activate the
circularly which send an interrupt signal to 8085 executes the IR4
interrupt service subroutine.
Now ,suppose that while the 8085 executing the TR4 arrives at
the IR2 input of the 8259 A since we assumed for this example that
IR2 was unmasked bit 2 if the IRR will be set .the priority resolve will
detect that this bit in the IRR is set and make a decision whether to
send interrupt to the processor. To make the decision ,the priority
resolves looks at the in-service register .If a higher priority bit is set
,then it means a higher priority interrupt is being service .the priority
resolves will wait until the higher priority bit in the ISR is reset before
be sending an interrupt signal to the . For the new interrupt input .if
the priority resolves finds that the new interrupt has higher priority.
Than the highest priority then the highest priority interrupts being
serviced, it will set the appropriate bit in the ISR and then it sends.
A new INT signal to CPU in this example,IR2 has a higher
priority than IR4 so the priority resolves will set the bit 2 of the ISR
and send new INT signal. If 8085 interrupt function has been enabled
(EI) at the start if IR4 service sub routine, then this new INT will again
interrupt the CPU. Upon receiving PIC sends the address if IR2
subroutine and CPU starts execution IR2 sub routine.
If the end of IR2 subroutine we send the PIC a command word
that resets the PIC a command word that resets bit 2 ISR so that
lower priority interrupts can be serviced A RESET instruction at the
end of the Ir4 subroutine return execution to the main program.
If IR4 procedure did not enable the interrupt input either EI
instruction the CPU would not expand to the IR2 caused INT signal
until it finished executing the IR4 dub-routine.
Priority status 7 6 5 4 3 2 1 0
Priority status 2 1 0 7 6 5 4 3
Buffered mode:
When the 8259A is user in a large system where bus during
buffer is required on the data bus and the cascading mode is used,
there the problem of enabling buffers. The buffered mode will
structure the 8259A to send an enable signal to / output
becomes active.
These modification forces the use of software programming to
determine whether the 8259A is a master or a slave. Bit 3 of ICW4
programs the buffered mode, & bit 2 in ICW4 determines whether it is
a master or a slave.
Cascade mode:
The 8259A can be easily internal connected in a system of one
master with up to 0 slaves. To handle up to 64 priority levels. When
designing the address decoder logic, each 8259A must be given its
can address pair (even &odd) is the I/O address space. The / of
all the slaves are connected to GND. The slave interrupt outputs are
connected to the master I Request inputs.
The master controls the slave through the 3 line cascade bus.
The cascade bus acts like chip selects to the slaves during the
sequence.
In a multiple 8259A system the slaves must be initialized as
well as the master. The master would be initialize in the same way as
indicate earlier except that NGL would be set to 0 and ICW3 would
needed to be filled A1would be put in each ICW3 bit for which the
corresponding IR bit is connected to a slave and 0A would be put in
the remaining bits. The SFNM bit may be set to 0 where initializing
the slaves thus, an ICW3 will be require for each slave, but for a
slave ICW3 has a different meaning for a slaves ICW3 has the form