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EC010- 806
Semester VIII
B.TECH in
ELECTRONICS AND COMMUNICATIONENGINEERING
List of Programs:
All programs were simulated using Testbenches & implemented in Xilinx Spartan-3 FPGA Kit
EXP NO: 01 DATE:
ALGORITHM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.
LOGIC DIAGRAM:
A B Y=AB
0 0 0 A B Y=A+B
0 1 0
0 0 0
1 0 0
0 1 1
1 1 1
1 0 1
1 1 1
Y=(A+B)
A B A B
0 0 1 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 0 1 1 0
XNOR GATE:
TRUTH TABLE:
LOGIC DIAGRAM:
A B
0 0 1
0 1 0
1 0 0
1 1 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use
IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity logicgates is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic_vector(6 downto
0)); end logicgates;
begin
c(0)<= a and b;
c(1)<= a or b;
c(2)<= a nand b;
c(3)<= a nor b;
c(4)<= a xor b;
c(5)<= a xnor b;
c(6)<= not a;
end dataflow;
module logicgates1(a, b,
c); input a;
input b;
OUTPUT: [6:0] c;
endmodule
TEST BENCH(VHDL):
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY logicgatestest_vhd IS
END logicgatestest_vhd;
BEGIN
tb : PROCESS
BEGIN
END PROCESS;
END testbench;
Simulation output:
Synthesis RTL Schematic:
Synthesis report:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : logicgates.ngr
Top Level Output File Name : logicgates
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :9
Cell Usage :
# BELS :7
# INV :1
# LUT2 :6
# IO Buffers :9
# IBUF :2
# OBUF :7
=========================================================================
TIMING REPORT
Clock Information:
------------------
No clock signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 13 / 7
-------------------------------------------------------------------------
Delay: 7.985ns (Levels of Logic = 3)
Source: a (PAD)
Destination: c<5> (PAD)
=========================================================================
CPU : 3.03 / 3.27 s | Elapsed : 3.00 / 4.00 s
RESULT:
Thus the outputs of Basic Logic Gates are verified by simulating and synthesizing the VHDL
and VERILOG code.
EXP NO: 02 DATE:
ALGORITHM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis
report. Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test
bench. Step7: Obtain the place and route report.
HALF ADDER:
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ha is
Port ( a,b : in STD_LOGIC;
s,c : out STD_LOGIC);
end ha;
architecture Behavioral of ha is
begin s<=a
xor b;
c<= a and b;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hfadd is
Port ( a,b : in STD_LOGIC;
su,cy : out STD_LOGIC);
end hfadd;
component xor_2
port(p,q:in std_logic;
r:out std_logic);
end component;
component and_2
port(x,y:in std_logic;
z:out std_logic);
end component;
begin
X1:xor_2 port map(a,b,su);
X2:and_2 port map(a,b,cy);
end Structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ha is
Port ( a,b : in STD_LOGIC;
s,c : out STD_LOGIC);
end ha;
architecture Behavioral of ha
is begin
p1:process(a,b)
begin
if(a='0' and b='0')
then s<='0';
c<='0';
elsif(a='0' and b='1')
then s<='1';
c<='0';
elsif(a='1' and b='0')
then s<='1';
c<='0';
else
s<='0';
c<='1';
end if;
end process;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY hatest IS
END hatest;
ARCHITECTURE behavior OF hatest IS
COMPONENT ha
PORT(
a : IN std_logic;
b : IN std_logic;
s : OUT std_logic;
c : OUT std_logic
);
END COMPONENT;
BEGIN
END;
VERILOG CODE:
module halfadder(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry= a&b;
endmodule
module halfadderstr(a,b,sum,carry);
input a,b;
output sum,carry;
xor x1(sum,a,b);
and a1(carry,a,b);
endmodule
SIMULATION OUTPUT:
HALF SUBSTRACTOR:
A B DIFFERENCE BORROW
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hs is
Port ( a,b : in STD_LOGIC;
d,bo : out STD_LOGIC);
end hs;
architecture Behavioral of hs is
signal p: std_logic;
begin d<=a
xor b; p<=
not a;
bo<= p and b;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hsub is
Port ( a,b : in STD_LOGIC;
d,bo : out STD_LOGIC);
end hsub;
component xor_2
port(p,q:in std_logic;
r:out std_logic);
end component;
component not_1
port(c:in std_logic;
d:out std_logic);
end component;
component and_2
port(x,y:in std_logic;
z:out
std_logic); end component;
signal
s:std_logic; begin
X1:xor_2 port map(a,b,d);
X2:not_1 port map(a,s);
X3:and_2 port map(s,b,bo);
end Structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hs is
Port ( a,b : in STD_LOGIC;
d,bo : out STD_LOGIC);
end hs;
architecture Behavioral of hs is
begin
p1:process(a,b)
begin
if(a='0' and b='0')
then d<='0';
bo<='0';
elsif(a='0' and b='1') then
d<='1';
bo<='1';
elsif(a='1' and b='0') then
d<='1';
bo<='0';
else
d<='0';
bo<='0';
end if;
end process;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY hstest IS
END hstest;
COMPONENT hs
PORT(
a : IN std_logic;
b : IN std_logic;
d : OUT std_logic;
bo : OUT std_logic
);
END COMPONENT;
BEGIN
END;
VERILOG CODE:
Using Dataflow Modelling:
module halfsub(a,b,diff,borrow);
input a,b;
output diff,borrow;
assign diff=a^b;
assign borrow=
(!a)&b; endmodule
Using Structural Modelling:
module halfsubstr(a,b,diff,borrow);
input a,b;
output diff,borrow;
wire p;
xor x1(diff,a,b);
not n1(p,a);
and a1(borrow,p,b);
endmodule
SIMULATION OUTPUT:
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fa is
Port ( a,b,cin : in STD_LOGIC;
s,c : out STD_LOGIC);
end fa;
architecture Behavioral of fa is
signal p,q,r: std_logic;
begin
s<=a xor b xor
cin; p<=a and b;
q<=a and cin;
r<=b and cin;
c<= p or q or r;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fa is
Port ( a,b,c : in STD_LOGIC;
Sum,carry: out STD_LOGIC);
end fa;
architecture Structural of fa is
component xor_2
port(p,q:in std_logic;
r:out std_logic);
end component;
component and_2
port(x,y:in std_logic;
z:out std_logic);
end component;
component or_2
port(u,v:in std_logic;
w:out std_logic);
end component;
signal
s1,s2,s3:std_logic; begin
X1:xor_2 port map(a,b,s1); X2:
xor_2 port map(s1,c,sum);
X3:and_2 port map(a,b,s2);
X4:and_2 port map(s1,c,s3);
X5:or_2 port map(s2,s3,carry);
end Structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fa is
Port ( a,b,c : in STD_LOGIC;
su,cy : out STD_LOGIC);
end fa;
architecture Behavioral of hs is
begin
p1:process(a,b,c)
begin
if(a='0' and b='0' and c=0)
then su<='0';
cy<='0';
elsif(a='0' and b='0' and c=1)
then su<='1';
cy<='0';
elsif(a='0' and b='1' and c=0)
then su<='1';
cy<='0';
elsif(a='0' and b='1' and c=1)
then su<='0';
cy<='1';
elsif(a='1' and b='0' and c=0)
then su<='1';
cy<='0';
elsif(a='1' and b='0' and c=1)
then su<='0';
cy<='1';
elsif(a='1' and b='1' and c=0)
then su<='0';
cy<='1';
else
su<='1';
cy<='1';
end if;
end process;
end Behavioral;
VHDL TEST BENCH:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fatest IS
END fatest;
COMPONENT fa
PORT(
a : IN std_logic;
b : IN std_logic;
cin : IN std_logic;
s : OUT std_logic;
c : OUT std_logic
);
END COMPONENT;
BEGIN
END;
VERILOG CODE:
Using Dataflow Modelling:
module fulladder
(a,b,cin,su,cy); input a,b,cin;
output su,cy;
wire p,q,r,t;
assign p=a^b;
assign su=p^cin;
assign q=a&b;
assign r=b&cin;
assign t=a&cin;
assign cy=q|r|t;
endmodule
SIMULATION OUTPUT:
FULL SUBSTRACTOR:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fs is
Port ( x,y,bin : in STD_LOGIC;
d,bo : out STD_LOGIC);
end fs;
architecture Behavioral of fs is
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fs is
Port ( a,b,c : in STD_LOGIC;
difference,borrow: out STD_LOGIC);
end fs;
architecture Structural of fs is
component xor_2
port(p,q:in std_logic;
r:out std_logic);
end component;
component and_2
port(x,y:in std_logic;
z:out
std_logic); end component;
component or_3
port(u,v,w:in std_logic;
t:out std_logic);
end component;
component not_1
port(c:in std_logic;
d:out std_logic);
end component;
signal
s1,s2,s3,s4,s5:std_logic; begin
X1:xor_2 port map(a,b,s1);
X2: xor_2 port map(s1,c,difference);
X3:not_1 port map(a,s2);
X4:and_2 port map(s2,b,s3);
X5:and_2 port map(s2,c,s4);
X4:and_2 port map(b,c,s5); X5:or_3
port map(s3,s4,s5,borrow);
end Structural;
Using Behavioral Modelling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fa is
Port ( a,b,c : in STD_LOGIC;
Diff,bo : out STD_LOGIC);
end fa;
architecture Behavioral of hs is
begin
p1:process(a,b,c)
begin
if(a='0' and b='0' and c=0)
then diff<='0';
bo<='0';
elsif(a='0' and b='0' and c=1)
then diff<='1';
bo<='1';
elsif(a='0' and b='1' and c=0)
then diff<='1';
bo<='1';
elsif(a='0' and b='1' and c=1)
then diff<='0';
bo<='1';
elsif(a='1' and b='0' and c=0)
then diff<='1';
bo<='0';
elsif(a='1' and b='0' and c=1)
then diff<='0';
bo<='0';
elsif(a='1' and b='1' and c=0)
then diff<='0';
bo<='0';
else
diff<='1';
bo<='1';
end if;
end process;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fstest
IS END fstest;
ARCHITECTURE behavior OF fstest
IS COMPONENT fs
PORT(
x : IN std_logic;
y : IN std_logic;
bin : IN std_logic;
d : OUT std_logic;
bo : OUT std_logic
);
END COMPONENT;
signal x_tb : std_logic ;
signal y_tb : std_logic ;
signal bin_tb : std_logic
; signal d_tb : std_logic;
signal bo_tb : std_logic;
BEGIN
uut: fs PORT MAP (
x => x_tb,
y => y_tb, bin
=> bin_tb,
d => d_tb,
bo => bo_tb
);
END;
VERILOG CODE:
module fullsubtractor
(a,b,c,difference,borrow); input a;
input b;
input c;
output difference;
output borrow;
wire p,q,r,s;
assign #3 difference=
a^b^c; assign #3 p=s&c;
assign #3 q=!a&b;
assign #3 r=b&c;
assign #3 s=!a;
assign #3 borrow=p|q|r;
endmodule
SIMULATION OUTPUT:
SYNTHESIS RTL SCHEMATIC:
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fa is
Port ( a,b,cin : in STD_LOGIC;
s,c : out STD_LOGIC);
end fa;
architecture Behavioral of fa is
signal s1,s2,s3: std_logic;
begin
s1<=a xor b;
s2<=a and b;
s<=s1 xor cin;
s3<=s1 and cin;
c<=s2 or s3;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder is
Port ( a,b,cin : in STD_LOGIC;
s,c : out STD_LOGIC);
end fulladder;
component or_2
port(u,v:in std_logic;
w:out std_logic);
end component;
signal i,j,k: std_logic;
begin
X1:hfadd port map(a,b,i,j);
X2:hfadd port map(i,cin,s,k);
X3:or_2 port map(j,k,c);
end Structural;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fuladdertest IS
END fulfaddertest;
COMPONENT fuladder
PORT(
a : IN std_logic;
b : IN std_logic;
cin:IN std_logic;
s : OUT std_logic;
c: OUT std_logic );
END COMPONENT;
--Inputs
signal a_tb : std_logic;
signal b_tb : std_logic;
signal cin_tb:std_logic;
--Outputs signal
s_tb : std_logic; signal
c_tb : std_logic;
BEGIN
END;
VERILOG CODE:
module fulladderstr(a,b,cin,s,c);
input a,b,cin;
output s,c;
wire p,q,r;
halfadderstr h1(a,b,p,q);
halfadderstr h2(q,cin,s,r);
or o1(c,q,r);
endmodule
SIMULATION OUTPUT:
SYNTHESIS RTL SCHEMATIC:
A B C DIFFERENCE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fa is
Port ( a,b,bin : in STD_LOGIC;
d,bo: out STD_LOGIC);
end fa;
architecture Behavioral of fa is
signal s1,s2,s3,s4,s5:
std_logic; begin
s1<=a xor b;
s2<=not a;
s3<=s2 and b;
d<=s1 xor bin;
s4<=not s1;
s5<=s4 and bin;
bo<=s3 or s5;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fullsub is
Port ( a,b,bin : in STD_LOGIC;
d,bo : out STD_LOGIC);
end fullsub;
component or_2
port(u,v: in std_logic;
w: out std_logic);
end component;
signal j,k,l:std_logic;
begin
X1: hsub port map(a,b,j,k);
X2: hsub port map(j,bin,d,l);
x3: or_2 port map(k,l,bo);
end Structural;
COMPONENT fulsub
PORT(
a : IN std_logic;
b : IN std_logic;
bin:IN std_logic;
d : OUT std_logic;
bo : OUT std_logic
);
END COMPONENT;
module fullsubstr(a,b,bin,d,bo);
input a,b,bin;
output d,bo;
wire p,q;
halfsubstr h1(a,b,p,q);
halfsubstr h2(p,bin,d,r);
or o1(bo,q,r);
endmodule
SIMULATION OUTPUT:
LOGIC DIAGRAM:
Cin
Using Structural
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ripplecarry is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
su : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end ripplecarry;
component fulladder
Port ( x,y,cin : in STD_LOGIC;
sum,carry : out STD_LOGIC);
end component;
begin
x1:fulladder port map(a(0),b(0),cin,su(0),c2);
x2:fulladder port map(a(1),b(1),c2,su(1),c3);
x3:fulladder port map(a(2),b(2),c3,su(2),c4);
x4:fulladder port
map(a(3),b(3),c4,su(3),cout); end Behavioral;
COMPONENT ripplecarry
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 down to 0);
cin:IN std_logic;
su: OUT std_logic_vector(3 downto 0);
cout : OUT std_logic
);
END COMPONENT;
--Inputs
signal a_tb : std_logic_vector(3 downto 0);
signal b_tb : std_logic_vector(3 downto
0); signal cin_tb:std_logic;
--Outputs
signal su_tb : std_logic_vector(3 downto 0);
signal cout_tb : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
END;
VERILOG CODE:
Using structural
module rpca(a,b,cin,s,c);
input[3:0]a; input[3:0]b;
input cin;
output[3:0]s;
output c; wire
c0,c1,c2;
fulladder fa1(a[0],b[0],cin,s[0],c0);
fulladder fa2(a[1],b[1],c0,s[1],c1);
fulladder fa3(a[2],b[2],c1,s[2],c2);
fulladder fa4(a[3],b[3],c2,s[3],cout);
endmodule
SIMULATION OUTPUT:
FAST ADDERS:
LOGIC DIAGRAM:
VHDL SOURCE CODE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity carryselectadder is
Port ( A,B : in STD_LOGIC_VECTOR (3 downto 0);
CIN : in STD_LOGIC;
SUM : out STD_LOGIC_VECTOR (3 downto 0);
COUT : out STD_LOGIC);
end carryselectadder;
component ripplecarry
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
su : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end component;
component mux2_1
Port ( d0: in STD_LOGIC;
d1:in std_logic;
s : in STD_LOGIC; o
: out STD_LOGIC);
end component;
begin
r1:ripplecarry port map(A,B,'0',x1,x2);
r2:ripplecarry port map(A,B,'1',x3,x4);
m1:mux2_1 port map(x1(0),x3(0),cin,SUM(0));
m2:mux2_1 port map(x1(1),x3(1),cin,SUM(1));
m3:mux2_1 port map(x1(2),x3(2),cin,SUM(2));
m4:mux2_1 port map(x1(3),x3(3),cin,SUM(3));
m5:mux2_1 port map(x2,x4,cin,COUT);
end Behavioral;
COMPONENT carryselectadder
PORT(
a : IN std_logic_vector[3:0];
b : IN std_logic_vector[3:0];
cin:IN std_logic;
sum : OUT std_logic_vector[3:0];
cout : OUT std_logic_vector[3:0];
);
END COMPONENT;
--Inputs
signal a_tb : std_logic_vector(3 downto 0);
signal b_tb : std_logic_vector(3 downto
0); signal cin_tb:std_logic;
--Outputs
signal sum_tb : std_logic_vector(3 downto 0);
signal cout_tb : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
END;
VERILOG CODE
module caryslctadr(a,b,cin,sum,cout);
input[3:0]a;
input[3:0]b;
input cin;
output[3:0]sum;
output cout;
wire [3:0]x1;
wire x2,x4;
wire[3:0]x3;
ripleadr l(a,b,(0),x1,x2);
ripleadr m(a,b,(1),x3,x4);
mux2 l1(x1[0],x3[0],cin,sum[0]);
mux2 l2(x1[1],x3[1],cin,sum[1]);
mux2 l3(x1[2],x3[2],cin,sum[2]);
mux2 l4(x1[3],x3[3],cin,sum[3]);
mux2 l5(x2,x4,cin,cout);
endmodule
SIMULATION OUTPUT:
RESULT:
Thus the OUTPUTs of Adders,Subtractors and Fast Adders are verified by synthesizing and simulating the
VHDL and VERILOG code.
EXP NO: 03 DATE:
ALGORITHM:
ENCODER:
D0 D1 D2 D3 D4 D5 D6 D7 X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Using Dataflow
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity encoder8_3 is
Port ( d : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC_VECTOR (2 downto 0));
end encoder8_3;
begin
y(0)<=d(4) or d(5) or d(6) or d(7);
y(1)<=d(2) or d(3) or d(6) or d(7);
y(2)<=d(1) or d(4) or d(5) or d(7);
end Behavioral;
Using Structural Modelling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity encoder8 is
Port ( d : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC_VECTOR (2 downto 0));
end encoder8;
begin
X1:or_4 port map(d(4),d(5),d(6),d(7),y(0));
X2:or_4 port map(d(2),d(3),d(6),d(7),y(1));
X3:or_4 port map(d(1),d(4),d(5),d(7),y(2));
end Structural;
Using Behavioural
Modelling library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity encoder8_3 is
Port ( i : in STD_LOGIC_VECTOR (7 downto 0);
En : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (2 downto 0));
end encoder8_3;
begin
PROCESS ( i, En
) BEGIN
IF En = '1' THEN
CASE i IS
WHEN "00000001" => y <= "000" ;
WHEN "00000010" => y <= "001" ;
WHEN "00000100" => y <= "010" ;
WHEN "00001000" => y <= "011" ;
WHEN "00010000" => y <= "100" ;
WHEN "00100000" => y <= "101" ;
WHEN "01000000" => y <= "110" ;
WHEN "10000000" => y <= "111" ;
WHEN OTHERS => y <= "ZZZ" ;
END CASE ;
ELSE
y <= "ZZZ"
; END IF ;
END PROCESS ;
END Behavioral;
VHDL TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY encdr_test IS
END encdr_test;
COMPONENT
encoder PORT(
a : IN std_logic_vector(3 downto 0);
y0 : OUT std_logic;
y1 : OUT std_logic
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal y0 : std_logic;
signal y1 : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
END;
VERILOG CODE
module encoder(a,y);
input [7:0]a;
output[2:0]y;
reg[2:0]y;
always @
(a) begin
case (a)
8'b00000001 : y= 0;
8'b00000010 : y= 1;
8'b00000100 : y= 2;
8'b00001000 : y= 3;
8'b00010000 : y= 4;
8'b00100000 : y= 5;
8'b01000000 : y= 6;
8'b10000000 : y= 7;
default : y= 3'bx;
endcase
end
endmodule
SIMULATION OUTPUT:
DECODERS:
0 0 1 0 1 1 1
0 1 1 1 0 1 1
1 0 1 1 1 0 1
1 1 1 1 1 1 0
VHDL SOURCE CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decoder2_4 is
Port ( a,b : in STD_LOGIC;
en:in STD_LOGIC;
z : out STD_LOGIC_VECTOR (3 downto 0));
end decoder2_4;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decoder2_4 is
Port ( a,b : in STD_LOGIC;
en:in STD_LOGIC;
z : out STD_LOGIC_VECTOR (3 downto 0));
end decoder2_4;
component nand_3
port( u,v,w:in std_logic;
x:out std_logic);
end component;
component not_1
port(c:in std_logic;
d:out std_logic);
end component;
begin
X1:not_1 port map(a,s1);
X2:not_1 port map(b,s2);
X3:nanad_3 port map(s1,s2,en,z(0));
X4:nanad_3 port map(a,s2,en,z(1));
X5:nanad_3 port map(s1,b,en,z(2));
X6:nanad_3 port map(a,b,en,z(3));
end Structural;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY decoder2to4test IS
END decoder2to4test;
COMPONENT decoder2to4
PORT(
a : IN std_logic;
b : IN std_logic;
z : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
BEGIN
uut: decoder2to4 PORT MAP (
a => a_tb,
b => b_tb,
z => z_tb
);
a_tb<='1','0' after 10ns, '1' after 40ns;
b_tb<='1','0' after 20ns, '1' after 50ns;
END;
VERILOG CODE
always @
(code) begin
if(code==0) data=8'b00000001; else
if(code==1) data=8'b00000010; else
if(code==2) data=8'b00000100; else
if(code==3) data=8'b00001000; else
if(code==4) data=8'b00010000; else
if(code==5) data=8'b00100000; else
if(code==6) data=8'b01000000; else
if(code==7) data=8'b10000000; else
data=8'bx;
end
endmodule
SIMULATION OUTPUT:
RESULT:
Thus the OUTPUTs of Encoder and Decoder are verified by synthesizing and simulating the VHDL
and VERILOG code.
EXP NO: 04 DATE:
ALGORITHM:
MULTIPLEXER:
LOGIC DIAGRAM:
TRUTH TABLE:
1
D0 2 9
8
4
1 Y S1 S0 Y
5
1
D2 2
8
9
0 0 D0
2
1
0 1 D1
D3 2 9
1
1 0 D2
2
1 1 D3
1
S1 S0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4_1 is
Port ( d : in STD_LOGIC_VECTOR (3 downto 0);
s0,s1 : in STD_LOGIC;
o : out STD_LOGIC);
end mux4_1;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_4 is
Port ( i : in STD_LOGIC_VECTOR (3 downto 0);
s0,s1 : in STD_LOGIC;
o : out STD_LOGIC);
end mux_4;
component or_4
port(x,y,z,v:in std_logic;
u:out std_logic);
end component;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY mux4to1test IS
END mux4to1test;
COMPONENT
mux4to1 PORT(
d : IN std_logic_vector(3 downto 0);
s : IN std_logic_vector(1 downto 0);
y : OUT std_logic
);
END COMPONENT;
--Inputs
signal d_tb : std_logic_vector(3 downto 0);
signal s_tb : std_logic_vector(1 downto 0);
--Outputs signal
y_tb : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
END;
VERILOG CODE
module muxstr(d,s,y);
input [3:0]d;
input [1:0]s;
output y;
wire e,f,p,q,r,t;
not n1(e,s[1]),n2(f,s[0]);
and a1(p,d[0],e,f),a2(q,d[1],e,s[0]),a3
(r,d[2],s[1],f), a4 ( t,d[3],s[1],s[0]);
or o1(y,p,q,r,t);
endmodule
SIMULATION OUTPUT:
LOGIC DIAGRAM: `
TRUTH TABLE:
S1 S0
INPUT OUTPUT
D S0 S1 Y0 Y1 Y2 Y3
1
1 0 0 1 0 0 0
1 0 1 0 1 0 0
2
1 1 0 0 0 1 0
2
Din 2
3
1
1 1 1 0 0 0 1
4 Y0
5
2
3
1
4 Y1
5
2
3
1
4 Y2
5
2
3
1
4 Y3
5
Enable
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux1_4 is
Port ( i : in STD_LOGIC;
s0,s1 : in STD_LOGIC;
o : out STD_LOGIC_VECTOR (3 downto 0));
end demux1_4;
begin
a<= not s0;
b<= not s1;
c<=a and b;
o(0)<=c and i;
d<=a and s1;
o(1)<=d and i;
e<=s0 and b;
o(2)<=e and i;
f<=s0 and s1;
o(3)<=f and i;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity demux_4 is
Port ( i : in STD_LOGIC;
s0,s1 : in STD_LOGIC;
o : out STD_LOGIC_VECTOR (3 downto 0));
end demux_4;
component and_3
port(p,q,r:in std_logic;
t:out std_logic);
end component;
signal
a,b:std_logic; begin
X1:not_1 port map(s0,a);
X2:not_1 port map(s1,b);
X3:and_3 port map(a,b,i,o(0));
x4:and_3 port map(a,s1,i,o(1));
X5:and_3 port map(s0,b,i,o(2));
X6:and_3 port map(s0,s1,i,o(3));
end structural;
ENTITY testbench IS
END testbench;
END;
VERILOG CODE
module demux (in, sel,
out); input in;
input [1:0] sel;
output [3:0] out;
SIMULATION OUTPUT:
RESULT:
Thus the OUTPUTs of Multiplexers and Demultiplexers are verified by synthesizing and simulating the
VHDL and VERILOG code.
EXP NO: 05 DATE:
ALGORITHM:
TRUTH TABLE:
CODE CONVERTER (BCD TO GRAY):
LOGIC DIAGRAM:
BCD GRAY
0000 0000
0001 0001
0010 0011
0011 0010
0100 0110
0101 0111
0110 0101
0111 0100
1000 1100
1001 1101
begin
g(3)<=b(3);
g(2)<=b(3) xor b(2);
g(1)<=b(2) xor b(1);
g(0)<=b(1) xor b(0);
end process p1;
end Behavioral;
Using Structural
Modelling entity sbcd is
Port ( b : in STD_LOGIC_VECTOR (3 downto 0);
g : out STD_LOGIC_VECTOR (3 downto 0));
end sbcd;
architecture Behavioral of sbcd
is component xor2
Port ( c : in STD_LOGIC;
d: in STD_LOGIC; si:
out STD_LOGIC);
end component;
begin
x1:xor2 port map(b(3),b(3));
x2:xor2 port map(b(3),b(2),g(2));
x3:xor2 port map(b(2),b(1),g(1));
x4:xor2 port map(b(1),b(0),g(0));
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bcd2g is
Port ( b : in STD_LOGIC_VECTOR (3 downto 0);
g : out STD_LOGIC_VECTOR (3 downto 0));
end bcd2g;
begin
p1:process(b)
begin
if(b<="0000") then
g<="0000";
elsif(b<="0001") then
g<="0001";
elsif(b<="0010") then
g<="0011";
elsif(b<="0011") then
g<="0010";
elsif(b<="0100") then
g<="0110";
elsif(b<="0101") then
g<="0111";
elsif(b<="0110") then
g<="0101";
elsif(b<="0111") then
g<="0100";
elsif(b<="1000") then
g<="1100";
elsif(b<="1001") then
g<="1101";
else
g<="----
"; end if;
end process;
end Behavioral;
VHDL TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_gray IS
END tb_gray;
VERILOG CODE
SIMULATION OUTPUT:
LOGIC DIAGRAM
BCD EXCESS 3
entity binarytoexc is
Port ( b : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0));
end binarytoexc;
begin
y<=b+"0011";
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bcd2excess is
Port ( a : in STD_LOGIC_vector(3 downto 0);
b : out STD_LOGIC_vector(3 downto 0));
end bcd2excess;
begin
p1:process(a)
begin
if(a<="0000") then
b<="0011";
elsif(a<="0001") then
b<="0100";
elsif(a<="0010") then
b<="0101";
elsif(a<="0011") then
b<="0110";
elsif(a<="0100") then
b<="0111";
elsif(a<="0101") then
b<="1000";
elsif(a<="0110") then
TRUTH TABLE:
BCD EXCESS 3
0000 0011
0001 0100
0010 0101
0011 0110
0100 0111
0101 1000
0110 1001
0111 1010
1000 1011
1001 1100
b<="1001";
elsif(a<="0111") then
b<="1010";
elsif(a<="1000") then
b<="1011";
elsif(a<="1001") then
b<="1100";
else
b<="----";
end if;
end process;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_excess3 IS
END tb_excess3;
--Outputs
signal y : std_logic_vector(3 downto 0);
BEGIN
END;
VERILOG CODE
module excess3(b,e);
input [3:0]b;
output [3:0]e;
assign #3 e=b+4'b0011;
endmodule
SIMULATION OUTPUT:
4 BIT COMPARATOR:
LOGIC DIAGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity comparator is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
x,y,z : out STD_LOGIC);
end comparator;
begin
p1:process(a,b)
begin
if(a>b) then
x<='1';
y<='0';
z<='0';
elsif(a=b) then
x<='0';
y<='1';
z<='0';
else
x<='0';
y<='0';
z<='1';
end if;
end process;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY testcomparator IS
END testcomparator;
--Outputs signal
x_tb : std_logic; signal
y_tb : std_logic; signal
z_tb : std_logic;
BEGIN
uut: comparator1 PORT MAP (
a => a_tb,
b => b_tb,
x => x_tb,
y => y_tb,
z => z_tb
);
a_tb<= 1001 after 10ns, 1100 after 50ns;
b_tb<= 1110 after 10ns, 0001 after 20ns, 1001 after 30ns, 1110 after 40ns;
END;
VERILOG CODE
module comparator(a,b,x,y,z);
input a,b;
output x,y,z; reg
x,y,z; always@(a
or b)
if(a>b)
begin
x = 0;
y = 0;
z = 1;
end
else if(a==b)
begin
x = 0;
y= 1;
z = 0;
end
else
begin
x= 1;
y = 0;
z = 0;
end
endmodule
SIMULATION OUTPUT:
RESULT:
Thus the OUTPUTs of Code converters and comparator are verified by synthesizing and simulating
the VHDL and VERI
EXP NO: 06 DATE:
ALGORITHM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using VHDL source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test
bench. Step7: Obtain the place and route report.
SR FLIPFLOP:
1
Q(t) S R Q(t+1)
S 3 1
2 3 0 0 0 0
2 Q
0 0 1 0
0 1 0 1
CP
0 1 1 X
1 0 0 1
1
1 3 1 0 1 0
3 2 Q
2
1 1 0 1
R 1 1 1 X
entity srflipflop is
Port ( clk : in STD_LOGIC;
s : in STD_LOGIC;
r : in STD_LOGIC;
rst : in STD_LOGIC;
q : inout STD_LOGIC;
qbar : inout STD_LOGIC);
end srflipflop;
begin
p1:process(clk,s,r,rst,q,qbar)
begin
if(rst='1') then
q<='0';
qbar<='1';
elsif(clk='1' and clk'event)
then if(s='0' and r='0') then
q<=q;
qbar<=qbar;
elsif(s='0' and
r='1')then q<='0';
qbar<='1';
elsif(s='1' and r='0') then
q<='1';
qbar<='0';
else q<='-
'; qbar<='-
'; end if;
end if;
end process;
end Behavioral;
VHDL TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY srflipfloptest IS
END srflipfloptest;
ARCHITECTURE behavior OF srflipfloptest
IS COMPONENT srflipflopt
PORT(
s : IN std_logic;
r : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic;
qbar : INOUT std_logic
);
END COMPONENT; signal
s_tb : std_logic ; signal r_tb :
std_logic ; signal clk_tb:
std_logic:='0'; signal rst_tb :
std_logic ; signal q_tb :
std_logic; signal qbar_tb :
std_logic;
BEGIN
uut: srflipflopt PORT MAP
( s => s_tb,
r => r_tb,
clk => clk_tb,
rst => rst_tb,
q => q_tb,
qbar => qbar_tb
);
END;
VERILOG CODE:
module srff(clk,s,r,reset,q,qbar);
input s,r,clk,reset;
output q,qbar;
reg q,qbar;
always@(posedge
clk) if(reset==1'b1)
begin
q<=0;
qbar<=0;
end
else if(s==1'b0&&r==1'b1)
begin
q<=0;
qbar<=1;
end
else if(s==1'b1&&r==1'b0)
begin
q<=1;
qbar<=0;
end
else
begin
q<="--";
qbar<="--";
end
endmodule
SIMULATION OUTPUT:
1
Q(t) J K Q(t+1)
K 2 9 1
8 3
2 Q 0 0 0 0
0 0 1 0
CP 0 1 0 1
0 1 1 1
1
1
3
1 0 0 1
2 9 2 Q 1 0 1 0
J 8
1 1 0 1
1 1 1 0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity jkflipflop is
Port ( j : in STD_LOGIC; k
: in STD_LOGIC; clk :
in STD_LOGIC; rst :
in STD_LOGIC; q :
inout STD_LOGIC;
qbar : inout STD_LOGIC);
end jkflipflop;
begin
p1:process(clk,j,k,rst,q,qbar)
begin
if(rst='1') then
q<='0';
qbar<='1';
elsif(clk='1' and clk'event)
then if(j='0' and k='0') then
q<=q;
qbar<=qbar;
elsif(j='0' and k='1')then
q<='0';
qbar<='1';
elsif(j='1' and k='0')
then q<='1';
qbar<='0';
else
q<=not q;
qbar<=not qbar;
end if;
end if;
end process;
end Behavioral;
VHDL TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY jktest IS
END jktest;
COMPONENT jkflipflop
PORT(
j : IN std_logic;
k : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic;
qbar : INOUT std_logic
);
END COMPONENT;
BEGIN
END;
VERILOG CODE:
module jk(clk,j,k,reset,q,qbar);
input j,k,clk,reset;
output q,qbar;
reg q,qbar;
always@(posedge
clk) if(reset==1'b1)
begin
q<=0;
qbar<=1;
end
else if(j==1'b0&&k==1'b0)
begin
q<=q;
qbar<=qbar;
end
else if(j==1'b0&&k==1'b1)
begin
q<=0;
qbar<=1;
end
else if(j==1'b1&&k==1'b0)
begin
q<=1;
qbar<=0;
end
else
begin
q<=~ q;
qbar<=~ qbar;
end
endmodule
SIMULATION OUTPUT:
1
D
2
3 1
3
Q
Q(t) D Q(t+1)
2
1
2
CP 0 0 0
1
0 1 1
1
3 2
3
Q 1 0 0
3
1 1 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d is
Port ( clk,rst,d : in STD_LOGIC;
q,qbar : inout STD_LOGIC);
end d;
architecture Behavioral of d is
begin
p1:process(clk,d,rst)
begin
if(rst='1')then
q<='0';
qbar<='1';
elsif(clk='1' and clk'event) then
if(d='0') then
q<='0';
qbar<='1';
else
q<='1';
qbar<='0';
end if;
end if;
end process;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY dtest IS
END dtest;
BEGIN
END;
VERILOG CODE:
module dff(clk,d,reset,q,qbar);
input d,clk,reset;
output q,qbar;
reg q,qbar;
always@(posedge
clk) if(reset==1'b1)
begin
q<=0;
qbar<=1;
end
else if(d==1'b0)
begin
q<=0;
qbar<=1;
end
else
begin
q<=1;
qbar<=0;
end
endmodule
SIMULATION OUTPUT:
SYNTHESIS RTL SCHEMATIC:
T FLIPFLOP:
Q(t) T Q(t+1)
1
T 2 9 1
8 3
2 Q
0 0 0
CP 0 1 1
1
1
3
1 0 1
2 9 2 Q
8
1 1 0
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Tflipflop is
Port ( t : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC; q
: inout STD_LOGIC;
qbar : inout STD_LOGIC);
end Tflipflop;
begin
p1:process( t,clk,rst,q,qbar)
begin
if(rst='1') then
q<='0';
qbar<= '1';
elsif(clk='1' and clk'event)
then if(t='0') then
q<= q;
qbar<=qbar;
else
q<= not q;
qbar<= not qbar;
end if;
end if;
end process;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ttestt IS
END ttestt;
BEGIN
uut: tflipflop PORT MAP (
t => t_tb,
SIMULATION OUTPUT:
LOGIC DIAGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity masterslve is
Port ( s,r : in STD_LOGIC;
clk,rst : in STD_LOGIC;
q,qbar : inout STD_LOGIC);
end masterslve;
begin
b<= not clk;
x1:srflipflop port map(s,r,clk,rst,p,a);
x2:srflipflop port map(p,a,b,rst,q,qbar);
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tmasterslave IS
END tmasterslave;
COMPONENT masterslve
PORT(
s : IN std_logic;
r : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic;
qbar : INOUT std_logic
);
END COMPONENT;
--Inputs
signal s : std_logic := '0';
signal r : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic := '0';
--BiDirs
signal q : std_logic;
signal qbar : std_logic;
-- Clock period definitions
constant clk_period : time := 10
ns; BEGIN
-- Instantiate the Unit Under Test
(UUT) uut: masterslve PORT MAP (
s => s,
r => r,
clk => clk,
rst => rst,
q => q,
qbar => qbar
);
clk<= not clk after 10 ns;
rst<= '1','0' after 20 ns;
s<='0','1' after 40 ns,'0' after 120 ns,'1' after 160 ns,'0' after 200 ns;
r<= '1','0' after 40 ns,'0' after 80 ns,'1' after 120 ns,'0' after 160 ns;
END;
VERILOG CODE
module mastrslav(s,r,rst,clk,q,qbar);
input s,r,clk,rst;
output q,qbar;
wire p,q,r;
srff s1(s,r,rst,clk,p,q);
not N1(r,clk);
srff s2(p,q,rst,r,q,qbar);
endmodule
SIMULATION OUTPUT:
SYNTHESIS RTL SCHEMATIC:
RESULT:
Thus the OUTPUTs of Flip Flops are verified by synthesizing and simulating the VHDL and VERILOG
code.
EXP NO: 07 DATE:
ALGORITHM:
LOGIC DIAGRAM :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity siso is
Port ( d,clk,rst : in STD_LOGIC;
q : out STD_LOGIC);
end siso;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY sisotest IS
END sisotest;
COMPONENT
siso PORT(
d : IN std_logic;
clk : IN std_logic;
rst : IN std_logic; q
: OUT std_logic );
END COMPONENT;
BEGIN
END;
VERILOG CODE:
module siso1(clk,reset,din,qout);
input clk,reset,din;
output qout;
reg[2:0]x;
reg qout;
always@(posedge
clk) if (reset)
qout<=1'b0;
else
begin
qout<=x[2];
x[2]<=x[1];
x[1]<=x[0];
x[0]<=din;
end
endmodule
SIMULATION OUTPUT:
LOGIC DIAGRAM :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sipo is
Port ( d,clk,rst : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0));
end sipo;
begin
p1:process(d,clk,rst,q)
begin if(rst='1')
then
q<="----";
elsif(clk='1' and clk'event)
then q(3)<=q(2);
q(2)<=q(1);
q(1)<=q(0);
q(0)<=d;
end if;
end process;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY sipotest IS
END sipotest;
COMPONENT
sipo PORT(
d : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic_vector(3 downto 0)
);
END COMPONENT;
BEGIN
uut: sipo PORT MAP
( d => d_tb,
clk => clk_tb,
rst => rst_tb,
q => q_tb
);
END;
VERILOG CODE:
module sipo(clk,reset,din,qout);
input clk,reset,din;
output[3:0]qout;
reg[3:0]qout;
reg [3:0]x;
always@(posedge
clk) if (reset==1'b1)
qout<=4'b0000;
else
begin
qout[3]<=x[3];
x[3]<=qout[2];
qout[2]<=x[2];
x[2]<=qout[1];
qout[1]<=x[1];
x[1]<=qout[0];
qout[0]<=x[0];
x[0]<=din; end
endmodule
SIMULATION OUTPUT:
LOGIC DIAGRAM :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pipo is
Port ( d : in STD_LOGIC_VECTOR (3 downto 0);
clk,rst : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end pipo;
begin
p1:process(d,clk,rst)
begin
if(rst='1') then
q<="----";
elsif(clk='1' and clk'event)
then q(3)<=d(3);
q(2)<=d(2);
q(1)<=d(1);
q(0)<=d(0);
end if;
end process;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY pipotest IS
END pipotest;
COMPONENT pipo
PORT(
d : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
rst : IN std_logic;
q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
BEGIN
uut: pipo PORT MAP
( d => d_tb,
clk => clk_tb,
rst => rst_tb,
q => q_tb
);
END;
VERILOG CODE:
module pipo(clk,reset,din,qout);
input clk,reset,din;
input[3:0]din; output[3:0]qout;
reg[3:0]qout;
always@(posedge
clk) if (reset)
qout<=4'b0000;
else
begin
qout[3]<=din[3];
qout[2]<=din[2];
qout[1]<=din[1];
qout[0]<=din[0];
end
endmodule
SIMULATION OUTPUT:
LOGIC DIAGRAM :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity piso is
Port ( clk,rst,load,shift : in STD_LOGIC;
d : in STD_LOGIC_VECTOR (3 downto 0);
q : out STD_LOGIC);
end piso;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY pisotest IS
END pisotest;
ARCHITECTURE behavior OF pisotest IS
COMPONENT piso
PORT(
clk : IN std_logic;
rst : IN std_logic;
load : IN std_logic;
shift : IN std_logic;
d : IN std_logic_vector(3 downto 0);
q : OUT std_logic
);
END COMPONENT;
signal clk_tb : std_logic :=
'0'; signal rst_tb : std_logic ;
signal load_tb : std_logic ;
signal shift_tb : std_logic ;
signal d_tb : std_logic_vector(3 downto 0)
; signal q_tb : std_logic;
BEGIN
VERILOG CODE:
module piso(clk,reset,din,shift,load,qout);
input clk,reset,load,shift;
input[3:0]din;
output qout;
reg qout;
reg[3:0]x;
always@(posedge
clk) if(reset==1'b1)
qout<=1'b0;
else if(load==1'b1&&shift==1'b0)
begin
x[0]<=din[0];
x[1]<=din[1];
x[2]<=din[2];
x[3]<=din[3];
end
else if(load==1'b0&&shift==1'b1)
begin
qout<=x[3];
x[3]<=x[2];
x[2]<=x[1];
x[1]<=x[0];
x[0]<=din[0];
end
endmodule
SIMULATION OUTPUT:
RESULT:
Thus the OUTPUTs of 8-bit shift register are verified by synthesizing and simulating the VHDL
and VERILOG code.
EXP NO: 08 DATE:
AIM:
To develop the source code for synchronous and asynchronous counter by using VHDL/VERILOG
and obtain the simulation, synthesis, place and route and implement into FPGA.
ALGORITHM:
SYNCHRONOUS COUNTER:
LOGIC DIAGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity syncounter is
Port ( clk,rst : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0));
end syncounter;
component t
Port ( t,clk,rst : in STD_LOGIC;
q,qbar : inout STD_LOGIC);
end component;
component and_2
Port ( x,y : in STD_LOGIC;
z : out STD_LOGIC);
end component;
end Behavioral;
VHDL TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY synctestbench IS
END synctestbench;
COMPONENT
sync_count PORT(
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic_vector(3 downto 0);
qbar : INOUT std_logic
);
END COMPONENT;
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal q : std_logic_vector(3 downto
0); signal qbar : std_logic;
BEGIN
-- Instantiate the Unit Under Test
(UUT) uut: sync_count PORT MAP (
clk =>
clk, rst =>
rst, q => q
);
clk <= not clk after 10ns;
rst <= '1','0' after 10 ns;
END;
VERILOG CODE
module syncntr(clk,rst,q);
input clk,rst;
inout[3:0]q;
wire [3:0]q;
wire x1,x2,x3,x4,x5,x6;
tff t1((1),clk,rst,q[0],x1);
tff t2(q[0],clk,rst,q[1],x2);
and a1(x3,q[0],q[1]);
tff t3(x3,clk,rst,q[2],x4);
and a2(x5,x3,q[2]);
tff t4(x5,clk,rst,q[3],x6);
endmodule
SIMULATION OUTPUT:
ASYNCHRONOUS COUNTER:
LOGIC DIAGRAM:
VHDL SOURCE CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity asyncounter is
Port ( clk,rst : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0));
end asyncounter;
signal x0,x1,x2,x3:std_logic;
begin
t1:t port map('1',clk,rst,q(0),x0);
t2:t port map('1',x0,rst,q(1),x1);
t3:t port map('1',x1,rst,q(2),x2);
t4:t port map('1',x2,rst,q(3),x3);
end Behavioral;
VHDL TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_asynccounter IS
END tb_asynccounter;
COMPONENT Async_Count
PORT(
t : IN std_logic;
clk : IN std_logic;
rst : IN std_logic;
q : INOUT std_logic_vector(3 downto 0)
);
END COMPONENT;
signal t_tb,clk_tb,rst_tb:std_logic;
signal q_tb: std_logic_vector (3 downto 0) ;
BEGIN
END;
VERILOG CODE
module asynchrnscntr(clk,rst,q);
input clk,rst;
inout [3:0]q; wire
x0,x1,x2,x3;
tff t1((1),clk,rst,q[0],x0);
tff t2((1),x0,rst,q[1],x1);
tff t3((1),x1,rst,q[2],x2);
tff t4 ((1),x2,rst,q[3],x3);
endmodule
SIMULATION OUTPUT:
RESULT:
Thus the OUTPUTs of Synchronous and Asynchronous counter are verified by synthesizing and
simulating the VHDL and VERILOG code.
EXP NO: 09 DATE:
ALGORITHM:
MOORE FSM:
LOGIC DIAGRAM:
VHDL SOURCE
CODE library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity moore_fsm is
Port ( a,clk : in STD_LOGIC;
z : out STD_LOGIC);
end moore_fsm;
end Behavioral;
st1:
begin
if(a) state<=st3;
else state<=st1;
end;
st2:
begin
if(a) state<=st3;
else state<=st1;
end;
st3:
begin
if(a) state<=st0;
else state<=st3;
end;
end case;
end;
end;
always@(posedge clk,posedge rst)
begin
if(rst)
z<=1;
else if(state==st3)
z<=1;
else
z<=0;
end;
endmodule
SIMULATION OUTPUT:
TRUTH TABLE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mealy_fsm is
Port ( a,clk : in STD_LOGIC;
z : out STD_LOGIC);
end mealy_fsm;
begin
p1: process(clk)
begin
if clk='0' then
p_state<=n_state;
end if;
end process p1;
p2: process(p_state,a)
begin
case p_state is
when st0=>
if a='1' then
z<='1';
n_state<=st3;
else
z<='0';
end if;
when st1=> if
a='1' then
z<='0';
n_state<=st0;
else
z<='1';
end if;
when st2=> if
a='0' then
z<='0';
else
z<='1';
n_state<=st1;
end if;
when st3=>
z<='0';
if a='0' then
n_state<=st2;
else
n_state<=st1;
end if;
end case;
end process p2;
end Behavioral;
Module mealyfsm(clk,rst,a,z);
input clk,rst,a;
output z;
reg[1:0]state;
reg z;
parameter st0=2b00;
parameter st0=2b01;
parameter st0=2b10;
parameter st0=2b11;
always@(posedge clk,posedge rst)
begin
if (rst)
begin
state<=st0;z<=0;
end;
else begin
case (state)
st0:
begin
if(a)begin
state<=st3;z<=1;
end;
else begin
state<=st0;z<=0;
end;
end;
st1:
begin
state<=st0;z<=0;
end
else begin
state<=st1;z<=1;
end;
end
st2:
begin
if(a)begin
state<=st1;z<=1;
end;
else begin
state<=st2;z<=0;
end;
end;
st3: begin
if(a)begin
state<=st1;z<=0;
end;
else begin
state<=st2;z<=o;
end;
end;
end case;
end; end;
endmodule
SIMULATION OUTPUT:
RESULT:
Thus the OUTPUTs of Moore and Mealy fsm are verified by synthesizing and simulating the VHDL and
VERILOG code.
EXP NO: 10 DATE:
FREQUENCY DIVIDER
AIM:
To develop the source code Frequency divider and multiplier by using VHDL/VERILOG and Obtained the
simulation, synthesis, place and route and implement into FPGA.
ALGORITHM:
LOGIC DIAGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL
entity frequency_divider is
Port ( clk,rst : in STD_LOGIC;
count : in integer range 1 to 31;
clkout : out STD_LOGIC);
end frequency_divider;
architecture Behavioral of frequency_divider
is signal counter:integer range 1 to 31:=1;
begin
p1:process(clk,rst,count,counter)
begin
if(rst='1') then
clkout<=clk;
elsif(clk='1' and clk'event)
then if(counter>1) then
clkout<=clk;
counter<=counter-
1; else
clkout<=not clk;
counter<=count;
end if;
end if;
end process;
end Behavioral;
VERILOG CODE
Module freq(clk,rst,count,clk_out);
Input clk,rst;
Output clk_out;
Reg counter[31];
always@(posedge
clk) begin
if(rst=1)
clk_out<=clk;
elseif(clk=1)then
if(counter>1)
clk_out<=clk;
counter<=counter-
1; else
clk_out<=not clk;
counter<=counter;
end
end
end module
ALTERNATE VERILOG CODE
module fredivider(clk,rst,clk_out);
input clk,rst;
output clk_out;
reg counter[15];
assign out_clk<=counter[15;
end module
SIMULATION OUTPUT:
SYNTHESIS RTL SCHEMATIC:
RESULT:
Thus the OUTPUTs of Frequency Divider are verified by synthesizing and simulating the VHDL
and VERILOG code.
EXP NO: 11 DATE:
ALGORITHM:
LOGIC DIAGRAM:
TRUTH TABLE:
VHDL SOURCE
CODE Main Program
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity alu is
Port ( a,b : in STD_LOGIC_VECTOR (7 downto 0);
cin : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end alu;
component arithunit
port(a,b:in std_logic_vector(7 downto
0); cin : in STD_LOGIC;
sel:in std_logic_vector(2 downto 0);
out1:out std_logic_vector(7 downto 0));
end component;
component mux
Port ( a: in STD_LOGIC;
b: in STD_LOGIC; s
: in STD_LOGIC; z:
out STD_LOGIC);
end component;
begin
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity logicunit is
Port ( a,b : in STD_LOGIC_VECTOR (7 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0);
out2 : out STD_LOGIC_VECTOR (7 downto 0));
end logicunit;
architecture Behavioral of logicunit
is begin
p1:process(a,b,sel)
begin
case sel is
when"000"=>out2<=not a;
when"001"=>out2<=not b;
when"010"=>out2<=a and b;
when"011"=>out2<=a or b;
when"100"=>out2<=a nand b;
when"101"=>out2<=a nor b;
when"110"=>out2<=a xor b;
when others=>out2<=a xnor b;
end case;
end process p1;
end Behavioral;
Arithmetic Unit
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity arithunit is
Port ( a,b : in STD_LOGIC_VECTOR (7 downto 0);
cin : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR (2 downto 0);
out1 : out STD_LOGIC_VECTOR (7 downto 0));
end arithunit;
begin
p1:process(a,b,cin,sel)
begin
case sel is
when "000"=>out1<=a;
when"001"=>out1<=a+"0001";
when "010"=>out1<=a-"0001";
when"011"=>out1<=b;
when "100"=>out1<=b+"0001";
when"101"=>out1<=b-"0001";
when "110"=>out1<=a+b; when
others=>out1<=a+b+cin; end
case;
end process p1;
end Behavioral;
VHDL TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY alutest IS
END alutest;
COMPONENT alu
PORT(
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
cin : IN std_logic;
sel : IN std_logic_vector(3 downto 0);
y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
BEGIN
a<="10010001";
b<="01010101";
cin<='1';
sel<="0000","1000" after 100ns;
END;
VERILOG CODE
module alu(clk, a, b,cin, opcode,
outp); input clk;
input cin; input
[7:0] a, b;
input [3:0] opcode;
output [7:0] outp;
endcase
end
endmodule
SIMULATION OUTPUT:
SYNTHESIS RTL SCHEMATIC:
RESULT:
Thus the OUTPUTs of Arithmetic Logic Unit are verified by synthesizing and simulating the VHDL and
VERILOG code.
EXP NO: 12 DATE:
BARREL SHIFTER
AIM:
To develop the source code for barrel shifter by using VHDL/VERILOG and obtain the simulation,
synthesis, place and route and implement into FPGA.
ALGORITHM:
LOGICAL DIAGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity barrel_shifter is
generic(n:integer:=7);
Port ( data : in STD_LOGIC_VECTOR (n-1 downto 0);
shift:integer range 1 to n-1;
r : in STD_LOGIC;
dataout : out STD_LOGIC_VECTOR (n-1 downto 0));
end barrel_shifter;
verilogmodule barrelshift(a,b,sh);
parameter N=8;
parameter shift=3; /*equal to log2(N)*/
input [N-1:0] a;
output [N-1:0] b;
input [shift:0] sh;
reg [N-1:0] b;
always @(sh or a)
case (sh)
3'b000: b = a;
3'b001: b = a>>1;
3'b010: b = a>>2;
3'b011: b = a>>3;
3'b100: b = a>>4;
3'b101: b = a>>5;
3'b110: b = a>>6;
3'b111: b = a>>7;
endcase
endmodule
VERILOG CODE
module barrel_shifter (data_out, data_in, load, clk,
reset); output [7:0] data_out;
input [7:0] data_in;
input load, clk, reset;
reg [7:0] data_out;
RESULT:
Thus the OUTPUTs of Barrel Shifter are verified by synthesizing and simulating the VHDL
and VERILOG code
EXP NO: 13 DATE:
AIM:
To develop the source code for traffic light controller by using VHDL/VEILOG and obtain the
simulation, place and route and implementation into FPGA.
ALGORITHM:
LOGIC DIAGRAM:
VHDL SOURCE CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tlc is
Port ( clk,rst : in STD_LOGIC;
g1,g2,g3,g4 : out STD_LOGIC_VECTOR (1 downto 0);
r1,r2,r3,r4 : out STD_LOGIC;
y1,y2,y3,y4 : out STD_LOGIC);
end tlc;
begin
p1:process(clk,rst)
begin
if(rst='1') then
present_state<=s1;
elsif(clk='1' and clk'event)
then case present_state is
when s1=>
if (counter=0) then
present_state<=s2;
y1<='1';
y2<='1';
y3<='0';
y4<='0';
counter<=c1;
else
present_state<=s1;
g1<="11";
g2<="00";
g3<="00";
g4<="01"; r1<='0';
r2<='1';
r3<='1';
r4<='1';
counter<=counter-1;
end if;
when s2=>
if (counter=0) then
present_state<=s3;
y1<='0';
y2<='1';
y3<='1';
y4<='0';
counter<=c1;
else
present_state<=s2;
g1<="01";
g2<="11";
g3<="00";
g4<="00";
r1<='1';
r2<='0';
r3<='1';
r4<='1';
counter<=counter-1;
end if;
when s3=>
if (counter=0) then
present_state<=s4;
y1<='0';
y2<='0';
y3<='1';
y4<='1';
counter<=c1;
else
present_state<=s3;
g1<="00";
g2<="01";
g3<="11";
g4<="00"; r1<='1';
r2<='1';
r3<='0';
r4<='1';
counter<=counter-1;
end if;
when s4=>
if (counter=0) then
present_state<=s1;
y1<='1';
y2<='0';
y3<='0';
y4<='1';
counter<=c1;
else
present_state<=s4;
g1<="00";
g2<="00";
g3<="01";
g4<="11";
r1<='1';
r2<='1';
r3<='1';
r4<='0';
counter<=counter-1;
end
if; end case;
end if;
end process;
end Behavioral;
VERILOG SOURCE CODE
module trafficlite(clk,rst,g1,g2,g3,g4,r1,r2,r3,r4,y1,y2,y3,y4);
input clk,rst;
output r1,r2,r3,r4,y1,y2,y3,y4;
reg r1,r2,r3,r4,y1,y2,y3,y4;
output [1:0]g1;
output[1:0]g2;
output[1:0]g3;
output[1:0]g4;
reg [1:0]g1;
reg[1:0]g2;
reg[1:0]g3;
reg[1:0]g4;
reg[1:0]state;
parameter s1 =
2'b00, s2 = 2'b01,
s3 = 2'b10 ,
s4 = 2'b11;
reg[1:0]counter;reg[1:0]c;
always@(posedge
clk) begin
if(rst==1'b1)
begin
state<=s1;
counter<=2'b11;
c<=2'b11;
end
else
begin
case (state)
s1:
begin
if (counter==2'b00)
begin
state<=s2;
y1<=1;
y2<=1;
y3<=0;
y4<=0;
counter<=c;
end
else
begin
state<=s1;
g1<=2'b11;
g2<=2'b00;
g3<=2'b00;
g4<=2'b01;
r1<=0;
r2<=1;
r3<=1;
r4<=1;
counter<=counter-
1; end
end
s2:
begin
if (counter==2'b00)
begin
state<=s3;
y1<=0;
y2<=1;
y3<=1;
y4<=0;
counter<=c;
end
else
begin
state<=s2;
g1<=2'b01;
g2<=2'b11;
g3<=2'b00;
g4<=2'b00;
r1<=1;
r2<=0;
r3<=1;
r4<=1;
counter=counter-1;
end
end
s3:
begin
if (counter==2'b00)
begin
state<=s4;
y1<=0;
y2<=0;
y3<=1;
y4<=1;
counter<=c;
end
else
begin
state<=s3;
g1<=2'b00;
g2<=2'b01;
g3<=2'b11;
g4<=2'b00;
r1<=1;
r2<=1;
r3<=0;
r4<=1;
counter=counter-1;
end
end
s4:
begin
if (counter==2'b00)
begin
state<=s1;
y1<=1;
y2<=0;
y3<=0;
y4<=1;
counter<=c;
end
else
begin
state<=s4;
g1<=2'b00;
g2<=2'b00;
g3<=2'b01;
g4<=2'b11;
r1<=1;
r2<=1;
r3<=1;
r4<=0;
counter=counter-1;
end
end
endcase
end
end
endmodule
SIMULATION OUTPUT:
RESULT:
Thus the OUTPUTs of Traffic Light Controller are verified by synthesizing and simulating the VHDL and
VERILOG code.
EXP NO: 14 DATE:
DESIGN OF MEMORIES
AIM:
To develop the source code for memories by using VHDL/VEILOG and obtain the simulation, place and
route and implementation into FPGA.
ALGORITHM:
BLOCK DIAGRAM:
RAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; USE
IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ram is
Port ( clk : in STD_LOGIC;
wr : in STD_LOGIC; addr:
in integer range 1 to 8;
datain : in STD_LOGIC_VECTOR (7 downto 0);
dataout : out STD_LOGIC_VECTOR (7 downto 0));
end ram;
begin
process(clk,wr)
BEGIN
if(clk='1' and clk'event)
then if(wr='1') then
mem(addr) <= datain;
else
dataout<=
mem(addr); end if;
end if;
end process;
end Behavioral;
VERILOG CODE
Module ram
(clk,wr,en,addr,di,do); input clk;
input wr;
input en;
input [7:0] addr;
input [7:0 ] di;
output [7:0] do;
reg [7:0] ram[31:0];
reg [7:0] do_r;
always @(posedge clk)
begin
if(en)begin
if(wr)
ram[addr]<=di;
else
do_r<=ram[addr];
end
end
endmodule
SIMULATION OUTPUT:
SYNTHESIS RTL SCHEMATIC:
ROM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; USE
IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ROMRO is
Port ( clk : in STD_LOGIC;
VERILOG CODE
module rominfr (clk, en, addr, data);
input clk;
input en;
input [4:0] addr;
output reg [3:0] data;
always @(posedge clk)
begin
if (en)
case(addr)
4b0000: data <= 4b0010;
4b0001: data <= 4b0010;
4b0010: data <= 4b1110;
4b0011: data <= 4b0010;
4b0100: data <= 4b0100;
4b0101: data <= 4b1010;
4b0110: data <= 4b1100;
4b0111: data <= 4b0000;
4b1000: data <= 4b1010;
4b1001: data <= 4b0010;
4b1010: data <= 4b1110;
4b1011: data <= 4b0010;
4b1100: data <= 4b0100;
4b1101: data <= 4b1010;
4b1110: data <= 4b1100;
4b1111: data <= 4b0000;
default: data <= 4bXXXX;
endcase
end
endmodule
SIMULATION OUTPUT:
SYNTHESIS RTL SCHEMATIC:
RESULT:
Thus the OUTPUTs of ROM and RAM are verified by synthesizing and simulating the VHDL and
VERILOG code.