ALS Assignments

Assignments / Labs
Assignment 1
AIM OF THE ASSIGNMENT:
Simulation of a Resistive circuits using Synopsys HSPICE, Study of CMOS Basics
ASSIGNMENT DESCRIPTION:
1. a. Design the following circuit
i. Find the voltage across 8 ohm resistor and current through 6k resistor by
using manually(Network analysis) at Vs=10v and do the same by using
HSPICE simulator and compare the manual and tool generated results?
ii. Find the transfer function of above network by using HSPICE simulator
and do the same using manually and compare the results?
iii. Perform the DC analysis as the Vs is vary from the 0 to 10v in the steps of
0.5v
b.
i. Write all possible symbol representation of PMOS, NMOS
ii. Implement sum, carry equation of HA using CMOS T
TIME LINES OF THE ASSIGNMENT:

The duration of the assignment is 1 week.
DELIVERABLES FOR THE ASSIGNMENT:

A document or an excel sheet describing your analysis, understanding and conclusions on the results
EVALUATION CRITERIA:
The assignment is evaluated for 10 marks.
5 Marks are awarded for the quality of the assignment deliverables
5 Marks are awarded for the your analysis and presentation
2D MATRIX
Remember Understand Apply Analyze Evaluate Create
Factual
Knowledge
Conceptual
Knowledge
Procedural
Knowledge
Meta
cognitive
Knowledge
Assignment - 2
Simulation of NMOS, PMOS transistors using Microwind and Drawing stick diagrams using
Eulers path
By using the Micro-wind Tool, Sketch the NMOS and PMOS Transistors at
layout level representations and simulate it for I-V characteristics, Transfer
characteristics? Vary the parameters like W, L, Vd, Vg, Vs, Vb and observe the
characteristics
Explain the rules for drawing stick diagram, draw the stick diagram for a
[A+BD]C function using Eulers path


A detailed report with Aim, Tools Used, procedure, Expected results, Observed
Results, Conclusions and summary of the assignment
A document or an excel sheet describing your analysis, understanding and
conclusions on the results
2D MATRIX

Factual
Knowledge
Conceptual
Knowledge
Procedural
Knowledge
Meta
cognitive
Knowledge
Assignment - 3
Simulation of NMOS, PMOS Transistors using HSPICE and Drawing layout diagrams
a. Plot the IV characteristics, Transfer characteristics of NMOS, PMOS Transistors

using tsmc35nm library.
b. Explain the layout design rules and draw the layout for CMOS inverter.


2D MATRIX
Factual
Knowledge
Conceptual
Knowledge
Procedural
Knowledge
Meta
cognitive
Knowledge
Assignment - 4
Simulation of CMOS Inverter, Current mirror using HSPICE
1.
a. Perform the Transient and DC analysis for a CMOS Inverter and plot the
Transfer curve, Input-Output voltages with respect to time?
b. Simulate and prove the functionality of a current mirror using HSPICE


2D MATRIX

Factual
Knowledge
Conceptual
Knowledge
Procedural
Knowledge
Meta
cognitive
Knowledge
Assignment - 5
Simulation of Special EXOR, EX-NOR Gates using Synopsys HSPICE
1. Perform transient analysis and observe the functionality of the following gates:
a. EX-NOR Gate using SUB CIRCUIT Instantiation of NOR Gate
b. EX-NOR gate using SUB CIRCUIT Instantiation of NAND gate

2D MATRIX
Factual
Knowledge
Conceptual
Knowledge
Procedural
Knowledge
Meta
cognitive
Knowledge
Assignment - 6
Pre-Post Synthesis Mismatch and Slack Analysis
Take a simple sequential flop, perform synthesis for it and analyze its schematic.
Consider a combinational logic with incomplete sensitivity list, perform synthesis for
it, analyze its schematic and observe the pre-post synthesis mismatch.
Consider an FSM design of a sequence detector (consider your own sequence) and
perform synthesis for it with different clock frequencies 500MHz, 800MHz and
1GHz.


1. Prepare a report on differences between 90nm Library and 32nm Library for an AND
cell & D-Flip Flop Cell. (For all possible combinations)
2. Timing Report (Try to make slack positive)
3. Area Report
4. QOR Report
5. Make a report on slack variation for different clock frequencies. - (For Question 3)
6. Mention the commands you have used to perform the synthesis flow
2D MATRIX
Factual
Knowledge
Conceptual
Knowledge
Procedural
Knowledge
Meta
cognitive
Knowledge
Assignment - 7
Analysis of Compile Schemes in Synthesis Flow
ASSIGNMENT DESCRIPTION :
1. Consider the FSM design in the previous assignment (Assignment 6), synthesize the
design with both compile & compile_ultra and analyze the differences between the
two compile schemes.
Synthesis Constraints to be applied:
1. Target Library : saed90nm_typ

2. Clock Frequency : 40 MHZ
3. Synthesis Methodology : Top Down Approach
4. Fan-out length : 1, 13.940 ( value, length)
5. Process: 1, Temperature: 25, Voltage: 1.2
Note: Add the remaining constraints accordingly. (If needed)


1. DC Script with Comments
2. DC Setup file
3. Make a report on the following for both compile & compile_ultra:
a. Timing
b. Area
c. QOR
4. Check_timing and check_design report (Both should be clean)
2D MATRIX
Factual
Knowledge
Conceptual
Knowledge
Procedural
Knowledge
Meta
cognitive
Knowledge
Assignment - 8
Power Analysis with Clock Gating
Consider the FSM design in the previous assignment (Assignment 6), synthesize the design
with clock gating (Refer lab-5) and report the differences between synthesizing the design
with clock gating and without clock gating.


1. DC Script
2. Power Report
3. Area Report
4. Timing Report
5. QOR Report
6. List the differences for Power & Area with & without Clock Gating
Note: Apply the same constraints as specified in the Assignment 7
2D MATRIX
Factual
Knowledge
Conceptual
Knowledge
Procedural
Knowledge
Meta
cognitive
Knowledge
Assignment - 9
Power Analysis with SAIF
Consider the FSM design in the previous assignment (Assignment 6), synthesize the design
with & without SAIF Files and observe the differences in Power Report.


1. DC Script
2. Power Report
3. Area Report
4. Timing Report
5. QOR Report
6. List the differences for Power with & without SAIF information.
2D MATRIX
Factual
Knowledge
Conceptual
Knowledge
Procedural
Knowledge
Meta
cognitive
Knowledge
Assignment - 10
Performing Static Timing Analysis for synthesized netlist and routed netlist
Consider the FSM design in the previous assignment (Assignment 6) and perform STA for
the synthesized and routed netlist.


1. PT script
2. Power Report
3. Area Report
4. Timing Report
5. Timing Histogram
6. QOR Report
2D MATRIX
Factual
Knowledge
Conceptual
Knowledge
Procedural
Knowledge
Meta
cognitive
Knowledge

ALS Assignments

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

ALS Assignments

Uploaded by

Copyright:

Available Formats

Assignments / Labs

Simulation of a Resistive circuits using Synopsys HSPICE, Study of CMOS Basics

1. a. Design the following circuit

TIME LINES OF THE ASSIGNMENT:

DELIVERABLES FOR THE ASSIGNMENT:

AIM OF THE ASSIGNMENT:

TIME LINES OF THE ASSIGNMENT:

DELIVERABLES FOR THE ASSIGNMENT:

Remember Understand Apply Analyze Evaluate Create

AIM OF THE ASSIGNMENT:

a. Plot the IV characteristics, Transfer characteristics of NMOS, PMOS Transistors

TIME LINES OF THE ASSIGNMENT:

DELIVERABLES FOR THE ASSIGNMENT:

AIM OF THE ASSIGNMENT:

Simulation of CMOS Inverter, Current mirror using HSPICE

TIME LINES OF THE ASSIGNMENT:

DELIVERABLES FOR THE ASSIGNMENT:

Remember Understand Apply Analyze Evaluate Create

AIM OF THE ASSIGNMENT:

Simulation of Special EXOR, EX-NOR Gates using Synopsys HSPICE

DELIVERABLES FOR THE ASSIGNMENT:

AIM OF THE ASSIGNMENT:

Pre-Post Synthesis Mismatch and Slack Analysis

TIME LINES OF THE ASSIGNMENT:

DELIVERABLES FOR THE ASSIGNMENT:

AIM OF THE ASSIGNMENT:

Analysis of Compile Schemes in Synthesis Flow

Synthesis Constraints to be applied:

1. Target Library : saed90nm_typ

Note: Add the remaining constraints accordingly. (If needed)

TIME LINES OF THE ASSIGNMENT:

DELIVERABLES FOR THE ASSIGNMENT:

AIM OF THE ASSIGNMENT:

Power Analysis with Clock Gating

TIME LINES OF THE ASSIGNMENT:

DELIVERABLES FOR THE ASSIGNMENT:

Note: Apply the same constraints as specified in the Assignment 7

AIM OF THE ASSIGNMENT:

Power Analysis with SAIF

TIME LINES OF THE ASSIGNMENT:

DELIVERABLES FOR THE ASSIGNMENT:

Note: Apply the same constraints as specified in the Assignment 7

AIM OF THE ASSIGNMENT:

TIME LINES OF THE ASSIGNMENT:

DELIVERABLES FOR THE ASSIGNMENT:

Note: Apply the same constraints as specified in the Assignment 7

You might also like