1

THEORY OF OPERATION

&

DESIGN ANALYSIS

OF

KLYSTRON POWER SUPPLY

by

Isaac Ozkaynak

Power Supply Consultants

 2

1. INTRODUCTION

The specification is given below.

1) Power: 500 W

2) Input voltage: 100 +/- 10 V

3) Output voltage: 1750 +/- 100 V

4) Power semiconductor derating: 70%

5) Output voltage regulation: 1%

6) Output voltage ripple: 1%

7) Efficiency: 0.94 (at full power)

8) Component weight: 1.8 kg (including input and output filters,

MOSFETs, transformers, rectifiers, and control circuitry but not

including mounting hardware or chassis)

9) Output stored energy: 2 J

10) Current-mode control

11) Control, input and output isolation

12) Adjustable output voltage

13) Short-circuit protected

14) Negative output

15) The final Klystron power supply will consists of four of these modules

connected in parallel on the input and in series on the output so that they can

operate at a total output voltage of 7000 V nominal.

 3

The approach taken for the implementation and its in depth discussion had already

been furnished in the previously submitted Design Concepts document and it will not be

repeated here for brevity.

2. NEW APPROACH TO THE IMPLEMENTATION

Figure 1 shows the power supply system arrangement. Each sub unit generates

1750V dc output voltage. The subunits are connected in parallel at their input ports and in

series at their output ports. Each sub unit is envisioned as identical in every circuit detail.

+
+
Unit 1 1750Vdc +
−

+
Unit 2 1750Vdc
−
100Vdc 7000Vdc
+
Unit 3 1750Vdc
−

+
Unit 4 1750Vdc −
−

Figure 1 – Klystron Power Supply System arrangement.

 4

Inside of each sub unit, there are

1 – A Main Power Processor, which generates 1750V output voltage,

2 – A Local House Keeping power supply, and

3 – A group of Feedback Control, Fault Protection, Input Current Inrush Limit

and external interface circuits for the external output voltage control and for

the external telemetry of experienced output voltage.

Figure 2 shows the topology of the main power processor, which is called Push-

Pull Forward Converter (PPF) . It has 14 isolated and center tapped secondaries, which

are connected in series. Each center tapped output, which we call cell, generates 125Vdc

and the total is 1750V. The turns ratio of secondary windings to primary windings is 2.

The choice of 125V for cellular outputs is based on the voltage rating of Radiation

Hardened Mosfet Switches. Currently, the only Megarad hardened MOSFETs, which are

available as off the shelf, and suitable for employment at the secondary side by their

electrical ratings, is 600V rated.

Figure 3 shows the gate drive waveforms of the Push-Pull Forward converter in

Figure 2. The primary switches are driven by pulse widths dictated by the control system.

However, the secondary switches are driven at fixed 50% duty ratio. The advantage of

this scheme is to prevent the voltage spikes at the drain terminals of the secondary

switches, since they are not clamped like the primary switches, when they are turned off.

Thus, the secondary switches are turned off at the end of the commutation sub intervals,

during which the secondary winding voltages are practically zero.

Before we proceed further, we need to develop both the steady state and the

Dynamic (AC Small Signal) models of the PPF Converter.

 5

Figure 2 – Topology of the main power processor.

 6

VGS1, VGS 2

TS
TS
2

TS
D⋅
2
0
t

VGS 3, VGS 4

0
t
Figure 3 – Gate Drive Waveforms of the PPF Converter.

3. MODELING OF PPF CONVERTER

For establishing the Large and Small Signal models, the PPF converter output

stages, Figure 2, need to be “folded in” to a single output. In multi output converters, only

one output can be subject to PWM control due to the singularity of output state variables
 7

i.e., there can be only one output state variable, voltage or current. This holds true on the

double, since we are not applying any “Weighted Control” on any other outputs, either.

In this folding-in process, all the other outputs along with their circuits are referred to the

output at which the PWM Control is applied. In this application, this process is facilitated

by the fact that all output circuits are identical. Thus,

1 – Output Filter Inductors are connected in parallel,

2 – Output Filter Capacitors are connected in parallel,

3 – Secondary Windings are respectively connected in parallel, and

4 – Secondary Synchronous Switches are respectively connected in parallel.

The “referred to single output or folded-in” topology is shown in Figure 4. During the

Q2
NP1 D2

Vg =100V NS1
Lf
C1

Q1 D3 Cf R
NP2 NS2
D1

Q3 Q4
−125V

Figure 4 – Folded-in Single Output PPF Converter.

 8

ON time sub interval of either one of the primary switches, the circuit connections are the

same and Figure 5 shows switching state for Q1 on time.

RS1 vo
Lσ 12 iL Lσ 34
RL n ⋅iL n
RP1 f n2 n2 f n ⋅io
Lf
n2 RC
Vg f
n2
N P1 vnp1 2 R
n2
Ron3 n2 ⋅ C f vC f
1 n2 n

Ron1

TS
Figure 5 – Switching State during Q1 on time subinterval, i.e., D ⋅ .
2

The State Space expressions for this switching state are derived and collected as

⎤ ⎡ ⎤
R R
⎡ diL f − e1 −
⎢
⎢ dt
⎥
⎥=⎢
⎢ Le1 (
n ⋅ Le1 ⋅ R + RC f ) ⎥ ⎡ 1 ⎤
⎥ ⎡ iL f ⎤ ⎢ ⎥
⎢ dvC f ⎥ ⎢ ⎥ ⋅ ⎢ v ⎥ + ⎢ Le1 ⎥ ⋅ vg (1)
⎥ ⎣⎢ C f ⎦⎥ ⎢⎣ 0 ⎥⎦
R 1
⎥ ⎢C ⋅ R + R −
⎢
⎣ dt ⎦ ⎢⎣ f Cf ( ) (
C f ⋅ R + RC f ) ⎥
⎦

where,

RS 1 RL Ron 3 R ⋅ RC f
Re1 = RP1 + n ⋅ Ron1 + + + + (2)
n n n n ⋅ R + RC f ( )
and
 9

Lf
Le1 = Lσ 12 + n ⋅ Lσ 34 + (3)
n

During the sub intervals of commutation, both of the primary switches are off. This sub

TS
interval is denoted as D′ ⋅ and defined as
2

TS TS T T
D′ ⋅ = − D ⋅ S = (1 − D ) ⋅ S → D′ = 1 − D (4)
2 2 2 2

During this sub interval, the secondary side commutates and the primary side clamp

capacitor charges. Figure 6 shows the secondary side switching state circuit.

RS1
n2 ⋅ Lσ 34 RL Lf iL vo
f io

RC
f
iL
f
1 iL
f iC R
2 f
2
Ron3 Cf

n2 ⋅ Lσ 23
RS 2

2
iL
f iL
2 f
D4
2

Figure 6 – Secondary Side during commutation sub interval.

 10

Q3 continues to conduct and the external anti-parallel diode of Q4, which is D4 is turned

on by the commutation, and the center tapped secondary windings are practically shorted.

In Figure 6, we justifiably assume, that

n 2 ⋅ Lσ 23 ≅ n 2 ⋅ Lσ 34
(5)
RS 1 ≅ RS 2

Therefore, there is no need for writing KVL equation for Loop 2. Furthermore, since

iL f
⋅ Ron 3 ≅ VD 4 (6)
2

in this particular application, the commutation currents flowing through the center tapped

secondary windings would approximately be equal. The State Space expressions for the

circuit in Figure 6 are derived and collected as

⎤ ⎡ ⎤
R R
⎡ diL f − e2 −
⎢
⎢ dt
⎥
⎥=⎢
⎢ Le 2 (
Le 2 ⋅ R + RC f ) ⎥
⎥ ⎡ iL f ⎤
⎢ dvC f ⎥ ⎢ ⎥ ⋅ ⎢v ⎥ (7)
⎥ ⎣⎢ C f ⎦⎥
R 1
⎥ ⎢C ⋅ R + R −
⎢
⎣ dt ⎦ ⎢⎣ f ( Cf ) (
C f ⋅ R + RC f ) ⎥
⎦

where

RS 1 + Ron 3 R ⋅ RC f
Re 2 = + RL + (8)
2 R + RC f

n2
Le 2 = ⋅ Lσ 34 + L f (9)
2
and

Le1 1
= (10)
Le 2 n

Eqn. (10) is only valid for the ideal converter.

 11

3.1 STEADY STATE SOLUTIONS

Through the application of X = − A−1 ⋅ b ⋅ Vg , we obtain and collect the steady

state solutions as

1
Vo = n ⋅ Vg ⋅ D ⋅ (11)
R R L ⎡ L ⎤1
n ⋅ D ⋅ e1 + n ⋅ e 2 ⋅ e1 ⋅ (1 − D ) +
⋅ ⎢ D + n ⋅ e1 ⋅ (1 − D ) ⎥
R ⎣
R Le 2 Le 2 ⎦RC f
1+
R
 

parasitics

and

n ⋅ Vg ⋅ D 1
I Lf = Io = ⋅ (12)
R R R L ⎡ L ⎤1
n ⋅ D ⋅ e1 + n ⋅ e 2 ⋅ e1 ⋅ (1 − D ) +
⋅ ⎢ D + n ⋅ e1 ⋅ (1 − D ) ⎥
R ⎣
R Le 2 Le 2 ⎦RC f
1+
R
 

parasitics

Solving Eqn. (11) for the variable D,

1 R
+ e2
RC f R
1+
D= R (13)
Vg Le 2 1 L ⎛ L ⎞ R R L
⋅ − ⋅ e 2 ⋅ ⎜ 1 − n ⋅ e1 ⎟ + e 2 − e1 ⋅ e 2
⎛ RC ⎞ L
n ⋅ ⎜ 1 + f ⎟ e1 ⎝
Vo Le1 Le 2 ⎠ R R Le1
⎝ R ⎠

The above expressions illustrate the effects of the Leakage Inductances in the

performance of a PPF Converter.

3.2 SMALL SIGNAL SOLUTIONS

The input voltage to state variable variations are given by

xˆ
= ( s ⋅ I − A) ⋅ b
−1
(14)
vˆg
 12

where

⎡ iˆL f ⎤
xˆ = ⎢ ⎥
⎢⎣ vˆC f ⎥⎦

⎡ s 0⎤
s⋅I = ⎢ ⎥
⎣0 s ⎦

⎡ Re1 Re 2 R⋅D R ⋅ (1 − D ) ⎤
⎢ − L ⋅ D − L ⋅ (1 − D ) − − ⎥
⎢ e1
A= ⎢
e2 (
n ⋅ Le1 ⋅ R + RC f ) (
Le 2 ⋅ R + RC f ) ⎥
R 1 ⎥
⎢ − ⎥
⎢
⎣ (
C f ⋅ R + RC f ) (
C f ⋅ R + RC f ) ⎥
⎦

⎡D⎤
b = ⎢ Le1 ⎥
⎢ ⎥ (15)
⎣⎢ 0 ⎦⎥

and

vˆo
= Gvd = C T ⋅ ( s ⋅ I − A) ⋅ b
−1
(16)
vˆg

where

⎡ R ⋅ RC f R ⎤
CT = ⎢ ⎥ (17)
⎣⎢ R + RC f R + RC f ⎦⎥

The exact expressions, and especially the system eigenfunction is too long to be furnished

here. Interested readers will find the exact expressions in the accompanying MathCAD

Analyses, “PPF_State_Space_Workout.mcd” and

“PPF_Klystron_Control_Secondary_Side_1.mcd”. Instead, we will furnish the plots of

these transfer functions here. Figure 7 shows the input voltage to inductor current transfer
 13

function. Figure 8 shows the plots of input voltage to output voltage transfer function.

This is the open loop Audio susceptibility.

Figure 7 – Plots of Input Voltage to Inductor Current Transfer function.

 14

Figure 8 – Plots of Input Voltage to Output Voltage transfer function.

 15

The duty ratio to the state variable variations are given by

xˆ
= ( s ⋅ I − A) ⋅ ⎡⎣( A1 − A2 ) ⋅ X + ( b1 − b2 ) ⋅ Vg ⎤⎦
−1

dˆ
(18)
vˆo
= C T ⋅ ( s ⋅ I − A) ⋅ ⎡⎣( A1 − A2 ) ⋅ X + ( b1 − b2 ) ⋅ Vg ⎤⎦
−1

dˆ

A1 , b1 and A2 matrices are given by Eqn. (1) and Eqn. (7), respectively, and b2 = 0 .

Figure 9 shows the plots of duty ratio to inductor current transfer function. We

can see, that the Current Injection Control (CIC, i.e., Current Mode) is not feasible for

this application. −20dB / dec. slope starts around 10 KHz. For taking advantage of the

slope and −90o phase, we need to arrange the intersection of voltage loop and inner

current loop around or close to 100KHz, which renders CIC inapplicable,

Figure 10 shows the plots of duty ratio to output voltage transfer function. The

shape of the plots suggest that the voltage mode control is feasible.

4. VOLTAGE MODE CONTROL

Voltage Mode Control implements two tier control via variable reference scheme.

With a near constant reference, the first tier controls the top most cellular output voltage,

Figure 2, to near -125V. The second tier controls the total output voltage to -1750V via

changing the variable reference of the first tier. Thus, the cellular output voltages may

experience limited deviation from 125V, but the total would be constant at -1750V. The

tacit assumption is that the limited deviations are acceptably small due to the fact that the

secondary side cellular output circuits are identical.

Figure 11 shows the error amplifier for the first tier. It senses the top most cellular

output voltage, whose positive port is tied to the load ground. It uses a variable reference
 16

Figure 9 – Plots of Duty Ratio to Inductor Current transfer function.

 17

Figure 10 – Plots of duty ratio to output voltage transfer function.

 18

vˆo′′
C p′′

Rz′′ R f ′′ C f ′′
R1′′
Cz′′
vˆc
R2′′
Ao

vˆR ⎛⎜⎜ s ⎞⎟⎟

⎝ ⎠

Figure 11 – Variable reference error amplifier.

which is generated by the Buffer Amplifier, Figure 12. In Figure 11, the error amplifier

transfer function for the ideal opamp is given by

vˆc ⎛ Z ′′f ⎞ vˆR Z ′′f

= ⎜1 + ⎟⋅ − (19)
vˆo′′ ⎝ Z i′′ ⎠ vˆo′′ Z1′′

where

⎛ 1 ⎞ R1′′⋅ (1 + s ⋅ CZ′′ ⋅ RZ′′ )

Z1′′ = R1′′// ⎜ RZ′′ + ⎟=
⎝ s ⋅ CZ′′ ⎠ 1 + s ⋅ CZ′′ ⋅ ( R1′′ + RZ′′ )
(20)
Z i′′ = R2′′ // Z1′′
 19

⎛ ⎞
vˆo ⎜⎜⎜ −1750V ⎟⎟⎟
⎝ ⎠
CP

CZ RF
R1

vˆo′ ⎜⎜⎜ +10V ⎟⎟⎟

⎛ ⎞
RO
⎝ ⎠

R2 RZ Ao′
Rb
CO R1′
Ra

R2′ Ao′
VR
vˆR ⎛⎜⎜ s⎞⎟⎟
Ra ⎝ ⎠

Rb

VR =5.1V

Figure 12 – Buffer Amplifier, which controls the variable reference.

and

1 + s ⋅ C ′′f ⋅ R′′f
Z ′′f =
s ⋅ ( C ′′f + C ′′p ) ⋅ (1 + s ⋅ Ce′′ ⋅ R′′f )
(21)
C ′′f ⋅ C ′′p
Ce′′ =
C ′′f + C ′′p

Notice, that Eqn. (19) would revert to an inverting amplifier transfer function, if we had

vˆR
used a constant reference voltage, since = 0 , then. For a Non-Ideal opamp, the Eqn.
vˆo′′

(19) becomes

vˆc Z i′′+ Z ′′f vˆ Z ′′⋅ Z ′′ 1

= ⋅ R− i f ⋅ (22)
vˆo′′ Z ′′f ⎛ 1 ⎞ vˆ′′ Z1′′ Z ′′f ⎛ 1 ⎞
+ Z i′′⋅ ⎜ 1 + ⎟ o + Z i′′⋅ ⎜ 1 + ⎟
Ao ⎝ Ao ⎠ Ao ⎝ Ao ⎠
 20

where Ao = open loop transfer function of the non-ideal opamp. In this particular

application, we use UC1825N for PWM IC. The built-in error amplifier in UC 1825N is

modeled as

27000
Ao ( s ) = (23)
⎛ s ⎞ ⎛ s ⎞
⎜1 + ⎟ ⋅ ⎜1 + 6 ⎟
⎝ 2 ⋅ π ⋅ 200 ⎠ ⎝ 2 ⋅ π ⋅ 5.5 ⋅ 10 ⎠

from the published data on the device by the manufacturer, Unitrode/Texas Instrument.

The Buffer amplifier in Figure 12 scales the output voltage of -1750V (HV) and

buffers it with a low gain. It uses 800 KRad hardened power opamp, LM6172, with

50mA sink or source capability. LM6172 is also a wide bandwidth and high slew rate

device. One slight disadvantage in LM6172 employment is, that it requires dual polarity

bias supply, particularly, ±15V . The open loop transfer function of LM6172 is modeled

as

s
172 1+
Ao′ ( s ) = 10 20
1
⋅ ⋅ 2 ⋅ π ⋅ 50 ⋅ 106 (24)
2
s ⎛ s ⎞
⎜ 1 + 6 ⎟
⎝ 2 ⋅ π ⋅ 80 ⋅ 10 ⎠

from the published data by the manufacturer. Figure 13 shows the plots of Eqn. (23) and

Eqn. (24).. Using the values of

R1′′ = 121K Ω
R2′′ = 5.11K Ω
R′′f = 4.99 K Ω
Rz′′ = 499Ω (25)
C z′′ = 470 pF
C ′′f = .018µ F
C ′′p = 0
 21

Figure 13 – Plots of UC1825N opamp open loop transfer function.

 22

Figure 14 shows the plots of error amplifiers of ideal and non-ideal opamps.

Figure 14 – Plots of Variable Reference Error Amplifier in Figure 11.

 23

The first amplifier in Figure 12 generates an output voltage across CO of 10V, when the

output voltage is 1750V. This is further scaled and applied to the following differential

amplifier, which generates a variable reference voltage at its output. This variable

reference voltage is centered at the median value of +5.1V, and changed according to the

deviation of HV from the targeted value of -1750V. In turn, the variable reference is used

by the error amplifier in Figure 11 for correcting the deviation.

The differential amplifier output voltage expression for an ideal opamp is given

by

Rb
vˆR = ⋅ ( vˆ A − vˆB ) + VR (26)
Ra

where v A = VR . The differential amplifier transfer function is obtained as

vˆR ( s ) R2′ R
A1 ( s ) = =− ⋅ b (27)
vˆo′ R1′ + R2′ Ra

for the ideal opamp. For the non-ideal opamp, the eqn. (26) becomes

Rb Ra
vˆR ( s ) = ⋅ ( vˆ A − vˆB ) + ⋅ VR (28)
Rb ⎛ 1 ⎞ Rb ⎛ 1 ⎞
+ Ra ⋅ ⎜ 1 + ⎟ + Ra ⋅ ⎜ 1 + ⎟
Ao′ ⎝ Ao′ ⎠ Ao′ ⎝ Ao′ ⎠

and Eqn. (27) becomes,

vˆR ( s ) R2′ Rb
A1′ ( s ) = =− ⋅ (29)
vˆo′ R1′ + R2′ Rb ⎛ 1 ⎞
+ Ra ⋅ ⎜ 1 + ⎟
Ao′ ⎝ Ao′ ⎠

From Eqn. (19), we obtain, that

vˆc ⎛ Z ′′ ⎞ vˆ Z ′′ vˆ′′
= ⎜1 + f ⎟ ⋅ R − f ⋅ o (30)
vˆo ⎝ Z i′′ ⎠ vˆo Z1′′ vˆo

where
 24

vˆR vˆR vˆo′

= ⋅ (31)
vˆo vˆo′ vo

and

vˆo′′ 1
= , m = 14 (32)
vˆo m

The Eqn. (32) is based on the assumption of 14 identical output stages were stacked. The

HV Buffer Amplifier transfer function is given by

vˆo′ R2 R ⋅ R 1 + s ⋅ CZ ⋅ RZ 1
Avb ( s ) = = ⋅ F O⋅ ⋅ (33)
vˆo R1 + R2 RZ 1 + s ⋅ CP ⋅ RF 1 + s ⋅ CO ⋅ RO

for the ideal opamp. Using the assumption of RZ  R2 , the same transfer function

becomes

R2 ⋅ RO ZF 1
′ ( s) =
Avb ⋅ ⋅ (34)
R1 + R2 Z F ⎛ 1 ⎞ 1 + s ⋅ CO ⋅ RO
+ Z I ⋅ ⎜1 + ⎟
Ao′ ⎝ Ao′ ⎠

where

RF
ZF =
1 + s ⋅ CP ⋅ RF
(35)
RZ
ZI =
1 + s ⋅ CZ ⋅ RZ

for the non-ideal opamp. Using Eqn.(27), (31), (32) and (33) in Eqn. (29), we obtain

vˆc ⎛ Z ′′ ⎞ Z ′′ 1
Fv ( s ) = = ⎜ 1 + f ⎟ ⋅ A1 ( s ) ⋅ Avb ( s ) − f ⋅ (36)
vˆo ⎝ Z1′′ ⎠ Z1′′ 14

for the ideal opamps. Using Eqn. (29), (31), (32) and (34) in Eqn (22), we obtain,

vˆc Z i′′+ Z ′′f Z ′′⋅ Z ′′ 1 1

Fv′ ( s ) = = ⋅ A1′ ( s ) ⋅ Avb
′ ( s) − i f ⋅ ⋅ (37)
vˆo Z ′′f ⎛ 1 ⎞ Z1′′ Z ′′f ⎛ 1 ⎞ 14
+ Zi ⋅ ⎜1 + ⎟ + Zi ⋅ ⎜1 + ⎟
Ao ⎝ Ao ⎠ Ao ⎝ Ao ⎠
 25

for the non-ideal opamps. Figure 15 shows the plots of Eqn. (36) and (37).

Figure 15 – Plots of entire error amplifier chain transfer function.

 26

Finally, we obtain the voltage loop transfer function as

Tv ( s ) = FM ⋅ Gvd ( s ) ⋅ Fv ( s ) (38)

for ideal opamps and

Tv′ ( s ) = FM ⋅ Gvd ( s ) ⋅ Fv′ ( s ) (39)

for non-ideal opamps. Using the values of

R1 = 1.74 M Ω
R2 = 5.11K Ω
RZ = 49.9 K Ω
CZ = 680 pF
RF = 100 K Ω
CP = 8.2 pF
(40)
RO = 49.9
CO = .022 µ F
R1′ = 4.99 K Ω
R2′ = 5.11K Ω
Ra = 49.9 K Ω
Rb = 10.0 K Ω

Figure 16 shows the plots of voltage loop expressions of Eqn. (38) and (39). We have

intentionally brought about an approximate cross over frequency of 6KHz with 87o

phase margin for cautionary reasons due to HV noise. In a fabricated physical unit, one

can experiment for going up to 10KHz .

The open loop output impedance of one cell is given by

⎛ ⎞
(R+ s ⋅ L f ) ⋅ ⎜ Rc +
L ⎜
1
s ⋅Cf
⎟⎟
Z P = 14 ⋅ ⎝ ⎠ (41)
1
RL + s ⋅ L f + Rc +
s ⋅Cf

where
 27

Figure 16 – Plots of Voltage Loop expressions.

 28

RL = .251Ω
L f = 300 µ H
(42)
Rc = 11.69mΩ
C f = 18µ F

The factor of 14 in Eqn. (41) stems from the fact, that all output stages are stacked up.

The closed loop output impedance expression is

ZP
Zo ( s ) = (43)
1 + Tv

for the voltage loop control. Figure 17 shows the plots of Eqn. (43). The maximum closed

loop output impedance is predicted as Z o = 110Ω for all frequencies, and the step load

deviation is predicted as 1.82% at the output of -1750V for .287 A load current

excursion.

Finally, the closed loop audio-susceptibility is given by

Gvg
G A ( s ) = 14 ⋅ (44)
1 + Tv

Figure 18 shows the plots of Eqn. (44). From Figure 18, we predict about 3.3% deviation

of the output voltage of -1750V for a ±10V step input voltage change.
 29

Figure 17 – Plots of Closed Loop Output Impedance expression.

 30

Figure 18 – Plots of Closed Loop Audio-susceptibility transfer function.

 31

5. FAULT PROTECTION

Throughout the load current range, i.e., from no load or open load to the nominal

maximum load, which is about .286A at -1750V, the PPF Converter would operate, as if

it were under CCM regime due to inductor current reversal facilitation at the secondary

through synchronous switch use. What should be done, when the load current exceeds

this .286A or the output shorts.

We can not employ dynamically control over the DC load current in this

application. Theoretically feasible though, but impractical due to very small duty ratios,

that it would impose. For example, under high quality short circuit, the output voltage at

.1
the cellular level may be .1V. With a 220V input, this would entail = .045% duty
220

ratio, and about 4.5ns On Time for the primary switches at 100KHz . This very reasoning

is also valid, if the CIC were applicable. Only the quadratic converters can cope with this

large input-output voltage difference under fault conditions, but they are inefficient for

the purpose of this application.

The next best alternative is to shutdown the converter upon fault condition,

subject to automatic recovery with periodicity. In this way, when the DC output current

exceeds a certain threshold, the unit is shutdown. This shutdown removes the “cognition”

of the fault condition, and thereby restarts the converter, subject to soft start each time.

The fault condition is defined as externally imposed over load and/or short circuit

condition. It does not, however, include internal causes, i.e., internal to the PPF

Converter.

Figure 19 shows the fault current sense arrangement. Since the return of control

electronics and the load is common, we would be sensing a positive voltage drop across
 32

Figure 19 – Fault Current Sense arrangement.

 33

the DC current sense resistor, Rcs . Although, we considered sensing a negative voltage

VCC = +15V

1KΩ vˆo′ ⎜⎜⎜ +5.1V ⎟⎟⎟

⎛ ⎞ 15KΩ
+vˆcs ⎝ ⎠
1KΩ
RZ Ao′
Rcs TO F / F
RO Ao′
100mΩ RF CO

1KΩ
1KΩ
CF

VR =5.1V
R1 1KΩ

Figure 20 – Fault Current Sense Circuit.

drop via placing the load ground at the other end of Rcs , but we chose the above approach

based on the Bode Plots of sense amplifier transfer functions. However, there is no

difference between the two alternatives with regard to first 2ms – 5ms of their unit step

response, examined by taking the inverse Laplace transforms of their transfer functions.

At the fault current level of .35A , the sensed voltage is amplified to a voltage

level of about 5.1V across CO , Figure 20. This voltage is then compared to 5.1V

reference and the Mosfet is driven to off state, if the current exceeds .35A. The sudden

rise of Mosfet drain voltage triggers a fast and Retriggerable monostable, Figure 21, and

brings about a forced low at the Soft Start, and forced high at the Shutdown
 34

Figure 21 – Retriggerable Monostable circuit.

terminals of the PWM IC. By the design of the monostable IC, MC14538BCD, the Q

output pulse duration is given by

T = Rx [ Ω ] ⋅ C x [ F ] (45)

In this application, we set it at 124ms , but it can easily be extended to longer durations.

Q and Q outputs drive very low input capacitance Mosfets, which, in turn, bring about

forced low at the Soft Start, and forced high at the Shutdown terminals of the PWM IC.

The application circuit is included in Sheet 3 of the Schematic Insert.

6. INRUSH CURRENT CONTROL

Due to both the conducted EMI Filter at the main converter input and the clamp

capacitor of the PPF Converter, an in-rush current is experienced when the power is

applied to the 100V Bus. This inrush current is mitigated by use of a temporary resistor in

series with the power bus. The magnitude of the resistor is chosen to reduce the peak
 35

inrush current to a magnitude to less than 10 amperes. Figure 22 shows the in-rush

Figure 22 – Inrush Current Limit circuit.

 36

current limit circuit. The two paralleled Mosfet switches are turned on after an about 2s

of time out period elapses. The intend here is to turn them on, when the EMI filter

capacitors are completely charged up the to Bus Voltage level. Figure 23 shows the

Figure 23 – Simulation data for the in-rush phase.

 37

simulation plots. The top plot is the EMI Filter Capacitor Voltage. The middle plot

depicts the rail voltage build up for the HKPS PWM IC, and the bottom plot is the in-rush

current profile. The HKPS PWM IC rail voltage reaches the threshold for the HKPS to

start. It declines to the Under Voltage Lock Out (UVLO) level within about 30ms, which

is a sufficient time to complete the HKPS start up.

Once the HKPS reaches steady state, the Mosfet switches of the in-rush limit

circuit, Figure 22, are not turned on for another one second. The reason is to allow the

EMI Capacitor Voltages to completely reach the bus voltage level for preventing any

likely excessive current in the P-Channel Mosfet switches. Then, in the further next one

second, the Main Power Processor starts in soft start fashion.

The power dissipated in the in-rush current limiter during this approximately 1.5

seconds, until the P-Channel Mosfet switches turn on,

1 ⎛ ⎞ ⎛ Vg −τt ⎞
T t
−

T ∫0 ⎝
P= ⎜ g
V ⋅ e τ
⎟⋅⎜ ⋅e ⎟ ⋅ dt ≅ 31.7W (46)
⎠ ⎝R ⎠

where

τ = .0942 s
R = 12Ω (47)
Vg = 110V

τ = exponential time constant, measured from Figure 23. We would be using a 100W

rated and TO-247 Case resistor. The power dissipation by the transient in-rush current

limit function does not pertain to the efficiency concern of the sub unit.
 38

7. OPERATIONAL PERFORMANCE

Other than the discussed topics above, the most important next issue is the

operational performance. In the above, we furnished how the primary elemental blocks

worked. In this section, we examine “how does the sub unit work?” along with the

uncovered minor details in the above. In the proceeding, we will also cover the power

losses as we encounter along the way.

The operation starts with DC Power being applied to the main power bus.

Through the in-rush current limit circuit, the initial in-rush current peak is limited to less

than 8A. Figure 24 shows the simulation circuit. As we observe, the Input EMI Filter is a

Figure 24 – PSIM Simulation Circuit for In-Rush Transient.

Pi Filter. R3, C1, Z1, R4 and DIAC2 functionally simulate the Bootstrap start up circuit

of the PWM IC. When the voltage across C1 reaches 16V, the load of about 100mA is

activated via DIAC2. Figure 23 shows the related salient waveforms. During this input

capacitor charge up period, in the first 400ms, the HKPS starts. HKPS generated bias

voltages quickly power the In-Rush Control Time Delay circuit, Figure 25. Until about

one second delay introduced by this circuit elapses, nothing happens. EMI Filter
 39

Figure 25 – In-Rush Control Time Delay circuit.

capacitors sit there, all charged up. When the In-rush Control Time delay elapses, The P-

Channel Mosfets in Figure 22 are turned on and locked in the On State. Thus, at this

moment,

1 – All Primary Side Capacitors are charged up to the Bus Voltage level,

2 – All HKPS outputs already settled at their steady state values, and

3 – The main power processor has not started yet.

Meanwhile, the Start-up Delay Circuit, Figure 26, which was powered up at the same

with the In-Rush Control Delay Circuit by the HKPS, but has twice the time delay length,

is ramping up to the moment, at which it will release the Soft Start port of the PWM IC

for starting the main power processor. When 2s time delay elapses, Q60 in Figure 26 is

turned off , and thus, the soft start of the main power processor is initiated.
 40

Figure 26 – Startup Delay Circuit.

The simulation circuit of the main power processor is too large for embedded here.

Instead, we will discuss its performance through the simulation waveforms. The reader is

advised to view the circuit schematic of the main power processor in sheets 1 & 2 of the

inserts. PSIM Software used in these simulations has some important limitations,

1 – The opamp models have unlimited current sourcing capability, and

2 – Simulations of time durations greater than 100ms takes too long and often

times returns error messages.

Therefore, it is next to impossible to simulate the start up operation with programmed 1s

soft start of the Main Power Processor. Instead, we furnish here what appears to be an

“accelerated” start-up, but nevertheless, a good indication of the robust stability of

 41

Figure 27 – Startup of the main power processor, referred to the cellular voltage.

feedback control design. On a physical sub unit, the ramp up section in Figure 27 would

take about 1s. The reason for that is to mitigate the output filter inductor currents to a

level close to their steady state nominal maximum. Otherwise, we have to design those

inductors for several times larger DC and HF AC current levels, thus ending up with

heavier magnetics.

The above mentioned limitations of the PSIM Software do not prevent obtaining

the steady state switching waveforms of the converter circuit. Figure 28 shows the

primary switch current under full load of 500W. We measure 5.7 A as the rms value of

the primary switch current. Thus, the device dissipation is

PPD = .11Ω ⋅ ( 5.7 ) ≅ 3.57W

2
(48)

Since there are two primary switches, the total power consumption would be 7.14W. This

is at the low line voltage of 90V. Figure 29 shows the primary winding currents. Again
 42

Figure 28 – Primary switch current and voltage waveforms.

we measure 4.94A as the rms value. Thus, the winding loss is

PP = 15mΩ ⋅ ( 4.94 ) ≅ .366W

2

(49)
PPT = .366W ⋅ 2 = .732W

The clamp capacitor does not experience any appreciable power dissipation due to

extremely low ESR of the MLC capacitor used. Finally, on the primary side, the input

current to the converter and the input current to the EMI Filter is shown in Figure 30.

On the secondary side, we examine the cellular level waveforms. Figure 31 shows

the output filter inductor current waveform under full load. We measure .199A as the rms

current. Thus, the power dissipation of one inductor is

PLcu = .251Ω ⋅ (.199 ) ≅ 10mW

2
(50)
 43

Figure 29 – PPF Main converter primary winding current waveforms.

Along with the core loss of

PLcore = 15.2mW

PLt = PLcu + PLcore = 25.2mW (51)

PLT = 14 ⋅ 25.2mW ≅ 353mW

Figure 32 shows the secondary synchronous switch current and voltage waveform. These

switches are driven at almost 50% duty ratio. During their off state time interval, their

anti-parallel diodes turn on for the commutation sub interval. From Figure 32, we

measure .142 A as the switch rms current. Thus, the secondary synchronous switch loss is

PSD = .6Ω ⋅ (.142 A) ≅ 12mW

2
(52)
 44

Figure 30 – Main converter input current (Top) and EMI filter input current (bottom).

The total secondary synchronous switch losses is 24 mW per cellular output The grand

total secondary switch losses for the main converter is then .336W. We should not feel

concerned about the glitch seen in Figure 32, bottom trace, since the device current is

zero during that very narrow interval, Figure 33.

Since the secondary winding currents are the same as the synchronous switch

currents, the secondary winding losses are

PS = .18Ω ⋅ (.142 A) ≅ 3.7mW

2

PSt = 3.7mW ⋅ 2 = 7.4mW (53)

PST = 14 ⋅ 7.4mW = .1036W

 45

Figure 31 – Cellular output filter inductor current waveform under full load.

Figure 32 – Secondary synchronous switch current and voltage waveform.

 46

Figure 33 – Magnified view of Figure 32 at the vicinity of the device voltage glitch.

From Figure 30, we measure the input current to the EMI Filter as 5.6893A. Thus, the

power loss in the P-Channel Mosfet switches for the In-Rush Control,

PI = .051Ω ⋅ ( 5.6893) ≅ 1.65W

2
(54)

Using the HF transformer core losses from the previously submitted document, we can

now arrange Table 1 for an initial assessment on the efficiency of the Main Power

Converter. We will update Table 1 later, with the loss estimates from the HKPS.
 47

TABLE 1

Cell Level Total at Full Power (500W)

HF Transformer Primary Losses N/A .732W

HF Transformer Secondary Losses .0074W .1036W

HF Transformer Core Losses N/A 2.1W

Output Inductor Losses .0252W .353W

Primary Switch Losses N/A 7.14W

Secondary Switch Losses .024W .336W

In-Rush Limit Switch Losses N/A 1.65W

TOTAL LOSSES 12.415W

EFFICIENCY 97.57%

EFFICIENCY WITH HKPS 97.55%

8. HOUSE KEEPING POWER SUPPLY (HKPS)

HKPS is based on the same topology with the Main Power Processor, i.e., PPF

Converter. This is because, it is one of the two most efficient topologies, and it is par with

the BIFPPF in most applications. Figure 34 shows the topological circuit of the HKPS,

which generates two sets of ±15V . One set is return referenced to the Main PPF

Converter Secondary, and it powers all control and sense electronics, which are also

return referenced the secondary. The other set is return referenced to the primary side of

the Main PPF Converter, and powers all the electronics at that side. The HKPS PWM IC

is return referenced to the Primary Side of the Main PPF Converter, therefore, the

feedback control is primary return referenced. Neither at the primary side, nor at the
 48

Figure 34 – HKPS Topological circuit.

secondary side, the peripheral support electronics do require a very precise regulation of
 49

the bias or rail voltages of ±15V . Furthermore, the loads, which appear as averaged DC

currents, are pseudo constant, determined by the average current need of the constant

number of “entities” they represent. During the switching transition sub intervals, the

relatively large load current excursions, especially at the +15V rails, are absorbed or

provided by the relatively large value output filter capacitors or intentional large value

ceramic bypass capacitors at the bias ports of the power client ICs.

The HKPS open loop transfer functions are derived in as much the same way as

the Main Converter. Therefore, we would furnish the summary plots of some important

ones, here.. Like in modeling the main power processor, we “fold” the secondary circuits

and refer them to the secondary circuit, where the feedback control is applied. Figure 36

shows the duty ratio to inductor current transfer function. The same reasons of why we

can not apply CIC are valid here, also. Any CIC arrangement would entail a cross over

frequency in the range of 50 KHz − 100 KHz , thus it is impractical, unless we use larger

inductance values, and therefore, heavier magnetics for the output filter inductors.

Nevertheless, the voltage mode control is quite satisfactory, and it is employed here.

Figure 37 shows the duty ratio to output voltage transfer function plots. We

observe that the HKPS is near open loop stable with an approximate 1 KHz cross over

(with FM included) and some sufficient phase margin for better than conditional stability.

The satellite output of the HKPS, which does not have the feedback control, would be

experiencing this feature for load only variations.

The error amplifier for the HKPS is practically the same circuit as in Figure 11

with the exception that it uses a constant reference, which is generated by the PWM IC.

Figure 38 shows the voltage error amplifier of the HKPS. It is the same circuit in
 50

Figure 36 – Plots of Duty Ratio to Inductor Current transfer function.

Figure 11, with the exception of component values and the use of constant reference

voltage, which is taken from its PWM IC. For the component values of
 51

Figure 37 – Plots of duty ratio to output voltage transfer function.

 52

vˆo
Cp

Rz Rf Cf
R1
Cz
vˆc
R2
Ao

VREF = 5.1V

Figure 38 – Error amplifier circuit for the HKPS.

R1 = 10.0 K Ω
R2 = 5.11K Ω
R f = 48.7 K Ω
Rz = 499Ω (55)
C f = .033µ F
C z = .0047 µ F
Cp = 0

Figure 39 shows the error amplifier transfer function plots for both the ideal and
 53

Figure 39 – HKPS Error Amplifier Transfer Function Plots.

 54

non-ideal opamps. Figure 40 shows the plots of voltage closed loop expression. We have

placed the cross over frequency to a cautious 4 KHz for keeping the second order peak at

around 50 KHz, -20dB or less. We measure approximately over 87o phase margin.

Figure 41 shows the closed loop output impedance transfer function plots. We measure

approximately Z o ≅ .024Ω which is a good value for an HKPS.

HKPS output power distribution is arranged as

1 – Two isolated +15V outputs are rated for 1A, each,

2 – Two isolated -15V outputs are rated for .5A each.

Table 2 summarizes the power losses of HKPS.

TABLE 2

Cell Level Total at Full Power (45W)

HF Transformer Primary Losses N/A .043W

HF Transformer Secondary Losses .0074W .0975W

HF Transformer Core Losses N/A .344W

Output Inductor Losses .0252W .305W

Primary Switch Losses N/A .069W

Secondary Switch Losses .024W .414W

TOTAL LOSSES 1.273W

EFFICIENCY 97.25%
 55

Figure 40 – Plots of voltage closed loop expression.

 56

Figure 41 – Closed Loop Output Impedance plots for the HKPS.

 57

9. REMOTE TELEMETRY

The main converter output voltage is scaled down to about -5V and amplified to

+10V across CO in Figure 42. This 10V becomes the bus voltage to the mini PPF

converter. Using 1 1 turns ratio, and constant duty ratio of near 50%, we transfer the

⎛ ⎞
Vo ⎜⎜⎜ −1750V ⎟⎟⎟
⎝ ⎠

CZ RF
R1

RO

R2 RZ Ao′
Q2
CO
RZ
NP1 D2

NS1
Vo
scale
C1

D3
Cf R Q1
NS2 D4 NP2
D1

Figure 42 – Telemetry circuit for the output voltage.

output voltage info to an external circuit via galvanic isolation. Employing .1% resistors
 58

in the sense amplifier circuit, telemetry with 5% or less worst case accuracy if feasible.

Selecting,

CO ⋅ RO = CZ ⋅ RZ
(56)
RZ  R2

the voltage across CO becomes

R2 R
Vo′ = ⋅ F (57)
R1 + R2 RZ

The estimate of worst case accuracy of this approach to the telemetry is not within the

scope of this report. However, it is strongly believed that a 5% or less accuracy should

be feasible with trimming of R2 and/or RF The load of the mini PPF Converter at its

secondary output port is assumed to be several KΩ . We need to point out here, that the

bandwidth of the mini PPF converter is limited to several hundred Hertz, and therefore

the remote telemetry is low bandwidth.

The remote control of the main PPF converter is established via another mini PPF

whose bus voltage is envisioned as variable 10V and the secondary output voltage is 5V

through 2/1 turns ratio. This PPF converter is driven by the telemetry PPF converter gate

signals through gate drive transformers. Its circuit is similar to that shown in Figure 42

without the buffer amplifier circuit. Its output follows the input bus voltage and becomes

the variable external reference voltage to the main converter.

 59

10. GATE DRIVE LOSSES

The main power processor has total 28 Mosfet Switches. IRHM7C50SE, at its

secondary. Their maximum total gate charge is 150nC. Thus, each device, switching at

100 KHz, requires

PG = Qg ⋅ VG ⋅ f S = 150nC ⋅ 15V ⋅ 100 KHz ≅ .225W (58)

as maximum Gate Power Consumption. The total gate power consumption of the

secondary switches is then,

PGST = .225 ⋅ 28 = 6.3W (59)

The main PPF converter has four Mosfet switches, IRHM8360, at its primary. Their

maximum total gate charge is 210nC. Thus, the total gate drive power consumption at the

primary,

PGPT = 4 ⋅ 210nC ⋅ 15V ⋅ 100 KHz ≅ 1.26W (60)

The total gate drive power consumption of the main PPF converter is then, 7.56W .

Furthermore, the HKPS has 8 Mosfet switches, IRHF8130 (IRHF7130) at its

secondary. Their total gate charge is 50nC, and each one may consume maximum 75mW.

Thus, the total secondary gate power consumption is

′ = .075W ⋅ 8 = .6W
PGST (61)

The HKPS primary switches are IRHM8360, and likewise,

′ = 2 ⋅ 210nC ⋅ 15 ⋅ 100 KHz = .63W

PGPT (62)

Moreover, the two remote telemetry PPF Converters may experience a maximum of

PGtele = 4 ⋅ 11nC ⋅ 15V ⋅ 100 KHz = 66mW (63)

 60

We update the previous Table 1 as shown in Table 3.

TABLE 3

Cell Level Total at Full Power (500W)

HF Transformer Primary Losses N/A .732W

HF Transformer Secondary Losses .0074W .1036W

HF Transformer Core Losses N/A 2.1W

Output Inductor Losses .0252W .353W

Primary Switch Losses N/A 7.14W

Secondary Switch Losses .024W .336W

In-Rush Limit Switch Losses N/A 1.65W

Gate Drive Losses of the Main N/A 7.56W

HKPS Losses N/A 1.273W

HKPS Gate Drive Losses N/A 1.23W

Gate Drive Losses of the Telemetry N/A .066W

TOTAL LOSSES 22.546W

TOTAL EFFICIENCY 95.68%

Thus, the total sub unit is highly likely to meet about 95% efficiency, when

an additional 3.7W is added as the "cumulative minor miscellaneous losses”.