FPGA Power Consumption Measurements and
Estimations Under Different Implementation
Parameters
Dimitrios Meidanis Konstantinos Georgopoulos
Department of Electronic and Department of Electronic and
Computer Engineering Computer Engineering
Technical University of Crete Technical University of Crete
Kounoupidiana, Chania, 73100, Greece Kounoupidiana, Chania, 73100, Greece Kounoupidiana, Chania, 73100, Greece
Email: dmeidanis@mhl.tuc.gr Email: kgeorgopoulos@isc.tuc.gr
AbstractThis paper investigates the effects of different design
tool (Xilinx ISE) optimisation schemes on FPGA power con-
sumption. Specifically, on-the-bench measurements are presented
for eight highly popular security algorithms, which have been
tested under a number of different synthesis and implementation
optimisation scenarios. The algorithms under investigation are
the BasicRSA, BasicDES, Camellia (with two distinct variations),
TripleDES, AES, DES, and MD5. Finally, the efficiency of the
design tool in generating accurate predictions on the power
consumption of a specific design is also addressed.
Results show that power consumption figures may vary from
a 306mW reduction (compared to nominal design effort) to a
33mW increase and average improvement on the power consump-
tion measured values ranges between 9.21% and -0.94% when
different optimisation schemes are utilised. The Xilinx XPower
Analyzer is also scrutinised; It provides estimates that are well
above what is actually measured and the estimation error ranges
between 17.5% to more than 200%. In the worst case, the XPower
estimate is 307mW greater than the least power consumption
value measured on-the-bench whereas it remains 258mW higher
than the average value measured for the same algorithm and
under all different optimisation scenarios. The least deviation
in results is measured between 23mW and 31mW, however, the
XPower estimate remains greater than that measured on-the-
bench.
Index TermsAES, DES, 3DES, Basic DES, RSA, Camellia,
MD5, Xilinx, FPGA, Power Estimation
I. INTRODUCTION
Contemporary FPGAs exhibit many millions of transistors
and this pushes the static power consumption of the chip to
unacceptable levels. In addition, the post-fabrication flexibility
provided by these devices is implemented using a large number
of pre-fabricated routing tracks and programmable switches,
which consume a significant amount of power every time
they switch. In addition, the programmable switches add
capacitance to each track, which further increases the power
dissipation of the FPGA.
This paper demonstrates, for the first time, the effects that
different design tool optimisation schemes have on FPGA
power consumption as well as the accuracy of those tools
978-1-4577-1740-6/11/$26.00
c 2011 IEEE
Ioannis Papaefstathiou
Department of Electronic and
Computer Engineering
Technical University of Crete
Email: ygp@mhl.tuc.gr
when estimating the overall power consumption of the device.
At the same time, it investigates the existence of a specific
optimisation scheme that leads to the minimisation of power
dissipation.
In order to perform this analysis, a number of encryption
and authentication algorithms have been selected. These are
the basic RSA, basic DES, Camellia, 3DES, AES, DES and
MD5. What they all have in common is the need for high
processing power and this can be a serious problem if their
FPGA implementation is to be commercialised both in terms
of energy efficiency and vulnerability to security information
attacks, [1] and [2].
Although different to this paper in terms of focus,
power measurements when implementing particular de-
signs/algorithms in FPGAs have been presented in [3] (matrix
multiplication algorithms) and [4] (selected digital signal pro-
cessing modules). In addition, it is worth mentioning similar
work on the topic of creating power efficient FPGAs [5], where
physical on-board measurements are used to extract accurate
power consumption prediction models for any given design.
This is typical of the research activity invested in FPGA
power consumption whereby one of the main objectives is
to develop an accurate power estimation technique or method-
ology that guarantees the desired performance and delivers
power efficient systems. Two distinct ways for achieving this
have been identified and they consist of i) extracting the
optimum way for design placement within the FPGA and
ii) calculating the effect of load capacitances that emerge
due to interconnections and CMOS gates, both of which are
presented in [6], [7], [8], [9], and [10]. Furthermore, a slightly
different insight to FPGA power consumption is demonstrated
in [11] where the most economical type of FPGA routing
architecture is looked into, i.e. bidirectional or unidirectional.
Finally, the work presented in this paper has evolved through
previous efforts that have been documented in [12] and [13].
The former gives a comparative analysis between actual and
theoretically calculated power consumption figures extracted
from implementing two security algorithms in Xilinx and
Altera FPGAs. The latter investigates the potential power
consumption benefits that may rise by introducing special
purpose hardware (instead of software) implementations of
CPU intensive tasks, such as, security applications to wireless
networks.
II. SECURITY ALGORITHMS
The security algorithms selected are widely used in data
encryption/decryption and authentication:
1) In cryptography, the Advanced Encryption Standard
(AES) [14] is a block cipher. It was announced by the National
Institute of Standards and Technology (NIST) after a 5-year
standardization process and it has now become highly popular.
2) The Data Encryption Standard (DES) [15] is a cipher
selected as an official Federal Information Processing Standard
(FIPS) for the United States since 1976, and has subsequently
enjoyed widespread use internationally. Fig. 1. Xilinx Digilent XUP Board
3) Triple DES (3DES) is a block cipher formed from the
Data Encryption Standard (DES) cipher by using the same
algorithm three times but each time with a different key. Rs
Iload
4) Basic DES is essentially a smaller and faster im- Vsense
plementation of the DES algorithm. It executes DES type
encryption/decryption in ECB (Electronic Codebook) mode S+ S- VCCINT

and is able to accept a new key for each operation without Vsupply ZXCT1021 FPGA
GND OUT
performance cost. GND

5) Basic RSA is a simplified version of the RSA algorithm

[16]. It is a public-key cryptography algorithm and it ensures
that whilst an encryption key is publicly revealed, it does not
reveal the corresponding decryption key.
6) Camellia [17] is a 128-bit block cypher and accepts 128-
bit, 192-bit or 256-bit keys. In our work, we use two distinct
versions of Camellia. The first only works with a 128-bit key
size whereas the second works with all key sizes. We have
named the first Camellia1 and the second Camellia2.
7) MD5 (Message-Digest algorithm 5) [18] is a widely-used
cryptographic hash function with a 128-bit hash value. As an
Internet standard (RFC 1321), MD5 has been employed in a
wide variety of security applications.
III. EXPERIMENTAL SET-UP
Each security algorithm has been implemented through a
Finite State Machine (FSM) that instructed the algorithm to
operate in an endless loop. This forced the FPGAs internal
structure to draw a constant amount of power, which could
then be measured according to the set-up explained below.
A. HARDWARE SET-UP
The FPGA used in this work was a Xilinx Virtex-II Pro
XC2VP30 and it was mounted on a Digilent XUP development
board [19], figure 1. This board has three separate power
sources, i.e. 1.5V, 2.5V and 3.3V, making it easy to isolate the
power consumed by the FPGA fabric alone. This was achieved
using the internal (core) power supply (1.5 V) rather than the
auxiliary and I/O power supplies (2.5 V and 3.3 V). It should
be stressed that very similar results have been recorded when
reproducing the experiment using a Virtex-5 110LX FPGA.
Vout
Fig. 2. Experimental Set-up
In particular, it was decided to use the resistive high-side
current measurement technique. This is a current measurement
configuration where a shunt resistor is introduced just before
an electrical load and right after its power supply. In other
words, the shunt resistor is placed in-between the power supply
(positive terminal) and the load. This way the potential drop
across the resistor can hint as to the current drawn by the load
and, hence, its power consumption, figure 2.
First, the on-board FPGA internal (core) supply voltage had
to be isolated in order to allow for the use of an external
1.5 V supply. The external supply was then connected to one
side of a shunt resistor (Rs ) and the other side of the resistor
was connected to the FPGA core supply input. To measure
the potential drop Vsense , a Zetex ZXCT1021 [20] (Simplest
Voltage Output Current Monitor) device was connected across
the shunt resistor generating an output Vout that is ten times
greater than Vsense . The high-side current sense monitor
(ZXCT1021) was required in order to amplify the potential
drop across the shunt resistor owed to its considerably small
size, i.e. 0.1 Ohm. Finally, signal out (Vout ) was fed into an
oscilloscope in order to capture its behaviour and store our
measurements.
 TABLE I
ISE M EASUREMENT S ET- UPS

set-up optimisation goal optimisation effort map effort level place and route mode power reduction
(speed/area) (normal/high) (standard/high) (normal/multi) (on/off)
A speed high standard normal off
B area high standard normal off
C speed high high normal off
D area high high normal off
E speed high standard multi off
F area high standard multi off
G speed high high multi off
H area high high multi off
I speed high standard normal on
J area high standard normal on
K speed high high normal on
L area high high normal on
M speed high standard multi on
N area high standard multi on
O speed high high multi on
P area high high multi on

B. ISE SET-UP we will refer to a unique combination of the aforementioned

ISE 10.1 is a design suite developed by Xilinx and it parameters in synthesis and implementation. Set-up A is in
was used as the platform where all security algorithms along fact the default, i.e. the one that ISE selects when the designer
with the different synthesis and implementation schemes were does not change any of those parameters.
applied. IV. ANALYSIS OF RESULTS
Synthesis offers two optimisation options and these are the
Each security algorithm was implemented on the target
optimisation goal and the optimisation effort. The first refers
FPGA using a different synthesis and implementation opti-
to either focusing on the reduction of the design area or
misation plan, i.e. set-up A to P. Each case yielded an on-
increasing the design speed whereas the second refers to the
the-bench power consumption measurement and the smallest
level of effort ISE will invest in achieving the settings under
numbers for each algorithm are listed in table II.
optimisation goal.
Similarly, in the implementation phase there are a number TABLE II
of options that can be addressed. The most important of those L EAST POWER CONSUMPTION FOR EACH ALGORITHM
are the map effort level, place and route mode and power
Algorithm optimum Power Improvement
reduction. Mapping fits the design into the available resources
set-up (mW) (%)
on the target device and the output from this step is a circuit
description file that physically represents the design mapped Basic RSA K 183 8.96
to the components in the FPGA. The effort level under this Basic DES A,D,J,L,P 93 0
step can be medium, standard or high and we have focused Camellia1 C,L 627 17.39
on the two latter options. Place and Route fits the design to Camellia2 A-F,I,J,N,P 948 0
the timing constraints set by the designer. It uses the Mapping 3DES B,N 165 6.78
output file and generates a new file that is used in bit-stream AES P 582 17.09
generation for device configuration. The place and route mode DES B,H,J,L,N,P 69 8
has five different settings and we have decided to use the first MD5 J,P 477 12.15
(Normal Place and Route), which is the default ISE setting,
and the last (Multi Pass Place and Route). Multi Pass Place The results presented in table II act as a guideline in terms
and Route is uniquely useful since it runs multiple place and of the most energy conserving synthesis and implementation
route solutions for a design and thus it helps find the best plans related to the security algorithms considered. It is
possible placement. noticeable that for most of the algorithms it is not just a single
Finally, power reduction is a setting that decides whether set-up that yields the best result. Often we notice that different
the routed design will be further optimised in order to achieve set-ups generate the same power consumption measurement
power consumption minimisation or not through two possible and, therefore, appear not to have any difference between them
options, on or off. All sixteen possible measurement set-ups in that respect.
are listed in table I. A highly interesting perspective is given by investigating
From this point on, when referring to set-up A, B, C etc. the percentages column of table II. These values represent the
 Total difference in power from default
amount of power consumption reduction achieved by the best 350

300

set-up, with respect to the default, as a percentage . Set-up A 250

is the default and that is why the algorithms with minimum 200

power consumption that include that particular set-up, yield an 150

overall improvement of 0%. On the other hand, the algorithms 100

50

that achieve the greatest improvement, using alternative set- 0

ups, are the Camellia1 and AES with an improvement of -50

A B C D E F G H I J K L M N O P

17.39% and 17.09% respectively. Setup

Furthermore, the case of the two Camellia algorithms is

of some interest. Camellia1 shows maximum improvement Fig. 3. Sum total of difference from default for each set-up
under just two different set-ups, whereas Camellia2 stays more
or less the same under most of the optimisation schemes. In
addition, Camellia2 appears to consume a significant amount Each algorithm is associated with sixteen power consump-
of power compared to Camellia1. tion values (16 different set-ups). Each value is now subtracted
This is attributed to the difference in key size between the from the default, hence, we obtain sixteen new values that give
two Camellia variants leading to circuits with significantly the extent of disagreement between each measurement from
different complexity. They have the same block size but differ the default. This is performed for every security algorithm
in key length, i.e. 128-bit for Camellia1 and 128/192/256-bit giving a total of 128 new values, eight for the difference
for Camellia2. In fact, using a 192 or 256-bit key size, as was between set-up A and set-up B, eight for the difference
the case during the evaluation phase, introduces six additional between set-up A and set-up C and so on. Finally, each set of
cypher rounds compared to the 128-bit key block cypher. More eight results produces a single number which is the result of
cypher rounds means additional processing, more wiring and their sum listed in the middle column of table III and shown
therefore more energy, until it generates the encrypted output. in figure 3. Positive values signify an overall power reduction
Furthermore, the added algorithmic complexity of Camellia2, for a specific set-up and negative values represent the exact
compared to Camellia1, should also explain why most of the opposite.
optimisation schemes fail to make a noticeable difference and TABLE III
offer a power consumption identical to that of the default set- S UM TOTAL & PERCENTAGE OF THE DIFFERENCE BETWEEN EACH SET- UP
up A. The more complex an algorithm, the harder it becomes & DEFAULT
for ISEs optimisation schemes to re-distribute it over the
Set-up Sum total of Percentage
FPGA resources in a manner that minimises power consump-
difference from A (mW) difference from A
tion. AES is the algorithm closest to the Camellia1 results
(even in terms of improvement) and that is understandable A 0 0.00%
since the actual algorithm implemented was the AES128 that B 126 3.60%
uses a 128-bit key on a 128-bit input block size data. C 183 5.23%
With respect to the DES results, it is only logical that D 204 7.11%
DES has the least power consumption compared to 3DES E -33 -0.94%
since the former applies the cypher algorithm once to the F 159 4.54%
data block whereas the latter applies it three times. Also, G 6 0.17%
DES achieves a slightly better improvement in terms of power H 156 4.45%
consumption minimisation (8%) with six different synthesis I 48 1.37%
and implementation schemes achieving this particular figure, J 255 7.28%
in contrast to 3DES that, owed to its higher complexity, K 189 5.40%
achieves a 6.78% reduction in power consumption under only L 288 8.23%
two different synthesis and implementation schemes. Basic M 75 2.94%
DES is a different algorithm to DES with much focus on N 264 7.54%
performance which should explain why it requires more power O 129 5.00%
than DES. Still, it remains well below the 3DES measurement. P 306 9.21%
So far, a direct insight has been provided that relates a
specific security algorithm to a unique synthesis and imple- The percentages in table III and figure 4 give a similar
mentation plan that ensures minimum power consumption for insight and they show what has been on average the difference
that particular type of FPGA. The results, however, provide between the default set-up power measurement and that of
evidence that should be of use even in different FPGA and ISE a different synthesis and implementation plan. Based on the
design suites. The next step in the analysis was to establish presented evidence, it was deduced that overall the best power
which of the sixteen different set-ups was the best overall, consumption performance is achieved under set-up P. This plan
i.e. which set-up achieved the lowest power consumption on gives the greatest (positive, which signifies power reduction)
average for all security algorithms. deviation from the default, which is 306mW or 9.21%. In
 a)

Percentage difference from default

10.00%

8.00% Xpower Measured Average Xpower Least Measured

6.00% 350

300

Difference in Power (mW)

4.00%

250

2.00%

200

0.00%
150

-2.00% 100
A B C D E F G H I J K L M N O P

50
Setup

Basic RSA Basic DES Cammelia1 Cammelia2 3DES AES DES MD5

Fig. 4. Percentage of difference from default for each set-up Security Algorithm

b)

%error between Xpower and Meas.Av. %error between Xpower and Least Meas.

terms of measurements obtained for each security algorithm

225

separately, set-up P gave the best results in five out of eight 200

cases making it the most efficient. In contrast, the worst overall 175

150

% Difference
performance is yielded by set-up E which measures a negative 125

deviation from the default and this signifies an overall power 100

75

increase, i.e. 33mW more power or a 0.94% increase in power 50

consumption. 25

Finally, Xpower Analyzer has been examined and compared 0

Basic RSA Basic DES Cammelia1 Cammelia2 3DES AES DES MD5

against the measured data. Interestingly enough, the tool Security Algorithm

generated the same values regardless of the set-up that was

tried and the XPower estimated values are summarised in
table IV for each security algorithm. To compare against the
measured power consumption values, table IV also lists i) the
average of all measured values for each algorithm as well as
ii) the smallest recorded value for each security algorithm.
Note that the smallest recorded values have also been listed in
table II. In all cases, a noticeable pattern is observed whereby
XPower will always come up with a worst estimate than the
actual measurement. The reasons to this lay with the XPower
software tool and it surely constitutes an area that merits
further investigation.
TABLE IV
X POWER ANALYZER , AVERAGE AND L EAST MEASUREMENTS FOR EACH
SECURITY ALGORITHM
Security XPower
Algorithm
Basic RSA
Basic DES
Camellia1
Camellia2
3DES
AES
DES
MD5
Figure 5 contains two different figures, i.e. a) and b).
a) contains two graphs that are based on the measurements
included in table IV and present the difference in milliwatts
between the XPower values and each of the other two sets of
values. The first is the average of all measured values and the
second is comprised of the smallest recorded values for each
security algorithm. Consequently, it is shown that in some
Fig. 5. a) Difference between XPower estimates and real measurements
(Average and Least) and b) % difference between XPower estimates and real
measurements (Average and Least)
cases the XPower results differ considerably to the on-the-
bench measurements, as in the case of the AES and Camellia1
algorithms, where the XPower/Least Measured difference is
calculated at 307mW and 283mW respectively. Similarly, the
XPower/Measured Average difference values for those same
algorithms (AES and Camellia1) are 258mW and 201mW.
On the other hand, the minimum amount of disagreement
between the XPower and on-the-bench results is found with
the 3DES and Basic RSA algorithms. The first algorithm
registers a XPower/Least Measured difference of 31mW and
a XPower/Measured Average difference of 23mW whereas the
Measured Least second algorithm gives 44mW and 27mW respectively.
Average Measured
Furthermore, Camellia1 and AES are characterised by the
(mW) (mW) (mW)
largest spread between the XPower/Least Measured difference
227 199.68 183 and the XPower/Measured Average difference, which is justi-
281 97.87 93 fied by the fact that these two algorithms achieve the greatest
910 708.93 627 improvement in power consumption minimisation according
1114 950.57 948 to table II. For Camellia1 this spread is calculated at 82mW
196 173 165 and for AES at 50mW. MD5 closely follows with a spread
889 630.75 582 of 39mW since it is the third in line algorithm in terms
141 74.25 69 of maximum power consumption minimisation, i.e. table II
562 515.81 477 shows a maximum of 12.15% reduction under two different
set-ups. The five remaining security algorithms (Basic RSA,
Basic DES, DES, 3DES and Camellia2) reveal a closeness
in results between the XPower/Least Measured difference
and the XPower/Measured Average difference. One reassuring
set of results is that concerning the three DES algorithms,
where the average and least measured values are so close
that the corresponding points in graph a) almost overlap.
Specifically, the distance between the two points in the graph
for Basic DES, DES and 3DES are 4.9mW, 5.3mW and 8mW
respectively.
Figure 5 b) provides a different angle on looking at the dis-
similarities between XPower and on-the-bench measurements.
It shows the percentage (%) difference between the power
consumption estimated by XPower and the one measured
during the experiment. Two sets of measurements are included,
the first refers to the difference between the XPower value
and the measured average while the second represents the
difference between XPower and the least measured value
(both for each security algorithm). As before, the difference is
greater in the case of XPower and the least measured values.
Furthermore, it is the two DES algorithms that trigger the
greatest error. These are the Basic DES, with a maximum %
error margin of 202%, and the ordinary DES, with a maximum
% error margin of 104%. On the other hand, the smallest %
error margins are found with Camellia2 and MD5 at 17.5%
and 17.8% respectively.
Consequently, an important observation can be made based
on the results of figure 5 and table IV. In general, the low
power consumption algorithms will give a high percentage
difference between XPower and real-life measurements. This
is logical since a 160mW difference between XPower and the
least measured average for Camellia2 (that overall consumes
approximately 1000mW of power) has a much less impact
than the 180mW difference for Basic DES (that overall con-
sumes approximately 100mW of power according to actual
measurements). Hence, XPower may not be as accurate with
low power consumption implementations compared to high
power consumption designs. However, this is not the only
parameter. The type of algorithm involved also affects the
results since Camellia1 and AES that pose great similarities
are close in terms of results, figure 5. Finally, attention should
be directed towards the design/implementation approach (i.e.
applied optimisations at the synthesis and implementation
phases) selected by the design engineer. It should be noted
that the analysis has been repeated using more recent ISE
Design Suites (up to ISE 12.4) and results show consistency
with what is documented in this paper.
V. CONCLUSIONS
This paper offers three major outcomes. Firstly, it identifies
the effects of different synthesis and implementation scenarios
on FPGA power consumption. Secondly, it manages to isolate
the synthesis and implementation set-up that will, on average,
tend to achieve the lowest power consumption in relation to
eight different security algorithms. Specifically, set-up P stands
out since it achieved an overall power reduction of 306mW or
9.21%, compared to the default.
Finally, this paper presents a range of results on the accuracy
of XPower Analyzer. Overall, XPower did not manage to
generate varying estimates along with the different set-ups.
In addition, it tends to provide a rather pessimistic view of
the FPGA power consumption. As an example, in the worst
case, the XPower estimate for block cypher AES is 307mW
greater than the least power consumption value measured on-
the-bench whereas it remains 258mW higher than the average
power consumption measured.
VI. ACKNOWLEDGMENTS
This work is funded by Secure Mobile visual sensor net-
works ArchiTecture research project (SMART, project num-
ber: 100032), funded within the ARTEMIS Joint Technology
Iniative as a Joint Undertaking project between the European
Commission, the member states and ARTEMIS Industrial
Association (ARTEMISIA).
R EFERENCES
[1] P. K. J. Jae and B. Jun, Differential power analysis, in Advances in
Cryptology: Proceedings of CRYPTO99, August 1999.
[2] T.S. Messerges, Power analysis attacks and countermeasures for cryp-
tographic algorithms, Doctoral Thesis, January 2000.
[3] V. Scrofanoss, R. Seonil Choi Prasanna, Energy efficiency of fpgas and
programmable processors for matrix multiplication, In Proceeding of
IEEE FPT, 2002, 2002.
[4] P. Waldeck and N. Bergmann, Evaluating software and hardware
implementations of signal-processing tasks in an fpga, In Proceeding
of IEEE ICFPT 2004, 2004.
[5] R. Jevtic and C. Carreras, Power measurement methodology for fpga
devices, IEEE Transactions on Instrumentation and Measurement,
vol. 60, January 2011.
[6] M. S. Zamani and E. Esmaili, Reducing power consumption in fpga
routing, in Proceedings of the 16th Canadian Conference on Electrical
and Computer Engineering, 2003.
[7] J. Anderson and F. Najm, Power estimation techniques for fpgas, IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12,
no. 10, October 2004.
[8] V. Degalahal and T. Tuan, Methodology for high level estimation of
fpga power consumption, in Proceedings of the ASP-DAC (Design
Automation Conference), Asia and South Pacific, 2005.
[9] S. N. Hyung Gyu Lee and N. Chang, Cycle-accurate energy measure-
ment and high-level energy characterisation of fpgas, in Proceedings of
the 4th International Symposium on Quality Electronic Design (ISQED),
2003.
[10] M. L.-V. I. Herrera-Alzu, M. A. Sanchez and P. Echeverria, Experimen-
tal methodology for power characterisation of fpgas, in Proceedings of
the 15th IEEE International Conference on Electronics, Circuits and
Systems, 2008.
[11] S. W. Peter Jamieson, Wayne Luk and G. Constantinides, An energy
and power consumption analysis of fpga routing architectures, in
Proceedings of the International Conference on Field-Programmable
Technology (FPT), 2009.
[12] D. Meidanis and I. Papaefstathiou, Power consumption estimations vs
measurements for fpga-based security cores, in Proceedings of the
International Conference on Reconfigurable Computing and FPGAs,
2008.
[13] , On the power consumption of security algorithms employed
in wireless networks, in Proceedings of the 6th IEEE Consumer
Communications and Networking Conference (CCNC), 2009.
[14] O. Cores, 128/192 aes overview, July 2004,
http://opencores.org/project,systemcaes.
[15] ASICS Inc, Des/triple des ip cores, September 2001,
http://www.opencores.org/projects.cgi/web/des/overview.
[16] A. S. Ronald Rivest and L. Adleman, A method for obtaining digital
signatures and publickey cryptosystems, Communications of the ACM,
vol. 21, pp. 120126, 1978.
[17] NTT, The history of ntt cryptographic algorithms, 2010,
http://info.isl.ntt.co.jp/crypt/eng/camellia/index.html.
[18] Universidad Rey Juan Carlos, Systemc/verilog md5, August 2004,
http://www.escet.urjc.es/ jmartine.
[19] Digilent Inc, Xup and spartan3 development boards, 2006,
http://www.digilentinc.com/Products/.
[20] Z. Semiconductors, ZXCT1021 Low Offset High-Side Current Monitor,
July 2007, http://www.diodes.com/zetex/pdfs/3.0/pdf/ZXCT1021.pdf.