FinFET

History,FundamentalsandFuture
TsuJaeKingLiu
DepartmentofElectricalEngineeringandComputerSciences
UniversityofCalifornia,Berkeley,CA947201770USA

June11,2012

2012SymposiumonVLSITechnologyShortCourse
 ImpactofMooresLaw
Transistor
Scaling
Higher Performance,
Investment
Lower Cost
Market
Growth
# DEVICES (MM)

CMOSgeneration:1um 180nm 32nm

YEAR
Source: ITU, Mark Lipacis, Morgan Stanley Research
http://www.morganstanley.com/institutional/techresearch/pdfs/2SETUP_12142009_RI.pdf 2
 1996:TheCallfromDARPA
0.25mCMOStechnologywasstateoftheart
DARPAAdvancedMicroelectronics(AME)ProgramBroad
AgencyAnnouncementfor25nmCMOStechnology
1998InternationalTechnologyRoadmapforSemiconductors(ITRS)
1999 2002 2005 2008 2011 2014 2017 2020
TechnologyNode 180 130 100 70 50 35 25 18
nm nm nm nm nm nm nm nm
GateOxide 1.92.5 1.51.9 1.01.5 0.81.2 0.60.8 0.50.6
Thickness,TOX (nm) Solutions Noknown
DriveCurrent,IDSAT beingpursued solutions

EndofRoadmap
UCBerkeleyprojectNovelFabrication,DeviceStructures,
andPhysicsof25nmFETsforTerabitScaleElectronics
June1997throughJuly2001
3
 MOSFETFundamentals
MetalOxideSemiconductor 0.25micronMOSFETXTEM
FieldEffectTransistor:
GATELENGTH,Lg

Gate

Source Drain
Sisubstrate
http://www.eetimes.com/design/automotivedesign/4003940/LCDdriverhighlyintegrated

GATEOXIDETHICKNESS,Tox

4
 MOSFETOperation:GateControl
Desired NchannelMOSFET CurrentbetweenSourceandDrain
characteristics: crosssection iscontrolledbytheGatevoltage.
HighONcurrent
Gate Nchannel&PchannelMOSFETs
LowOFFcurrent gateoxide
Leff operateinacomplementarymanner
N+ P N+ CMOS=ComplementaryMOS
Source Body Drain
log ID
ElectronEnergyBandProfile ION

DRAINCURRENT
n(E) exp(E/kT)
increasingE

Inverseslopeis
subthreshold swing,S
IOFF
Sourceincreasing [mV/dec]
GATEVOLTAGE
VGS Drain 0 VTH
VDD
distance
5
 CMOSDevicesandCircuits
CIRCUITSYMBOLS CMOSINVERTERCIRCUIT
VDD VOUT INVERTER
Nchannel Pchannel
S LOGICSYMBOL
MOSFET MOSFET
G G VDD
D
VIN V
S D S D D OUT
S VIN
GND 0 VDD
CMOSNANDGATE
STATICMEMORY(SRAM)CELL
NOTAND(NAND) WORDLINE
TRUTHTABLE

0 1
or or
BITLINE 1 0 BITLINE

6
 ImprovingtheON/OFFCurrentRatio
Gate logID ION

Cox Ctotal
S
Cdep Cox
Source Body Drain
VDD VGS
ThegreaterthecapacitivecouplingbetweenGateandchannel,the
bettercontroltheGatehasoverthechannelpotential.
higherION/IOFF forfixedVDD,orlowerVDD toachievetargetION/IOFF
reduceddraininducedbarrierlowering(DIBL):
logID
increasing
VDS
Source increasing Drain IOFF
VDS
VGS
7
MOSFETinONState(VGS >VTH)
width velocity inversionlayerchargedensity
I D W v Qinv
gateoxide
capacitance

v eff Qinv Cox (VGS VTH )
mobility gateoverdrive
DRAINCURRENT,ID

Gate

Source Drain
Substrate

DRAINVOLTAGE,VDS
8
 EffectiveDriveCurrent(IEFF)
CMOSinverterchain:
VDD
V1 V2 V3 V2 tpLH V3 IH +IL
VDD/2
V1 tpHL IEFF = 2
TIME
IH (DIBL=0) IDSAT
VDD NMOSDRAINCURRENT VIN=VDD
S

D IH VIN=0.83VDD
VIN VOUT
D
VIN=0.75VDD
S
GND
IL
VIN=0.5VDD

0.5VDD VDD
NMOSDRAINVOLTAGE=VOUT
M.H.Naetal.(IBM),IEDMTechnicalDigest,pp.121124,2002 9
 CMOSTechnologyScaling
XTEMimageswiththesamescale
courtesyV.Moroz (Synopsys,Inc.)

90nmnode 65nmnode 45nmnode 32nmnode

T.Ghani etal., (afterS.Tyagi etal.,IEDM 2005) K.Mistry etal., P.Packan etal.,

IEDM 2003 IEDM 2007 IEDM 2009

Gatelengthhasnotscaledproportionatelywithdevice
pitch(0.7xpergeneration)inrecentgenerations.
Transistorperformancehasbeenboostedbyothermeans.

10
MOSFETPerformanceBoosters
Strainedchannelregions eff
Highkgatedielectricandmetalgateelectrodes Cox
CrosssectionalTEMviewsofIntels32nmCMOSdevices

P.Packan etal.(Intel),IEDMTechnicalDigest,pp.659662,2009 11
 ProcessInducedVariations
Subwavelengthlithography:
Resolutionenhancement
techniquesarecostlyandincrease
processsensitivity

Gatelineedgeroughness: courtesyMikeRieger (Synopsys,Inc.)

photoresist

Randomdopant fluctuations(RDF):
Atomisticeffectsbecome
significantinnanoscale FETs
A.Brownetal.,
SiO2 Gate IEEETrans.
Nanotechnology,
p.195,2002
Source Drain
A.Asenov,Symp.VLSITech.Dig.,p.86,2007
12
AJourneyBackthroughTime
 WhyNewTransistorStructures?
Offstateleakage(IOFF)mustbesuppressedasLg isscaleddown
allowsforreductionsinVTH andhenceVDD
Leakageoccursintheregionawayfromthechannelsurface
Letsgetridofit! Lg
UltraThinBody
MOSFET:
Gate
Gate

Source
Source Drain
Drain
Siliconon
BuriedOxide
Insulator(SOI)
Substrate Wafer

14
 ThinBody MOSFETs
IOFF issuppressedbyusinganadequatelythinbodyregion.
Bodydopingcanbeeliminated
higherdrivecurrentduetohighercarriermobility
Reducedimpactofrandomdopantfluctuations(RDF)

UltraThinBody(UTB) DoubleGate(DG)
Lg

Gate
Gate
Source Drain
Source Drain TSi TSi
BuriedOxide
Gate
Substrate

TSi <(1/4) Lg TSi <(2/3) Lg

B.Yuetal.,ISDRS1997 R.H.Yanetal.,IEEETED1992 15
 EffectofTSi onLeakage
Lg =25nm;Tox,eq =12

TSi =10nm TSi =20nm

106 G SiThickness[nm] G
0.0
4.0
S D
3x102 8.0
12.0
S D
G 16.0

101 20.0

LeakageCurrent G
Density[A/cm2]
@VDS =0.7V Ioff =2.1nA/m Ioff =19A/m

16
 DoubleGateMOSFETStructures

PLANAR:

VERTICAL FIN:

L.Geppert,IEEESpectrum,October2002 17
 DELTAMOSFET
D.Hisamoto,T.Kaga,Y.Kawamoto,andE.Takeda(HitachiCentralResearchLaboratory),
Afullydepletedleanchanneltransistor(DELTA) anovelverticalultrathinSOIMOSFET,
IEEEElectronDeviceLetters Vol.11,pp.3639,1990

Improvedgatecontrol
Wl =0.4m
observedforWg <0.3m
Leff=0.57m
18
 DoubleGateFinFET
Selfalignedgatesstraddlenarrowsiliconfin
Currentflowsparalleltowafersurface
Gate Length, Lg
S
Source

G
G
Gate 2 D

Gate 1
Current
Flow
Drain

Fin Height, Hfin

Fin Width, Wfin

19
 1998:FirstNchannelFinFETs
D.Hisamoto,W.C.Lee,J.Kedzierski,E.Anderson,H.Takeuchi,K.Asano,T.J.King,J.Bokor,andC.Hu,
AfoldedchannelMOSFETfordeepsubtenthmicronera,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.10321034,1998
PlanView

Lg =30nm
Wfin =20nm
Hfin =50nm

Lg =30nm
Wfin =20nm
Hfin =50nm

DeviceswithLg downto17nm
weresuccessfullyfabricated
20
 1999:FirstPchannelFinFETs
X.Huang,W.C.Lee,C.Kuo,D.Hisamoto,L.Chang,J.Kedzierski,E.Anderson,H.Takeuchi,Y.K.Choi,
K.Asano,V.Subramanian,T.J.King,J.Bokor,andC.Hu,Sub50nmFinFET:PMOS,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.6770,1999

Lg =18nm
Wfin =15nm
Hfin =50nm

Transmission
Electron
Micrograph

21
2000:VestedInterestfromIndustry
SemiconductorResearchCorporation(SRC)& AMDfundproject:
DevelopmentofaFinFET processflowcompatiblewitha
conventionalplanarCMOSprocess
DemonstrationofthecompatibilityoftheFinFET structure
withaproductionenvironment
(October2000throughSeptember2003)

DARPA/SRCFocusCenterResearchProgramfundsprojects:
ApproachesforenhancingFinFET performance
(MSDCenter,April2001throughAugust2003)
FinFETbasedcircuitdesign
(C2S2Center,August2003throughJuly2006)

22
 FinFETStructures

Original:
Gatelast Gate
processflow
Source Si Fin
Drain

Gate
Improved:
Gatefirst
processflow
Source Drain

23
 FinWidthRequirement
MeasuredFinFET DIBL

Toadequately
suppressDIBL,
Lg/Wfin >1.5
Challengefor
lithography!

N.Lindert etal.(UCBerkeley),IEEEElectronDeviceLetters,Vol.22,pp.487489,2001 24
 SubLithographicFinPatterning
SpacerLithography
a.k.a.SidewallImageTransfer(SIT)andSelfAlignedDoublePatterning(SADP)
1. Deposit & pattern sacrificial layer 3. Etch back mask layer
to form spacers

SOI SOI

BOX BOX

4. Remove sacrificial layer;

2. Deposit mask layer (SiO2 or Si3N4)
etch SOI layer to form fins

SOI fins

BOX BOX

Note that fin pitch is 1/2 that of patterned layer

25
 BenefitsofSpacerLithography
Spacerlitho.providesforbetterCDcontrolanduniformfinwidth

SEMimageof
FinFET with
spacerdefinedfins:

Y.K.Choietal.(UCBerkeley),IEEETrans.ElectronDevices,Vol.49, pp.436441,2002 26
 SpacerDefinedFinFETs
Y.K.Choi,N.Lindert,P.Xuan,S.Tang,D.Ha,E.Anderson,T.J.King,J.Bokor,andC.Hu,
"Sub20nmCMOSFinFET technologies,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.421424,2001

Lg =60nm,Wfin =40nm
TransferCharacteristics OutputCharacteristics

27
 2001:15nmFinFETs
Y.K.Choi,N.Lindert,P.Xuan,S.Tang,D.Ha,E.Anderson,T.J.King,J.Bokor,C.Hu,
"Sub20nmCMOSFinFET technologies,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.421424,2001

TransferCharacteristics OutputCharacteristics

Drain Current, Id[uA/um]

-2 -2
Drain Current, Id [A/um]

10 10 600 600
Vd=-1.0 V P+Si0.4Ge0.6 Vd=1.0 V NMOS
-4 Gate -4 500 PMOS |Vg-Vt|=1.2V 500
10 10
Vd=-0.05 V Vd=0.05 V 400 400
10
-6 -6
10 Voltage step
300 : 0.2V 300
-8 N-body= -8
10 18 -3 10
2x10 cm 200 200
-10 -10
10 10 100 100
-12
PMOS NMOS -12
10 10 0 0
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
Gate Voltage, Vg [V] Drain Voltage, Vd [V]
Wfin =10nm;Tox =2.1nm

28
 2002:10nmFinFETs
B.Yu,L.Chang,S.Ahmed,H.Wang,S.Bell,C.Y.Yang,C.Tabery,
SEM C.Hu,T.J.King,J.Bokor,M.R.Lin,andD.Kyser,
image: "FinFET scalingto10nmgatelength,"
InternationalElectronDevicesMeetingTechnicalDigest,pp.251254,2002

OutputCharacteristics
TEMimages

Thesedeviceswere
fabricatedatAMD,using
opticallithography.

29
 HoleMobilityComparison
MeasuredFieldEffectHoleMobility
160
Vg-Vth=.8V
DGFEThashigherhole
140
mobilityduetolower
Mobility(cm2/V-sec)

120 <100> channel

transverseelectricfield
100
80
FinFET
60 Forthesamegate
40 Bulk FET overdrive,holemobility
20
inDGFinFET is2 thatin
acontrolbulkFET
0
0 0.5 1
Effective Field (MV/cm)

30
 FinFET ProcessRefinements
Y.K.Choi,L.Chang,P.Ranade,J.Lee,D.Ha,S.Balasubramanian,A.Agarwal,T.J.King,andJ.Bokor,
"FinFET processrefinementsforimprovedmobilityandgateworkfunctionengineering,"
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.259262,2002

Finsidewallsmootheningfor Gateworkfunctiontuning
improvedcarriermobilities forVTH adjustment

31
 FinFETReliability
Y.K.Choi,D.Ha,J.Bokor,andT.J.King,ReliabilitystudyofCMOSFinFETs,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.177180,2003

StressBiasCondition:Vg=Vd=2.0V
30
Narrowerfin improved
Id / Id [%]

20 Lg=80nm
hotcarrier(HC) immunity
10

0
HClifetimeandoxideQBD
arealsoimprovedby
VT / VT [%]

-10 smootheningtheSifin
-20 W fin=18nm W fin=26nm
sidewallsurfaces(byH2
W fin=34nm W fin=42nm annealing)
-30
0 1 2 3
10 10 10 10
Stress Time [sec]

32
 TriGateFET

Lg =60nm
Wfin =55nm
Hfin =36nm

B.Doyleetal.(Intel),IEEEElectronDeviceLetters,Vol.24,pp.263265,2003 33
 SOIMultiGateMOSFETDesigns
TriGateFET
Relaxedfindimensions
WSi >Lg/2;HSi >Lg/5

FinFET
Narrowfin
WSi ~Lg/2

bodydimensions
requiredfor
DIBL=100mV/V
HSi /Leff

Tox =1.1nm

UTBFET
UltrathinSOI
WSi /Leff HSi ~Lg/5
afterYangandFossum,IEEETrans.ElectronDevices,Vol.52,pp.11591164,2005 34
 DoubleGatevs.TriGateFET
TheDoubleGateFETdoesnotrequireahighlyselective
gateetch,duetotheprotectivedielectrichardmask.
Additionalgatefringingcapacitanceislessofanissuefor
theTriGateFET,sincethetopfinsurfacecontributesto
currentconductionintheONstate.
DoubleGateFET TriGateFET

channel

afterM.Khare,2010IEDMShortCourse 35
 IndependentGateOperation
ThegateelectrodesofadoublegateFETcanbeisolated
byamaskedetch,toallowforseparatebiasing.
Drain
Onegateisusedforswitching. Gate1
Back
TheothergateisusedforVTH control. Gated
Gate2
FET
Source

D.M.Friedetal.(CornellU.),
IEEEElectronDeviceLetters, L.Mathewetal.(Freescale Semiconductor),
Vol.25,pp.199201,2004 2004 IEEEInternationalSOIConference
36
 BulkFinFET
FinFETs canbemade
onbulkSiwafers
lowercost
improvedthermal
conduction
withsupersteep
retrogradewell
(SSRW)orpunch
throughstopperat
thebaseofthefins
90nmLg FinFETs
demonstrated
Wfin =80nm
Hfin =100nm
DIBL=25mV
C.H.Leeetal. (Samsung),SymposiumonVLSITechnologyDigest, pp.130131,2004 37
Bulkvs. SOIFinFET
(comparedtoSOIFinFET)

H.Bu (IBM),2011IEEEInternationalSOIConference 38
2004:Highk/MetalGateFinFET

D.Ha,H.Takeuchi,Y.K.Choi,T.J.King,W.Bai,
D.L.Kwong,A.Agarwal,andM.Ameen,
MolybdenumgateHfO2 CMOSFinFET technology,
IEEEInternationalElectronDevicesMeetingTechnical
Digest,pp.643646,2004

39
 IDSAT BoostwithEmbeddedSiGe S/D
Processflow:

IOFF vs.ION

25%improvementinIDSAT
isachievedwithsilicon
Lg =50nm germaniumsource/drain,
Wfin =35nm
Hfin =65nm
dueinpart toreduced
parasiticresistance

P.Verheyen etal.(IMEC),SymposiumonVLSITechnologyDigest,pp.194195,2005 40
 FinDesignConsiderations

FinWidth GateLength
DeterminesDIBL

Source
FinHeight
Limitedbyetchtechnology
Tradeoff:layoutefficiency

Drain
vs. designflexibility

FinPitch
Determineslayoutarea Pfin FinHeight
LimitsS/Dimplanttiltangle FinWidth
Tradeoff:performancevs.layoutefficiency

41
 FinFETLayout
LayoutissimilartothatofconventionalMOSFET,except
thatthechannelwidthisquantized: Pfin

Source Source
Gate Gate
Drain Drain

Source Source
BulkSiMOSFET FinFET
TheS/Dfinscanbemergedbyselectiveepitaxy:

Intel
M.Guillorn etal.(IBM),Symp.VLSITechnology2008 Corp.
42
ImpactofFinLayoutOrientation

Ifthefinisoriented||or to
thewaferflat,thechannel
surfacesliealong(110)planes.
lowerelectronmobility
higherholemobility
Ifthefinisoriented45 tothe
(Seriesresistanceismore waferflat,thechannelsurfaces
significantatshorterLg.) liealong(100)planes.
L.Changetal.(IBM),SISPAD 2004 43
 FinFETBasedSRAMDesign
BestPaperAward:Z.Guo,S.Balasubramanian,R.Zlatanovici,T.J.King,andB.Nikolic,
FinFETbasedSRAMdesign,IntlSymposiumonLowPowerElectronicsandDesign,pp.27,2005
6TSRAMCellDesigns CellLayouts ButterflyCurves

Reducedcellareawith
independentlygatedPGs

44
 StateoftheArtFinFETs
22nm/20nmhighperformance
CMOStechnology
Lg =25nm

XTEMImagesofFin

C.C.Wuetal.(TSMC),IEDM 2010 45
 LookingtotheFuture

2010InternationalTechnologyRoadmapforSemiconductors(ITRS)
2012 2014 2016 2018 2020 2022 2024
GateLength 24nm 18nm 15nm 13nm 11nm 10nm 7nm
GateOxide
Thickness,TOX (nm)
DriveCurrent,IDSAT

EndofRoadmap
(always~15yrs away!)

46
 FinFET vs.UTBBSOIMOSFET
CrosssectionalTEMviews
of25nmUTBSOIdevices
NFET TSi =5nm

PFET TSi =5nm

K.Chengetal.(IBM),SymposiumonVLSI B.Doris(IBM),2011 *C.C.Wuetal.

TechnologyDigest,pp.128129,2011 IEEEInternational (TSMC),IEDM
SOIConference 2010

47
 ProjectionsforFinFET vs. UTBBSOIMOSFETs
300
FDSOI Open: FinFET
Electron Mobility (cm2/V.s) 250 Closed: FDSOI Open: FinFET
Unstrained Closed: FDSOI
Longi.
NMOS: 200 Trans.
Vertical
Electron 150
Mobility Unstrained Unstrained
Longi. Longi.
FinFET Trans. Trans.
100 Vertical Vertical
12 12 12 12 13 12 12 12 12 13 12 12 12 12 13
2x10 4x10 6x10 8x10 10 2x10 4x10 6x10 8x10 10 2x10 4x10 6x10 8x10 10
-2 -2 -2
Inversion Charge Concentration (cm ) Inversion Charge Concentration (cm ) Inversion Charge Concentration (cm )
TechnologyNode: 20nm 14/16nm 10/12nm
tSOI =7nm; tFIN =10nm tSOI =5nm; tFIN =7.5nm tSOI =3.5nm; tFIN =5nm
300 0
270 Unstrained FinFET Unstrained FinFET 0 Unstrained
240 0
Hole Mobility (cm2/V.s)

Longi. Longi. Longi.

210 Trans. Trans. 0 Trans.
PMOS: 180
150
Vertical Vertical 0
0
Vertical
FinFET
Hole 120 0
FDSOI
Mobility 90 0

60 FDSOI 0
FDSOI

12 12 12 12 13 12 12 12 12 13 12 12 12 12 13
2x10 4x10 6x10 8x10 10 2x10 4x10 6x10 8x10 10 2x10 4x10 6x10 8x10 10
-2 -2 -2
Inversion Charge Concentration (cm ) Inversion Charge Concentration (cm ) Inversion Charge Concentration (cm )

N.Xu etal. (UCBerkeley),IEEEElectronDeviceLetters,Vol.33,pp.318320,2012 48

 RemainingFinFET Challenges
VTH adjustment
Requiresgateworkfunction(WF)orLeff tuning
DynamicVTH controlisnotpossibleforhighaspectratiomultifindevices
Fringingcapacitancebetweengateandtop/bottomofS/D
Mitigatedbyminimizingfinpitchand
usingviacontacted,mergedS/D
M.Guillorn,Symp.VLSITechnology2008

Parasiticresistance Conformaldopingisneeded
UniformS/Ddopingis e.g.Y.Sasaki,IEDM2008
difficulttoachievewith
conventionalimplantation
H.Kawasaki,IEDM2008

Variability
Performanceisverysensitivetofinwidth
WFvariationdominantforundoped channel
T.Matsukawa,Symp.VLSITechnology 2008
49
RandomDopantFluctuationEffects
Channel/bodydopingcanbeeliminatedtomitigateRDFeffects.
However,duetosource/draindoping,atradeoffexistsbetween
performance&RDFtoleranceforLg <10nm:

SOIFinFET w/atomistic
IOFF andVT vs.TSi IONvs.TSi
S/Dgradientregions: 1E-4
SD = 3nm 100 SD = 3nm

ION (mA / m)
1E-6 75 0.8
IOFF (A / m)

VT (mV)
50
1E-8 0.4
25

1E-10 0
4.5 5.5 6.5 4.5 5.5 6.5
Lg =9nm,EOT=0.7nm TSi (nm) TSi (nm)

V. Varadarajan et al. (UC-Berkeley), IEEE Silicon Nanoelectronics Workshop, 2006 50

 Bulkvs.SOIMultiGateFETDesign
Toeasethefinwidth
requirement,thefin
heightshouldbe
reduced.
HSi /Leff

trigateSOI(thickBOX)
[J.G.Fossum etal.,IEDM 2004]
Thebulktrigatedesign
hasthemostrelaxed
bodydimension
requirements.
SSRW(atthebaseof
thefin)improves
electrostaticintegrity
WSi /Leff

X.Sunetal.(UCBerkeley),IEEEElectronDeviceLetters, Vol.29,pp.491493,2008 51
 SOIMOSFETEvolution
TheGateAllAround(GAA)structureprovidesforthegreatest
capacitivecouplingbetweenthegateandthechannel.

http://www.electroiq.com/content/eiq-2/en/articles/sst/print/volume-51/issue-5/features/nanotechnology/fully-gate-all-around-silicon-nanowire-cmos-devices.html

52
ScalingtotheEndoftheRoadmap
32nm 22nm beyond10nm
planar multigate stackednanowires
segmentedchannel
3D:

IntelCorp.
quasiplanar: C.Dupretal.(CEALETI)
IEDM2008

Stackedgateallaround
(GAA)FETsachievethe
P.Packanetal.(Intel),
IEDM2009 highestlayoutefficiency.
B.Ho(UCB),ISDRS 2011
53
 Summary
TheFinFET wasoriginallydevelopedformanufactureof
selfaligneddoublegateMOSFETs,toaddresstheneed
forimprovedgatecontroltosuppressIOFF,DIBLand
processinducedvariabilityforLg <25nm.
TriGateandBulkvariationsoftheFinFET havebeen
developedtoimprovemanufacturabilityandcost.
Ithastaken~10yearstobring3Dtransistorsintovolume
production.

MultigateMOSFETsprovideapathwaytoachieving
lowerpowerand/orimprovedperformance.
FurtherevolutionoftheMOSFETtoastackedchannel
structuremayoccurbytheendoftheroadmap.
54
 Acknowledgments
CollaboratorsatUCBerkeley
Profs.Hu,King,Bokor

Prof.
Subramanian Digh Hisamoto Hideki Takeuchi Xuejue Huang Wen-Chin Lee Jakub Kedzierski

YangKyu
Choi

Stephen Tang
Leland Chang Nick Lindert

Sriram
Kyoungsub Radu
Peiqi Xuan Balasubramanian Zheng Guo Pushkar Ranade, Charles Kuo, Daewon Ha Prof. Nikolic
Shin Zlatanovici

Earlyresearchfunding:DARPA,SRC,AMD
UCBerkeleyMicrofabrication Laboratory
(birthplaceoftheFinFET)
55