Abstract

Advances in microelectronic technologies have facilitated implementation

of leading-edge circuits particularly in the realm of ultra-low-power circuits
and systems. The focus of this thesis is on the design of reliable integrated
solutions for telemonitoring of biomedical implants. In particular, we focus
on diagnosing in-stent restenosis (re-narrowing) of coronary arteries after
angioplasty. To achieve more ecient wireless power delivery, a modified
version of conventional medical stent, namely antenna stent or stentenna, is
used. In this work, two dierent systems are designed and fabricated in a
0.13-m complimentary metal-oxide semiconductor (CMOS) process.
The first telemonitoring system converts the capacitive changes of the
(pressure) sensors directly to a corresponding frequency change which will be
transmitted to the external reader. Unique to this design is the alignment
unit which is designed to improve the physical alignment of external induc-
tive antenna with the implanted stentenna for the purpose of wireless power
transfer. The system starts operating with the rectified voltage of as low
as 500 mV while consuming 4.15 W, 3.4 W of which is consumed by the
transmitter. The system is designed such that, in alignment mode, the fre-
quency of the pilot signal is directly proportional to the value of the rectified
supply voltage. The monitoring unit, start operating from the supply voltage
of 870 mV while drawing 111.25 A. This system has been successfully tested
in an in-vitro setup. The measured sensitivity of the system is 555 kHz/fF.
This system is capable of detecting capacitance change of as low as 1.3 fF.
The sensor interface circuit of the second system consists of a capacitance-
to-voltage converter and the transmitter includes a voltage-to-frequency con-
verter. The frequency for the transmitted signal is proportional to the
changes of the capacitance of the sensor. Measurement results of a proof-of-
concept prototype show that the system operates from a harvested supply
of as low as 350 mV (from input power of -43.76 dBm at 1.25 GHz) while
drawing less than 100 nA from its harvested supply. The sensitivity of the
system is measured to be 55 kHz/fF.

iii
 Preface

I, Kamyar Keikhosravy, am the principle contributor of all chapters of

this dissertation. Professor Shahriar Mirabbasi who supervised the research
has provided technical consultation and editing assistance on the manuscript.
Pouya Kamalinejad provided technical assistance in the design of high-eciency
rectifiers and reviewed the relative parts of the manuscript. Arash Zargaran
Yazd also provided technical assistance in simulating the optimum frequency
of transmission and preparing the relative manuscripts. Also, Professor
Kenichi Takahata and Professor Victor Leung provided technical and editing
assistance. The material of some of the chapters, as described below, is either
already published or is under review:
Conference papers:

1. K. Keikhosravy, A. Zargaran-Yazd, and S. Mirabbasi, On the use

of smart stents for monitoring in-stent restenosis, in International
Conference of the IEEE Engineering in Medicine and Biology Society
(EMBC), pp. 32313234, Aug. 28Sept. 1 2012 (Chapter 2).

2. K. Keikhosravy, P. Kamalinejad, S. Mirabbasi, K. Takahata, and

V. C. Leung, An ultra-low-power monitoring system for inductively
coupled biomedical implants, in IEEE International Symposium on
Circuits and Systems (ISCAS), pp. 22832286, May 2013 (Chapter 3).

3. K. Keikhosravy, P. Kamalinejad, S. Mirabbasi, K. Takahata, and

V.C.M. Leung, A feasibility study of using backscattering for telemon-
itoring of in-stent restenosis, International Conference of the IEEE
Engineering in Medicine and Biology Society (EMBC), pp. 5167-5170,
2013 (Chapter 6).

iv
 4. K. Keikhosravy, P. Kamalinejad, S. Mirabbasi, and V.C.M. Le-
ung, A Wideband unity-gain buer in 0.13-mm CMOS,IEEE Inter-
national Conference on Electronics, Circuits, and Systems (ICECS),
2013 (Chapter 4).

5. P. Kamalinejad, K. Keikhosravy, S. Mirabbasi, and V.C.M. Leung,

An eciency enhancement technique for CMOS rectifiers with low
start-up voltage for UHF RFID tags, Green Computing Conference
(IGCC), 2013 International , vol., no., pp.1,6, 27-29 June 2013.

6. P. Kamalinejad, K. Keikhosravy, S. Mirabbasi, and V.C.M. Leung,

A CMOS rectifier with an extended high-eciency region of opera-
tion,IEEE International Conference on RFID Technology and Appli-
cations (RFID-TA), September 2013.

7. P. Kamalinejad, K. Keikhosravy, M. Magno, S. Mirabbasi, V.C.M.

Leung, and L. Benini, A high-sensitivity fully passive wake-up radio
front-end for wireless sensor nodes, to be presented in IEEE Interna-
tional Conference on Consumer Electronics (ICCE), January 2014.

Journal papers

1. K. Keikhosravy and S. Mirabbasi, Monolithic current-sensing topol-

ogy for system-on-chip applications, IET Electronics Letters, vol. 48,
no. 21, pp. 1334-1336, October 11, 2012. (Appendix C)

2. A. Zargaran-Yazd, K. Keikhosravy, H. Rashtian, and S. Mirabbasi,

"Hardware-ecient phase-detection technique for digital clock and data
recovery,IET Electronics Letters , vol. 49, no. 1, pp. 20-22, January
3, 2013.

3. K. Keikhosravy and S. Mirabbasi, A 0.13-mm CMOS ultra-low-

power capacitor-less LDO regulator using bulk-modulation technique,To
appear in IEEE Transactions on Circuits and Systems-I (Appendix B).

4. K. Keikhosravy, D. Brox, P. Kamalinejad, S. Mirabbasi, and K.

v
Takahata, An ultra-low-power 35-nW wireless monitoring system for
biomedical applications,submitted (Chapter 5).

vi
Table of Contents

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii
Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Coronary Angioplasty and Stenting . . . . . . . . . . . . . . . 2
1.3 System Building Blocks and General Telemonitoring Approaches 5
1.3.1 Passive approach . . . . . . . . . . . . . . . . . . . . . 7
1.4 Active Telemetry Approach . . . . . . . . . . . . . . . . . . . 11
1.4.1 Frequency of transmission . . . . . . . . . . . . . . . . 11
1.4.2 Telemetry based on inductive coupling . . . . . . . . . 14
1.4.3 Telemetry based on electromagnetic waves propagation 16

vii
 1.4.4 Ultrasonics-based telemetry . . . . . . . . . . . . . . . 17
1.5 Challenges in Wireless Monitoring of Restenosis in Coronary
Arteries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.6 Summary of Contributions . . . . . . . . . . . . . . . . . . . . 19
1.6.1 The proposed capacitance to frequency based telemon-
itoring system . . . . . . . . . . . . . . . . . . . . . . . 19
1.6.2 The proposed capacitance to voltage based telemoni-
toring system . . . . . . . . . . . . . . . . . . . . . . . 20
1.6.3 Study and analysis of telemonitoring based on backscat-
tering . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.7 Thesis Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2 Frequency of Operation . . . . . . . . . . . . . . . . . . . . . 23
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 Calculating The Optimum Frequency . . . . . . . . . . . . . 24
2.3 Modeling Smart Stents Environment for EM Simulations . . . 26
2.4 Experimental and Simulation Results . . . . . . . . . . . . . . 29

3 Telemonitoring System Based on Capacitance to Frequency

Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2 Power Harvesting Unit . . . . . . . . . . . . . . . . . . . . . . 35
3.2.1 Auxiliary and main transmitters . . . . . . . . . . . . . 40
3.2.2 Decision circuit . . . . . . . . . . . . . . . . . . . . . . 43

viii
 3.3 Simulation and Measurement Results . . . . . . . . . . . . . . 45

4 Ultra-Wideband Analog Unity Gain Buer . . . . . . . . . 57

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . 59
4.2.1 Circuit implementation . . . . . . . . . . . . . . . . . . 62
4.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 65

5 Capacitance-to-Voltage Converter Based Telemonitoring Sys-

tem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.2 The Proposed Telemonitoring Architecture . . . . . . . . . . . 74
5.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . 81
5.3.1 Rectifier stage . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.2 Clock generator . . . . . . . . . . . . . . . . . . . . . . 84
5.3.3 Current source . . . . . . . . . . . . . . . . . . . . . . 85
5.3.4 Sample-and-hold circuit . . . . . . . . . . . . . . . . . 87
5.3.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . 88
5.4 Simulation and Experimental Results . . . . . . . . . . . . . . 89
5.4.1 DC performance . . . . . . . . . . . . . . . . . . . . . 91
5.4.2 Transient response . . . . . . . . . . . . . . . . . . . . 95
5.4.3 Frequency response . . . . . . . . . . . . . . . . . . . . 96
5.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

ix
6 Feasibility Study on Backscattering Technique . . . . . . . 102
6.1 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 105

7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.1 Research Contributions . . . . . . . . . . . . . . . . . . . . . . 112
7.1.1 Design and implementation of auxiliary systems and
circuit blocks . . . . . . . . . . . . . . . . . . . . . . . 115
7.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

A A Monolithic Capacitor-less Wide-Band LDO Voltage Reg-

ulator in 0.13-mm CMOS . . . . . . . . . . . . . . . . . . . . 134
A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
A.2 LDO Regulator Analysis . . . . . . . . . . . . . . . . . . . . . 137
A.2.1 Load regulation and line regulation . . . . . . . . . . . 138
A.2.2 Settling time . . . . . . . . . . . . . . . . . . . . . . . 139
A.3 The Proposed LDO Architecture . . . . . . . . . . . . . . . . 143
A.3.1 Challenges with the conventional error amplifier . . . . 143
A.3.2 Analytical background . . . . . . . . . . . . . . . . . . 146
A.3.3 EA structure . . . . . . . . . . . . . . . . . . . . . . . 148
A.3.4 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . 150
A.3.5 Opamp schematic . . . . . . . . . . . . . . . . . . . . . 153
A.3.6 Band-gap circuit . . . . . . . . . . . . . . . . . . . . . 154

x
 A.4 Experimental and Simulation Results . . . . . . . . . . . . . . 156
A.4.1 DC measurements . . . . . . . . . . . . . . . . . . . . . 157
A.4.2 Transient measurements . . . . . . . . . . . . . . . . . 159
A.5 AC Response . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
A.6 Concluding Remarks . . . . . . . . . . . . . . . . . . . . . . . 165

B A 0.13-m CMOS Low-Power Capacitor-less LDO Regulator

Using Bulk-Modulation Technique . . . . . . . . . . . . . . 167
B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
B.2 The Proposed LDO Structure . . . . . . . . . . . . . . . . . . 171
B.3 The Proposed Bulk Modulation Technique . . . . . . . . . . . 175
B.3.1 Driving capability . . . . . . . . . . . . . . . . . . . . . 175
B.3.2 Transient behavior . . . . . . . . . . . . . . . . . . . . 179
B.3.3 Stability analysis . . . . . . . . . . . . . . . . . . . . . 183
B.4 Simulation and Experimental Results . . . . . . . . . . . . . . 188
B.4.1 DC response . . . . . . . . . . . . . . . . . . . . . . . . 189
B.4.2 Transient response . . . . . . . . . . . . . . . . . . . . 191
B.4.3 Frequency response . . . . . . . . . . . . . . . . . . . . 197
B.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

C A monolithic Current-Sensing Topology for System-on-Chip

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
C.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
C.2 Proposed Technique . . . . . . . . . . . . . . . . . . . . . . . . 205

xi
C.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

xii
List of Tables

2.1 List of parameters of equation (2.2.1) used to predict the complex

relative permittivity of tissues from 10Hz up to 100GHz [1] . . . . 27

3.1 Performance summary and comparison of the proposed architecture

with the state-of-the-art designs for similar applications. . . . . . . 56

4.1 Performance summary and comparison with the state-of-the-art ana-

log buers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1 Performance summary and comparison between state-of-the-art de-

signs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7.1 The summary of performance of the proposed systems in this work 114

A.1 Dimensions of transistors in the architecture shown in Fig. A.3.5 . 154

A.2 Transistor Dimensions of Band-gap Circuit . . . . . . . . . . . . . 156

A.3 Performance summary and comparison with the state-of-the-art LDOs.166

B.1 Performance summary and comparison with the state-of-the-art LDOs.199

xiii
List of Figures

1.3.1 A generic building block diagram of a biomedical telemonitoring

system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3.2 Equivalent electrical schematic diagram of a generic smart stent. . 7

1.3.3 Electrical schematic diagram of the reader and stent in passive ap-

proach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.3.4 The spectrum of input impedance Zin seen from reader side, for

this simulation Csen1 = 1 pF , Csen2 = 0.9 pF, Rstent = 1 ,

Lstent1 = Lstent2 = 50 nH , Lext = 1 F , Rrange = 50 and k = 0.01 10

1.4.1 The three-dimensional view of the stentenna [2] . . . . . . . . . . . 11

1.4.2 Simulated matched power gain versus frequency (dierent causes

of loss has been shown on frequency axes). [3] . . . . . . . . . . . 13

1.5.1 Eciency of power transmission with respect to the distance be-

tween reader and transponder antenna [3] . . . . . . . . . . . . . . 19

2.2.1 (a) Anatomical position of heart (side view) [4] demonstrating dier-

ent layers of tissue between external reader and stent (b) Coronary

arteries are not covered by lung (front view) [5] . . . . . . . . . . . 25

xiv
2.3.1 The simulation setup in HFSS. The 2D contour of specified absorp-

tion rate (SAR) is shown on the skin surface. This value is kept

below the maximum allowable of 1.6 W/kg [2] . . . . . . . . . . . . 28

2.4.1 Experimental setup for measuring deliverable power to a stent an-

tenna buried under 40 mm of ground beef. . . . . . . . . . . . . . 31

2.4.2 Experimental and simulated operational power gain (dB) versus fre-

quency [2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.4.3 Power density (PD) of signals transmitted by the stent [2] . . . . . 33

3.1.1 Building blocks of the proposed embedded telemonitoring system. . 35

3.2.1 Schematic of the center tapped stentenna and dierential rectifier. 37

3.2.2 Schematic of the second stage of the rectifier and the input capaci-

tance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.2.3 Schematic of the proposed telemonitoring system. . . . . . . . . . . 39

3.3.1 Micrograph of the fabricated telemonitoring system consisting of

1. auxiliary transmitter, 2. main transmitter, and the DBC and

decision circuit, and 3. rectifier circuit. . . . . . . . . . . . . . . . . 45

3.3.2 The micrograph of the chip emphasizing on the wire bond intercon-

nect in the CQFP80 package. . . . . . . . . . . . . . . . . . . . . . 46

3.3.3 Schematic of the measurement setup. . . . . . . . . . . . . . . . . . 46

3.3.4 The measured output voltage versus the input voltage amplitude of

the rectifier stage at 2.4 GHz. . . . . . . . . . . . . . . . . . . . . . 48

3.3.5 Measured response of dierent blocks of the transponder circuit as

a function of the gradual increase of the input voltage level. . . . . 50

xv
3.3.6 Schematic of the unity gain buer used for measuring the perfor-

mance of the system. . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.3.7 Small-signal (in blue) and large-signal (in red) frequency response

of the unity gain buer designed for testability of proposed system. 52

3.3.8 TX spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.3.9 The in-vitro measurement setup used in this work. . . . . . . . . . 54

3.3.10Transmitted signal frequency of alignment unit versus received input

level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.1.1 The architecture of a conventional amplifier based analog buer. . 59

4.2.1 Architecture of compound amplifier used in this design. . . . . . . 60

4.2.2 Pole-zero location of the proposed buer . . . . . . . . . . . . . . 61

4.2.3 The overall schematic of analog buer presented in this work. . . 62

4.2.4 Frequency response of the opamp and OTA. . . . . . . . . . . . . . 63

4.2.5 Frequency response of the compound amplifier. . . . . . . . . . . . 63

4.2.6 Simulated output voltage level of the OTA with and without the

common-mode feedback circuit. . . . . . . . . . . . . . . . . . . . . 64

4.2.7 Measured step response of the proposed buer for (a) 350 mV and

(b) 700 mV of input step amplitudes. . . . . . . . . . . . . . . . . 65

4.3.1 Micrograph of the presented buer. . . . . . . . . . . . . . . . . . . 67

4.3.2 Measured magnitude frequency response of the proposed buer. . . 68

4.3.3 Output spectrum for a 133.33 mVpp input sinusoid at 100 MHz. 68

5.1.1 Building blocks of a typical telemonitoring system. . . . . . . . . 73

5.2.1 Overall configuration of the proposed telemonitoring system. . . . 76

xvi
5.2.2 The simulated transient response of the CVC block for CSensor =

1.9 pF and CRange = 1.4 pF at supply voltage of (a) 0.35 V (b)

1.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.3.1 Schematic of one stage of the three-stage dierential rectifier. . . . 82

5.3.2 The schematic of clock generator current source and biasing circuit. 84

5.3.3 Example graphs of the simulated output current of the proposed

architecture for VDD = 0.35 V (solid line) and VDD = 1.0 V (dashed

line). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5.3.4 The architecture of the sample-and-hold used in CVC block . . . . 88

5.3.5 Schematic of active transmitter used in this design. . . . . . . . . . 88

5.4.1 Micrograph of the proposed telemonitoring system (a) without (b)

with built-in variable capacitor. . . . . . . . . . . . . . . . . . . . 90

5.4.2 The wire-bond matching used in this work. . . . . . . . . . . . . . 90

5.4.3 The micrograph of the wire bond interconnects for CQFP80 pack-

age. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

5.4.4 Simulated and measured quiescent current for dierent supply voltages 92

5.4.5 The measure performance of the rectifier for dierent input signal

frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5.4.6 The measured generated output voltage of the rectifier, while driv-

ing the CVC system, versus dierent amplitude of the input voltage

at 1.250 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

5.4.7 Measured sensor and range voltages for CRange = 1.3 pF and (top)

CSensor = 7.6 pF and (bottom) CSensor = 2.7 pF. . . . . . . . . . 96

xvii
5.4.8 Measured frequency spectrum of the proposed telemonitoring sys-

tem for dierent C at supply voltage of 0.35 V (top) and 1.0 V(bottom). 97

5.4.9 The simulated and measured output voltage of CVC block and

transmitted frequency of the overall system for dierent values of

C for (a) 1.0 V of supply voltage and (b) 0.35 V supply voltage

(CSensor = CRange + C). . . . . . . . . . . . . . . . . . . . . . . . 98

6.0.1 Schematic diagram of backscattering telemonitoring system using

stent antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

6.0.2 Comparison of the mesh of medical stent and stentenna . . . . . . 104

6.1.1 In-vitro measurement setup. . . . . . . . . . . . . . . . . . . . . . . 107

6.1.2 Measured backscattered power level versus dierent load values and

input powers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

6.1.3 Backscattered power of stentenna compered to conventional stent. 109

6.1.4 The Measured backscattered power from stentenna along vertical

and horizontal axes. . . . . . . . . . . . . . . . . . . . . . . . . . . 110

6.1.5 The measured normalized backscattered power received from the

stentenna versus tissue thickness. . . . . . . . . . . . . . . . . . . . 110

6.1.6 Measured backscattered power with/without layers of ground beef. 111

A.1.1A generic block diagram of an LDO voltage regulator. . . . . . . . 136

xviii
A.2.1Settling time of two conventional LDO regulators with unity-gain

frequencies of 1 GHz (solid line) and 100 MHz (dashed line), for

(a) 500 ns (b) 1 ns load current transitions. The fast regulator has

less output change for the same load transition speed. Also, it can

be seen that for a slower load transition time, the output change

( vout ) is less severe for the faster regulator. . . . . . . . . . . . . 141

A.3.1Small signal transconductance of a nMOS in 0.13 m process versus

drain-source current. In this simulation the drain-source voltage

kept constant and the overdrive voltage is swept. . . . . . . . . . 146

A.3.2Sample Bode plots of two first-order systems S1 , S2 and their par-

allel combination S3 , calculated in Matlab. In this example, G1 =

60 dB, G2 = 20 dB, p1 = 10 rad/s and p2 = 100 k rad/s. . . . . . . 148

A.3.3Compound error amplifier structure similar to that of [6] which

consists of an OTA and an opamp and is used in the proposed LDO

regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

A.3.4Pole/zero locations of the open-loop voltage gain of the proposed

LDO regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

A.3.5Schematics of the opamp used in the error amplifier . . . . . . . . 154

A.3.6Band-Gap Reference voltage and bias circuit . . . . . . . . . . . . 155

A.4.1Micrograph of the test chip which includes an open-loop LDO (LDO

1), a close-loop LDO (LDO 2), and some additional test blocks. . 157

A.4.2Measured DC line regulation in no-/full-load conditions. . . . . . . 158

A.4.3Measured and simulated DC load regulation and quiescent current

of LDO regulator with built-in reference generator. . . . . . . . . . 159

xix
A.4.4Measured turn-on settling time w/o external reference voltage . . 160

A.4.5Regulated ac-coupled output voltage of the regulator for VIN =

1.27 + (0.55) sin((2)38MHz). . . . . . . . . . . . . . . . . . . . . 160

A.4.6Measured transient load regulation for: (a) full load to no-load (b)

no-load to full-load transitions with CL = 0.7 pF. . . . . . . . . . . 161

A.4.7(a) Simulated open-loop gain and phase responses for full load (500 A)

and no load (10 A) with CL =0.5 pF. (b) Measured gain and phase

responses for full load (500 A) and CL

=10 pF. . . . . . . . . . . 162

A.5.1Measured PSR of the proposed regulator under full load (500A). 164

B.1.1Block diagram of a generic LDO voltage regulator. . . . . . . . . 169

B.1.2Schematic of the proposed LDO regulator. To facilitate testing VB

is applied externally. . . . . . . . . . . . . . . . . . . . . . . . . . . 170

B.2.1Simulated gmb versus dierent bulk-source voltages for a typical

pmos pass transistor with (W/L) = (50 m/0.12 m). . . . . . . . 172

B.2.2Block digram of the proposed LDO regulator. . . . . . . . . . . . . 174

B.3.1Ibulk vs. VSB for VS = Vin = 1.2 V and VG = 800 mV. The size

of the pmos transistor is the same as the pass transistor used in

presented LDO regulator(50m/120nm). . . . . . . . . . . . . . . 176

B.3.2The simulated ISD versus Vbulk for pass transistor. Note that the

value of the ISD is normalized for VBS = 0 or Vbulk = 1.2 V. . . . . 178

B.3.3Recovery time analysis for LDO regulator with and without bulk

modulation technique in (a) sudden plunge and (b) increase of the

load current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

xx
B.3.4(top) The phase margin of two regulators in extreme conditions.

The proposed regulator in blue remains stable even when the con-

ventional regulator is about to experience 180 of phase margin,

(bottom) Total parasitic capacitance of the bulk of the pass tran-

sistor versus the equivalent load resistance RL . . . . . . . . . . . . 183

B.3.5Simulated open-loop bode diagram of the proposed LDO configura-

tion with and without bulk modulation technique for load currents

of (a) 3 mA (RL = 0.33 k), (b) 2 mA (RL = 0.5 k), and (c) 0

mA (no-load). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

B.3.6Micrograph of the overall design including two LDO regulators high-

lighted by blue-dashed line. . . . . . . . . . . . . . . . . . . . . . . 188

B.4.1Experimental results of load regulation of the proposed regulator

compared to the conventional one. . . . . . . . . . . . . . . . . . . 189

B.4.2Measured DC response of the regulators to dierent input DC voltage.190

B.4.3Measured start-up transition of the two regulators with and without

bulk modulation technique. . . . . . . . . . . . . . . . . . . . . . . 191

B.4.4Simulated line regulation. . . . . . . . . . . . . . . . . . . . . . . . 192

B.4.5(a) The worst-case recovery time of both regulators measured from

1 mA to 3.2 mA load transition with the 5 ns transition speed

(averaged over 32 signals) and (b) the measured performance of

transient load regulation for load transition speed of 200 ns(averaged

over 16 signals). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

xxi
B.4.6(a) Simulated and (b) measured transient response of regulators,

when the load current suddenly changes to 0 mA and (c) simulated

current load change. . . . . . . . . . . . . . . . . . . . . . . . . . . 196

B.4.7Measured and post-layout simulated PSR performance of regulators

while supplying 1 mA of load current. . . . . . . . . . . . . . . . . 198

B.4.8Measurement setup for PSR experiments. . . . . . . . . . . . . . . 198

C.1.1Top layout view of the proposed current-sensing technique. The

sensing path, formed by spiral-like path using two dierent metal

layers and vias, is encircling the current path. . . . . . . . . . . . . 204

C.1.2The current sheet is broken into several wires carrying equal currents

Ik . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

C.2.1Skin eects depth versus frequency of the passing current. . . . . . 207

C.2.2Calculated (n) for dierent values of n, in 0.13 m CMOS process. 208

C.2.3The measured sensed voltage versus amplitude of current. The fre-

quency of the current in this experiment is 7 GHz. . . . . . . . . . 211

C.2.4Measured trans-resistance gain versus input current frequency as

well as calculated gain obtained from (C.2.6) and simulation results

using Momentum . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

xxii
Acknowledgments

First and foremost, I would like to thank my parents and supportive family;
their tremendous support and help have been the driving force of all my
achievements.
I would also like to thank my advisor, Professor Shahriar Mirabbasi, for
his supervision and guidance during my Ph.D. research. I appreciate his
countless contributions and advice during the course of this research. He is
indeed much more than an academic supervisor, I would always remember
his altruistic support and valuable advice and will benefit from them in the
upcoming stages of my life.
I would also like to acknowledge the Natural Sciences and Engineering Re-
search Council of Canada (NSERC) and the Canadian Institutes of Health
Research for funding this project.
I would also like to thank Canadian Microelectronics Corporation (CMC Mi-
crosystems) for providing CAD tool support and facilitating chip fabrication.
All my colleagues working at the System-on-a-Chip (SoC) Research Labora-
tory deserve a huge thank you for their kind support.
In addition, I would like to especially thank my previous professors, Professor
Parviz Jabedar Maralani at University of Tehran, and Professor Maher Kayal
at cole Polytechnique Federal de Lausanne (EPFL) for their valuable lessons
that enlightened my perspective in research and life.

xxiii
Dedication

To my parents

xxiv
 "# ( & , -/ 1234 5
OP
"7 1:; >=B GH
IKL MN RS

!
!
sad-ha fereshte boose bar aan dast mizanand
kaz kaare khalgh yek gereh-e-baste vaa konad
!

Hundreds of Angles are kissing a Hand

That Opened a tied Snag of the man

Mostafa Etemaadzadeh (M.D.)

xxv
Chapter 1

Introduction

1.1 Motivation

Advances in Complimentary Metal-Oxide Semiconductor (CMOS) transis-

tors technologies have facilitated implementation of leading-edge circuits such
as ultra-low-power systems. Ultra-low-power circuits are essential in many
applications including biomedical implants particularly when the implant is
required to operate from a harvested energy source. Many such implants
are used for monitoring ranging from electrocardiogram (ECG) [7] to elec-
troencephalogram (EEG) [8], from blood pressure [914] to pressure and
temperature monitoring in ophthalmic devices [15] to arterial blood-oxygen
saturation [16]. Due to the depth and size of the implanted device some
designs are more challenging than others [14, 1719]. Aside from some fully
passive designs [2022], the majority of the reported monitoring systems rely

1
on power harvesting from an external reader. As it will be discussed in the
following chapters, the depth of the implant plays an important role on the
power budget of the implanted telemonitoring system. Lower power budget
for deeper implants accompanied by more signal loss for communications be-
tween the external reader and the implanted device adds to the design com-
plexity of such systems. This work is focused on designing power-ecient
implantable monitoring systems. In particular, we focus on monitoring of
in-stent restenosis using an stent with embedded sensors and associated elec-
tronic circuitry. The proposed techniques are general and can be used in
other telemonitoring applications.

1.2 Coronary Angioplasty and Stenting

Heart disease management plays a major role in health-care policies for va-
riety of reasons including patient wellness as well as high treatment cost.
In Canada alone, the cost of heart disease and stroke in physician services,
hospital costs, lost wages and decreased productivity is more than $20.9 bil-
lion every year [23]. Even with advances in health care, on average 16,000
Canadians die each year due to a heart attack [24]. In 2007, approximately
1.3 million Canadians (4.8% of the total population) were living with a heart
disease [25] . According to the American Heart Association, in 2008 the esti-
mated total cost of heart failure in the United States totaled more than $35
billion. The 1.1 million hospitalizations for congestive heart failure (CHF)

2
amounted to nearly $29 billion in hospital charges . As illustrated by the
Home-Care Management Systems study (TEN-HMS), home-based telemoni-
toring systems can facilitate more economical and convenient treatments for
patients with heart failure. . This can be attributed to the fact that patients
equipped with such home-care systems spend less time in hospitals result-
ing in less hospitalization costs [26, 27]. Such telemonitoring systems require
ultra-low-power circuits that either harvest energy from the environment or
have an extended battery longevity. Design of such low-power circuits is the
focus of this research.
Particularly, we consider the wireless monitoring of the in-stent resteno-
sis for patients who had coronary-artery angioplasty. Coronary-artery an-
gioplasty is a surgical method for treating narrowed arteries in patients with
coronary artery disease (CAD). A stent is a mesh like tube which is in-
serted into the blocked or narrowed artery site to keep the lumen open.
Although stent placement significantly decreases the probability of resteno-
sis in angioplasty (as compared to balloon-only angioplasty), studies done
on patients with bare-metal stenting (BMS) show 33% of them suer from
restenosis within 6 months after the surgery [14]. In recent years, drug-eluted
stents (DES) have gained popularity due to their success in reducing in-stent
restenosis. Despite their success, recent studies show that the restenosis oc-
currence in DES sites after one year is around 3.5% and after 2 years reaches
to 4.9% [28]. The probability of restenosis is higher for the smaller vessel
size, for example, restenosis risk increases by 79% for a vessel of 2.7 mm as

3
compared to a vessel of 3.4 mm in diameter [29]. Our research is focused
on an alternative wireless system for monitoring restenosis in stented coro-
nary arteries for both small and large arteries. The presented system oers
both economical and time-saving benefits achieved by supplementing cur-
rent methods of diagnosis with a more convenient wireless technique using
the proposedsmart stentsystems. The term Smart in smart stent refers
to the ability of the proposed stent to monitor, sense and report restenosis.
The proposed smart stent employs the stentenna, i.e., a special helical stent,
reported in [30] to establish an inductive link between the external reader
and the implanted stentenna. The presented smart stent (stentenna with
embedded sensors and telemonitoring circuits) enables two dierent wireless
monitoring approaches. As will be explained later, one approach is to re-
motely measure the value of the embedded capacitive sensors, via inductive
coupling between the stentenna and an external inductor (reader); in essence,
using the stentenna and its sensor as a passive transponder. An alternative
approach is to use an active telemetry system by utilizing an embedded tele-
monitoring integrated circuit (IC) with the stentenna and using the stent as
an transceiver antenna.

4
1.3 System Building Blocks and General Tele-

monitoring Approaches

Other than a few exceptions [2022], most of the reported techniques for
wirelessly diagnosing restenosis are based on monitoring the blood pressure
in an implanted stent site using integrated capacitive pressure sensors [9, 12,
14, 18, 3137].

External Power
Harvesting
Reader
Sensor
Transceiver Sensor(s)
Interface

Telemonitoring system
Tissue

Figure 1.3.1: A generic building block diagram of a biomedical telemonitoring

system.

In case of restenosis, the blood pressure dierence between the two sides
of the stent will increase. Therefore, by monitoring this pressure dierence
the restenosis level can be diagnosed. The reported wireless monitoring med-
ical devices working based on this concept generally consist of the following
building blocks (Fig. 1.3.1):

Sensor : This component is usually a micro-electromechanical device that

converts a physical quantity to a parameter that can be observed and

5
 processed by the following stage(s). For example, for measuring pres-
sure, capacitive pressure sensors are widely used. These sensors convert
the change of pressure to a corresponding change of capacitance.

Sensor interface: This unit interfaces with the sensor and converts the
sensory data to a useful signal that can be transmitted to the external
reader via the transceiver.

Power Harvesting unit: This block generally consists of an energy har-

vesting block that harvests energy for example from an incident RF
signal and then supply power to the rest of units.

Transceiver : This unit establishes the communication link between the im-
planted biomedical device and the external reader and transmits the
sensory data. The communication link is usually a wireless medium.

External Reader : This block monitors and processes the sensory informa-
tion received from the implant. Depending on the monitoring method,
this unit may also transfer power and some command data to the im-
planted device through the forward link.

Depending on the telemonitoring approach used (passive or active) the struc-

ture of these blocks would change.

6
1.3.1 Passive approach

In this approach the impedance of the implanted sensor is passively measured.

Typically, the approach is based on inductive coupling between an external
impedance analyzer (as an external reader) and the implanted device (in this
case, stentenna). Fig.1.3.2 illustrates the equivalent circuit of a generic smart
stent of Fig.1.4.1. In this schematic, Csen represents the capacitance of the
pressure sensor, Rstent represents the stent electrical resistance and Rcont is
the equivalent resistance of the interconnects which connect the output of
the capacitive pressure sensor to the neutral point of the stent (middle of
stent).

Rstent Lstent1 Lstent2 Rstent

Rcont Rcont

Csen1 Csen2

Figure 1.3.2: Equivalent electrical schematic diagram of a generic smart stent.

The capacitive pressure sensors and the stent make an LC band-pass filter
which can be characterized by an external reader. Assuming coupling factor
of k between the external reader with an inductance of Lext and the smart
stent with an inductance of Lstent , the mutual inductance M can be written
as:

p
M =k Lstent Lext (1.3.1)

7
 As shown in (1.3.1), the mutual inductance is directly proportional to
the coupling factor k as well as the inductance of the stent and the external
reader. Figure.1.3.3 shows the equivalent circuit schematic of the external
reader and the modified equivalent schematics of the stent.

Rstent
M1
Rrange
Lstent1 Csen1

Lext
M2
Zin Lstent2 Csen2

Rstent

Figure 1.3.3: Electrical schematic diagram of the reader and stent in passive
approach

In Fig.1.3.3, Rrange is the series resistance between external reader and

the external inductor. Using nodal analysis, the input impedance seen at the
left hand side of the circuit will be:

Zin (j!) = Rrange + j!Lext + (1.3.2)

M12 ! 2 M22 ! 2
+
Rstent + j!Lstent1 + 1/j!Csen1 Rstent + j!Lstent2 + 1/j!Csen2

Assuming Rstent 0, the maximum of Zin (j!) occurs at the frequencies

where the denominator of each fraction becomes zero. These two frequencies

8
are in fact the center frequencies of the two LC tank filters, described earlier.
To obtain these frequencies, the imaginary parts of the denominators must
equal zero; which gives us:

1 1 1 1 1 1
f1 = !1 = p , f2 = !2 = p (1.3.3)
2 2 Lstent1 Csen1 2 2 Lstent2 Csen2

Fig.1.3.4 illustrates the magnitude and phase of Z in (j!) versus frequency.

The peaks in magnitude of impedance which corresponds to the dips in phase,
drop as the Rstent increases. Therefore, the peak reduces as the electrical
resistivity of the stent increases. Equation (1.3.2) also shows that the mutual
inductance M , between the external stent and the reader has a second-order
impact on the phase dips (and magnitude peaks). However, since M is a
function of coupling factor k, therefore, the peaks and dips are a function of
k 2 . On the other hand, the eciency of power transfer in any inductively
coupled link is given by [38]:

k 2 Qext Qstent
= (1.3.4)
1 + k 2 Qext Qstent

where Qext , Qstent are the quality factors of the external reader and internal
inductors . As presented in [39], the coupling factor reduces as dierences
between the external coil radius and the stent radius increases. This means
that for any given size of the stent, there is an optimum external inductor size
which leads to an optimal coupling factor k. Thus, to achieve the desired
coupling factor and quality factor a minimum internal inductor is needed.

9
Figure 1.3.4: The spectrum of input impedance Zin seen from reader side,
for this simulation Csen1 = 1 pF , Csen2 = 0.9 pF, Rstent = 1 , Lstent1 =
Lstent2 = 50 nH , Lext = 1 F , Rrange = 50 and k = 0.01

That is why the commercially available stents should be modified to provide

a better inductance. In addition, It can be shown that the inductive coupling
delivers higher power transmission eciency than EMWP for the distances
p
shorter or on the order of rm = rstent rext , where rstent is the radius of the
expanded stent and rext is the radius of the external inductor coil [38].

10
1.4 Active Telemetry Approach

In the active telemetry, the sensory data is transferred via an active transceiver.
To design the internal telemonitoring system, first, the optimum frequency
for power transmission has to be found. Due to the unique structure of the
stentenna, a series of electromagnetic (EM) simulations are done to calculate
the optimum frequency. In the next stage, the maximum deliverable power
is calculated. In the following sections, we briefly review the simulation pro-
cedure and results.

Figure 1.4.1: The three-dimensional view of the stentenna [2]

1.4.1 Frequency of transmission

Simulation results show that transmission losses through tissues are a func-
tion of frequency of incident signals. The reported inductively coupled bio-
telemetry devices operates in sub-GHz frequencies [12, 31, 32, 4043]. The
choice of frequency was mainly due to:

11
 Tissues absorption increases for higher frequency signals and therefore
lower frequencies are desired to minimize the absorption loss in tissues.

However, due to the sudden change of medium on the skin surface of

the patient (air-skin interface) a portion of the signal reflects and as
a result reduces the eciency of transmission. This phenomenon has
more pronounced for incident fields with lower frequencies.

By taking into account the above mentioned factors, it is possible to compute

an optimum frequency which comprises the losses caused by both phenom-
ena. The frequency is in sub-GHz range (10 to 100 MHz) and has been
applied to almost every design up until very recent years [12, 31, 32, 4043].
However, the eciency of the implanted antenna have been overlooked. This
eciency has a maximum value in GHz frequency range (depending on the
shape and the size of the antenna). In the sub-GHz range, the loss due to
antennas eciency is quite higher than that of the tissue and reflection loss.
Figure.1.4.2 presents simulated losses as a function of frequency [3]. By incor-
porating both dielectric loss of tissues and antenna eciency it is envisioned
that the optimum frequency for a millimeter scale biomedical devices is in
the range of 1 to 5 GHz. A recent study [3] and measurement results [44]
confirm that considering the attenuation of antenna, dielectric dispersion in
tissue begins to play a major role in GHz range frequencies.

12
Figure 1.4.2: Simulated matched power gain versus frequency (dierent
causes of loss has been shown on frequency axes). [3]

Generally, the power budget for in-vivo telemonitoring is quite tight.

In general, the RF signal used for wireless power delivery has to penetrate
through the tissues of the patient and reach the implanted stent. Since the
tissues absorbs a significant portion of the emitted power, there are strict
regulations for the maximum radiated power from an external reader. Ac-
cording to Federal Communications Commission (FCC) [45] regulations for
an averaging time of 6 minutes the radiated power density must not exceed
5 mW/cm2 for the frequency range of 1.5 to 100 GHz and f /300 mW/cm2

13
for frequency range of 300 to 1500 MHz where f is the frequency of trans-
mission in MHz. The frequency of operation mainly depends on the shape,
dimensions, and the depth of the implanted device. Generally, the smaller
the size of the antenna the higher the optimum frequency of operation will
be. However, the absorption of tissues is directly proportional to the fre-
quency of transmission. This trade-o is further discussed in [3]. As it will
be discussed in detail, for the proposed smart stent the maximum calculated
deliverable power is about 50 W, which impose significant challenges on the
design of a reliable transponder integrated circuit. Aside that the technique
that is being used for both power delivery and/or transmitting the sensory
data can fall into 4 categories. The following sections review the commonly
used methods for telemetry in biomedical devices.

1.4.2 Telemetry based on inductive coupling

In this approach, the telemetry is based on mutual inductance between an

internal transmitter and external reader. Two types of telemetry based on
inductive coupling have been reported. In the first type, the implanted ca-
pacitive pressure sensor is integrated with a high quality inductor to form an
LC tank. The internal inductor which works as an antenna is coupled with
an external inductor (reader) establishing a link as shown in Fig.1.3.1). The
internal inductor which acts as a transmitter introduces a passive transpon-
der [40, 41] . This technique is usually referred to as thepassive approach.
The impedance seen from the external reader (using a network analyzer)

14
is a function of the internal inductor and sensor impedance. Therefore, the
changes in sensory variable (e.g., pressure) can be tracked by sensing the cen-
ter frequency of the LC tank. To detect the center frequency of the coupled
LC filter, the frequency of the phase-dip is usually measured. To measure
the phase-dip of the coupled LC tank, a network analyzer with high reso-
lution in phase detection has to be utilized in the reader side which casts
doubt on the low-cost and portability of the wireless monitoring device (e.g.
in [40] D < 0.01 ). However, the main drawback of this method comes
from the internal inductor Lint . As shown in [38], the size dierence be-
tween the implanted inductor (Lint ) and external inductor (Lext ) will eect
the power transmission eciency of the inductive coupling and has to be
kept under a certain threshold. Thus, the internal inductor needs to be big
enough to establish the minimum coupling factor k while serving the min-
imum quality factor Qstent ( 2.6 mm x 1.6 mm in [41] and 6 mm x 2 mm
in [40] )1 . Furthermore, to maintain the minimum coupling, by increasing the
depth of the implant, a larger internal inductor is needed. As a result, the
methods introduced in [40,41] cannot meet the geometrical constraints of the
coronary artery. In the second category of monitoring devices an active tele-
monitoring system is employed to send the sensory data back to the reader
by establishing a backward link as shown in Fig. 1.3.1. This telemonitoring
system can oer higher sensitivity in a smaller implant size [31, 32, 42, 43] .
1
It will be shown later, that there is a maximum size for external inductor dictated by
the stents size.

15
In this method, the monitoring resolution will be determined by the internal
capacitance to voltage or frequency converter (CVC or CFC) circuit which is
integrated along with the implanted biomedical device. Due to the proxim-
ity of CVC or CFC circuits to the sensors, these systems have less noise and
can lead to higher transducer (detection) sensitivity. The main advantage of
this method compared to the electromagnetic wave propagation (radiation)
technique is higher eciency in short coupling distances [14, 38]. Similar
to the passive approach based designs, the reported designs based on active
telemonitoring system have large inductive transmitters (5 mm diameter and
6mm x 6 mm in [31, 42]and [32] respectively) which makes those techniques
impractical for coronary arteries with average diameter of 2.75 mm [46] .

1.4.3 Telemetry based on electromagnetic waves prop-

agation

This approach is based on electromagnetic radiation in which the implanted

antenna receives a portion of electromagnetic waves propagated by trans-
mitting antenna to power up the active internal telemonitoring system. As
shown in the Fig. 1.3.1, the backward link which carries the sensors data to
the reader can be based on either electromagnetic propagation [9,14,37,44] or
electromagnetic back-scattering phenomenon [32, 47]. The main advantage
of establishing the wireless link based on electromagnetic wave propagation
(EMWP) (compared to inductive coupling) is that there is no need for align-

16
ing the primary and the secondary inductive coils (in order to achieve an
excellent matching and maximum power delivery). In addition, it is pos-
sible to achieve higher power transmission eciency in longer transmitting
distances (compared to the inductive coupling method) [14]. However, as
mentioned earlier, for short coupling distances (near field e.g. less than 10
cm) the inductive link can deliver more power eciency, as it becomes an
issue for one of the similar designs which utilized an active telemetry system
based on EMWP. Reported measurements in [14] indicate insucient incom-
ing power which lead to inability in powering up the on-chip transducer IC
(functionality failure in in-vivo experiment) .

1.4.4 Ultrasonics-based telemetry

In this method the ultrasonic transducer harvests the energy of the acous-
tic waves and converts them to an electrical form of energy applicable for
the internal telemonitoring system. Although this technique attracts lots of
attention in dierent bio-medical applications [33], due to the physical geom-
etry and structural dimensions of the coronary artery and the cardiovascular
stent, this method seems impractical.

17
1.5 Challenges in Wireless Monitoring of Resteno-

sis in Coronary Arteries

As stated earlier, the coronary arteries have an average diameter size of 2.75
mm which makes the design of an implantable transducer challenging. The
small diameter of the coronary artery imposes size limits on the internal
antenna which in turn to achieve a reasonable antenna eciency calls for
higher operating frequency. This will make the design of high-eciency in-
ternal transponder more challenging. The reception of incident signal at the
stent site is directly influenced by the tissues electromagnetic (EM) proper-
ties and their thickness. As it is explained in more detail in the next chap-
ter (Fig.2.2.1), several layers of tissue are between the implanted stent and
the external reader. These layers absorb most of the incoming waves (with
electric or magnetic nature) energy. The results of a recent study which is
presented in Fig.1.5.1 reveals the power gain eciency in transmitting elec-
tromagnetic signals will plunge to 0.1% when the implant depth is around
30 mm [3]. These results are in agreement with another in-vivo experiment
showing 47 dB of reduction in received power in EM based implanted an-
tenna with the depth of 35 mm [37] . Knowing the average depth of the
coronary artery is 39 mm [48] it can be observed that we should expect less
than 0.03% power gain delivery. As will be shown further on, there is a max-
imum deliverable power due to the existence of a maximum allowable power
density exposure to living tissue.

18
Figure 1.5.1: Eciency of power transmission with respect to the distance
between reader and transponder antenna [3]

1.6 Summary of Contributions

As mentioned there are dierent school of thoughts for designing such tele-
metric systems. In this work various techniques for telemonitoring of in-stent
restenosis are presented. The proposed structures are designed and fabricated
in a 0.13 m CMOS process and successfully tested in in-vitro setups. In the
following subsections, we briefly overview these contributions.

1.6.1 The proposed capacitance to frequency based tele-

monitoring system

Having simple design in mind, the sensory interface for the first type of tele-
monitoring system is a simple capacitance to frequency converter (CFC).

19
Since in the inductive coupling, maximum power delivery is achieved when
the reader and the implanted antenna are well aligned, a novel alignment
architecture is proposed which ensures the alignment between these two com-
ponents. The measurement results and simulation results confirm the excel
performance of this work compare to similar reported designs. Detail archi-
tecture and functionality of this system is discussed in the following chapters.
The main advantage of this design in comparison to capacitance to voltage
converter based system are higher sensing resolution, simplicity and lack of
needs of a reference or dierential capacitance. Although the power con-
sumption of this system (CFC) in comparison to similar reported systems
is about half of the most power ecient one, however, compare to the next
proposed system (CVC) is not of its merits.

1.6.2 The proposed capacitance to voltage based tele-

monitoring system

To extend the features and flexibility of the first version of telemonitoring

system (CFC based system), the sensor interface circuit is formed by a ca-
pacitance to voltage converter (CVC) stage followed by a CFC stage. Adding
the CVC stage increased the complexity of the system but by careful design
and applying ultra low power design techniques, the overall design provides
more features compare to the first system while consuming much less power
consumption. The proposed telemonitoring system (embedded integrated

20
circuit) consumes 35 nW at 350 mV supply voltage.

1.6.3 Study and analysis of telemonitoring based on

backscattering

Data transmission based on backscattering phenomenon is one of the most

power ecient method of communication. Use of relaxation oscillator can
significantly reduce the power consumption compare to conventional active
oscillators [15]. In this method the data transmission can be done by modu-
lating the antenna load. To study the feasibility of this method using smart
stent (stent as an antenna), a set of experiments are performed which sup-
ports the expectations . more detailed explanations are provided in the
following chapters.

1.7 Thesis Outlines

In this work, dierent techniques for wireless monitoring of biomedical data

is applied and compared. In total, 6 dierent prototypes have been designed,
laid out, and fabricated. The proposed systems oer power consumption
performance and resolution that compare favorably with those of reported
state-of-the-art techniques.
The organization of this thesis is as follows. Chapter 2 discuss the opti-
mum frequency of transmission for this application using stentenna. Chap-
ter 3 Introduce the CFC based telemonitoring system while Chapter 5 provide

21
in-detail description of proposed CVC based system. Chapter 4 presents the
design and implementation of a unity-gain buer specifically developed for
testing the circuits designed in this work. Chapter 6 provides explanation on
feasibility of backscattering technique using smart stent and finally Chapter 7
provides concluding remarks and summary of achievements.

22
Chapter 2

Frequency of Operation

2.1 Introduction

As stated in earlier sections the inductive coupling delivers higher power

transmission eciency as compared to other techniques. Therefore, we have
also chosen inductive coupling for powering up the telemonitoring integrated
circuit (IC) used in this work. In order to establish an inductive link between
the implanted antenna and external reader, a relatively large transmitting
antenna (compared to the size of the artery) is required. In addition, to
maintain this link for biomedical devices implanted in further depth, even
larger transmitting inductor (internal antenna) is needed1 . In 2003, [30] in-
troduced, an inductive stent with minimum modifications in the structure of
1
In order to deliver the minimum required power to transponder circuit in further
depths, the quality of the inductive link has to be increased which leads to a bigger
internal inductor.

23
conventional medical stent. The experimental results shown in [12] proves
the concept of remote monitoring via proposed inductive stent (stentenna).
Having a stent as an inductor facilitates wireless monitoring of the pres-
sure in small arteries such as the coronary artery by eliminating an extra
bulky transmitting inductor [31, 32, 4042]. However, a set of simulation and
measurements are needed to obtain the optimum frequency range of power
transfer using proposed stentenna [30] . Simulation and measurement results
provided in the following sections prove the feasibility and advantages of the
presented stentenna.

2.2 Calculating The Optimum Frequency

To simulate the optimum frequency for this application (having stentenna as

an transceiver antenna), first the environment where the stent is located in
should be modeled. Fig. 2.2.1 shows, all dierent tissues between the external
reader and the smart stent placed inside the coronary artery. Fortunately,
about 65% of this space is taken by rib bones (ribs) which have less absorption
loss than live tissues. In addition, as the Fig. 2.2.1(b) demonstrates, that
part of heart where hosts the coronary arteries is not covered by lung. That
simplifies the modeling since we know that the tissues thickness would not
change by patients breathing.
In order to model the tissues absorption, the equivalent dielectric loss
for each type of tissue have to be modeled . Therefore following equivalent

24
 (a)

(b)

Figure 2.2.1: (a) Anatomical position of heart (side view) [4] demonstrating
dierent layers of tissue between external reader and stent (b) Coronary
arteries are not covered by lung (front view) [5]

complex permittivity model for dielectric spectrum of tissues has been used
[1] :

5
X "n i
"(!) = "1 + + (2.2.1)
n=1
1 + (j!n )(1 ) j!"

where " = "s "1 and " is the permittivity at field frequencies where
! o 1, "s is the permittivity at ! n 1, i is the static ionic conductivity ,

25
"0 is the permittivity of free space and is time constant of polarization mech-
anism. Two key factors for modeling any tissues for electromagnetic (EM)
simulation in high frequencies are complex values of dielectric permittivity
and permeability. A detail description on these parameters are provided in
the modeling section. Table 1 presents complex permittivity coecients in
each dierent tissues between external reader and stent associated with the
thickness of each tissues.

2.3 Modeling Smart Stents Environment for

EM Simulations

For obtaining maximum power delivered series of simulation has been per-
formed using Ansys HFSS v.13 and Comsol Multiphysics 4.2. Following are
the summary of tissues between skin and coronary artery.

Skin with mean thickness of 1.22 mm

Adipose-Layer just below skin Muscle and intercostals muscles Mean thick-
ness of 10 mm

Ribs Thickness varies between 25 mm

Pericardium Surrounds heart and is 1.15 mm thick

Coronary-artery Wall thickness is 1.2 mm

26
Blood Inside the coronary artery, the diameter of the coronary artery after
stenting can reach up to 5 mm

Table 2.1: List of parameters of equation (2.2.1) used to predict the complex
relative permittivity of tissues from 10Hz up to 100GHz [1]
Ribs Blood Blood fat
dry wet Pericar-
Tissue (concel- vessel in the (infil-
skin skin dium
lous) wall artery trated)
Thickness
1.22 1.22 1.15 20.0 1.2 5 10
(mm)
"1 4.0 4.0 4.0 2.5 4.0 4.0 2.5
"1 32.0 39.0 50.0 18.0 48.0 56.0 9.0
"2 1100 280 7000 300 2500 5200 35
3.1 1.2 2.0 2.0 3.3
"3 0.0 0.00
104 106 104 105 104
3.0 2.5 2.0 5.0 1.0
"4 0.0 0.00
104 107 107 107 107
1 0.00 0.10 0.10 0.22 0.10 0.10 0.20
2 0.20 0.00 0.10 0.25 0.15 0.10 0.10
3 - 0.16 0.10 0.20 0.25 - 0.05
4 - 0.2 0.00 0.00 0.00 - 0.01
1 (ps) 7.23 7.96 7.23 13.26 7.96 8.38 7.96
2 (ns) 32.48 79.58 353.68 79.58 63.66 132.63 15.92
3 (s) - 1.59 318.31 159.15 265.26 - 159.15
4 (ms) - 1.592 2.274 15.915 6.366 - 15.915
0.0002 0.0004 0.2000 0.0700 0.0300 0.7000 0.0350

The average distance between heart and skin is 39 mm [48] which is in

close agreement with above geometries. The compositions of intercostals
muscles and muscles are roughly the same, and thus for the purpose of simu-
lations they are considered as one layer of muscle. Furthermore, pericardium
consists of connective tissue and mesothelium which have similar electromag-

27
netic properties and thus they are grouped together with coronary artery
wall.
In order to increase the accuracy of the simulations, the magnetic sus-
ceptibility of the blood should be taken into account. Blood magnetic sus-
ceptibility is dierent in case of oxygenated or deoxygenated blood. For
arterial oxygenated blood the value of the magnetic susceptibility has been
measured to be 6.610 7
while this quantity for the deoxygenated blood
is 3.5106 [49]. Thus, the value of relative permeability r = m + 1 is
0.999, 9934 and 1.000, 0035 which is approximately 1 (the default value for
all tissues).

Figure 2.3.1: The simulation setup in HFSS. The 2D contour of specified

absorption rate (SAR) is shown on the skin surface. This value is kept below
the maximum allowable of 1.6 W/kg [2]

28
2.4 Experimental and Simulation Results

The simulation setup in ANSYS HFSS is presented in Fig. 2.3.1 (and ap-
peared in [2]). As expected (and as analyzed in [3]), there is an optimum
frequency for power gain transmission for smart stent at which the power
transmission gain reaches 28 dB. Fig.2.4.2 shows the transmission operat-
ing power gain (dB) for dierent excitation frequencies. According to these
results the optimum frequency is about 0.8 GHz. To simulate the maximum
deliverable power we have to apply the maximum allowable power Pin to the
reader antenna and calculate the received power PL using following formula:

PLmax = Gmax max

P Pin (2.4.1)

The maximum excitation power at the external coil, set by the Federal
Communication Council (FCC), limits the maximum radio-frequency radia-
tion exposure (RRE) to lower than 5 mW/cm2 over the frequency range of
0.1 to 5 GHz (For frequencies below 1500 MHz the power limit is frequency
in MHz divided by 300) [45]. By applying Pin
max
= 35.58 mW, the maximum
power density on the skin reaches to 2.56 mW/cm2 (which is very close to the
maximum allowable of 2.66 mW/cm2 at 800 MHz). Therefore, using (2.4.1),
the maximum deliverable power is:

29
 28
PLmax = 10( 10
)
35.58 mW= 56 W (2.4.2)

In order to verify the simulation results obtained from ANSYS HFSS

and COMSOL Multi Physics finite element simulator, a similar experi-
mental setup as depicted in Fig. 2.4.1 has been employed. In this experiment
to mimic the surrounding tissues around the implanted stent, the inductive
stent is surrounded by ground beef with extra fat. The reader coil is the same
as that modeled for EM simulations and is connected to one port of a vector
network analyzer (VNA), Anritsu MS2034A. The two sides of the stent are
connected to the other port of the VNA and the scattering parameters of
the system are measured. To ensure that the returning path is not intro-
ducing an unwanted induction loop and a ground plane has been utilized.
The ground plane makes the returning signal to travel exactly underneath
the buried stent and therefore it avoids forming a parasitic loop between
returning path and stent. The operating power gain is given by:

PL |s21 |2 (1 | L|
2
)
GP = = (2.4.3)
Pin |1 s22 L |2 (1 | in |
2)

where s21 and s12 are the forward and reverse gain scattering parameters
of the system and L and in are the load and input reflection coecients.
PL is the delivered power on the stent site and Pin is the excitation power at
the reader terminal. Note that in this measurement (and simulation) setup,
all system terminals are terminated to a 50 W impedance and therefore,

30
 L = in = 0. In such conditions, Eq. (2.4.3) for operating power gain
(GP ) can be simplified to GP = |s21 |2 . In this experiment, the stent has
been surrounded by ground beef of the depth of 40 mm and the reader is
located at 4 mm distance from the ground beef surface. The experimental
value of power gain versus frequency are also appended in Fig.2.4.2.

Figure 2.4.1: Experimental setup for measuring deliverable power to a stent

antenna buried under 40 mm of ground beef.

EM simulation results for stentenna shown in Fig. 1.4.1 and , estimate

56 W induced power while the skin has been exposed to 2.56 mW/cm2 of
power density. To compare this result with measured induced power based
on EMWP for 35 mm depth for implanted stentenna, the expected power
transmission gain () is 0.03% therefore, total received power on the stent
site having exposure power density of Pin is given by:

Pr = Pin A

31
 where A represents the area of the stent exposed to the incident waves.
Assuming Pin = 2.66 mW/cm2 , A = 20 mm (2.75 mm) = 1.728 cm2 ,
Pr = 1.37 W. Based on this simple calculation, even if we assume 100%
eciency for the implanted stent as an antenna, with the inductive-coupling-
based power delivery approach, one can achieve 56 W 1.37 W ( 55 W)
more power at the implant site. This shows the advantage of using stentenna
for small vessels such as coronary artery.

20
COMSOL
30 Measurement
HFSS
40
Power Gain (dB)

50

60

70

80

90

100 6 7 8 9
10 10 10 10
frequency (Hz)

Figure 2.4.2: Experimental and simulated operational power gain (dB) versus
frequency [2].

Assuming that most of the transferred power will be used for the trans-
mission of sensor signals (in this case, 50 mW), we can calculate the power

32
density of the backward link established by internal IC on the surface of the
skin. Fig. 2.4.3 presents the 2D map of observable power density on the skin
surface, transmitted from the smart stent. The observed power which has
the maximum of 5 pW/cm2 over the simulated skin area can be sensed by
careful design of the reader antenna. Note that the asymmetric power density
map caused by radiation of the stent can be attributed to the asymmetric
geometry of the stent. As can be seen from stentennas diagram (Fig. 1.4.1),
to improve the physical strength of the stentenna, two platfroms are added
at each side of the stent which result ina asymmetric radiation pattern of the
stent.

Figure 2.4.3: Power density (PD) of signals transmitted by the stent [2]

33
Chapter 3

Telemonitoring System Based

on Capacitance to Frequency
Conversion

3.1 Introduction

In this section the design and performance analysis of the proposed tele-
monitoring system based on direct conversion of capacitance to frequency is
presented. Fig. 3.1 shows the block diagram of the proposed monitoring IC.
As shown, the proposed system consists of two main building blocks, a har-
vesting unit to provide the required supply voltage to the rest of the system,
and alignment and monitoring unit which consists of two transmitters and a
DC biasing circuitries and a decision circuit. The decision circuit is placed to

34
Figure 3.1.1: Building blocks of the proposed embedded telemonitoring sys-
tem.
improve the reliability of the inductive coupling link between the implanted
stentenna and the external reader. The following sections further elaborate
the functionalities and performance of the above-mentioned building blocks.

3.2 Power Harvesting Unit

To eciently convert the received RF power to an stable DC power to supply

the entire monitoring system circuitry, a three stage dierential-drive rectifier
is used [50]. In standard CMOS technology, the dierential-drive rectifier
outperforms conventional Dickson-based rectifier specifically for small input
levels and is therefore the best candidate to serve as the power conversion unit
in the monitoring system. Note that in the alignment mode, the stentenna
receives very small input levels (well below the threshold of CMOS transistors
in 0.13 m CMOS technology) which mandates a high-eciency rectifier
to guarantee that sucient power is delivered to the succeeding circuitry.
The superior power conversion eciency (PCE) of dierential-drive rectifier

35
(compared to conventional Dickson-based single-input rectifier) justifies the
extra complexity imposed by the dierential input requirement. In practice,
the two dierential input (in+ and in- in Fig. 3.2.1) could be extracted from
the two ends of a center-tapped stentenna, while the its center could be used
as the ground.
It should be noted that it is the combined eciency of the stentenna and
the rectifier that determines the overall performance of the power harvesting
unit. That is, a good matching has to be established between the stentenna
and the input of the rectifier to guarantee that sucient power is delivered
from the stentenna to the rectifier and subsequently, from the rectifier to
the entire monitoring system. At the frequency of interest (2.4 GHz), the
stentenna could be modeled by an inductor and the rectifier is modeled by
the parallel combination of a capacitor Cin and a resistor Rin as shown in
Fig.3.2.2 [51]. The resistive (real) part of the input impedance represents the
average DC current drawn from the inputs by the load (succeeding circuitry)
and the parasitic losses and is therefore load dependent. The capacitive
(imaginary) part of the input impedance accounts for the series combination
of the coupling capacitors (CC in Fig. 3.2.2) and the parasitic capacitance
of the switching transistors MPi, Ni (Cpar ). To achieve a good matching be-
tween the stentenna and the rectifier, the capacitive (imaginary) component
of the rectifiers input impedance and the inductance of the stentenna have
to resonate at the frequency of operation (i.e. 2.4 GHz). For this purpose,
although the inductance of the stentenna is dictated by its geometry, the

36
input capacitance of the rectifier could be designed so as to resonate with
the inductance of the stentenna at 2.4 GHz. As shown in Fig.3.2.2, given
that CC Cpar , the input capacitance of the rectifier is dominated by
the parasitic capacitance of the switching transistors (Cpar ). Note that Cpar
is composed of the source/drain capacitance of Mp1, n1 and the gate capaci-
tance of Mp2, n2 as shown in Fig. 3.2.2. Therefore, by optimizing the size of
switches, a high PCE and the appropriate input capacitance for the operation
frequency of 2.4 GHz could be achieved simultaneously.

in+
DCout
stentenna

in+
GND

load
in-

in-
Rectifier (differential)

Figure 3.2.1: Schematic of the center tapped stentenna and dierential

rectifier.

To improve the eciency of the the system and to ensure that the system
is able to operate with small incoming signal amplitude, a voltage matching
in+
in+
Zin+ = Rin+ + jXCin+ CC Cin+
CC
Mn1 Mp1
Cpar
Cpar
out1 out2
Cpar

CS/D, n1 CS/D, p1
Mn2 Mp2

Zin- = Rin- + jXCin- CC CG, n2 CG, p2

in-

Figure 3.2.2: Schematic of the second stage of the rectifier and the input
capacitance.

37
circuit is placed between the stentenna and the rectifier stage. The voltage
matching circuit consists of a series inductor that will resonate with the
input capacitance of the rectifier stage. However, for transmitting sensory
data through stentenna a power matching circuit is required to ensure that
most of the available power at transceiver unit is transmitted to the external
reader. Simulation results show that the designed rectifier can provide up to
1.0 V of supply voltage from a voltage-matched incoming dierential signal
of 74.92 mV amplitude (-25.1 dBm). The power eciency of the rectifier
is simulated to be 64% at 1.0V output voltage and 41% at 400 mV output
voltage.
In contrast to typical telemonitoring architecture, the proposed system
does not include a voltage regulator stage for three main reasons: firstly, the
incident signal received by the rectifier is at 2.4 GHz, thus the fundamental
frequency of ripples of the rectifier stage will be at 2.4 GHz. A regulator which
is capable of actively rejecting 2.4 GHz ripples should have a high closed-loop
bandwidth and therefore is power hungry [52] and is not feasible for this low-
power application. Secondly, in the architecture of the monitoring circuit no
digital blocks or clock signals are used and therefore the load variation is
not significant. This relaxes the voltage regulation requirements and some
degree of voltage variations can be tolerated. Thirdly, since the rectifier is
driving an ultra-low power monitoring circuit which could be modeled as
large equivalent resistance, the combination of the large load resistance and
the rather small smoothing capacitance at the output of the rectifier form a

38
 VDDaux VDDmain
VDD

M21 M22 M16 M17

M4 M3 M6 M8 M10 M12

Laux R1 Lmain

ok ok
Cpar M2 VB aVin CSensor

M1
M19 M20 M14 M15
M5 M7 M9 M11
RBG R2
VB M18 VB M13

Dynamic biasing circuit Decision Circuit

Main Transmitter
Auxiliary Transmitter
39

Figure 3.2.3: Schematic of the proposed telemonitoring system.

passive RC filter. This filter suciently attenuates the high frequency ripples
at the output of the rectifier.

3.2.1 Auxiliary and main transmitters

For relatively short distances between the transmitter and receiver, despite
superior power transfer eciency of the inductive link as compared to electro-
magnetic wave propagation (EMWP), misalignment in inductive coupling
can significantly deteriorate the power transfer eciency [53]. To establish
an ecient power transfer link between the external reader and the internal
IC using inductive coupling, the internal and external antennas have to be
reasonably aligned. To achieve such alignment an ultra-low-power auxiliary
transmitter is designed which transmits pilot signals to the external reader
depending on the amplitude of the internal rectified voltage. The alignment
unit transmits a frequency that is directly proportional to the amplitude of
the received rectified voltage. A low-power complimentary crossed-coupled
LC oscillator similar to [54] is used for both auxiliary (alignment) and main
transmitter oscillator circuit (as shown in Fig. 3.2.3), however, as described
below, the auxiliary oscillator is designed to have a significantly lower power.
As shown in Fig. 3.2.3, the overall small-signal transconductance of the
oscillator circuit is given by:

tot
gm = 2gmn + 2gmp (3.2.1)

40
 where gmn and gmp are the small-signal transconductance of the NMOS
and the PMOS transistors, respectively. To have a sustained oscillation the
following condition has to be satisfied:

tot
gm Gparalel (3.2.2)

where Gparallel , is the total equivalent conductance of the passive elements

in the tank circuit and includes the parasitic conductance of the inductor and
capacitor. Note that the combined transconductance of cross-coupled active
components is a negative conductance.
The total amount of parallel positive (passive) conductance can be cal-
culated as follows:

Gparallel = Gind cap

par + Gpar + gdsn + gdsp (3.2.3)

where gdsn and gdsp are the transconductance of NMOS and PMOS tran-
sistors, respectively and Gind
par , Gpar are the equivalent parallel conductance
cap

par and Gpar are

of inductor and capacitor at the output. The amount of Gind cap

directly proportional to the frequency of operation and the quality factor of

the corresponding energy storage elements (i.e., the series resistance of those
elements). Assuming, storage elements with quality factors of QL = !L/Rs,L
and QC = 1/(Rs,C !C) where Q2 1:

1 Rs,L
Gind
par = 2
2 2 (3.2.4)
Rs,L (QL + 1) ! L

41
and,

1
Gcap
par = Rs,C ! 2 C 2 (3.2.5)
Rs,C (Q2C + 1)

in which Rs,L and Rs,C are the series (parasitic) resistance of the storage ele-
ments. To decrease the power consumption in auxiliary transmitter, Gparallel
has to be reduced which in turn decreases the required gm
tot
(recall 3.2.3).
Therefore, less bias current will be needed to achieve the required transcon-
ductance. According to (3.2.3), Gparallel , can be reduced by increasing the
inductance L and decreasing the capacitance C of the output tank of the
transmitter (Fig. 3.2.3). Note that ! is the resonance frequency of the tank,
p
i.e., the angular frequency of oscillation, and is equal to 1/ LC.
Based on the above discussion, one can reduce the capacitance of the
LC tank in order to decrease the bias current and consequently, the power
consumption of the oscillator. At the frequency of interest and for a su-
ciently large inductor, the capacitor can be reduced to values comparable to
the parasitic capacitors of the NMOS and PMOS transistors. Therefore, the
parasitic capacitance of the devices could be used as the main capacitor of
the LC tank.
In addition to the power consumption improvement, relying on the par-
asitic capacitance of the devices makes the frequency of operation of the LC
oscillator a bias-dependent value. This in turn is useful as the bias value
can be monitored based on the oscillation frequency, which is one the main

42
purposes of the alignment unit.
In practice, the main transmitter is directly connected to the capacitive
pressure sensors which have a base capacitance of 1.6 pF. One such capac-
itance that mimics the capacitance of the pressure sensor is integrated on
the chip for test purposes. Note that due to variation of the rectified supply
voltage (VDDmain in Fig. 3.2.3) the operating point of the main transmitter
may change which results in changes in the parasitic capacitance and thus
the frequency of oscillation. Therefore, in order to minimize the variations
of the operating point, the dynamic biasing circuit (DBC) attempts to mini-
mize the changes of the bias voltage over the operation range of the rectified
supply voltage (i.e., VDDmain from 0.85 to 1.2 V in Fig. 3.3.5).

3.2.2 Decision circuit

The operation of the decision circuit is as follows. At the start-up, if the

received power (induced voltage) is insucient for the proper operation of
the monitoring system (i.e., main transmitter), the controller turns the main
oscillator o and switches the auxiliary low-power transmitter on. Switching
o the main oscillator at the start up reduces the current load of the rectifier
which in turns helps boosting the rectified output voltage [50, 55].
By gradually adjusting the relative position of the primary (reader) and
secondary (stentenna) coils towards achieving a perfect alignment, the in-
duced voltage level starts to build up at the output of the rectifier. Since the
capacitor of the LC tank of the auxiliary oscillator is formed by the parasitic

43
capacitances of the transistors, any change in the harvested supply voltage
of this oscillator can change the operating point of the transistors and hence
the capacitance of the oscillator. This change in the capacitance can be ob-
served by the change in the transmit frequency of the auxiliary transmitter.
Note that the frequency of transmission for auxiliary oscillator (alignment
transmitter) is in a dierent range as compared to the frequency range of the
main oscillator (monitoring transmitter). Therefore, based on the received
frequency range, the operator can distinguish which unit is operating. After
the required power threshold for proper operation of the monitoring system is
achieved, the controller switches o the auxiliary oscillator and turns on the
main transmitter. Note that the internal threshold voltage of the inverters
(in Fig. 3.2.3) is used as the reference voltage for the decision circuit which
enables the use of a simple chain of inverters as a low power comparator. On
the other hand, as explained earlier, at the start-up, when the rectified volt-
age is low, the DBC, sets the tail current of the auxiliary transmitter at the
minimum operational level to guarantee that a link is established between the
reader and stent. The proposed alignment unit for monitoring the received
power can also be used in non-inductive wireless monitoring systems (e.g.,
EMWP-based links). Although both oscillators are sharing the same sten-
tenna for transmission and thus their output nodes are connected, when the
alignment unit is activated (when Saux in Fig. 3.1 is on) the supply voltage of
the main transmitter is float ( Smain in Fig. 3.1 is o) and therefore the main
oscillator load the stentenna with a high impedance. Consequently, when the

44
auxiliary transmitter is active it is not loaded by the main transmitter. A
similar scenario works when the main oscillator is activated.

3.3 Simulation and Measurement Results

Two proof-of-concept prototypes of the proposed system are designed and

fabricated in a 0.13 m CMOS process; one is tested using on-chip probing
(Fig. 3.3.1) and the other one is packaged and tested (Fig. 3.3.2). The overall
chip occupies 0.484 mm2 (1100 m 440 m). The second prototype is
packaged in a standard 80-pin ceramic quad flat package (CQFP 80). We
first present the experiments that are carried to measure the performance of
the system when a weak input is supplied to the chip directly from a signal
generator. Then, we present the in-vitro measurements of the overall system
while the power is wirelessly delivered to the system.

Figure 3.3.1: Micrograph of the fabricated telemonitoring system consisting

of 1. auxiliary transmitter, 2. main transmitter, and the DBC and decision
circuit, and 3. rectifier circuit.

45
Figure 3.3.2: The micrograph of the chip emphasizing on the wire bond
interconnect in the CQFP80 package.

Infiniimum
DSO81304A
Agilent 83732B
Picosecond 5310

InfiniiMax RFin
1169A in+ in-

Wire-bond
LWB interconnects

` `
Cin- Cin- Rin

Rectifier Telemonitoring

Tele-monitoring chip

CQFP-80 package

Printed Circuit Board

Figure 3.3.3: Schematic of the measurement setup.

The simulated power conversion eciency (PCE) of the rectifier at 2.4 GHz
for a load current of 178 A (where the monitoring transmitter start oper-

46
ating and supply voltage of the monitoring unit is at 850 mV) is 52%.
Note that the wire bond inductor in the package is used as the input volt-
age matching network. The inductive behavior of the wire bonds that con-
nect the IC pads to the package leads have been studied in the literature
(e.g., [56]). Given that we had access to the electrical model of the 80-pin
CQFP package used in this work (the model was provided to us by CMC Mi-
crosystems) and we could estimate the length of the wire bonds connecting
the input signals to the rectifier (by properly positioning the chip inside the
package), we designed the input capacitance of the rectifier in such a way
that the combination of the wire bond inductance and the input capacitance
of the rectifier resonates at the frequency of interest (i.e., 2.4 GHz). The
micrograph of the associated wire-bond interconnect for CQFP80 package is
shown in Fig. 3.3.2. For a wire-bond length of 3.5 mm, the wire-bond induc-
tance is estimated (and later verified by measurement) to be LWB =15.5 nH.
Thus, the input capacitance of the rectifier is designed to be 280 fF in order
to resonate with 15.5 nH inductance of the wire bonds at 2.4 GHz. Fig. 3.3.3
shows the test setup for this measurement. As shown in the figure, the input
voltage is measured with an Agilent 1169A 12-GHz InfiniiMax active probe
which is connected right at the input pins of the package to avoid the ad-
verse eects of the dierential balun and PCB traces. The measured output
voltage versus input voltage of the rectifier block is shown in Fig. 3.3.4.
At the rectified voltage of 500 mV (which corresponds to 10 mV input
amplitude level and 30 dBm input power as shown in Fig. 3.3.4) the aux-

47
iliary transmitter starts to operate reliably while drawing 6.8 A of current.
The decision circuit switches o the auxiliary transmitter when the output
voltage of the rectifier reaches 870 mV. The monitoring (main) transmitter
is turned on when the rectified voltage reaches 880 mV. It should be noted
that there is a small voltage drop across the switch Smain in Fig. 3.1 and
therefore, VDDmain is about 10 mV lower than the rectified voltage. The
monitoring transmitter draws 178.3 A when it starts to operate. The nom-
inal transmission frequency of the monitoring transmitter is expected to be
2.12 GHz (since the inductance of the LC tank is 3.53 nH and the sensor base
capacitance is set to 1.6 pF). The measured nominal frequency is 2.031 GHz
(see Fig. 3.3.8) which can be attributed to the parasitic capacitance added
by the measurement setup.

3
Rectified supply voltage (DC)

2.5
VoutDC = 880 mV
2 Vinamp = 69.35 mV
Pin = 13.18 dBm

1.5
Align. Mont.
1
Dynamic bias Constant bias
0.5

0
1 5 10 50 100 200
Input signal amplitude (mV)

50 36 30 16 10 4
Input power (dBm)

Figure 3.3.4: The measured output voltage versus the input voltage ampli-
tude of the rectifier stage at 2.4 GHz.

As discussed earlier, depending on the amplitude of the induced signal

48
on the stentenna, the overall system operate either in the alignment mode or
the monitoring mode. To measure the steady-state behavior of the system
and to measure the overall current of the system we have used the HP 4155A
semiconductor parameter analyzer to mimic the gradual increase in the DC
voltage of the rectifier output and measure the current drawn by the system.
Fig. 3.3.5 shows the behavior of the system as a function of the rectified
voltage.
As expected the DBC enables the auxiliary transmitter at 7.5 mV of in-
put amplitude signal which corresponds to 300 mV of rectified voltage and
which makes the auxiliary supply voltage to be at 262 mV. Note that this
voltage is still not enough for the transmitter to start oscillating. By increas-
ing the rectified voltage to 500 mV, the auxiliary voltage reaches to 485 mV.
At this supply voltage the auxiliary transmitter starts oscillating and the
overall current drained by the system is only 8.3 A (yields to total power
consumption of 4.15 W). Note that the alignment (auxiliary) transmitter
draws 5.85 A of total current. At this point the frequency of transmission
(as provided in Fig. 3.3.10) is 180 MHz. By Increasing the rectified voltage
the DBC increases the biasing voltage (VB shown in Fig. 3.3.5) of auxiliary
transmitter to mimic the main transmitters current load. Meanwhile the
alignment transmitter keep increasing the transmission frequency as the rec-
tified voltage increases. This Biasing voltage is shown in Fig. 3.3.5 as VB and
as shown it will keep raising till input level reaches 700 mV. After this point
the biasing voltage decreases and remains at 480 mV while DBC disables the

49
axillary transmitter and enables the monitoring transmitter.
1.2 Total current drained by system 300
Supply voltage of monitoring unit (Ok signal)
VB (from DBC)

1 Suppy voltage of alignment unit (Okbar signal) 250

0.8 200

Total current (A)

Voltage (V)

Monitoring unit
operates
0.6 150
Alignment unit
operates

0.4 100

0.2 ~870 mV 50

0.3 0.4 0.6 0.8 1 1.2

Rectified voltage (V)

Figure 3.3.5: Measured response of dierent blocks of the transponder circuit

as a function of the gradual increase of the input voltage level.

Simulation results show that the DBC and decision units consume 326 nW
and 19.943 nW at their peak of consumption in alignment phase respectively
(at 0.87 V of rectified supply voltage). The measurement results reveals that
the DBC and decision units combined, consume 1.225 W when the rectified
voltage reaches 500 mV and 8.7 W for the rectified supply voltage of 870 mV
(e.g., auxiliary supply voltage of 847 mV). Note that DBC block itself is
simulated to consume 669.12 nW in its peak of consumption in monitoring
phase (at 1.2 V supply voltage). In addition the decision circuit consumes
902.8 nW for maximum rectified voltage of 1.2 V.

50
 VDD_Buffer

Vin
EA

Vout
VDD_Buffer

Figure 3.3.6: Schematic of the unity gain buer used for measuring the
performance of the system.

The spectrum of the auxiliary and main transmitter are measured using
Agilent PXA signal analyzer (N9030A). Since the transmitters output is
matched to the input impedance of the antenna stent (approximately 1 k)
and the input impedance of the measurement devices are 50 a unity gain
buer circuit is required to measure the performance of the transmitters
(alignments and monitoring).
Fig. 3.3.6 illustrates the block-diagram of the unity-gain buer used in this
circuit. The buer has a measured large-signal bandwidth of 2 GHz [57].

51
 10
Small signal
Large signal

Voltage gain (dB)

3
3 dB BW @ 1.65 GHz

5 3 dB BW @ 2.63 GHz
1M 10M 100M 1G 2G3G
Frequency (Hz)

Figure 3.3.7: Small-signal (in blue) and large-signal (in red) frequency re-
sponse of the unity gain buer designed for testability of proposed system.

Fig. 3.3.8 presents the buered spectrum of the transmitter when the
CSensor = Cbase = 1.6 pF with an extra 230 fF parasitic capacitance added
by adaptors and test setup. Aside from better eciency of wireless power
transfer, another advantage of transmitting at higher frequencies is the im-
proved sensitivity of the overall system as given by the following expression:

@f @ 1
= p
@C @C 2 LC
C=Cbase C=Cbase
(3.3.1)
1 f0
=
2 Cbase
p
Where f0 = 1/2 LCbase . For an inductance of 3.353 nH (note that due
to the use of buer the eect of bond-wire inductance on the inductance of
the LC tank is negligible) and total base capacitance (including parasitics)

52
Cbase = 1.83 pF the sensitivity of the monitoring transmitter is 555 kHz/fF.

Figure 3.3.8: Measured spectrum of the transmitter. The alignment trans-

mitter for the rectified voltage of 650 mV (a), The main transmitter connected
to CSensor = 1.83 pF. (b).

The experimental setup for in-vitro measurements is shown in Fig. 3.3.9.

As shown in the figure, the prototype IC is mounted on the printed-circuit
board (PCB) and is powered up wirelessly through an external antenna (An-
ritsu P/N 2000-1030-R). We used 5 cm of ground beef to mimic the eect
of tissue. The received power from antenna, even without matching is su-

53
ciently large to start up the monitoring transmitter. As expected the adapter
attached to stentenna adds an extra parasitic capacitance of 0.92 pF and thus
lowers the monitoring frequency to 1.731 GHz.

External
Antenna

IC mounted
on the PCB

Overview of
the test setup

Front view External

Antenna
Monitoring TX to PXA
-53 dBm @ 1.731 GHz

PXA signal analyzer Modeling tissues and lumen

Stentenna

GND

Side view

Figure 3.3.9: The in-vitro measurement setup used in this work.

Fig. 3.3.10 depicts the frequency sensitivity of auxiliary transmitter ver-

sus output voltage of rectifier (received input power). The importance of the
alignment unit is further highlighted when the patients tissue thickness is
above average and consequently, the received power is very small. The mea-
sured results shown in Fig. 3.3.10 confirm the simulated and expected design
targets. Table. 3.1 summarizes the performance of the system and compares

54
it with relevant state-of-the-art designs.

600
f/V=1.397 (MHz/mV)
500
Frequency of TX (MHz)

400

300

200 Measured frequency of the alignment

Quadratic fit
500 600 700 800 900
Supply voltage (mV)

Figure 3.3.10: Transmitted signal frequency of alignment unit versus re-

ceived input level.

The summary of performance of this design as well as a comparison be-

tween the performance of the proposed telemonitoring system and the state-
of-the-art designs for similar applications is presented in Table 3.1.

55
 Table 3.1: Performance summary and comparison of the proposed architecture with the state-of-the-art designs
for similar applications.
This work [11] [14] [58] [59] [12]
Year 2013 2013 2010 2009 2006 2006
CMOS process (m) 0.13 N.A. 0.13 1.5 3 (BiC- N.A.
MOS)
Supply voltage (V) from 0.5 operates N.A. 2.5 2 2.5 N.A.
at 0.88
RF 13.18 N.A. 8** - 0*** N.A.
sensitivity* (dBm)
Power consumption 156.9 W N.A. 2 mW 300 W 340 W N.A.
Area (mm2 ) 0.484 4 0.49 4.84 10 2.52
56

Implant depth (mm) up to 30 4 35 10 0 0

Sensitivity (kHz/fF) 555 7.5 N.A. N.A. 0.00075 28.7
Sensor base 1.6 5-10 5.23 2 10 4.6
capacitance (pF)
Measurement setup in-vitro in-vivo in-vivo in-vivo in-vitro in-vitro
Method of active passive active active active passive
telemonitoring
* Minimum input signal power to turn-on the chip based on 50 matching. Excluding the required o-chip circuits.
** Extrapolated from the measured results of the IC. 1.0 V harvested supply.
*** Achieved using o-chip components (1 1 cm2 ). Resolution of 0.5 mmHg.
Area of the passive sensor. Resolution of 0.125 mmHg.
Chapter 4

Ultra-Wideband Analog Unity

Gain Buer

In this section, an ultra wide-band analog voltage-mode buer is presented

which can drive a load impedance of 50 . The presented feedback-based
buer uses a compound amplifier which is a parallel combination of a high-
DC gain operational amplifier and a operation transconductance amplifier
to achieve a high unity gain bandwidth. A proof-of-concept prototype is
designed and fabricated in a 0.13 m CMOS process. The simulation and
measurement results of the proposed buer are in good agreement. The pro-
totype buer circuit consumes 7.34 mW from a 1.3-V supply, while buering
a 2 GHz sinusoidal input signal with a 0.4 V peak-to-peak (Vpp ) amplitude
and driving an AC-coupled 50- load.

57
4.1 Introduction

Wide-bandwidth unity-gain analog buers are used in a variety of high-speed

and agile applications such as analog-to-digital converters [60], switch capac-
itors [61], sample-and-hold circuits [62] and active probes in measurement
instruments. A simple and commonly used architecture for such buers is a
source-follower-based buer [6163]. However, achieving high linearity and
spurious-free dynamic range (SFDR) as well as an accurate gain in such
buers are challenging [63], although dierent techniques to address these
problems have been investigated [64]. In cases where the gain accuracy and
flatness are not crucial, source-follower architectures are used for driving low
impedance values such as a 50 load (or a large capacitive load). In these
cases, a relatively large driving transistor is required. This large transistor
in eect limits the input bandwidth of the circuit. One way to ameliorate
this issue is to cascade multiple source-follower stages and gradually increase
the size of the transistors. Each additional stage adds extra pole to the
system which results in deteriorating the stability and overall bandwidth of
the system. Furthermore, testing high-frequency circuits typically requires
a buer since many high-speed integrated circuits are not capable of driv-
ing the standard 50- input impedance of the high-frequency measurement
instruments. Thus, having a monolithic unity-gain buer (voltage follower)
with relatively flat and accurate gain is desirable. To achieve such a mono-
lithic analog buer feedback-based buers are typically used, e.g, using an

58
operational amplifier in a unity-gain feedback structure ensures a relatively
accurate gain in the presence of process, supply voltage, and temperature
(PVT) variations. Fig. 4.1.1 shows one possible architecture for such de-
signs. The bandwidth of this buer is mainly limited by the bandwidth of
the operational amplifier and the size of the driving transistor.

VDD_Buffer

In
A MD

+
Out
V_Bias

Figure 4.1.1: The architecture of a conventional amplifier based analog buer.

4.2 Proposed Architecture

To have an accurate flat gain, the open-loop gain of the buer has to be
relatively large. The overall open-loop gain of the buer can be written as
follows:

A(!) (!) = G(!) gm0 (!) Zout (!) 1 (4.2.1)

where G(!) is the voltage gain of the amplifier A and gm0 (!) is the small-
signal transconductance of the driving transistor (MD in Fig. 4.1.1) at the

59
input frequency of !, Zout (!) is output impedance seen at the output node
of the buer, and (!) is the feedback gain which for the structure shown
in Fig. 4.1.1 is equal to 1. The closed-loop voltage gain of the buer can be
written as:

Vout A(!) A(!)

(!) = = (4.2.2)
Vin 1 + A(!) (!) 1 + A(!)

From (4.2.2), the overall gain of buer in approximately 1 over the range
of frequencies where A(!) 1. Since for the most part the open-loop gain
of the buer is provided by the amplifier A, a wide bandwidth amplifier is
needed. However, designing amplifiers with both high voltage gain and high
bandwidth is challenging. One elaborate solution is the compound amplifier
introduced in [6]. The architecture of this amplifier is shown in Fig. 4.2.1.

VDD

M4 M3
OPAMP

v IN M2 M1 v IN

VBias_ext M5

Figure 4.2.1: Architecture of compound amplifier used in this design.

As shown in the figure to achieve high gain at low frequencies, a high DC

60
gain but low bandwidth amplifier, namely an operational amplifier (opamp),
is used. The operational amplifier is in parallel with a high bandwidth oper-
ational transconductance amplifier (OTA). The generic magnitude frequency
response of the overall buer along with its typical pole zero locations is
shown in Fig. 4.2.2. As described in [6], the combination of the OTA and
opamp will introduce a zero, namely zOT A , which helps to compensate for
the adverse eects of the dominant pole of the opamp. Although the buer
is generally connected to a small load impedance (e.g., 50 ), to ensure the
stability of this architecture a zero (zESR ) is also added (using a series com-
bination of a resistor and a capacitor, i.e., combination of RESR and Cz in
Fig. 4.2.3) to the output of the amplifier to compensate for the output load.

p
Opamp
Open-loop Voltage Gain (dB)

p
z OTA OTA

p
load
zESR
Frequency

Figure 4.2.2: Pole-zero location of the proposed buer

61
 VDD_Buffer
M4
M3 M5 M11 M19 M20 M22 M26 M27 MD
M9 VB Cc
RESR
M17 M18
Out In Cz
VB M24 M25

Vbias_OTA
M8

Out
VC M15 M16
Out VC
M2 Vbias_OTA
M7 In Out M23
Vopamp M13 M14
M1

M6 Vopamp VB
R1 R2 M10 M12 M21 M28

Biasing circuit Opamp OTA

Figure 4.2.3: The overall schematic of analog buer presented in this work.

4.2.1 Circuit implementation

The schematic of the presented buer is shown in Fig. 4.2.3. To achieve

a large low-frequency gain a telescopic cascode architecture is used for the
opamp. The buer has an input impedance of 8 G in parallel with 127 fF
(averaged from DC to 1 GHz). For the purpose of driving a low-impedance
load, a relatively large driving transistor, namely, MD, is used. The simulated
frequency response of the opamp as well as that of the OTA are shown in
Fig. 4.2.4. Fig. 4.2.5 shows the frequency response of the overall compound
amplifier. The drop in the low-frequency gain of the compound amplifier (as
compared to the opamp low-frequency gain) is due to the loading eect of
the diode-connected active load of the OTA. This gain drop also results in
pushing the dominant pole of the opamp to higher frequencies (as can be
seen in Figs. 4.2.4 and 4.2.5).

62
 80 OTA
60 Opamp

Gain (dB)
40
5.9 GHz
20
10.47 MHz
0
0 2 4 6 8 10
10 10 10 10 10 10
frequency (Hz)

200
Phase margin (degree)

150
72
100

50 50

0 0 2 4 6 8 10
10 10 10 10 10 10
frequency (Hz)

Figure 4.2.4: Frequency response of the opamp and OTA.

40
Gain (dB)

20
Zero Introduced by OTA
3.5 GHz
0

0 2 4 6 8 10
10 10 10 10 10 10
frequency (Hz)

200
Phase margin (degree)

150

100 45

50

0 0 2 4 6 8 10
10 10 10 10 10 10
frequency (Hz)

Figure 4.2.5: Frequency response of the compound amplifier.

Since the buer is expected to operate for input signals with relatively
large voltage swing, and the output of the buer follows the input signal,
special attention should be paid to biasing of the circuit. To put this in

63
perspective, consider the case that the input is a step with a large amplitude.
Since the output follows the input, both input terminals of the OTA will
experience large voltage levels which results in lowering the drain voltage
of transistors M24 and M25 of the OTA. In this case, transistors M24 and
M25 may enter the triode region of operation. A similar scenario applies
when the input signal is at a low voltage level, where the voltage level of the
drain terminal of M26 and M27 of the OTA will increase and therefore these
pmos transistors may enter into triode region of operation. To maintain a
reasonable voltage level at the drain of these transistors a common-mode
feedback circuitry shown in Fig. 4.2.3 consisting of an analog inverter (i.e.,
transistors M6 to M9) along with biasing circuit is used. This feedback circuit
facilitates the operation of the circuit over a wider input voltage range by
properly adjusting the tail current of the OTA. Fig. 4.2.6 shows the simulated
output voltage of the OTA with and without the common-mode feedback
circuit.

1
Output DC voltage of OTA (V)

With commonmode feedback

Without commonmode feedback
0.8

0.6

0.4

0.2
0 0.2 0.4 0.6 0.8 1
Input common voltage level (V)

Figure 4.2.6: Simulated output voltage level of the OTA with and without
the common-mode feedback circuit.

64
 (a)

(b)

Figure 4.2.7: Measured step response of the proposed buer for (a) 350 mV
and (b) 700 mV of input step amplitudes.

4.3 Experimental Results

A proof-of-concept prototype of the proposed buer is designed and fab-

ricated in a 0.13-m CMOS process. Fig. 4.3.1 shows the chip micrograph
along with the layout view of the buer (the inset in the figure). The overall

65
 Table 4.1: Performance summary and comparison with the state-of-the-art analog buers.
Process Supply Power Bandwidth Area
Year Slew rate (V/s) Load
(m) (V) (mW) (MHz) (m2 )
SR : 185,
This work 2013 0.13 1.3 7.34 2000 50 || 20 pF 6059
SR+:254
66

[65] 2011 0.35 0.75 0.153 1.366 10 pF 55000

[61]* 2011 0.5 1.5 0.0585 10 2 pF
SR : 35,
[66] 2010 0.5 3.3 0.198 13.4 30 pF 17000
SR+ :29
[67] 2009 0.35 3.3 4.8 90 200 13 pF 29100
* Simulation results.
circuit occupies 6059 m2 . The the chip consumes 7.34 mW from a 1.3 V
supply voltage while buering a 2 GHz sinusoidal input signal and driving
an AC-coupled 50- load.

Figure 4.3.1: Micrograph of the presented buer.

Fig. 4.2.7 shows the measured transient step response of the buer a
small and a relatively large input steps. The simulation results show that the
buer provides almost the same performance for both small and large input
steps which can be attributed to the common-mode feedback circuit used
in the OTA. In the transient measurements (Fig. 4.2.7) the load including
the input impedance of the measurement equipment (Tektronix DPO4054
Oscilloscope) is a 20 pF capacitive load in parallel with a 50 resistor. The
pulse generator used in these measurements is HP8110A which can generate
pulses with a rise time of 8 ns.

67
Figure 4.3.2: Measured magnitude frequency response of the proposed buer.

Figure 4.3.3: Output spectrum for a 133.33 mVpp input sinusoid at

100 MHz.

The frequency response of the buer is measured in the closed-loop con-

figuration. For an input signal of 400 mVpp , the frequency response of the

68
closed-loop buer is measure with an Agilent vector network analyzer E5061B
and is shown in Fig. 4.3.2. As can be seen from the figure, the 3 dB band-
width of the buer is 2 GHz. The total harmonic distortion (THD) of the
buer is measured using an Anritsu MS2034A for a 100 MHz input signal
with a peak-to-peak amplitude of 133 mVpp . The measured result is shown
in Fig. 4.3.3. The buer achieves a THD of 25.5 dB. For a input signal of
1 MHz with a peak-to-peak amplitude of 270 mVpp the THD of the buer is
34 dB.

69
Chapter 5

Capacitance-to-Voltage
Converter Based
Telemonitoring System

In this chapter an ultra-low-power system for wireless monitoring of capac-

itive sensors based on capacitance-to-voltage converters is discussed. The
proposed architecture is designed to consume even less power in compare to
the first system (CFC) and therefore it is particularly suitable for biomed-
ical implants where the implanted device is deep inside the body or has
minute dimensions. The proposed telemonitoring system consists of a radio-
frequency (RF) power harvesting block providing the supply voltage for the
rest of the system, a capacitive sensor interface, and an RF transmitter to
transfer sensory data to the external reader. The sensor interface consists of

70
a capacitance-to-voltage converter and the transmitter includes a voltage-to-
frequency converter. The frequency for the transmitted signal is proportional
to the change of the capacitance of the sensor. A proof-of-concept prototype
is designed and fabricated in 0.13 m CMOS. Measurement results show that
the system operates from a harvested supply of as low as 350 mV (from input
power of 43.76 dBm at 1.25 GHz) while drawing less than 100 nA from its
harvested supply.

5.1 Introduction

Ultra-low-power circuits are essential in many applications including biomed-

ical implants particularly when the implant is required to operate from a har-
vested energy source. This class of biomedical implants include implantable
telemonitoring systems for diagnostics such as coronary blood pressure mon-
itoring systems [14, 17, 18, 32, 37, 42, 44]. Such devices use a wireless link
to transfer power to the implant as well as to communicate information to
outside the body. One of the main challenges in engineering such devices
is adhering to the regulatory requirements regarding power exposure of live
tissues. These geographically segmented regulations are governed by regional
agencies such as the Federal Communications Commission (FCC) in North
America [45] which limit the strength of the radio-frequency (RF) signals
used to transmit power and/or communicate data to and from the implant.
Due to the high absorption coecient of tissue in the ultra-high-frequency

71
(UHF) range, these limitations on the RF signal strength restrict the range
of communication, making the design of ultra-low-power electronics for deep
implants a vital consideration [3, 14]. In this work, an ultra-low-power inte-
grated circuit is designed for integration with a custom-made coronary stent
acting as an antenna [12]. The device harvests RF power from the antenna
stent, interface with a micro-electromechanical system (MEMS) pressure sen-
sor, and transmit the sensor data to the outside of the body using the same
antenna. This device is of particular interest for monitoring stent occlu-
sion (restenosis), which occurs in 4.9% [68] of patients who receive stents
within a year of surgery, significantly altering the coronary blood pressure
and potentially causing heart attacks. Studies have determined the power
requirements of such wirelessly powered systems for monitoring and trans-
mitting blood pressure data [17], and reveal that the power harvested by the
implantable device at a depth of 39 mm from the surface of the body can
be as low as 56 W. Since the average distance from a coronary stent to the
surface of the patients body is about 39 mm [69], this application requires
further reduction in the power requirements of previously reported wireless
monitoring systems [9,14,35,42,44,58,59,70]. Although ultra-low-power sys-
tems for intraocular implants have already been proposed [13], they have a
shorter read range and larger antennas than the proposed coronary monitor-
ing system. Also, in the context of this work, special consideration must be
given to the low eciency of the stent-based antennas (e.g., antenna stent
or stentenna [12]) that make low-power requirements on the electronics even

72
more stringent.

Forward link Reference

(power delivery ) and Biasing
Circuit

External Matching
Reader Rectifier Regulator
circuit
Backward link
(sensory data)
Sensor
Transmitter Interface Sensor(s)
Circuit

Internal Tele-monitoring System

Figure 5.1.1: Building blocks of a typical telemonitoring system.

Fig. 5.1.1 illustrates a generic biomedical telemonitoring system that con-

sists of a power harvesting unit, a sensor interface circuit, and a transmit-
ter block. The power harvesting unit typically includes a rectifier stage
and in some cases it also includes a low-dropout (LDO) voltage regula-
tor [13, 14, 34, 43, 71]. The sensor interface processes the sensory data, which
consists of one or more environmental/biomedical variables such as pres-
sure [1214, 58, 72, 73], temperature [13], and oxygen level, ... [8, 10, 16]. In
this work, we interface to capacitive pressure sensors which have been used
frequently in devices that monitor intraocular or blood pressure. To reduce
the power consumption and complexity of the system, the sensor interface
circuit and transmitter can be merged in an analog capacitance-to-frequency
converter (CFC) comprised of an LC CMOS oscillator whose capacitor is that
of the capacitive pressure sensor. A drawback of using such a CFC structure
is the fixed sensitivity and resolution of the telemonitoring systems [32,58,74].
Another issue is that the center frequency of the output signal depends on

73
the base capacitance of the sensor (i.e., the nominal fixed capacitance of the
sensor) which may vary or limit the frequency range of operation. To over-
come this problem, an alternative design approach has been proposed where
the dierence between the capacitance of the pressure sensor and a reference
capacitor is used to control the frequency of a transmitter [13, 59, 75]. Many
such designs use rather complex circuitry which requires a relatively high
supply voltage or consumes a high power that limits the operating range of
the overall monitoring system.
In this work, we focus on reducing the turn-on voltage of the overall
telemonitoring system. To eliminate the dependency of the transmission fre-
quency on the base capacitance of the sensor, an alternative capacitance-to-
frequency converter structure is presented. The proposed architecture con-
sists of a capacitance-to-voltage converter (CVC) stage followed by a voltage-
to-frequency converter, i.e., a voltage-controlled oscillator (VCO) stage. The
transmission of the data is performed using an ultra-low-power/low-voltage
VCO.

5.2 The Proposed Telemonitoring Architec-

ture

One of the target applications of the proposed system is to monitor restenosis

in coronary arteries. The depth of the coronary artery (on average 39 mm
from the surface of the body) along with relatively small diameter of the

74
artery (average diameter of 2.74 mm [76]) poses significant challenges to the
design of such telemonitoring systems. Given the limited amount of received
power in such a system (around 56 W [17]), to have a sucient current
budget for all the various building blocks of the system to reliably operate
it is necessary that the system operates with a relatively low supply voltage.
The proposed system is designed to operate from a supply voltage as low as
0.35 V. As will be discussed, this improved current budgeting facilitates the
use of a broader range of capacitive sensors with a larger base capacitance.
The architecture of the proposed telemonitoring system is shown in Fig.
5.2.1. The first stage consists of a rectifier stage which provides the supply
voltage for the rest of the circuit. Simulation results show that the rectifier
is capable of providing up to 1.0 V from a minimum input power level of 6.3
mV input signal amplitude, in dierential configuration. We can translate
that input voltage to 34 dBm input power level, if the input impedance
were 50 . For input power level of 17.8 dB the rectifier supplies 11 W
of output power at 1.0 V output voltage. Since in biomedical telemonitoring
applications, the impedance of the implanted antenna may change depending
on the application, we have not included the matching circuit of the antenna
inside the IC. In practice, either an application specific matching network
should be used or ideally an adaptive matching network should be employed.
More discussion on this is provided in Section 5.3.
The presented configuration uses a CVC stage which generates a voltage
representing the change of the capacitance of the capacitive sensor. The

75
 In+
Rectifier
In-
Bias and reference
voltage
ICh ICh CLK CLK

CVC_OUT OUT+/-
76

VRef VRef A S/H S/H

CLK CSensor CRange
CLK & CLK CLK & CLK
CLK CLK CLK
Clock Gen.

Figure 5.2.1: Overall configuration of the proposed telemonitoring system.

structure of the CVC system is shown in Fig. 5.2.1. Two identical current
sources are utilized to charge up the sensors capacitance and a fixed range
(reference) capacitance . A clock generator provides two phases of operation
of the CVC circuit. The charging phaseconsists of charging the sensor and
the range capacitors, after which they are discharged to ground during the
resetting phase. According to Fig. 5.2.1, the voltage across the capacitive
sensor is:

t
1 ICh t

VSensor = V0 + iCh (t)dt = V0 + (5.2.1)
CSensor CSensor

where V0 is the voltage of the sensor capacitance at the beginning of the

charging phase, t is the charging time period, and ICh is the constant cur-
rent generated by the current source. Because the resetting phase discharges
the sensor capacitor to ground, V0 is taken to be 0 V in this analysis. The
symmetric structure of the circuit allows a similar equation to be written
for the range voltage, VRange . When VSenso reaches to the level of a reference
voltage, VRef (see Fig. 5.2.1), the circuit turns o the current source charging
the range capacitor, and the dierence between the voltage across the capac-
itor and the reference voltage is amplified to improve sensing resolution. The
time when the range capacitor current source is turned o, namely, tstop , can
be calculated as:

CSensor VRef
tstop = (5.2.2)
ICh

77
 Substituting this stop time into (5.2.1), the output of the dierential
amplifier A with DC voltage gain A0 is :

kICh CSensor
VCV C = A0 ( 1)VRef
CRange ICh

kCSensor CRange
= (5.2.3)
CRange

where = A0 VRef , and k is the current ratio between the sensor and range
capacitor current sources. Note that for k = 1 , (5.2.3) can be simplified to:

VCV C = ( /CRange ) C (5.2.4)

where C = CSensor CRange . To optimize sensitivity of the CVC block,

the range capacitance CRange is typically set equal to the base capacitance of
the sensor. Note that according to (5.2.4), the sensitivity of the CVC block
can be tuned by adjusting the voltage gain A0 , and the reference voltage
VRef , but is independent of the charging current ICh .
The output voltage of the CVC block is fed to a transmitter and sets the
transmitters frequency. To improve the sensing resolution and reduce the
transmitter phase noise caused by fluctuations in this control voltage, the
maximum voltage output of the amplifier is sampled and held at the end
of each charging phase to achieve a stable DC voltage proportional to C.
Implementation is accomplished using two sample and hold blocks cascaded
in a complimentary fashion (Fig. 5.2.1) at the output of amplifier A . The

78
result is that the CVC output voltage tracks changes in the sensor capacitance
with each clock cycle.
The simulated performance of the CVC block for 0.35 V and 1.0 V supply
voltages is shown in Fig. 5.2.2.

79
 1

0.9
0.8
0.7 VRef=575 mV
Voltage (V)
0.6
0.5
0.4
VSensor
0.3 VRange
CLK
0.2 CVCOUT

0.1 VRef

0
0 0.2 0.4 0.6 0.8
time (ms)

(a)

0.35

0.3
VSensor
0.25 VRange
CLK
Voltage (V)

0.2 CVCOUT
V =146 mV
Ref VRef

0.15

0.1

0.05

0
0 0.5 1 1.5 2 2.5 3 3.5 4
time (ms)

(b)

Figure 5.2.2: The simulated transient response of the CVC block for
CSensor = 1.9 pF and CRange = 1.4 pF at supply voltage of (a) 0.35 V
(b) 1.0 V.

80
5.3 Circuit Implementation

In this section, the design and implementation of dierent building blocks

of the proposed telemonitoring system as well as their performance are pre-
sented.

5.3.1 Rectifier stage

To harvest the incoming energy, a dierential rectifier stage is used which

is based on [77]. For the purpose of this work, the rectifier is optimized to
provide a high power eciency at the operating frequency of 1.25 GHz. To
improve the eciency of the the system and to ensure that the system is
able to operate with small incoming signal amplitude, a voltage matching
circuit is placed between the embedded antenna and the rectifier stage. The
voltage matching circuit consists of a series inductor that will resonate with
the input capacitance of the rectifier stage. However, for transmitting sensory
data through the implanted antenna a power matching circuit is required to
ensure that most of the available power at transceiver unit is transmitted to
the external reader.
In contrast to typical telemonitoring architectures, the proposed system
does not include a voltage regulator stage for three main reasons: firstly, the
incident signal received by the rectifier is at 1.25 GHz, thus the fundamental
frequency of ripples of the rectifier stage will be at 1.25 GHz. A regulator
which is capable of actively rejecting 1.25 GHz ripples should have a high

81
 in+
in+
Zin+ = ZCin+ Rin+ CC Cin+
Mn1 Mp1 CS/D,n1 CS/D,p1

CS/D
out1 out2 CG,n2 CG,p2

CG

Mn2 Mp2

Zin- = ZCin- Rin- CC

in-

Figure 5.3.1: Schematic of one stage of the three-stage dierential rectifier.

closed-loop bandwidth and therefore is power hungry [52] and is not feasible
for this low-power application. Secondly, in the architecture of the moni-
toring circuit no digital blocks or clock signals are used and therefore the
load variation is not significant. This relaxes the voltage regulation require-
ments and some degree of voltage variations can be tolerated. Thirdly, since
the rectifier is driving an ultra-low power monitoring circuit which could
be modeled as a large equivalent resistance, the combination of the large
load resistance and the rather small smoothing capacitance at the output of
the rectifier form a passive RC filter. This filter suciently attenuates the
high-frequency ripples at the output of the rectifier. Nevertheless, in appli-
cations where the power budget permits the use of an additional regulator,
the improved regulator structures presented in Appendices A and B can be
used.
In this work, a three-stage dierential rectifier [50] is used to eciently
convert the RF energy to DC power in order to supply the entire succeeding
circuitry. The second stage of the rectifier is shown in Fig. 5.3.1. At the

82
frequency of interest, i.e., 1.25 GHz, where the parasitic inductance values
could be neglected, the input impedance of the rectifier could be modeled
by the parallel combination of a capacitor Cin and a resistor Rin (as shown
in Fig. 5.3.1 [51]). Note that the capacitive part of the input impedance ac-
counts for the combination of the coupling capacitors CC (which is typically
a linear capacitance) and the parasitic capacitance values of the switching
transistors MP i,N i (nonlinear capacitance). The resistive part of the input
impedance represents the average DC current drawn from the dierential in-
puts and parasitic losses and therefore varies with the load. Note that in the
alignment mode when the input level is small, the eect of nonlinear compo-
nent variations are minimal and thus the input impedance could be consid-
ered constant. In order to produce a suciently high output power/voltage
to drive the alignment unit for a small input level, the input of the rectifier is
matched to the impedance of the source (antenna stent). In practice, match-
ing could be achieved by optimizing the sizing of the coupling capacitors CC
and switching transistors such that the resulting input capacitance of the
rectifier resonates with the inductance of the stentenna at the frequency of
interest. Note that as shown in Fig. 5.3.1, given that CC CG CS/D ,
the input capacitance of the rectifier is dominated by the capacitance seen
at the source/drain of the PMOS and NMOS switching transistors (CS/D ).
Although the source/drain parasitic capacitance of the switches is voltage
dependent, its value is almost constant for a large range of input levels and
therefore, a single inductor per each dierential branch is used to resonate

83
 VDD
M1 M2 M8 M9 VBCLK M31 M32
M10 M20
M16
VBCLK CLK
M29 M30
M11
... CLK

{
M7 M6 M33
VRef
x3 M27 M28
M3 M12 CLK
M15 M18 VBCM
VBVCO ICh
M17 M19 M22 M25 M26
M5
M4 M13
VBCM

R VBCM
M21 M23 M24
M14

Reference Voltage and Biasing Clock Generator Current Source

Figure 5.3.2: The schematic of clock generator current source and biasing
circuit.

with this capacitor.

5.3.2 Clock generator

Fig. 5.3.2 presents the schematic of the circuit used for generating the clock
signal. To generate the clock while operating from a low supply voltage,
a ring-based oscillator is employed. To decrease the dynamic power con-
sumption, the length of the transistors are chosen to be large enough. This
in turn will reduce the output clock frequency. The clock frequency must
be low enough so that the voltage across the sensor capacitor in the CVC
block can reach the reference voltage during the charging phase (duration
tstop ). Assuming a clock with a 50% duty cycle, this requires that the clock
frequency satisfies:

1
= Tclock > 2 (tstop + tsetup + thold ) (5.3.1)
fclock

84
 where tsetup and thold are the setup time and hold time of the subsequent
sample-and-hold stage. In this design, tstop is much larger than tsetup + thold
and therefore the minimum clock period is approximately 2tstop . Note that
the factor of 2 is due to the 50% duty-cycle clock. On the other hand, the
clock frequency must be high enough such that the change in the voltage
across the range capacitor, VRange , due to the leakage current stays within
an acceptable range. It can be shown that to keep the voltage change across
the range capacitance to within 2%, the clock period should satisfy:

Tclock < 2 0.02 (Rleakage CRange ) (5.3.2)

where Rleakage is the total resistance to ground in parallel with the range
capacitor. Rleakage is primarily due to the reset switch. For adjusting the
clock frequency, the tuning circuitry consisting of transistors M15 M20 shown
in Fig. 5.3.2 is used adjust the frequency of the clock generator. This circuitry
allows the clock frequency to be adjusted by setting the voltage V BCLK .

5.3.3 Current source

The current source architecture along with its associated bias circuitry are
shown in Fig. 5.3.2. A voltage-controlled current source stage is implemented
using a cascode stage of NMOS transistors M21 M22 and the corresponding
current mirror stage is a modified version of [78]. In this design, to decrease
the output current to the pico ampere range, the cascode configurations

85
consisting of transistors M23 M28 are used as active loads for the PMOS
current mirror consisting of M29 M32 which in turn sets the output current
ICh . The output current can be adjusted between 150 pA to 800 nA by
changing the bias voltage of the current source stage. The solid and dashed
traces in Fig. 5.3.3 show the simulated output of the current source for supply
voltages of 0.35 V and 1.0 V, respectively. The simulation results show that
the current source generates a constant current over an output voltage range
of 0 to 0.8VDD within 98.8% of the nominal current at 0.35 V and 99.4% of the
nominal current at 1.0 V supply. For small values of the sensor capacitance
(i.e., 0.1 to 1 pF), the bias voltage and corresponding output current should
be lowered to ensure the sensor capacitor charging time is in a reasonable
range for correct operation of the CVC stage. Simulation results of this case
are shown by the two lower traces in Fig. 5.3.3. These to traces correspond
to the cases where the circuit delivers 219 pA at 0.35 V and 329 pA at 1.0 V,
with 86.3% and 86.76% of nominal current, respectively.

86
 3
10

VBias=35mV @ VDD=0.35 V
VBias=185mV @ VDD=0.35 V 729 nA
2
10 VBias=55mV @ VDD=1.0 V
VBias=805mV @ VDD=1.0 V
ICh (nA)

1
6.43 nA
10

328 pA 219 pA
0
10

1
10
0 0.2 0.4 0.6 0.8
Output Voltage (xVDD)

Figure 5.3.3: Example graphs of the simulated output current of the proposed
architecture for VDD = 0.35 V (solid line) and VDD = 1.0 V (dashed line).

5.3.4 Sample-and-hold circuit

Two cascaded sample-and-hold stages which in eect form a peak detector

circuit, are used in the CVC block (Fig. 5.3.4). Each sample-and-hold stage
contains unity gain buers at its input and output to avoid unwanted loading
eects [79]. The buers are implemented using a generic single-stage dieren-
tial to single-ended amplifier architecture with NMOS input transistors and
active current mirror load [80]. The buers can operate from a relatively low
supply voltage, The dummy transistors D1 and D2 are half the size of M1 and
M2, respectively, and are added to reduce the eect of charge injection [79].

87
 CLK CLK

D1
M1
Input

A Output
A
CH

M2

D2
CLK CLK

Figure 5.3.4: The architecture of the sample-and-hold used in CVC block

5.3.5 Transmitter

VDD

M8 M6

100 nH 100 nH

OUT OUT+
CVC_OUT

M9 M7

VBVCO M10

Monitoring Transmitter
Figure 5.3.5: Schematic of active transmitter used in this design.

As shown in Fig. 5.3.5, a complementary cross-coupled LC CMOS oscillator

[54] is used due to its high power eciency. Same technique that has been
used for alignment transmitter in previous design (see Chapter 3) is also

88
applied to further reduce the power consumption. In addition, to increase
the frequency sensitivity ( !/ C) a small variable capacitance is used in
the transmitter LC tank. The value of this variable capacitance (varactor) is
adjusted by the output voltage of the CVC block, and thus any change in the
CVC output voltage shifts the oscillation frequency of the transmitter. At a
supply voltage of 1.0 V, the transmit frequency is 659 MHz. However, at a
lower supply voltage of 0.35 V the transmit frequency is 85 MHz. Note that
the drop in the frequency at lower operation voltage can be attributed to
parasitic capacitance of the output node as the parasitic capacitance values
are larger at lower voltages.

5.4 Simulation and Experimental Results

A proof-of-concept prototype is designed and fabricated in a 0.13 m CMOS

process. Fig. 5.4.1 shows a micrograph of a test chip that contains two
dierent telemonitoring designs. Both designs (a) and (b) have connections
to interface with a MEMS capacitive pressure sensor, while design (b) also
has a variable capacitance (varactor) that can be used instead of a MEMS
pressure sensor for testing purposes. The dimensions of each design are
1060 m 360 m (0.381 mm2 ), and as it is visible in the micrograph,
most of the layout area is dedicated to the transmitter inductor (which is the
equivalent inductor of two series inductors) . The simulated and measured
performance of the system is discussed in the following subsections.

89
Figure 5.4.1: Micrograph of the proposed telemonitoring system (a) without
(b) with built-in variable capacitor.

Wire-bond
Zin,rec VDD

RFin Cin Rin

LWB

Rectifier Tele-monitoring

Tele-monitoring chip

CQFP-80 package

Figure 5.4.2: The wire-bond matching used in this work.

90
Figure 5.4.3: The micrograph of the wire bond interconnects for CQFP80
package.

5.4.1 DC performance

The overall system consumes 10.4 W at a supply voltage of 1.0 V. Note that
in this measurement the transmitter output feeds an integrated unity gain
buer, and thus the loading of an antenna is not accounted for. In practice,
when an antenna is used a matching circuit is required for maximum power
transfer to the antenna. When the supply voltage is decreased to 0.35 V,
the system draws 100 nA (measured with a HP34401A multimeter) which
corresponds to an overall power consumption 35 nW. Fig. 5.4.4 shows the
total quiescent current of the system (excluding the power of the buer) for
dierent supply voltages.

91
 100

Quiescent current (A) 10

0.1
Measured
Simulated
0.35 0.6 0.8 1 1.2
Supply voltage (V)

Figure 5.4.4: Simulated and measured quiescent current for dierent supply
voltages

To maximize the performance of the rectifier, the input of the rectifier

must be voltage matched (i.e., resonate) with the signal source at the operat-
ing frequency. Although, in practice, this rectifier will receive power from an
antenna stent (or similar biomedical implanted antenna), for test purposes,
we used a signal generator to emulate the received signal from the antenna.
To be able to match the rectifier input stage without using on-board
discrete components, as shown in Fig. 5.4.2, the intrinsic inductance of the
package wire bonds is used. The RF input is supplied by an Agilent 83732B
signal generator through a Picosecond 5310 balun and the input voltage to
the rectifier is measured at the corresponding package pins using an active
probe (1169A 12 GHz InfiniiMax). For interconnects with closely spaced wire

92
bonds, [56] provides a closed form expression for the inductance of the wire
bonds as a function of their geometric parameters. We used the wire bond
parameters and typical length and spacing used for a 80-pin ceramic quad flat
package (CQFP80). For a wire-bond length of 4.9 mm ( LW B = 32.78 nH) ,
as shown in Fig. 5.4.3, which is typical for the wire-bond length of CQFP80
when the pads and the associated pins are located at the corner of the chip
and package, the input capacitance of the rectifier is designed to be 457 fF
(simulated) in order to resonate with 32.78 nH inductance of the interconnect
wire-bonds at 1.25 GHz.
(Output DC voltage)/(amplitude of input signal)

100
1.25 GHz
80

60

40

20

0
0.4 0.6 0.8 1 1.5 2 2.5
frequency (GHz)

Figure 5.4.5: The measure performance of the rectifier for dierent input
signal frequencies

Note that the capacitive input impedance of the CMOS rectifier facilitates
a simple impedance matching with the inductance of the stentenna. Through
appropriate sizing of the coupling capacitors and switching transistors, the

93
input capacitance of the rectifier could be arbitrarily optimized to resonate
with the inductance of the stentenna at the frequency of interest which elimi-
nates the need for a sophisticated and bulky matching networks. Considering
the target application and optimum frequency range for power delivery, we
have considered to match the rectifier at 1.30 GHz. After populating the
printed circuit board, the matched frequency turned out to be at 1.25 GHz.
Fig. 5.4.5 shows a measure of the performance of the rectifier defined as the
ratio of the value of the generated supply voltage to the amplitude of the
input signal versus dierent input-signal frequencies. In this particular ap-
plication, since the frequency of the signal transmitted from the implanted
device to the outside world is around 600 MHz or lower, we have decided to
use a 1.3 GHz signal for power transmission to avoid potential interference
between power and data transmission. However, depending on the appli-
cation, one can adjust the resonant frequency of matching circuit for power
transmission to optimize the performance at the desired frequency. Fig. 5.4.6
illustrates the generated supply voltage by the rectifier versus dierent val-
ues of the input signal amplitude. The presented rectifier unit can generate
required supply voltage of 0.35 V from the input signal amplitude of as low
as 2.05 mV ( 43.76 dBm). This measurement results also show that the
rectifier can generate supply voltage of 1.0 V from 18.7 mV ( 24.74 dBm).

94
 2

Output supply voltage (V)

1.5

0.5
0.35
At 1.25 GHz

2.05 10 20 30 40 50 60
Amplitude of the input signal (mV)

Figure 5.4.6: The measured generated output voltage of the rectifier, while
driving the CVC system, versus dierent amplitude of the input voltage at
1.250 GHz.

5.4.2 Transient response

For the purpose of testing, the IC is mounted on a custom designed FR4

printed circuit board (PCB). For initial testing, a 5 pF capacitor is connected
between the sensor nodes of the IC in place of a capacitive pressure sensor,
and no capacitor is connected to the range nodes. Because of the additional
parasitic capacitance of the PCB traces and connectors, the sensor and range
capacitance values are measured to be CSensor = 7.6 pF and CRange = 1.4 pF.
A measurement of the voltages across each capacitor at a supply voltage of
0.35 V is shown in Fig. 5.4.7 (top). When the 5 pF capacitor is removed,
the capacitance values are Csensor
= 2.6 pF and CRange
= 1.4 pF. Fig. 5.4.7
(bottom) shows the range and sensor capacitor voltage waveforms for this
case.

95
 Range
0.3 Sensor
Voltage (V) 0.2 Vref
0.1
0

0 5 10 15 20 25 30

0.3
Voltage (V)

0.2
Vref
0.1
0

0 5 10 15 20 25 30
time (ms)

Figure 5.4.7: Measured sensor and range voltages for CRange = 1.3 pF and
(top) CSensor = 7.6 pF and (bottom) CSensor = 2.7 pF.

5.4.3 Frequency response

To have a measure of the sensitivity of the system, that is, the equivalent
frequency change for a small capacitance dierence between sensor and range
capacitors (e.g., on the order of tens of femto Farad), we used simulation to
find the equivalent capacitance of the integrated varactor for dierent values
of the control voltage. After canceling the intrinsic capacitance dierence
between range and sensor capacitors by adding compensation capacitors,
for a given C we ran the simulation and read the output voltage of the
CVC block and by changing the control voltage of the varactor we adjusted
the CVC_OUT of the circuit till it matches with the simulated value. For

96
larger C (in lower supply voltage), we added an external capacitance to
build an oset. In this case, we measured the transmitted frequency and
relate it to the value of C we calculate in the simulation. Fig. 5.4.9(a)
shows the simulated output voltage of the CVC stage for dierent calculated
capacitance values, C, where CSensor = CRange + C, and the equivalent
measured transmission frequency at 1.0 V supply voltage.

40
C=1 pF
45
C=1 pF
50
55
78.91 MHz 83.36 MHz
60
65
70
Supply voltage of 0.35 V
75
60 70 80 90 100
frequency (MHz)
10
C=300 fF
20
C=300 fF
30
40
580.4 MHz 604.5 MHz
50
60
70
80 Supply voltage of 1.0 V
90
560 570 580 590 600 610 620
frequency (MHz)

Figure 5.4.8: Measured frequency spectrum of the proposed telemonitoring

system for dierent C at supply voltage of 0.35 V (top) and 1.0 V(bottom).

97
 1 620
Supply voltage of 1.0 V
0.9 615

610
0.8

Frequency (MHz)
CVCOUT (V)
605
0.7
600
0.6
595
0.5
590
0.4 585

400 200 0 200 400

C (fF)

(a)

0.24 84
Supply voltage of 0.35 V
0.22
83
0.2 Frequency (MHz)
C= 600 fF 82
0.18
CVCOUT

0.16 f= 1.85 MHz 81

0.14
80
0.12
79
0.1

78
1 0.5 0 0.5 1
C (pF)

(b)

Figure 5.4.9: The simulated and measured output voltage of CVC block
and transmitted frequency of the overall system for dierent values of C
for (a) 1.0 V of supply voltage and (b) 0.35 V supply voltage (CSensor =
CRange + C).

98
 Fig. 5.4.9(b) presents the same scenario for supply voltage of 0.35 V. Note
that for lower supply voltage the reference voltage VRef is lower (almost 4
times lower as compared to 1.0 V supply voltage) as well as the DC gain of
amplifier A (see (5.2.4)).
Fig. 5.4.8 shows the output spectrum of the transmitter for dierent val-
ues of the sensor capacitance and supply voltage. The frequency spectrum
at 0.350 V supply voltage is shown at the top of the figure. The solid red line
corresponds to CSensor
= 2.5 pF and CRange
= 1.4 pF ( C = 1.1 pF), while
the dashed blue line corresponds to CSensor
= 2.5 pF and CRange
= 3.5 pF
( C = 1 pF). The spectrum corresponding to a 1.0 V supply voltage is
shown at the bottom where the solid red line corresponds to CSensor
= 2.5
pF and CRange
= 2.2 pF ( C = 300 fF) and the blue dashed line is for
CSensor
= 2.5 pF and CRange
= 2.8 pF ( C = 300 fF). The measured
sensitivity of the system for supply voltage of 0.35 V and 1.0 V is 3.1 kHz/fF
and 55.0 kHz/fF respectively. Since the input impedance of the spectrum an-
alyzer used for testing (an Anritsu MS2034A) is 50 , and thus it requires a
relatively large current from the transmitter, the output signal is first buered
using a unity gain buer. The wide-band unity gain buer used for this pur-
pose is also on chip. Note the lower output frequency generated at 0.35 V
supply voltage. As mentioned in Section III, this is due to the operation
of the transistors in the sub-threshold regime where the eects of parasitic
capacitance are increased [80]. Thus, depending on the supply voltage, there
is a range of choices for the output transmission frequency [3, 17] that can

99
 Table 5.1: Performance summary and comparison between state-of-the-art designs
This work [11] [13] [14] [58] [59] [12]
Year 2013 2013 2011 2010 2009 2006 2006
Process (m) 0.13 N.A. 0.13 0.13 1.5 3 N.A.
BiCMOS
Supply Voltage (V) 0.35 N.A. 1.5 2.5 2 and 2.5 3 N.A.
RF 43.76 N.A. 10.5 8 to 0 N.A.
Sensitivity* (dBm)
35 nW@0.35 V
Power N.A. 2.3 W 2 mW 300 W 340 W N.A.
11 W@1.0 V
Consumption
Area (mm2 ) 0.381 4 0.7 0.49 4.84 10 2.52
Implant depth designed for 50 4 4 35 10 0 0
(mm)
3.1@0.35 V
100

Sensitivity 55.0@1.0 V 7.5 1.6 6.64 0.8 0.00075 28.7

kHz/fF kHz/fF fF/mmHg fF/mmHg fF/mmHg kHz/fF kHz/fF
5@0.35 V
Sensor Base 5-10 5.6 5.23 2 10 12-
20@1.0 V
Capacitance (pF) 16
Measurement setup in-vitro in-vivo in-vitro in-vivo in-vivo in-vitro in-
vitro
Method of active passive active active active active passive
telemonitoring
*
Minimum input signal power to turn-on the chip based on 50- matching.
Extrapolated from measurement results.
Using discrete components (1x1 cm2 ).
Excluding the o-chip rectifier.

Passive sensor area.

Uses active components such as transistors.

Uses only passive components such as inductors and capacitors.
be optimized depending on the size and depth of the implanted antenna. As
explained in [3], for deeper implants (with fixed antenna dimensions), the
optimal output frequency shifts to a lower frequency, since tissue absorption
becomes a more dominant eect. This conveniently matches the behavior of
the transmitter output frequency which drops with decreased supply voltage.

5.5 Discussion

As discussed here, the proposed telemonitoring system is able to operate

from both a low (0.35 V) and a relatively high (1.0 V) harvested supply
voltage. One way to further improve the eciency of the circuit is to utilize
a rectifier circuit that has optimal eciency for two dierent input signal
amplitudes. An example of such a rectifier is presented in [74]. Another
possible improvement to the design is to replace the simple clock generator
used in this work with a dierential clock generator that has a fixed tail
current. Designing the clock generator circuit in this way result in savings
in the chip area since it requires a smaller size transistors. Finally, the
simple amplifier A used in CVC design can be replaced by a more elaborate
amplifier keeping the low-supply-voltage specification in mind. For example a
programmable-gain amplifier can be realized by adjusting the feedback gain
of a feedback-based amplifier which in turn controls the sensitivity of the
overall design.

101
Chapter 6

Feasibility Study on
Backscattering Technique

In this section the feasibility of telemonitoring sensory data using stentenna

base on modulating the stentenna load is studied. Fig. 6.0.1 illustrates the
system-level schematic of the proposed backscattering-based in-stent resteno-
sis telemonitoring system. Backscattering refers to reflecting of the incident
power (wave) back to the direction of the transmit power (wave). Backscat-
tering can be used as a power-ecient means for communication [15, 81] .
As shown in the figure, the external transmitter radiates a radio-frequency
(RF) carrier signal that penetrates into the patients body. The RF signal is
used for harvesting energy to operate the implanted telemonitoring system
embedded on the smart stent(i.e., the stent with embedded sensors and
IC) [17]. The sensors embedded on each end of the stent (typically capac-

102
itive sensors) will help monitoring the blood flow through the stent. The
change of capacitance of these sensors can be used as an indicator of the
status of restenosis. The stent itself is used for RF energy harvesting as well
as an antenna for transmitting sensory data to the external reader. The task
of the telemonitoring system is to facilitate RF energy harvesting and con-
trol data transmission. The data transmission is performed through varying
the impedance seen by the stent. This is achieved by selectively opening or
closing the switch as shown in Fig. 6.0.1. Backscattering can accommodate
various modulation schemes including amplitude, frequency and phase shift
keying [81].

y=
-sin
x, x
[0y=
,2
-s] in
x, x
[0,2

Reader Antenna
]

y=
-sin
x, x
[0,2
]
y=
-sin
x, x
[0
,2
Directional ]

Coupler Transponder
Stent

IC

Signal
1/f fdata RL
da
Gen. ta

Spectrum
Analyzer
Tissue

y=
-sin
x, x
[0

Figure 6.0.1: Schematic diagram of backscattering telemonitoring system

,2 ]
y=
-sin
y=
-sin x, x y=
x, x [0,2 - sin
[0,2
x, x

using stent antenna

] ] [0,2
]

As mentioned above, RF power transmission in biomedical implants is

typically achieved through one of the following techniques: inductive cou-

103
 Conventional stent
Antenna stent
Figure 6.0.2: Comparison of the mesh of medical stent and stentenna

pling (near-field), electromagnetic wave propagation (far-field), and ultra-

sonic wave propagation. The ultrasonic-based power harvesting has been
used in various biomedical applications [33], however, due to the physical
geometry and dimensions of the arteries using this method is impractical.
Compared to inductive coupling, electromagnetic wave propagation does not
require exact alignment of the primary and the secondary coils to achieve
maximum power delivery. Although electromagnetic based systems provide
better power transmission eciency for longer telemetry distances [14], for
implants within 4 cm of the skin where most of the transmitted power is
absorbed by tissues, the inductive coupling can be a viable approach [17].
The conventional stent is a mesh-like tubular device shown in Fig. 6.0.2
which is similar to a coil whose turns are linked together. Although this
linking bridges improve the structural strength of the stent they significantly
reduce its eective inductance. Therefore, to achieve a higher inductance

104
for the purpose of establishing a better inductive link, stentenna (Fig. 6.0.2)
have been proposed [82] which resemble the structure of a helical coil. In
this work, we will experimentally compare the performance of monitoring
systems based on both conventional and stentenna.
From the frequency of operation point of view, a recent study shows that
the optimum frequency for power transmission through tissues using sten-
tenna as an inductive receiver is in the range of 800 MHz to 1.5 GHz [17].
This relatively high range of frequency can be attributed to the small dimen-
sion of the stent [3]. From the standpoint of data transmission techniques,
the up link which transfers sensory data back to the external reader can be
established either using an active transmitter (e.g., oscillator) [9,14,58,59,70]
or electromagnetic back-scattering approach in which a passive transmitter
such as relaxation oscillator [15, 32] or a simple LC filter [12, 73, 83] are used.
The active transmitters are relatively power hungry, e.g., more than two order
of magnitude higher in [58] than the backscattering-based counterpart [15].
The higher required power can adversely impact the reliability of the teleme-
try system.

6.1 Experimental Results

To investigate the feasibility of backscattering-based telemonitoring approach,

a proof-of-concept setup has been used. Fig. 6.1.1 shows the in-vitro exper-
imental setup used for measurements. A 100 kHz square-wave clock sig-

105
nal drives a discreet quadruple bilateral analog switch (Texas Instrument-
74HC4066N) which modulates the impedance seen by the stent through
opening and closing the switch across the stent (Fig. 6.0.1). To observe (re-
trieve) the backscattered modulated sensory data a spectrum analyzer (An-
ritsu MS2034A) has been used along with a directional coupler (Mini Circuits
15542 ZFDC-SMA) that separates the received signal from the transmitted
signal. The experiments are performed in a RF enclosure (ETS-Lindgren
Table Top Enclosure). Both conventional and stentenna are tested in free
space. The stentenna is also tested while covered by dierent thicknesses of
ground beef to mimic dierent implant depth.

106
 Figure 6.1.1: In-vitro measurement setup.

All experiments are performed at 900 MHz. Fig. 6.1.2 shows the exper-
imental backscattered power versus dierent load resistances. This results
show that having a telemonitoring system with lower power consumption can
improve the backscattering reflected power and hence the performance of the
telemonitoring system. In addition, Fig. 6.1.2 verifies that the eciency of
transmission is independent of the transmitted power level of reader antenna
as changing the transmitted power by 10 dB results in approximately 10 dB
change in the received backscattered power. For the rest of experiments, the

107
antenna is switched between short and 100 k which is close to the load seen
by the stent (e.g., assuming that the telemonitoring system draws a current
of 10 A from a harvested 1 V supply).

65

70
Backscattered power (dBm)

75

80

85

90

Pin=0.0 dBm
95
Pin=10.0 dBm

0.1 1 10 100 1000

Load resistance RL (k)

Figure 6.1.2: Measured backscattered power level versus dierent load values
and input powers.

As shown in Fig. 6.1.3, for a transmission power of 100 W, the sten-

tenna provides better performance as compared to conventional stent for
typical distances between the reader and the stent. This experiment has
been performed in air (free space).
To analyze the radiation pattern of the stentenna, the backscattered
power level of the stentenna are measured in two directions (vertical and

108
 60
Antenna stent
Conventional stent

Recieved backscattered power (nW)

50

40
PTX=100 W
30

20

10

1 2 3 4 5 6
Distance (cm)

Figure 6.1.3: Backscattered power of stentenna compered to conventional

stent.

horizontal directions relative to the stent) as shown in Fig. 6.1.4. The ex-
perimental results reveal that the external reader should be positioned above
the stent in order to achieve a better transmission eciency.

109
 50
Vertical
Horizontal
60
Backscattered power (dBm)

70

80

90

100
0 1 2 3 4 5 6
Distance (cm)

Figure 6.1.4: The Measured backscattered power from stentenna along

vertical and horizontal axes.

Figure 6.1.5: The measured normalized backscattered power received from

the stentenna versus tissue thickness.

110
Figure 6.1.6: Measured backscattered power with/without layers of ground
beef.

Figure. 6.1.5 illustrates the normalized received backscattered power as a

function of implant depths. To calculate the normalized power, the measured
received backscattered power of the stentenna in the presence of a layer of
ground beef between the stent and the reader antenna is divided by the
received backscattered power measured for the same geometry without the
ground beef layer. Fig. 6.1.6 shows the results of the aforementioned two
experiments (with and without a layer of ground beef). For the experiment
with no layer of ground beef the distance between the antenna and the stent
is given on the right axis.

111
Chapter 7

Conclusion

7.1 Research Contributions

The focus of this work is on the design of ultra-low-power telemonitoring

systems that can be powered wirelessly. Such systems are demanded in
many biomedical applications including telemonitoring of restenosis. Since
this work uses an inductive stent, namely, stentenna, a comprehensive in-
vitro simulations and measurements are performed to obtain the optimum
frequency of operation. As discussed in Chapter 2, the results of these ex-
periments show that the optimum range of frequency for this particular ap-
plication is between 0.5 GHz to 2.5 GHz [17]. In addition, the maximum
deliverable power is estimated (by measurement) to be 56 W at 800 MHz
for implanted stent with the depth of 39 mm. Having an estimation of
the power budget for the telemonitoring system, two dierent systems are

112
designed and implemented in a 0.13 m CMOS process. The first system
which uses a simple capacitance-to-frequency converter (CFC) unit, benefits
from its simple design and alignment feature. The intention behind design-
ing an alignment system (which is unique to this work) is to improve the
inductive coupling between external antenna and implanted antenna (in this
case stentenna). This design start monitoring the blood pressure with the
supply voltage of 0.88 V and power consumption of 156.9 W. This system
transmits the sensory data at 2.03 GHz, while oering 555 kHz/1fF. The
power consumption of the first prototype is higher than the second prototype,
however it consumes half of the most power ecient state-of-the-art design
for similar application ( [13] has better power consumption performance than
the first design however is for a dierent application). The focus of second
architecture, is on further reduction of power consumption and improving
adaptability of this system to dierent capacitive sensors. Experimental re-
sults show that the second architecture oers 2.7 mmHg resolution at 1.0 V
supply voltage while consuming only 11 W power, which is more than 12
times less than the first system. Having ultra-low-power design in mind,
the configuration of the second system is based on capacitance-to-voltage
converter (CVC) architecture and low head-room analog and digital blocks,
which allows operation of this system for rectified supply voltages as low as
350 mV. The total power consumption of system in such low supply volt-
age is measured to be only 35 nW. This is almost 4000 times lower than
first design and 65 time lower than state-of-the-art design [13]. In addition

113
to design of above-mentioned systems, telemonitoring using stentenna based
on backscattering phenomena is also studied and experienced. As shown in
Chapter 6, a preliminary in-vitro measurements are performed for both con-
ventional and stentenna. To mimic the real environment of the stent, the
stent is covered with dierent thicknesses of ground beef. As expected, the
stentenna provides more ecient link in compare to the conventional stent
thanks to its inductive characteristics. The measured results confirm the fea-
sibility of the backscattering technique for telemonitoring of restenosis using
smart stents. This study also shows that the backscarttered data can be ob-
served from stentenna which is implanted as deep as 50 mm inside patients
body. Table 7.1 summarize the performance of the designs proposed in this
work.

Table 7.1: The summary of performance of the proposed systems in this work

First system (CFC) Second system (CVC)

2
Area (mm ) 0.484 0.381
Power consumption 156.9 W 35 nW-11W
Sensitivity (kH/fF) 555 3.1-55
Resolution (mmHg) 1.65 2.7-50
Maximum Depth of operation (mm) 30 60
RF sensitivity (dBm) -13.18 43.76
Supply Voltage 0.87 0.35

114
7.1.1 Design and implementation of auxiliary systems

and circuit blocks

In addition to above-mentioned systems and architectures, we have also de-

signed and implemented auxiliary circuits to facilitate development and test
of the proposed ultra-low-power systems. The ultra wide-band unity-gain
analog buer presented in Chapter 4is one example of such designs. More
details on designs and performance achievements of these blocks are available
on Appendix A to Appendix C. The experimental results confirm the wide-
band performance of the buer. The bandwidth of this buer is measured
to be 2.0 GHz while it consumes 7.34 mW from a 1.3-V supply. This design
is fully monolithic and can be used in variety of applications, in particular,
for testing high-frequency and low-power circuits.
To monitor the current in the telemonitoring system and manage the
power consumption a proof-of-concept none-invasive and passive ac current
probe is also designed and fabricated [84]. This architecture operates based
on electromotive force (emf) phenomenon and is capable of sensing a varying
current over a wide range of frequencies. Simulation and measurement results
of a proof-of-concept prototype implemented in a 0.13-mm CMOS confirm the
performance of the presented technique for currents with frequencies up to 8
GHz. Note that in our experimental results, the high-frequency performance
limit is due to the measurement setup. Furthermore, the presented method
can be used to sense currents over a wide range of amplitudes and the ampli-

115
tude detection sensitivity of the technique improves as the frequency of the
current signal which is being measured increases.

7.2 Future Works

As the main objective of this work is to monitor the blood pressure through
live tissues, conducting in-vivo tests are envisioned as a major future goal. To
achieve that, The presented systems has to be embedded on a clinical version
of stentenna and implanted inside live animal test subjects. In such design,
the eects of biocompatible coating on the performance of the overall system
needs to be studied. In the final design, the electronic system requires to have
access to both sides of the stentenna as well as the middle part (serves as
natural reference node) and the capacitive sensor. Reliable implementation
of these connection is also a subject of future work.
In addition, some minor design modifications are also envisioned to im-
prove the performance of the circuits. As discussed in Chapter 5, the pro-
posed telemonitoring system is able to operate from both a low (0.35 V) to
typically (1.0 V) supply voltage. One way to further improve the eciency
of the circuit is to utilize a rectifier block that has optimal eciency for two
dierent input signal amplitudes. An example of such a rectifier is presented
in [74]. Another possible improvement to the design is to replace the simple
clock generator used in this work with a dierential clock generator that has
a fixed tail current. Designing the clock generator circuit in this way leads

116
to chip area saving because smaller transistors are required. Finally the am-
plifier A in CVC design can be replaced by an amplifier with a negative
feedback configuration. In that case, the amplifier gain can be controlled by
adjusting the feedback resistor which in turn modifies the sensitivity of the
overall design.
Finally, to improve the reliability of the telemonitoring system and online
adjustment of the performance of the overall system based on the amount of
the induced current, the integrated current sensor presented in Appendix C
can be incorporated in telemonitoring systems. The proposed current sensor
virtually consumes zero power and therefore other than small are overhead,
it would not compromise the power consumption of the system.

117
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Appendix A

A Monolithic Capacitor-less
Wide-Band LDO Voltage
Regulator in 0.13-mm CMOS

Low drop out voltage regulators are common block in many applications
that are based on energy harvesting. At the beginning of our research we
start improving the basic building blocks of our proposed telemonitoring sys-
tem. As one of the important building blocks of any power conversion chain
(PCC), we first reviewed and modified the conventional LDO regulator ar-
chitecture to make it more suitable for our application (we also improved the
rectifiers architecture). The main concern in our application is attenuation
of the high frequency ripples that are generated by the RF to DC converter
which requires increasing the bandwidth of the currently used LDO voltage

134
regulators. Another important concern is the size of the pass transistor and
transient time of regulation. The following two appendices present alterna-
tive solutions that can reduce the power consumption, active area and recov-
ery/settling time of the conventional regulators with no or little overhead.
In this appendix, an ultra wide-bandwidth LDO regulator is presented that
is capable of rejecting high frequency ripples from the unregulated voltage
source and provide a supply voltage with much less noise and fluctuations for
sensitive analog and mixed-signal circuits. We believe that the advantages
of such regulator architectures are not limited to this particular application
and can be adopted by other designs and/or applications.

A.1 Introduction

Due to their high power eciency and simple design, low-dropout (LDO)
voltage regulators have become popular in many applications including portable
devices, biomedical implants, and power harvesting structures [85]. In mono-
lithic solutions, the power consumption and silicon area of the regulators are
of critical importance. Several studies have focused on decreasing the power
consumption of LDO regulators [6, 86, 87]. Although these studied present
elegant solution to achieve lower power LDOs, in most of them transient re-
sponse and accuracy of the regulator have been compromised. Furthermore,
to decrease the regulator area, dierent regulation techniques and architec-
tures have been proposed [8789]. Some of these approaches aim at eliminat-

135
ing the large output capacitors leading to capacitor-free regulators [90, 91]
which in turn result in a smaller chip area. These regulators are typically
more suitable in regulating low frequency ripples (either from the input volt-
age or the output load). However, in many applications, such ripples occur
at higher frequencies [9294].

Figure A.1.1: A generic block diagram of an LDO voltage regulator.

A generic block diagram of an LDO regulator is shown in Fig. A.1.1. In

highly integrated systems such as system-on-chip (SoC) designs the load cur-
rent will have fluctuations with the clock edges which in turn appear as noise
on the power supply. To eliminate the impact of such high-frequency dis-
turbances a wide-bandwidth regulator is needed. In such cases, it is desired
that the open-loop unity-gain frequency (UGF) of the error amplifier (EA)
in the regulator be higher than the highest fundamental frequency of the rip-

136
ples. Typically, regulator structures that have high-frequency ripple rejection
consume relatively high power and thus are not suitable for low-power and
portable applications [52, 86]. To minimize the eect of such noise on the
sensitive analog circuits, designers usually provide additional clean analog
supply voltage, which results in extra wiring and area to accommodate the
additional supplies. These noises, however, can be attenuated using a high
UGF regulator.
In this design an ultra-wide-bandwidth regulator is presented which is
intended for ultra-low-power systems. The design utilizes the compound er-
ror amplifier presented in [6]. The proposed regulator oers fast transient
response, high power-supply rejection (PSR), even at high frequencies, along
with a low power consumption and a small area. Section A.2 provides a
brief analysis of the key performance parameters of regulators. Section A.3
presents the proposed regulator structure. Simulation and measurement re-
sults are presented in Section A.4 and concluding remarks are provided in
Section A.6.

A.2 LDO Regulator Analysis

Key performance parameters of an LDO regulator, namely, line regulation,

load regulation, settling time, and stability are all aected by the perfor-
mance of the the error amplifier. Here, after a brief formulation of these
performance parameters, analysis and design of the proposed LDO structure

137
will be presented.

A.2.1 Load regulation and line regulation

Load regulation is defined as the ratio of the regulated output voltage change,
Vout , to the output load (current) change, Iout , i.e., Vout / Iout . Accord-
ing to Fig. A.1.1, the small-signal change in the output current change can
be written as:

R2
Iout (!) = Vout (j!) A(!) gm (!) (A.2.1)
R2 + R1

where A(!) is the voltage gain transfer function of the error amplifier and
gm (!) represents the transconductance of the pass transistor at the angular
frequency !. By rearranging (A.2.1), the following equation for load regula-
tion can be obtained:

Vout 1 R2 + R1
(!) = (A.2.2)
Iout A(!) gm (!) R2

Based on (A.2.2), to minimize output variations caused by the load fluc-

tuations with fundamental frequency of !0 , A(!0 ) has to be maximized1 .
Therefore, to attenuate high-frequency voltage fluctuations a relatively high
bandwidth regulator would be needed which can provide a sucient open-
loop voltage gain at the frequency of fluctuations.
1
Increasing gm increases the settling time of the regulator and is not a feasible option
[95].

138
 Line regulation is a measure of the ability of the regulator to maintain its
regulated output voltage level in the presence of variations in the input volt-
age level. It is defined as Vout / Vin , where Vout and Vin are changes in
the output and input voltages, respectively. Based on [95], the line regulation
can be calculated as:

Req (R1 +R2 )

Vout rds +Req
(!)
= (A.2.3)
Vin R1 + R2 + G(!) R2 Req

where, G(!) = A(!) gm (!) is the open-loop gain, rds is the small-signal
equivalent resistance seen between the drain and source of the pass transis-
tor, RL is the load resistance, and Req = (R1 + R2 )||RL . As expected, line
regulation at any given frequency (e.g., at !0 ) can be improved by increas-
ing the voltage gain of the error amplifier at that frequency (e.g., A(!0 )).
Since typically the low-frequency changes in the input voltage have larger
amplitude, to have appropriate regulation, large low-frequency gain for error
amplifier is desired. Serving both open-loop high DC gain and high band-
width is one the main reasons that make use of proposed regulator beneficiary
in RF applications.

A.2.2 Settling time

The settling time (also referred to as the recovery time) is the time that it
takes for the output of the regulator to settle within a given percentage of the
regulated output value, when a step change has occurred in the load current.

139
The settling time is a function of the closed-loop bandwidth of the regulator
and thus it depends on the open-loop bandwidth of the error amplifier. It
also a function of driving capability of error amplifier and pass transistor [96].
To illustrate the settling time dependence to the performance of the error
amplifier, following example is served. Fig. A.2.1 shows the settling times of
two conventional LDO regulators, with two dierent error amplifiers. The
slow regulator has an error amplifier with a bandwidth of 6.26 MHz and
unity gain frequency of 100 MHz, while the faster regulator uses an error
amplifier with a bandwidth of 51 MHz and unity gain frequency of 1.0 GHz.
Both regulators have the same open-loop DC gain of 43.65 dB in the presence
of the maximum load. The settling time of these two regulators has been
simulated for two dierent load current transitions of 1 ns and 500 ns 2 . As
will be explained shortly, the results in Fig.A.2.1 show that the settling time
will increase for faster output load transitions.
2
In the 0.13 m CMOS technology.

140
 fast regulator tst2
1.15
slow regulator tst1
regulated voltage (V) 1.1

1.05

0.95

0.9
tst1
0.85
tst2
0.8
Load transition time= 500 ns
0.75
0.95 1 1.05 1.1 1.15 1.2 1.25
time (sec) x 10
5

(a)

1.2 tst1

1.1
tst2
1
regulated voltage (V)

0.9

0.8
tst1
0.7

0.6
tst2
0.5
fast regulator Load transition time= 1 ns
0.4 slow regulator

1.25 1.3 1.35 1.4 1.45 1.5

time (sec) x 10
5

(b)

Figure A.2.1: Settling time of two conventional LDO regulators with unity-
gain frequencies of 1 GHz (solid line) and 100 MHz (dashed line), for (a)
500 ns (b) 1 ns load current transitions. The fast regulator has less output
change for the same load transition speed. Also, it can be seen that for a
slower load transition time, the output change ( vout ) is less severe for the
faster regulator.

141
 The response time of an LDO regulator (shown in Fig.A.1.1) can be
written as [96]:

1
tsettling
= + tslew1 + tslew2
BWcl
1 vEA vout
= + Cpar + Cout (A.2.4)
U GFol Islew1 Islew2

where BWcl and U GFol are the closed-loop bandwidth and open-loop unity-
gain frequency of system, respectively. tslew1 and tslew2 represent the
components of the settling time due to slewing of the error amplifier and
pass transistor, respectively. tslew1 and tslew2 can be written as a function
of Islew1 and Islew2 , which are the slew current of error amplifier and pass
transistor, respectively. Cpar is the parasitic capacitance of the gate of the
pass transistor and Cout is the total capacitance seen at the output node of the
regulator. In (A.2.4), vEA = ( R1R+R
2
2
) A vout is the voltage change at the
output of the error amplifier, where A is the gain of the error amplifier and
vout is the voltage change at the output of the regulator, when regulators
load changes from its full-load to full load. From (A.2.4) it can be seen
that the settling time is related to four main factors: regulator closed-loop
bandwidth, vout , capacitance Cpar and Cout , and finally the the driving
capability of error amplifier and pass transistor.
By optimizing the maximum load capability of the regulator for ultra low
power applications, it is possible to decrease Cpar of the pass transistor and

142
Cout of the output node remarkably. But in order to further decrease the
recovery time, suitable for agile applications, it is necessary to decrease the
output variations caused by either load or line fluctuations. As it is discussed
earlier, decreasing the output variations is only possible by increasing the
gain of the error amplifier 3 . In this design, the main goal is to increase
the bandwidth of the error amplifier, which, as mentioned earlier, has more
impacts on the performance of the regulator.

A.3 The Proposed LDO Architecture

This architecture combines two amplifiers, an opamp and an operational

transconductance amplifier (OTA) to achieve both high low-frequency gain
and high UGF. In the next section the challenges with using conventional
error amplifier in fulfilling the requirements discussed A.2and proposed one
possible solution using compound error amplifier first introduced in [6].

A.3.1 Challenges with the conventional error amplifier

Note that one can argue that these ripples can be filtered out using a passive
filter, thus there is no need for such wide-band regulator. Since the equivalent
resistance seen from output node of the regulator is normally small (on the
order of ohms to few kilo ohms), to have feasible RC filter, depending on
maximum load of the regulator, a large capacitance at the output is needed
3
Increasing the open-loop gain of regulator by means of pass transistor is not applicable
since minimum parasitic capacitance on the pass transistors gate is desirable.

143
(e.g., 0.01 to 1 F ). Consequently, as it will be explained in detail in the
following sections, large capacitance at the output of regulator will slow down
the recovery time in load regulation. As mentioned earlier, to filter high-
frequency ripples, the UGF of the regulator has to be beyond the fundamental
frequency of the ripple. This in turn requires a high-UGF error amplifier. On
the other hand, to improve the precision and speed of the regulator, the low-
frequency gain of the EA has to be large. Since there is a trade-o between
low-frequency gain and UGF of an amplifier, we are using the architecture
first introduced in [6]. This architecture combines two amplifiers, an opamp
and an operational transconductance amplifier (OTA) to achieve both high
low-frequency gain and high UGF.
Having a low power design in mind, we use a single-stage error amplifier to
also minimize the parasitic capacitances that result in poles. Based on BISIM
model ver. 4 [97] for transistors, in saturation region gds = ID where is
the channel-length modulation parameter. Since in the this case increasing
gm will be possible only by increasing source drain current ID 4 , the small-
signal output resistance rds = 1/gds of output stage transistors will decrease
as well as Rout . Therefore, by increasing gm of a single stage amplifier, the
DC gain would converge to some certain value. This maximum gain in 0.13-
m CMOS technology assuming reasonable size and power consumption is
about 30 dB.
With a simple single stage OTA amplifier, the dominant pole is at the
4
Note that the over-drive voltage is fixed by DC operational points

144
output node and equals pout = 1/ (Cout Rout ), where Cout and Rout are capac-
itance and resistance seen at the output of the amplifier. Assuming a phase
margin larger than 45o (and assuming no zeros before UGF), The unity gain
frequency would be equal to gain bandwidth product of the amplifier:

1 gm
gm Rout = . (A.3.1)
Cout Rout Cout

where gm is the small-signal transconductance of input stage transistor (e.g.

M1 or M2 in Fig. A.3.3). Based on (A.3.1), to increase UGF, gm has to
be increased. With a feasible amount of gm a very high UGF is achievable.
The voltage gain is a product of transconductance and Rout where, Rout =
rdsn ||rdsp , and rdsn and rdsp are the small signal output resistance of nMOS
and pMOS transistors at the output of presumed single stage amplifier. One
can say by increasing gm the DC gain as well as unity gain frequency should
improve. This is not the case, Since gm is inversely related to rdsn and rdsp
and therefore Rout .

145
Figure A.3.1: Small signal transconductance of a nMOS in 0.13 m process
versus drain-source current. In this simulation the drain-source voltage kept
constant and the overdrive voltage is swept.

A.3.2 Analytical background

In this section the eect of paralleling of two systems is analyzed. As ex-

plained in [6], let us assume the amplifiers, S1 and S2 , are linear and their
transfer functions are:

1 1
S1 = G 1 , S 2 = G2 . (A.3.2)
1 + /p1
s 1 + s/p2

146
where G1 and G2 are DC gain, p1 , p2 are systems poles. In a practical
scenario, similar to that used in the proposed LDO, G2 p2 o G1 p1 and
G1 o G2 and p2 o p1 . The parallel combination of the two systems has
the following transfer function:

s
1+ z1
S3 = (G1 + G2 ) s s . (A.3.3)
(1 + p1
)(1 + p2
)

p1 p2 (G1 +G2 )
where z1 = p1 G1 +p2 G2
. By simplifying (A.3.3) using the above mentioned
assumptions, we have:

s
1+
S3
= G1 s
ze1
s . (A.3.4)
(1 + p1
)(1 + p2
)

where ze1 = p1 G1 /G2 . The introduced zero, ze1 is located at the frequency
where the gain of the two systems are equal. Fig.A.3.2 shows an example
gain and phase response of each system and those of the combined of the
overall parallel system. In general, S3 benefits from both high DC gain and
high bandwidth characteristics. In this work, we use a similar concept and
further modify the structure to achieve ultra-high frequency ripple rejection,
fast settling time, and high power supply rejection up to 1 GHz.

147
Figure A.3.2: Sample Bode plots of two first-order systems S1 , S2 and
their parallel combination S3 , calculated in Matlab. In this example, G1 =
60 dB, G2 = 20 dB, p1 = 10 rad/s and p2 = 100 k rad/s.

A.3.3 EA structure

The structure of the error amplifier is shown in Fig. A.3.3. It consist of a

simple single-stage OTA combined with an opamp to provide the high UGF
and high DC gain for the EA.
To elaborate the relation between OTA and Opamp amplifiers, assume
a vIN change in the positive input of error amplifier. This excitation will
produce the change in current iD as shown in Fig. A.3.3 which is equal to
iD = iOT
D
A
+ iOpamp
D , in which iOT
D
A
is the current produced by OTA

148
and iOpamp
D is the current generated by Opamp. From our small-signal
knowledge we know that iOT
D
A
= gmn vIN and iOpamp
D = A1 A2 A3
(1/rout
Opamp
) vIN , where gmn is the small-signal transconductance of the input
stage nMOS transistors (M1 or M2 shown in Fig.A.3.3), A1 , A2 , A3 are the
voltage gain of the first, second and third stage of the Opamp presented
Opamp
in Fig. A.3.5, and rout is the equivalent small-signal output resistance of
the Opamp. Knowing that the small-signal output voltage of the compound
amplifier is given by:

gmp3
vout = iD OT A
rout (A.3.5)
gmp4

Figure A.3.3: Compound error amplifier structure similar to that of [6] which
consists of an OTA and an opamp and is used in the proposed LDO regulator.

149
 where rout
OT A
is the small-signal output resistance of OTA and gmp3 , gmp4
are the small-signal transconductance of pMOS transistors (M3 and M4 in
Fig. A.3.3). By simplifying above equations: It can be shown that the voltage
gain of the compound amplifier can be calculated as:

OT A

vout rout
AV = = AOT
V
A
+ AOpamp
V Opamp
. (A.3.6)
vin rout

In (A.3.6), AOT A and AOpamp are the voltage gain of the OTA and opamp,
Opamp
and rout
OT A
and rout are the small-signal output resistance of the OTA and
opamp, respectively. In addition, (A.3.6)confirms that the presented am-
plifier (also can be seen in [6]) is the parallel of high DC gain Opamp and
ultra high band width OTA amplifiers. Simulation and measurement results
shown in followed by Section support this argument.

A.3.4 Stability

Since the output impedance of LDO regulator with a common-source pass

transistor is large (Fig. A.1.1), the overall output impedance of such regu-
lators is approximately equal to the load impedance. Assuming a constant
load capacitance, variations of the load resistance results in variations of the
output pole over a wide range of frequency. This is one of the reasons that
makes the design of stable regulators challenging.
The open-loop small- signal output resistance of the regulator can be cal-
pass
culated as Rout = RL || (rds || (R1 + R2 )) RL . Assuming a constant output

150
capacitance Cout , the output pole of the regulator (which is usually the dom-
inant pole) is given by pout = 1/Cout Rout
= 1/Cout RL . Since the output pole is a
function of RL , extreme changes of the output load leads to wide frequency
variations of pout . This is one the challenges in designing such regulators. If
the designer doesnt set this pole as a dominant pole of the regulator, phase
margin of the regulator can drop to negative values (in no-load condition)
and brings the regulator to an unstable state. The conventional method to
ensure that the stability of the regulator is to add a large capacitor (in the
order of few F ) to the output node of the regulator. This capacitor is typi-
cally an o-chip capacitor and it is added to make sure that even in the worse
case (full-load) the output pole remains dominant. In this work, to avoid the
use of such a large capacitor (having a monolithic design in mind), the out-
put capacitance is minimized and ensured that the output pole will remain
the third dominant pole of the system. To achieve a high phase margin an
extra zero is also added by adding a capacitor in series with a resistor in par-
allel with the output of EA (or equivalently the gate of the pass transistor).
Since this zero has to be at a frequency lower than the open-loop UGF of
the regulator, a higher UGF leads to an smaller capacitor.

Pole-zero locations in proposed LDO

Fig. A.3.4 presents a simplified bode diagram of the proposed system. The
dominant pole is introduced by the opamp amplifier described in the above
section. At fz1 = 1/2 AV a zero from paralleling two system is
Opamp
p1/AOT A
V

151
introduced (as described before as ze1 ) which increases the phase margin and
bandwidth of the regulator.

Figure A.3.4: Pole/zero locations of the open-loop voltage gain of the pro-
posed LDO regulator

The next pole belongs to OTA; This is the dominate pole of OTA and
since the OTA is designed to have a phase margin of more than 70 , the
second dominate pole of it would be far enough. Therefore, in this stability
studies, we do not need to consider the eect of the second pole of the OTA
which would be the fourth pole of the overall regulator. In order to maintain
the phase margin of the regulator above 45 , the changes of the output pole
due to the change in loads should be taken into account . For this reason, an
ESR zero has been inserted at zESR frequency. This will insure that, even in
no-load condition, where the output pole frequency (the last pole shown in
Fig. A.1.1) is behind the UGF of the regulator, the overall phase margin of
the regulator will stay above 45 .

152
 The third pole of the overall regulator belongs to the output node, namely
pout .

A.3.5 Opamp schematic

Several high DC gain opamp has been reported in the articles which most of
them has cascoded and complex architectures. To maximize the power supply
rejection ratio and to obtain the required DC gain with minimum voltage
headroom, the schematic shown in Fig. A.3.5 is used for the opamp. In this
architecture, to benefit from the high DC gain at a low voltage headroom, an
structure called composite cascode is utilized in Widlar opamp architecture
[98]. We have modified the structure of [98] by self-biasing of M8, i.e., the
DC voltage level of M7,8 are generated by using a diode-connected M8.

153
 Figure A.3.5: Schematics of the opamp used in the error amplifier

Table A.1: Dimensions of transistors in the architecture shown in Fig. A.3.5

Transistor Width (m) Length(m)

M1,M2 2 0.5
M3,M4 20 0.5
M5,M6,M8,M11 1 2
M7,M8 0.5 2
M12,M14,M16 0.2 1
M13,M15,M17 2 1
M9 0.5 5
M10 0.3 5

A.3.6 Band-gap circuit

To stabilize the output voltage of the regulator to a designated value and

also to have a built-in biasing circuitry, a band-gap circuit has been designed

154
along with the Regulator. The schematics of band-gap circuit is shown in Fig.
A.3.6 and the transistor dimensions are presented in Table A.2. According
to the simulation the band-gap circuit can generate 550 mV reference voltage
for the regulator for the minimum power supply of 700 mV.

Figure A.3.6: Band-Gap Reference voltage and bias circuit

155
 Table A.2: Transistor Dimensions of Band-gap Circuit
Transistor Width (m) Length (m)
M1,M2 1 1
M3 10 1
M4,M11 5 1
M5 2 1
M6 20 1
MM7 1 4
M8 1.9 3
M9 2 4
M10 12 1
M12,...,M16 0.5 5
M17,M18,M19 0.3 0.12

A.4 Experimental and Simulation Results

The presented LDO is designed and fabricated in 0.13-m CMOS. The chip
micrograph is shown in Fig. A.4.1. The chip area is 0.096 mm2 , excluding
the test pads, which includes two copies of the regulator (one with a low-pass
filter for open-loop testability). The regulator occupies 0.00405 mm2 . Unless
otherwise stated, in all measurements VIN = 1.2 V and If ullload = 500 A.

156
Figure A.4.1: Micrograph of the test chip which includes an open-loop LDO
(LDO 1), a close-loop LDO (LDO 2), and some additional test blocks.

A.4.1 DC measurements

The total measured quiescent current of the regulator in no-load condition

is 44 A. The distribution of the bias current to the error amplifier, refer-
ence voltage circuit and feedback resistors are about, (36.023+6.729) A,
7.0996 A and 10.977 A respectively. The average DC output voltage gen-
erated by internal reference voltage, in no-load and full-load conditions are

157
1.03 V and 1.000 V. The measured DC (steady-state) line regulation for two
cases of full load and no load are shown in Fig. A.4.2. The measured line regu-
lations in no-load and full-load conditions are 70 mV/0.4 V and 35 mV/0.4 V,
respectively. These measurements a performed using HP 4155A semiconduc-
tor parameter analyzer.

1
Regulated voltage (V)

0.8

0.6

0.4

0.2 0A
100 A
500 A
0
0.4 0.6 0.8 1 1.2 1.4 1.6
Input voltage Vin (V)

Figure A.4.2: Measured DC line regulation in no-/full-load conditions.

158
 1.05
Measured

Regulated voltage (V)

1 Simulated

0.95

0.9

0.85

0.8
0 0.2 0.4 0.6 0.8 1
55

50
IQ (A)

45

40
0 0.2 0.4 0.6 0.8 1
Load current (mA)

Figure A.4.3: Measured and simulated DC load regulation and quiescent

current of LDO regulator with built-in reference generator.

A.4.2 Transient measurements

The turn-on 2% settling time is measured using both internal and external
reference voltage in no-load condition (worse case); The values are 2.7 s and
2 s, respectively.
In this experiment to eliminate the impact of the built-in reference volt-
age, an external reference voltage has been applied.
As shown in Fig. A.4.4, turn-on settling time for the regulator with built-
in voltage band-gap circuit is measured to be 2.7 s, and the turn-on settling
time with applied external reference voltage measured to be 2 s.

159
Figure A.4.4: Measured turn-on settling time w/o external reference voltage

Figure A.4.5: Regulated ac-coupled output voltage of the regulator for

VIN = 1.27 + (0.55) sin((2)38MHz).

160
 1.05

Regulated voltage (V) 2%

0.95

0.9 150 ns

0.85

0.8
0 100 200 300 400 500 600
time(ns)

(a)
1.08
1.06
160 ns
Regulated voltage (V)

1.04
1.02
2%
1
0.98
0.96
0.94
0.92

0 100 200 300 400 500 600

time(ns)

(b)

Figure A.4.6: Measured transient load regulation for: (a) full load to no-load
(b) no-load to full-load transitions with CL = 0.7 pF.

161
 40 UGF of 0.7 to 1 GHz

Gain(dB)
20 Effect of
LP filter

0 UGF 70 MHz

1k 10k 100k 1M 10M 100M 1G

100
Zero introduced by No load @ 0.5 pF
50 compound amplifer Full load @ 0.5 pF
Phase (deg)

Full load @ 10pF

0
PM of 47 to 40
50 Effect of
LP filter
100 PM 81

150
1k 10k 100k 1M 10M 100M 1G
Frequency (Hz)

(a)

Opamps dominant
60 pole
Gain (dB)

40
Effect of
LP filter Zero intruduced by
20 compound amplifier
~60 MHz of UGF
0 @ 500A
1k 10k 100k 1M 10M 100M
150
100
Phase (deg)

50 Effect of Zero introduced by

compound amplifier ~80 PM
LP filter
0
50
100
1k 10k 100k 1M 10M 100M
Frequency (Hz)

(b)

Figure A.4.7: (a) Simulated open-loop gain and phase responses for full load
(500 A) and no load (10 A) with CL =0.5 pF. (b) Measured gain and phase
responses for full load (500 A) and CL
=10 pF.

162
A.5 AC Response

To measure the open-loop frequency response, special attention has to be

paid that all blocks inside the regulator are biased properly. One possible
approach is to add a low-pass filter (LPF) in series with the positive input
of the error amplifier. In this way, the regulator can obtain its DC operating
point (since for low frequencies including DC the low pass filter act as a short
circuit and the loop is closed) and at the same time we can measure the open-
loop frequency response for frequencies higher than the LPF cut-o frequency
(since the loop is practically open at frequencies much higher than the LPF
cut-o frequency). Fig. A.4.7 (a) shows the simulated frequency response
of the open-loop regulator. As confirmed by these results, the frequency
response of the open-loop regulator has a DC gain of about 41 dB for no-load
and 34 dB for full-load condition, while the open-loop unity gain frequency
is 0.73 GHz for no-load and 1.00 GHz for full-load condition. Note that for
measurement results we have to use an interface to derive the 50 input
impedance of the vector network analyzer (Agilent E5061B) and connect
the output of the regulator (which can drive maximum of 2 k at 1.0 V)
to the measurement device. This extra interface circuit adds about 10 pF
load capacitance to the output node of the regulator. Due to this extra
capacitive load the measured unity gain frequency of the regulator is reduced
to 60 MHz while it still shows the existence of the zero introduced by
the compound error amplifier and the corresponding stability improvement.

163
As mentioned earlier, this regulator is designed for ultra low power agile
applications with the maximum expected capacitive load of 500 fF.

0 21.3 @ 1GHz
12.62 @ 1MHz
10

20
PSR (dB)

60 Hz

30

40 27.1 @ 100 MHz

50

100 1k 10k 100k 1M 10M 100M 1G

Frequency (Hz)

Figure A.5.1: Measured PSR of the proposed regulator under full load
(500A).

Experimental results for PSR and load regulation are shown in Figs. A.5.1
and A.4.6 respectively. To implement fast load transitions, an external
CMOS low-voltage RF SPST switch (ADG751) with ton
= 9 ns, is used
and is driven by a voltage source with rising and falling time of 1.6 ns. The
PCB with the switch circuit adds 0.7 pF to the output of regulator. Mea-
sured results show that the settling time of the proposed regulator to reach to
98% of its final value is 160 ns in worse case (full load to no load transition)
which is in agreement with simulation results. Note that a portion of the
outputs ripple during load transition is caused by the SPST switch.
Table A.3 presents the performance summary of the LDO and compares

164
it with state-of-the-art LDOs.

A.6 Concluding Remarks

An ultra-wide-bandwidth LDO regulator designed for low-power agile appli-

cations is presented. Experimental results verify the high-frequency regula-
tion capability of the presented regulator along with its fast recovery time
for load and line regulations. Its ultra-low-power and small area makes this
regulator suitable for portable devices and biomedical applications.

165
 Table A.3: Performance summary and comparison with the state-of-the-art LDOs.
[99] [100] [101] [6] [86] [102] This Work
Year 2013 2013 2010 2006 2010 2009 2013
Technology (m) 0.18 0.065 0.09 0.8 0.18 0.13 0.13
max load
IQ (A) 40 0.9 33-145 300 35 50 44
Area 0.00405mm2 10.86 4.20 3.07 585.18 76.54 12.1 1
Settling time (s) 1.172 6 160 100 0.16
166

ILoadmax (mA) 100 100 140 1380 150 2 0.5

56 @ 10 MHz 67 @ 1 MHz 50 @ 1 kHz, 12.6@ 1 MHz
PSR (dB) 58 @ 10 kHz 64.3 @ 1 kHz
30 @ 30 MHz 56@ 10MHz 27 @ 100 MHz, 21.3 @ 1 GHz
Bandwidth 10 MHz 20 kHz 1.57 GHz @ full load
Vout (mV ) 100 69 94 110 196 15 150
Vdrop out (mV ) 200 200 >150 300 541 200 80

* Including digital unit for battery charger

**from no-load to full-load
Appendix B

A 0.13-m CMOS Low-Power

Capacitor-less LDO Regulator
Using Bulk-Modulation
Technique

In this appendix, an alternative method for deceasing the dimensions of the

bulky pass-transistors in low-drop-out voltage regulators are presented and
analyzed. The proposed technique can increase the current delivery of the
regulator as well as the speed of load and line regulations. This technique can
be used in low-power applications such as biomedical applications and tele-
monitoring. To demonstrate the enhancements achieved by this technique,
we applied it to a conventional LDO structure and compare the performance

167
factors of the enhancedregulator with the conventional regulator without
this technique. In the following sections this technique is more elaborated
and verified by simulation and measurement results.

B.1 Introduction

Low-drop-out (LDO) voltage regulators are commonly used in electronic sys-

tems particularly in portable or low-power applications. Their main function
is to provide a stable supply voltage by minimizing (ideally eliminating) the
ripples and noises caused by imperfect power sources and/or variable load
currents. In portable devices and many biomedical implants the power con-
sumption of the regulator as well as its recovery time are among the impor-
tant design considerations. Furthermore, in applications that use a wireless
power transfer scheme, e.g., radio-frequency (RF) power harvesting, the reg-
ulator has to eliminate the high-frequency ripples caused by the first stage of
power conversion chain (PCC). Typically, low-complexity integrated LDOs
have a relatively slow recovery time [103107]. Therefore, extensive studies
have been and are being pursued to improve the recovery time, as well as load
and line regulation performance of integrated LDOs [103,108112] . In many
of such designs the improvement in recovery time is achieved by employing
additional and often fairly complex circuitry [110112] which in turn results
in higher power consumption and/or larger chip area.

168
 VIN

Vref
EA MPass
Vout
Reference
and biasing
circuit

CL RL

Feedback
circuit
Load

Figure B.1.1: Block diagram of a generic LDO voltage regulator.

Fig. B.1.1 illustrates the generic configuration of a conventional LDO

voltage regulator. As shown in the figure, the system consists of an error
amplifier (EA), a reference voltage generator, a feedback circuit and a pass
element (i.e., pass transistor). Based on the structure of the pass element,
two dierent LDO categories are recognized: common-drain (CD) structure
which uses an n-type pass element and common-source (CS) structure which
utilizes a p-type pass element. For a CD LDO regulator, it is desirable to
use a low-threshold pass transistor. Using a low-threshold device will also
have an impact on the fabrication cost, therefore, this type of regulator is
typically not suitable for low-cost applications. On the other hand, using a
CS pass element may introduce stability issues and thus typically requires
a large external capacitor [86, 108]. To ameliorate this issue particularly
in fully integrated designs, capacitor-free monolithic regulators have been

169
 VB VIN
M3 MPass
M4 M5 M14 M12 M13 M15 M21 M22

VB Cc

M10 M11
Vref
M19 M20

Regulated
A

voltage
Vref VC M8 M9
VC
M2 VOTA
Vref M23
Vopamp Rb1 M6 M7 R1
M1
VOTA
Vopamp
Rb3 Rb2 M16 M18 M17 R2

Reference and biasing circuit Gate Error Amplifier (EA-a) Bulk Error Amplifier (EA-b)

Figure B.1.2: Schematic of the proposed LDO regulator. To facilitate testing

VB is applied externally.

proposed [87, 99, 103, 110]. Usually, these structures utilize left-half plane
(LHP) zero which is introduced by the equivalent series resistance (ESR) of
the output capacitor to stabilize the circuit without the need of using a very
large external capacitor. However, one of the challenges of this compensation
technique is that the eective ESR of a capacitor varies with load as well as
temperature [105, 110, 113] and thus the frequency of the zero would change
accordingly.

In addition to using relatively large external capacitors, conventional LDO

regulators usually use a large pass transistor which not only occupies a large
chip area but also introduces a large parasitic capacitance as the load of the
error amplifier. This large load capacitance adversely aects the open-loop

170
bandwidth of the regulator.
In this work, to address the above-mentioned issues, we present an alter-
native simple technique that modulates the bulk voltage of the pass element
to enhance the performance of the LDO. The proposed structure improves
line and load regulations as well as the driving capability of the regulator
while it reduces the power consumption of the LDO as compared to con-
ventional LDOs with similar performance. Furthermore, as compared to
conventional approaches, the technique also improves the transition recovery
time for no-load to and from full-load conditions, thus, making it suitable for
applications where load conditions may change rapidly.

B.2 The Proposed LDO Structure

The proposed technique takes advantage of body eect to reduce the thresh-
old voltage of the pass transistor for any given current load. In this section,
after a brief review of the body eect, we present and analyze the proposed
LDO structure.
The change of threshold voltage of a MOS transistor as a function of
its source to bulk voltage is referred to as body eect. For long-channel
devices, the threshold can be approximated by [80, 97]:

p p
|Vth | = |Vth0 | + VSB + 2| F| 2| F| (B.2.1)

171
 where Vth is the threshold voltage of the device for VSB 6= 0, and Vth0 is
the nominal threshold voltage value for VSB = 0, is the body-bias coecient
and 2| F| is the surface potential.

2.5

1.5
gmb (mS)

0.5

0
0 0.2 0.4 0.6 0.8 1 1.2
Vbulk (V)

Figure B.2.1: Simulated gmb versus dierent bulk-source voltages for a typical
pmos pass transistor with (W/L) = (50 m/0.12 m).

Given that for pmos transistors < 0, from (B.2.1), it can be seen that
by decreasing the bulk voltage in pmos transistors the absolute value of the
threshold voltage decreases. For a fixed VSG , this change in the threshold
voltage will result in an increase in the drain-source current and vice versa.
Since the eect of the bulk voltage on the drain-source current is similar to
that of the gate voltage, the body eect is sometimes referred to as back-gate

172
eect [80]. The small-signal bulk transconductance of a pmos transistor can
be derived as:

@ID
gmb = = p gm (B.2.2)
@VSB 2 VSB + 2| F|

where gm is the small-signal transconductance of the device. Using (B.2.1)

to replace |Vth | in (B.2.2), one can show that the bulk transconductance
(gmb ) has a maximum which is a function of VSB . Fig. B.2.1 shows gmb of
the pmos pass transistor used in this work, as a function of Vbulk . This
simulation result shows that gmb of a pmos transistor, with the aspect ratio
of (W/L) = (50 m/0.12 m) when its source is connected to 1.2 V, reaches
its maximum in the vicinity of Vbulk
= 700 mV, or equivalently, VSB
= 500
mV. As it will be explained later, this is one of the reasons that the DC
operating point of the bulk error amplifier has been chosen to be 700 mV.

Proposed configuration

Voltage regulators that are used in low-power RF energy harvesting appli-

cations are desired to have a bandwidth greater than the fundamental fre-
quency of the ripples of the unregulated supply voltage (i.e., incident RF
signal). Furthermore, a relatively large open-loop DC voltage gain is needed
to provide an accurate regulated output voltage. In this work, we present
a voltage regulator architecture that not only satisfies the above-mentioned

173
criteria but also improves the driving capability of the regulator.

VIN

Vref Vref
MPass
EA-a EA-b

Reference
and biasing
circuit Vout

R1

CL RL
R2

Feedback Load

Figure B.2.2: Block digram of the proposed LDO regulator.

The block diagram of the proposed LDO regulator is shown in Fig.B.2.2.

The bulk of the pass transistor is connected to the output of an extra error
amplifier, namely, EA-b. Since typically gmb is smaller than gm , to achieve
a higher open-loop DC gain the amplifier with a larger DC gain (i.e., EA-a) is
connected to the gate of the pass transistor while the amplifier with a higher
bandwidth (i.e, EA-b) is connected to the bulk terminal. Therefore, the main
error amplifier will provide the high DC gain for accurate regulation while
the bulk amplifier provides agile response to the output changes. Fig.B.1.2
illustrates the overall schematic of the presented LDO regulator. Detailed
analysis is provided in the next section.

174
B.3 The Proposed Bulk Modulation Technique

In this section, we present dierent attributes of the proposed bulk modu-

lation technique and discuss dierent performance metrics of the regulator.
More specifically, in the time domain, the recovery time of the regulator for
dierent types of line and load regulations are analyzed. Furthermore, the
stability of the regulator for dierent resistive and capacitive loads is inves-
tigated through a detailed pole-zero analysis in the frequency domain. Note
that all the presented simulation results are based on post-layout simulations.
The results are later verified through measurements of a proof-of-concept pro-
totype that includes two LDOs one with and the other without proposed bulk
modulation technique. The prototype is implemented in a 0.13 m CMOS
technology.
Here, we demonstrate the enhancements resulted from the proposed tech-
nique by applying it to a conventional LDO regulator, however, one can apply
the proposed technique to other LDO architectures as well.

B.3.1 Driving capability

As will be discussed, one of the main benefits of modulating the bulk of

the pass transistor is that for a given aspect ratio of the pass transistor,
bulk modulation improves the output current delivery. On the same token,
using bulk modulation one can achieve the same current delivery with a
smaller pass transistor. To improve the current delivery for a given transistor

175
 3
10
2
10 127 C
1 30 C
10
0
27 C
10
IBulk (A)

VBulk=0.7 V
3
10

5
10

7
10
0.2 0.3 0.4 0.5 0.6 0.7
VSB(V)

Figure B.3.1: Ibulk vs. VSB for VS = Vin = 1.2 V and VG = 800 mV. The size
of the pmos transistor is the same as the pass transistor used in presented
LDO regulator(50m/120nm).

overdrive voltage, we rely on the fact that one can reduce the threshold
voltage of the pass transistor by applying a proper voltage (refer to B.2.1)
to its bulk. To reduce the threshold voltage, the applied bulk voltage has to
be lower than the source voltage, i.e., VIN of the regulator. Fig. B.3.1 shows
a generic plot of the bulk current of a pmos pass transistor (with an aspect
ratio of (W/L) = (50 m/0.12 m) used in this design) versus its source-
bulk voltage VSB = VS VB . As shown, the source-bulk current will increase
drastically when the source-bulk voltage is increased. This is expected,
since for positive values of VSB the source-bulk diode will be forward biased
and beyond some threshold voltage will fully turn on. Figure B.3.1 shows
that the bulk current of the pass transistor is negligible as compared to the

176
total quiescent current over an extended range of temperature, given that
the overall quiescent current of the circuit is 99 A. As expected the forward
biased source-bulk diode drains more current at higher temperatures. For
bulk voltage of 0.7 V (VSB = 0.5 V) the source-bulk leakage current is less
at most around 1A (at 127 C). Therefore, if the DC voltage of the bulk
error amplifier EA-b is around 0.7 V, the source-bulk diode does not conduct
excessive amount of current. Note that we are interested to set the DC
voltage level of the pass transistor bulk as low as possible to maximize the
driving capability of the pass transistor. In this design, we set the DC output
voltage of EA-b to 0.7 V when the common-mode DC voltage of its inputs
are at Vref . As a result when the regulator is at steady state, the bulk
voltage of its pass transistor is at 0.7 V. We designed the EA-b amplifier and
sized the transistors in such a way that the output DC voltage has minimum
changes due to process variations and mismatches. Based on the Monte Carlo
simulation results (N=100), the DC voltage of EA-b amplifier has a mean
value of 695.95 mV with the standard deviation of 77.0 mV.

177
 2.5

Normalized ISD 2

1.5

0.5
0 0.2 0.4 0.6 0.8 1 1.2
V
bulk

Figure B.3.2: The simulated ISD versus Vbulk for pass transistor. Note that
the value of the ISD is normalized for VBS = 0 or Vbulk = 1.2 V.

Fig. B.3.2 shows the relation between the Vbulk and the normalized source-
drain current of the pass pmos transistor (normalized to the source-drain cur-
rent when VBS = 0), for a constant gate-source voltage of 400 mV. According
to this figure, the current delivery to the load can be improved by applying
a proper voltage to the bulk. Note that to avoid turning on the source-bulk
diode, the bulk voltage has to be larger than 700 mV (at 127 C) . By choos-
ing Vbulk = 0.7 V the current delivery of pass transistor is twice as much as
the current delivery of the conventional structure where the Vbulk of the pmos
pass transistor is equal to its source voltage (i.e., VBS = 0 V). Therefore, by
applying Vbulk = 0.7 V, we can expect about %100 improvement in the cur-
rent delivery of the regulator. Note that this simulation result is obtained

178
under a constant gate-source voltage, if the gate-source voltage changes, this
improvement may reduce accordingly. This improvement is verified by both
simulation and measurement results in the following section (Fig. B.4.1(a)).

B.3.2 Transient behavior

The load-regulation recovery time is an important performance metric of

LDO regulators, in particular, for regulators that are used for supplying
power to digital or mixed-signal circuits with a high-activity blocks. Referring
to Fig. B.2.2, it can be shown that for agile changes in the load current, the
recovery time of the output voltage can be written as [111, 114]

1 1 VA
trec t + tslew = + Cpar (B.3.1)
BWcl BWcl Islew

where BWcl is the close-loop bandwidth of the regulator and tslew is the
time delay due to the slewing of the error amplifier while driving the pass
transistor. In (B.3.1), Cpar is the total parasitic capacitance seen at the
output of the error amplifier (mainly dominated by the gate capacitance of
the pass transistor) and VA and Islew are the output voltage change and
maximum slew current of the error amplifier. Furthermore, it can be shown
that the output voltage change due to such agile load current change is also
a function of the recovery time [114].

179
 1.15 X: 7.02

Regulated voltage (V)

Y: 1.116
EAb correction and slew
EAa correction and slew
1.1
vout= 0.12
1.05 X: 7.054
Y: 1.024
X: 7.128
Y: 1.024

1
trec
0.95 trec
w/o bulk modulation
with bulk modulation
7 7.05 7.1 7.15 7.2
3
Load current (mA)

2.5
2
1.5
1
0.5
7 7.05 7.1 7.15 7.2
time (us)

(a)
1.1
trec
1
Regulated voltage (V)

X: 2.018 X: 2.09
Y: 0.9808 Y: 0.9808
0.9
vout= 0.3 trec

0.8
vout= 0.5 EAa correction and slew

0.7
EAb correction and slew

0.6 w/o bulk modulation

with bulk modulation
0.5
1.95 2 2.05 2.1
3
Load current (mA)

2.5
2
1.5
1
0.5
1.95 2 2.05 2.1
time (us)

(b)

Figure B.3.3: Recovery time analysis for LDO regulator with and without
bulk modulation technique in (a) sudden plunge and (b) increase of the load
current.

180
 In a conventional regulator (Fig. B.2.2 excluding EA-b), when the load
current suddenly drops, the output of EA-a will increase up to VIN to reduce
the pass transistor current as much as required to regulate the output voltage.

In the proposed technique, when bulk modulation is applied to the pass

transistor, the fastererror amplifier (EA-b) will sense the change and in-
1
creases the bulk voltage of the pass transistor from its equilibrium voltage
up to the maximum value of Vin . This will cause an increase of the threshold
voltage of the pass transistor which further helps to reduce the current of
the pass transistor and thus shortens the recovery time. The simulated re-
covery time of the two LDO regulators (with and without bulk modulation)
are compared in Fig. B.3.3.
The behavior of the conventional and the proposed regulators when the
output load current has a sudden increase is dierent. This load current
change will cause a voltage drop at the output. In the conventional regula-
tor, the error amplifier adjusts the gate voltage of the pass transistor to a
very low voltage. Since it is a large signal change at the output of the error
amplifier, it causes a time delay due to slewing, tslew . In addition, due to
the low bandwidth of the error amplifier 2 , the amount of the output voltage
1
The equilibrium bulk voltage is the bulk voltage of pass transistor when the output
of the regulator is set to its designated value. At equilibrium, the inputs of both error
amplifiers are equals to the reference voltage. EA-b is designed to have the equilibrium
output voltage of 700 mV.
2
Conventional LDO regulators, typically use a high-DC-gain low-bandwidth amplifier
as an error amplifier [87, 112, 115117].

181
change is typically large which results in a slow recovery. In the proposed
regulator, using bulk modulation of the pass transistor, the bandwidth of the
overall system is increased. Furthermore, by using the second error amplifier
(i.e., EA-b) the overall slew time of the output node, namely, tslew , is de-
creased. Thus, as depicted in Fig. B.3.3, both recovery time and the output
voltage change are decreased. To further elaborate this enhancement, note
that by applying the proposed bulk modulation technique, one can use a
smaller aspect ratio pass transistor while achieving the same current delivery
of the conventional regulator. The smaller pass transistor implies a smaller
parasitic capacitance and thus a faster operation. In addition, since the bulk
amplifier (EA-b) is designed to have a higher bandwidth than the standard
error amplifier (EA-a), it can sense the changes in the output voltage faster,
and thus result in a faster operation and less voltage fluctuations.

182
 200

Phase margin (deg)

100

100

0.3 0.5 1 2 3 5 10 20 30 50
180
Cbulk (fF)

160

140
0.5 1 2 3 5 10 20 30 50
RL (k)

Figure B.3.4: (top) The phase margin of two regulators in extreme conditions.
The proposed regulator in blue remains stable even when the conventional
regulator is about to experience 180 of phase margin, (bottom) Total
parasitic capacitance of the bulk of the pass transistor versus the equivalent
load resistance RL .

B.3.3 Stability analysis

For the proposed architecture, the low-frequency small-signal open-loop gain

of the regulator can be written as:

pass
AV = f Rout [(A1 dc
pass
gm ) + (A2 dc gmb )] . (B.3.2)

In this equation, f is the feedback gain and is equal to R2

R1 +R2
, Rout =
pass
RL ||rds = R is the open-loop output resistance of the regulator, where
pass
rds is the small-signal drain-source output resistance of the pass transistor,
RL is the equivalent resistance of the load which is typically much smaller

183
 pass
than rds , A1 dc and A2 dc are the low-frequency small-signal voltage gain
pass
of the main and bulk error amplifiers, respectively, and gm
pass
and gmb are
the small-signal gate and back-gate (body) transconductance of the pass
transistor. From (B.3.2), the overall open-loop gain of the regulator is a
function of the sum of the gains of the two error amplifiers. It can be shown
that the open-loop phase response of the regulator at any given frequency
would follow the phase of the error amplifier that has a higher gain at that
frequency.

Referring to the open-loop gain and the phase response of the regulator
shown in Fig. B.3.5, the open-loop structure has a dominant pole which
belongs to EA-a (namely, the dominant pole of the opamp in EA-a, !opamp ).
This pole is at node A shown in Fig. B.1.2 and is independent of the load
current of the regulator. The second pole is the dominant pole of the EA-b
which is given by:

1
!OT A = (B.3.3)
(Cbulk + Cota ) rota

where, Cbulk is the total parasitic capacitance seen at the bulk of the pass
transistor, Cota = Cpar
n p
+ Cpar is the parasitic capacitance seen at the output
stage of the EA-b and rota is the small-signal output resistance of the EA-
b. Note that Cpar
n
and Cpar
p
are the total parasitic capacitance at the output

184
 100
with BM
80 w/o BM

60 Introduced zero UGF

improvment

Gain (dB)
40
ILoad= 3 mA UGF=17 MHz
20

0 UGF=1.75 MHz

20 2 4 6 8
10 10 10 10

PM
150

Phase margin (deg)

improvment
Introduced zero

100

50
PM=86

0 PM=132

50 2 4 6 8
10 10 10 10
frequency (Hz)

(a)
100
with BM
80 w/o BM

60 Introduced zero UGF

improvment
Gain (dB)

40
ILoad= 2 mA UGF=110 MHz
20

0 UGF=3.9 MHz

20 2 4 6 8
10 10 10 10

PM
150
Phase margin (deg)

improvment
Introduced zero

100

50
PM= 80

0 PM=82

50 2 4 6 8
10 10 10 10
frequency (Hz)
(b)

100 with BM
w/o BM
Gain (dB)

50
UGF=117.8 MHz
ILoad= 0 mA

0 UGF=27.33 MHz
2 4 6 8
10 10 10 10
200
Phase margin (deg)

100

0 PM=11.9
PM= 105
100 2 4 6 8
10 10 10 10
frequency (Hz)

(c)
Figure B.3.5: Simulated open-loop bode diagram of the proposed LDO con-
figuration with and without bulk modulation technique for load currents of
(a) 3 mA (RL = 0.33 k), (b) 2 mA (RL = 0.5 k), and (c) 0 mA (no-load).
185
node of the EA-b amplifier, that are introduced by nmos and pmos transistors
connected to that node respectively. Due to the use of the two amplifiers in
parallel, a zero is created in between these two poles. It can be shown that
pass
this zero is at the frequency !z where A1 (!z ) gm
pass
= A2 (!z ) gmb . Since
this zero is always in between the above mentioned poles, it compensates the
phase drop caused by the first dominant pole. The third pole of the system
is located at the output node of the regulator and is usually at a higher
frequency (compared to the above mentioned two poles) and is given by:

1
!L = (B.3.4)
2 (CL + Cpar ) Rout

where, CL and Cpar are the load and parasitic capacitance at the output node
of the regulator. The variation of the load current which can be interpreted
as the variation of RL may cause an instability in the system. The problem
arises when the value of the load current is very small and at the same time
large capacitive load is attached to the system. In this case !L will be at
lower frequencies and may fall below the unity gain frequency (UGF) of the
regulator, and therefore may deteriorate the phase margin.
In a conventional LDO regulator, any decrease in the output load current
will lead to an increase in the open-loop voltage gain of the regulator (refer
to (B.3.2)), and consequently, it will increase the UGF of the conventional
regulator as given by:

186
 U GF
= !opamp Av . (B.3.5)

This increase in UGF may jeopardize the phase margin and therefore the
stability of the overall system. An illustrative example is shown in Fig. B.3.5
(b). The transient response of this case is shown in Fig. B.4.6.
In the presented regulator, the frequency of the second dominant pole of
the regulator depends on the load current. When the load current decreases
the gain of the regulator will increase but at the same time Cbulk will increase
as well. This increase of Cbulk is a consequence of the change in the pass
transistor operating point. Since a part of the parasitic capacitance seen
from the bulk of the transistor is the parasitic capacitance between bulk and
drain, due to the increase in the bulk-drain voltage gain the Miller equivalent
capacitance seen at the bulk will increase. Fig. B.3.4 illustrates this relation.
The increase of Cbulk consequently leads to a decrease of the frequency of
!OT A as the second dominant pole of the regulator. Since the eect of the first
dominant pole (!opamp ) has been compensated by !z , the unity gain frequency
in the proposed regulator is more robust to changes of the load current. As
a result, the proposed regulator supports a wider output capacitance range
while preserving its stable regulation. This robustness is verified by both
simulation and measurement as shown in Figs. B.3.5 (b) and B.4.6.

187
Figure B.3.6: Micrograph of the overall design including two LDO regulators
highlighted by blue-dashed line.

B.4 Simulation and Experimental Results

To validate the proposed technique, two regulators (one with and one without
the proposed bulk modulation technique) are designed and fabricated in a
0.13-m CMOS technology. To study the open-loop frequency response of
the circuit an open-loop version of the regulator has also been designed and
implemented. Fig. B.3.6 shows the micrograph of the chip which occupies
218.9113.0 m2 . The area of the proposed regulator is 66.5536.8 m2 .
The simulated and measured steady-state (DC), transient, and frequency
response of the regulators are compared to confirm the performance of the
presented structure.

188
 1.05
1
79% improvment
0.95
X: 0.005
Regulated voltage (V) X: 0.0028
Y: 0.9457 Y: 0.9489
0.9

0.85
46%
0.8 improvment

0.75

0.7 With BM measured

0.65 W/o BM measured
X: 0.005
W/o BM simulated Y: 0.6555
0.6 With BM simulated
1 2 3 4 5 6
Load current (mA)

Figure B.4.1: Experimental results of load regulation of the proposed regu-

lator compared to the conventional one.

B.4.1 DC response

The proposed regulator draws 99.04 A from a 1.2 V supply for ILoad =5 mA,
which is 53% more than the conventional regulator due to the use of ad-
ditional bulk amplifier. In particular, EA-a draws 38.6 A, EA-b draws
51.01 A, and reference voltage and biasing circuits draw 9.43 A from the
supply.
Fig. B.4.1 compares two regulators for DC load regulation when the input
voltage Vin =1.2 V is applied. The experimental results are obtained using
an HP 4155A semiconductor parameter analyzer and are compared with
simulation results. As both measurement and simulation results indicate,
the load regulation performance of the bulk modulated regulator is improved

189
by 79% at 0.95 V output regulated voltage.

Vin

W/o Bulk Modulation

With Bulk Modulation
1
Voltage (V)

0.5

0 5 10
time (ms)

Figure B.4.2: Measured DC response of the regulators to dierent input DC

voltage.

Fig. B.4.2 illustrates the DC line regulation of the proposed regulator

and the conventional one. In this measurement, to obtain the DC response
of the regulators the input voltage (Vin ) is varied slowly in the form of a ramp
from 0 to 1.4 V in 7 ms. The presented DC response confirms that using
the proposed bulk modulator technique the regulator works with a lower
supply voltage. This feature can be attributed to the fact that the threshold
voltage of the pass transistor at low input voltages is decreased which in
turn makes the regulator more responsive to lower input voltages. The lower
turn-on voltage can be very useful in low-power applications, for example in
wireless power delivery applications such as biomedical implants and RFID

190
applications (where a regulator is used in the power conversion-chain). The
magnitude of the measured DC line regulation for the proposed regulator is
1.48% while its conventional counterpart shows 2.26% for the input voltage
range of 1.1 to 1.37 V (as shown in Fig. B.4.2).

1.2

0.8
Voltage (V)

Vin

0.6 With bulk modulation

W/o bulk modulation
0.4

0.2

0
0 5 10 15 20
time (s)

Figure B.4.3: Measured start-up transition of the two regulators with and
without bulk modulation technique.

B.4.2 Transient response

One of the important performance metrics for any LDO regulator is its start-
up time which indicates how fast the regulator can provide the regulated
voltage. Fig. B.4.3 compares the start-up time in the presence and absence of
the proposed bulk modulation technique. Note that without bulk modulation
the start-up time is longer than 10 s. The technique improves the start-

191
up by a factor of 15. This improvement can be attributed to the wideband
bulk error amplifier as well as the lowering of the threshold voltage of the
pass transistor. In this experiment a pulse input voltage with raising time
of 5 ns is applied to both regulators at 1 mA of load current. Note that
we are comparing both regulators for the same load current. Therefore, the
load current of 1 mA is chosen since both regulators are able to supply that.
Note that using the load current of 2.88 mA, which as shown in Fig. B.4.1
is the maximum current load delivery of the regulator without the proposed
technique, will make the comparison unfair since the conventional regulator is
operating at its maximum load current capacity while the proposed regulator
is operating at almost half of its current capacity (maximum current delivery
of 5 mA).
Line regulation is another important performance parameter of LDOs.
The simulated line regulation of both regulators are presented in Fig.B.4.4.

1.4

1.3

1.2

1.1
Voltage (V)

0.9

0.8
with BM
0.7 w/o BM
VIN

0 50 100 150
time(ns)

Figure B.4.4: Simulated line regulation.

192
 One may think that bulk modulation of the pass transistor may cause
more sensitivity to supply noise, however, having wide bandwidth error am-
plifier connected to the bulk node of the pass transistor not only does not
worsen the line regulation, but as demonstrated by simulation (Fig. B.4.4)
and verified by measurement results (Fig. B.4.7) it slightly enhances the line
regulation performance.

193
 1.25 with bulk modulation
65 ns w/o bulk modulation
1.2

Regulated voltage (V)

1.15

1.1

1.05 X: 3.6
X: 2.152
Y: 1.003 Y: 1.007

1
X: 0.06314 X: 3.605
Y: 0.9874
0.95 Y: 0.9829

0.9 2.15 s
0 0.5 1 1.5 2 2.5 3 3.5
time (s)

(a)
1.2
trec =1.02 s
Regulated voltage (V)

1.1 X: 60.1
Y: 1.019

1
0.9 trec=20.1 s
0.8
0.7
w/o bulk modulation
0.6 with bulk modultion
0.5
0 10 20 30 40 50 60
Load current (mA)

0 10 20 30 40 50 60
time(s)

(b)

Figure B.4.5: (a) The worst-case recovery time of both regulators measured
from 1 mA to 3.2 mA load transition with the 5 ns transition speed (aver-
aged over 32 signals) and (b) the measured performance of transient load
regulation for load transition speed of 200 ns(averaged over 16 signals).

As discussed earlier the proposed bulk modulation technique improves

the recovery time of the regulator as compared to the conventional regulator.
Fig. B.4.5 presents the experimental results of the recovery time of both pro-
posed and conventional regulators for two load transition speeds of 5 ns and

194
200 ns. Note that for the 5 ns transition speed the proposed regulator with
bulk modulation technique has the recovery time of 65 ns (see Fig. B.4.5(a))
as compared to 2.15 s in the conventional case. The presented waveforms in
part a and b are averaged over 32 and 16 signals, respectively, to reduce the
eect of the unwanted noise. The recovery time of the proposed regulator for
the slower load transition (i.e., 200 ns transition time) is 1.02 s as compared
to 20.1 s for the conventional regulator as shown in Fig. B.4.5(b).

195
 1.2

Regulated voltage (V)

1

0.8

0.6

With bulk modulation

0.4
W/o bulk modulation

1 0.5 0 0.5 1
time(s)

(a)
1.2 W/o bulk modulation
With bulk modulation
1.15
Regulated voltage (V)

1.1

1.05
1

0.95

0.9

0.85

0.8
1 0.5 0 0.5 1
time (s)

(b)
1
Load current (mA)

0.8
0.6
0.4
0.2
0
1 0.5 0 0.5 1
time(s)

(c)

Figure B.4.6: (a) Simulated and (b) measured transient response of regu-
lators, when the load current suddenly changes to 0 mA and (c) simulated
current load change.

Note that the experimental results shown in Fig. B.4.6 (b) contain higher

196
ripples as compared to the simulation results shown in sub-figure (a). The
larger ripples can be attributed to the discrete switch that is used to change
the current load of the regulator. The input and output terminals of the
switch are designed based on the assumption of 50 source and load impedance
and connecting them to a higher impedance (in this case, 1 V/1 mA=1 k)
results in some reflections of voltage (electric field) which can result in a
higher voltage variation (ripple) at the output of the regulator.

B.4.3 Frequency response

Simulation results shown in Fig. B.3.5 verify the position of the zero and
validates the overall voltage gain obtained in (B.3.2). The bandwidth of
the EA-b is designed to be 129 MHz which corresponds to the unity gain
frequency of 2.0 GHz. For the main error amplifier on the other hand a
bandwidth of 1.48 kHz is chosen which corresponds to UGF of 105 MHz.
The EA-a and EA-b have a DC gain of 25.4 and 83.9 dB, respectively.

197
 20
Experimental with BM
0 Experimental w/o BM
Simulation with BM
20 Simulation w/o BM

PSRR (dB) 40 PSRR 41.15 @ 10MHz

60

80
PSRR 57.11 @ 1MHz
100
PSRR 93.56 @ 1kHz
120 4 5 6 7 8 9
10 10 10 10 10 10
frequency (Hz)

Figure B.4.7: Measured and post-layout simulated PSR performance of

regulators while supplying 1 mA of load current.

Vin
Regulator Vout

Rs

P1 P2
ENA- Vector
50 Network Analyzer 50

Figure B.4.8: Measurement setup for PSR experiments.

Fig. B.4.7 illustrates the eect of the parallel EA-b on power supply
rejection (PSR) of the regulator. As expected, the improvement in the line

198
 Table B.1: Performance summary and comparison with the state-of-the-art LDOs.
This work This work
[101] [86] [87] [118] [119] [99] [100]
w/o BM with BM
Year 2010 2010 2010 2011 2012 2013 2013 2013 2013
Technology
0.09 0.18 0.13 0.13 0.18 0.18 0.065 0.13 0.13
(m)
max load
IQ ()A 33 145 35 45 1.33 120 40 0.9 44.03 99.04
Area
normalized to 5.075 126.53 10.20 12.42 65.3 17.95 6.94 1 1
0.00245 mm2
Settling time
N/A 100 0.07 28 4.8 1.172 6 2.15 0.065
(s)
199

Full load:
140 150 2 50 5 100 100 3 5
ILoad max (mA)
-93.6@1 kHz,
-93.8@1 kHz, -
-56@10 MHz,
PSR(dB) -64.3@1 kHz -55@1 MHz N/A -65@1 kHz N/A -58@10 kHz -58.23@1 MHz, 57.11@1 MHz,
-30@30 MHz
-41.15@10 Hz -41.15@10
MHz
Closed-loop
N/A 20 kHz 100 kHz 80-200 kHz 680 kHz 10 MHz N/A 74 MHz 121 MHz
bandwidth
Vout (mV) 94 196 120 250 0.61 100 69 50 50

Worst-case settling time.

Post-layout simulation PSR.

Load regulation from no-load to full-load transition.
regulation is achieved by adding the extra bulk error amplifier, EA-b. To
further investigate the line regulation performance of the proposed circuit
at dierent frequencies, a PSR measurement is conducted. Since the mea-
surement instrument has an input resistance of 50 , as shown in Fig. B.4.8,
the series resistance RS of 1 k is added to ensure that the total current of
both regulators during this measurement is limited to 1 mA. The adverse
eects of this additional resistance are removed using proper calibration and
de-embedding. Note that port 1 (shown in Fig. B.4.8 as P1) is sending an
interference signal with a designated frequency to the input of the regulator
while port 2 measures the regulated (attenuated) signal. To measure the
PSR, we should multiply the scattered parameter s21 by the ratio of the
voltage divider at P2 (i.e., 1050/50=26.44 dB).

As can be seen from the figure, the measured and simulated PSR perfor-
mances of the bulk-modulated regulator confirm that not only the PSR of
the proposed bulk-modulated regulator is not adversely aected, but also it
is slightly better than the conventional regulator. As shown in Table B.1 the
proposed regulator achieves superior PSR. However, this PSR performance
can be attributed to the following reasons. The main reason is the relatively
small full load current of the proposed regulator as compared to the similar
designs which in turn facilitates larger loop-gain and thus better power sup-
ply rejection ratio. Secondly, the wide bandwidth error amplifier EA-b oers

200
a better PSR at higher frequencies. The last reason is due to the careful
layout design of the regulators to make sure that the input voltage paths are
not close to any sensitive nodes of the regulator.

B.5 Conclusions

This work presents a bulk-modulation technique for LDO regulators. Sim-

ulation and measurement results confirm the performance improvements in
load driving capability and recovery time when the technique is applied to a
conventional LDO regulator. The improvement of the stability of the regula-
tor, specially in no load condition is also studied and presented. As compared
to a conventional LDO, the extra error amplifier used to drive the bulk of
the pass transistor draws an additional 51 A current while it improves the
load delivery capability by 79% and the recovery time by more than 10 folds.
Table B.1 presents the performance summary of the proposed LDO and com-
pares it with a conventional LDO regulator without bulk modulation as well
as other state-of-the-art LDOs. It should be noted that the proposed tech-
nique can also be applied to other LDO structures.

201
Appendix C

A monolithic Current-Sensing
Topology for System-on-Chip
Applications

It is important to be able to have a sense of the power consumption of any

telemonitoring systems, specially for those applications that have very lim-
ited power budget. The initiative idea of the following design came from
the need of measure the received power to the telemonitoring system with
minimum cost of power consumption. Due to our limited area for embed-
ded integrated circuit only a monolithic structure would be an option. Since
the nature of the induced current in any telemonitoring system with energy
harvesting technique is an alternative current, we decided to design a mono-
lithic, none-invasive AC current sensor to achieve our goal. In the following

202
sections, the motivation for designing such sensors for broader applications,
as well as, analytical discussion about proposed architecture is presented.
Simulation and measurement results are provided to verify the performance
of the presented current sensor.

C.1 Introduction

Sensing current has a wide range of applications in many integrated circuit

(IC) and system-on-chip (SoC) designs. The applications of current sensing
extend from fault diagnosing in complex ICs [120, 121] to monitoring cur-
rent in switching DC-DC converters [122, 123], to protecting confidentiality
of cryptosystems [124], to testing and analyzing the performance of mixed-
signal and RF circuits [121]. In many such applications it is desirable to use a
non-invasive current-sensing technique, i.e., the sensing circuit virtually does
not disturb the test circuit current. In particular, many present and emerging
applications require a high-bandwidth current sensing circuit. State-of-the-
art monolithic current-sensing schemes have bandwidths in the range of a few
MHz up to 3.4 GHz [120]- [124]. Although a current-sensing technique that
uses exotic material and is based on giant magneto impedance (GMI) eect
with bandwidths up to 30 GHz has been previously discussed (refer to [125]
for an overview of this and other techniques), such techniques require a rela-
tively large foot-print as well as use of exotic materials and are not amenable
to implementation in standard CMOS processes. Given that emerging appli-

203
cations are operating at increasingly higher frequencies, having an ecient
high-bandwidth current-sensing technique suitable for integration in low-cost
CMOS technologies is desirable. In this work, a simple electromotive-force-
based technique that operates over a wide frequency range and requires a
small foot print for non-invasive current-sensing in CMOS ICs and SoCs is
presented.

Figure C.1.1: Top layout view of the proposed current-sensing technique.

The sensing path, formed by spiral-like path using two dierent metal layers
and vias, is encircling the current path.

Bt
r
. . . . . . . . . . . . . . . .
.. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. m
. . . . . . . . B
. . . . . . . . B B
. . . . . . . . . . . . . . . . .
t
. . . . . . . .
. . . . . . . . .
... . . . . . . . .
. . . . . . . . x P
... ... ... ... ... ... ... ... .. .. .. .. .. .. .. .. m
. . . . . . . .
. . . . . . . . . . . . . . . . y
n
x
W

Figure C.1.2: The current sheet is broken into several wires carrying equal
currents Ik

204
C.2 Proposed Technique

The proposed technique is based on Faradays law, where a variable magnetic

field caused by a varying current (I), induces a voltage dierence between
any two points on a neighbouring loop (e.g., V1 and V2 in Fig. C.1.1). The
amplitude of the induced voltage is proportional to the amplitude as well
as the frequency of the varying input current. Thus given the frequency of
the input current, by monitoring the induced voltage the amplitude of the
input current can be deduced. The layout view of the proposed monolithic
current-sensing device is shown in Fig. C.1.1. The metal plate in the centre
carries the current I that is to be measured. The varying current (I) induces
a voltage dierence between two terminals V1 and V2 of the rectangular helix
structure surrounding the central current path. This voltage dierence is
given by:

d B
V1 V2 = " = (C.2.1)
dt

where " is the induced emf, and d B /dt is the rate of change of the total flux.
The total flux, B, is the overall flux passing through all of the individual
loops. Assuming there are total of N individual loops and the passing flux
through each individual loop is B, then B =N B. As shown in Fig. C.1.1,
the horizontal spacing between the top and bottom traces of each loop is
designed to be much shorter than the length of the path carrying the current

205
that is to be measured (i.e., l L). Given that l L, one can make
a simplifying assumption that the magnetic field (B) in the vicinity of the
current path edge is only a function of the distance x from the edge of the
current path (refer to Fig. C.1.2).
To obtain an expression for B(x) let us assume that the current path is formed
by n(2m+1) wires (Fig. C.1.2) each carrying a current of Ik = I/[n(2m+1)].
Since we intend to measure high-frequency current, the skin eect [126] has
to be taken into account. The skin depth (i.e., the depth below the surface
of the conductor at which the current density has fallen to e 1
(about 0.37)
of the surface current density) is given by [126]:

r
2
= (C.2.2)
!

where is the skin depth, and are the electrical conductivity and
the magnetic permeability of the conductor, respectively, and ! is the an-
gular frequency of the current. For the prototype design considered in this
work, this skin depth at 20 GHz is 0.56 m (see Fig. C.2.1). Given that the
thickness of the current path is less than 0.3 m, we can assume that overall
current I is uniformly distributed along the cross section of the path (the
thickness of the path is smaller than the skin depth).

206
 100
Skin effects Depth (m)

10

0.1
100M 1G 10G
frequency(Hz)

Figure C.2.1: Skin eects depth versus frequency of the passing current.

Given the simplifying assumption that B in the vicinity of a long current-

carrying wire is only a function of distance from the wire, i.e., x, the overall
B at point P in the vicinity of the current path (as shown in Fig. C.1.2),
can be calculated by applying the superposition principle. In this context,
one can show that at point P the magnetic field components along the x
direction cancel each other and the overall B is along the y direction and can
be written as:

Ik Pn 1
Bn (x) = 2
[ i=0 x+r(2i+1)
Pn Pm (C.2.3)
2(x+r(2i+1))
+ i=0 j=0 (x+r(2i+1))2 +(r(2j+1))2
]

207
 where r is the radius of each wire and is given by r = W/2n, and m is the
number of virtual wires forming the thickness of the current path (Fig. C.1.2).
m is calculated from 2m + 1 = f loor(l/(2r)).

20

15
(x1012)

10

5
100 150 200 250 300 350 400 450
n
Figure C.2.2: Calculated (n) for dierent values of n, in 0.13 m CMOS
process.

Furthermore, = 0 r where 0 is the magnetic permeability of the

vacuum and r is the relative magnetic permeability of the medium (for
silicon dioxide r
= 1). In (C.2.3), the first term is the magnetic field caused
by the middle row of wires, and the second term is the magnetic field caused
by the rest of the wires. Therefore, the magnetic flux B can be written as:

208
 w l l
B = B ds = Bn (x)dxdy = w Bn (x)dx (C.2.4)
0 0 0
S

where S is the closed surface of the loop through which B(x) is passing.
In the prototype integrated current sensor the dimensions of each loop are
w = 700 nm and l = 400 nm (Fig. C.1.1). The induced electromotive force
is:

2 RT
"(t) = [Ii (n)] f cos(2f t) (C.2.5)
Rpath

where Ip is the peak of the input current I = Ip sin(2f t) and (n) =

w
2N l 0 Bn (x)dx/I. Taking into account that in practice the two sides of the
sensing path are typically terminated to an impedance (in this work, the ter-
mination impedance on each side of the sensing path is the input impedance
of the measurement instrument, i.e., oscilloscope, which is RT = 50 ), the
sensing system can be modelled with the equivalent circuit shown in the
inset of Fig. C.1.1. Note that this model is based on the fact that ideally
the induced emf generated across the sensing path is independent of the ter-
mination impedance. Therefore, one can model the induced voltage across
sensing path with an ideal current source in series with the equivalent lumped
resistance of the sensing path, i.e., Rpath . This induced current source can
be intuitively justified since the induction path can be considered as the

209
secondary winding of a current transformer, where the input (i.e., primary)
winding has one turn. Note that voltage across this fictitious current source
violates the kirchho voltage law as the Kirchho voltage law is not valid for
non-conservative electric field. Therefore, the voltage dierence V1 V2 can
be written as: V1 V2 = (2 RT /Rpath ) emf.
The trans-resistance gain of the overall current sensor can be derived as:

|"| 2 50
= (n) f (C.2.6)
|I| Rpath

Fig. C.2.2 shows the results of calculating (n) for dierent values of n in
0.13 m CMOS process. We expect that by increasing the number of divisions
(n) we will get closer to the actual answer. This assumption is supported by
the results shown in Fig. C.2.2; As shown, for n > 300, (n) ! 8 10 12
.
In this case, assuming n = 450, and for l = 0.2624 m and W = 3 m we
will have (450) = 7.99 10 12
. Furthermore, given the geometry of the
design and the fact that in this proto-type design there are 23 series sets of
6 parallel vias and the resistance of those vias account for most of the path
resistance, we can calculate the overall resistance of the path as follows:

Rpath
= Rvias = (Rvia /6) 23 (C.2.7)

Note that in 0.13 CMOS process Rvia = 1.799 . Given that from
(C.2.7), Rpath
= 6.90 .

210
 35

30
Induced voltage (mV)

25

20

15

10

0
0 1 2 3 4 5 6 7
I (mA)

Figure C.2.3: The measured sensed voltage versus amplitude of current. The
frequency of the current in this experiment is 7 GHz.

Figure C.2.4: Measured trans-resistance

211 gain versus input current frequency
as well as calculated gain obtained from (C.2.6) and simulation results using
Momentum
 As (C.2.6) shows, contrary to other methods of sensing current, by in-
creasing the frequency of the sensed current I the magnitude of the trans-
resistance gain increases (Fig.C.2.4). This is the main advantage of this
method as compared to previously reported techniques. In addition, the
sensing of the current is non-invasive and is done passively with no extra
power consumption, thus, makes the proposed approach suitable for ultra low
power applications. Fig.C.2.4, compares the analytical expression of trans-
resistance gain (V1 V2 )/I stated in (C.2.6) with simulated and measured
results in dierent frequencies. As expected, by increasing the frequency, the
trans-resistance gain increases up toll a frequency at which the parasitic ca-
pacitance shorts the current path and sensing path together. Note that the
measured trans-resistance has less bandwidth than the simulated one, which
can be attributed to the limited bandwidth of the measurement instruments
used in this experiment.
Fig. C.2.3 presents the measured induced voltage V1 V2 versus amplitude
of the current. The red curve represents the best linear fit of the measured
results. As expected from (C.2.5) and is verified by measured results there
is a linear relation between sensed voltage and the amplitude of the current.

C.3 Conclusion

A simple monolithic non-invasive passive current-sensing method for ultra-

low-power applications is presented. A detailed analytical treatment of the

212
technique is provided. The method can be used to sense varying currents up
to several GHz (8 GHz in the presented prototype). The measured results
are inline with the analytical and simulation results.

213