Colour Television Chassis

QFU1.2E
LA

Contents Page
1.Revision List 2
2.Technical Specs, Diversity, and Connections 2
3.Precautions, Notes, and Abbreviation List 7
4.Mechanical Instructions 11
5.Service Modes, Error Codes, and Fault Finding 20
6.Alignments 40
7.Circuit Descriptions 45
8.IC Data Sheets 47
9.Block Diagrams 49
10.
Circuit Diagrams and PWB Layouts Drawing PWB
310431366124 SSB 59 99-100
310431366185 SSB 101 141-142
310431366186 SSB 143 183-184
C 310431366652 Amplifier panel 185
272217190763, 272217190764, 272217190766
Keyboard Control Module 187
282206502664,
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 EN 2 1. QFU1.2E LA Revision List

1. Revision List
Manual xxxx xxx xxxx.0 Manual xxxx xxx xxxx.3
First release. Chapter 2: Table 2-1 updated (added CTNs).
Chapter 6: added white tone values; see section 6.3.1.
Manual xxxx xxx xxxx.1
Chapter 2: Table 2-1 updated (added CTNs). Manual xxxx xxx xxxx.4
Chapter 4: added additional Ambilight unit handling info; Chapter 2: Table 2-1 updated (added CTNs).
see section 4.3.2. Chapter 4: updated and added cable wiring (added CTNs).
Chapter 6: added white tone values (added CTNs).
Manual xxxx xxx xxxx.2 Chapter 9: added wiring diagrams (added CTNs).
Chapter 2: Table 2-1 updated (added CTNs). Chapter 10: added schematics (AL).
Chapter 11: added styling sheets (added CTNs).

2. Technical Specs, Diversity, and Connections

Index of this chapter:
2.1 Technical Specifications
2.2 Directions for Use
2.3 Connections 2.1 Technical Specifications
2.4 Chassis Overview For on-line product support please use the CTN links in Table
2-1. Here is product information available, as well as getting
Notes: started, user manuals, frequently asked questions and
Figures can deviate due to the different set executions. software & drivers.
Specifications are indicative (subject to change).

Table 2-1 Described Model Numbers and Diversity

2 4 7 9 10 11
Schem
Mechanics Descr. Block Diagrams atics Styling
Light Sensor, IR/LED Module)
itecture

odule)
dule

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 Technical Specs, Diversity, and Connections QFU1.2E LA 2. EN 3

2 4 7 9 10 11
Schem
Mechanics Descr. Block Diagrams atics Styling

(Wireless LAN USB, Light Sensor, IR/LED Module)

General Power Architecture

(Keyboard Control Module)

Amplifier control module
Connection Overview

Assembly Removal

(Sensor Module)
Control & Clock
Wiring Diagram
Wire Dressing

Power Supply
Power Supply

Supply lines

(AmbiLight)
Audio
Video

Sheet
SSB
I2C

CTN
42PFL7108K/12 2.3 4-4 4.3 7.2 7.3 - 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.11 11.2
10.12
42PFL7108S/12 2.3 4-4 4.3 7.2 7.3 - 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.11 11.2
10.12
42PFL7108S/60 2.3 4-4 4.3 7.2 7.3 - 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.11 11.2
10.12
42PFL7108T/12 2.3 4-4 4.3 7.2 7.3 - 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.11 11.2
10.12
46PDL8908S/12 2.3 4-7 4.3 7.2 7.3 - 9.9 9.9 - - 9.10 - 10.1 - 10.5 10.8 10.9 10.12 11.4
46PDL8908S/60 2.3 4-7 4.3 7.2 7.3 - 9.9 9.9 - - 9.10 - 10.1 - 10.5 10.8 10.9 10.12 11.4
46PFL8008K/12 2.3 4-5 4.3 7.2 7.3 - 9.9 9.9 - - 9.10 - 10.1 - 10.5 10.7 10.9 10.15 11.3
46PFL8008S/12 2.3 4-5 4.3 7.2 7.3 - 9.9 9.9 - - 9.10 - 10.1 - 10.5 10.7 10.9 10.15 11.3
46PFL8008S/60 2.3 4-5 4.3 7.2 7.3 - 9.9 9.9 - - 9.10 - 10.1 - 10.5 10.7 10.9 10.15 11.3
46PFL8008S/98 2.3 4-5 4.3 7.2 7.3 - 9.9 9.9 - - 9.10 - 10.1 - 10.5 10.7 10.9 10.15 11.3
47PFL6008H/12 2.3 4-3 4.3 7.2 7.3 9.2 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.15 11.1
47PFL6008K/12 2.3 4-3 4.3 7.2 7.3 9.2 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.15 11.1
47PFL6008S/12 2.3 4-3 4.3 7.2 7.3 9.2 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.15 11.1
47PFL6008S/60 2.3 4-3 4.3 7.2 7.3 9.2 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.15 11.1
47PFL6158K/12 2.3 4-3 4.3 7.2 7.3 9.2 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.15 11.1
47PFL6158S/12 2.3 4-3 4.3 7.2 7.3 9.2 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.15 11.1
47PFL6188K/12 2.3 4-3 4.3 7.2 7.3 9.2 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.15 11.1
47PFL6188S/12 2.3 4-3 4.3 7.2 7.3 9.2 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.15 11.1
47PFL6198K/12 2.3 4-3 4.3 7.2 7.3 9.2 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.15 11.1
47PFL6678K/12 2.3 4-3 4.3 7.2 7.3 9.2 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.15 11.1
47PFL6678S/12 2.3 4-3 4.3 7.2 7.3 - 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.15 11.1
47PFL7008H/12 2.3 4-4 4.3 7.2 7.3 - 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.7 10.9 10.12 11.2
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 EN 4 2. QFU1.2E LA Technical Specs, Diversity, and Connections

2 4 7 9 10 11
Schem
Mechanics Descr. Block Diagrams atics Styling

(Wireless LAN USB, Light Sensor, IR/LED Module)

General Power Architecture

(Keyboard Control Module)

Amplifier control module
Connection Overview

Assembly Removal

(Sensor Module)
Control & Clock
Wiring Diagram
Wire Dressing

Power Supply
Power Supply

Supply lines

(AmbiLight)
Audio
Video

Sheet
SSB
I2C

CTN
55PFL6188S/12 2.3 4-3 4.3 7.2 7.3 9.3 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.8 10.9 10.16 11.5
55PFL6198K/12 2.3 4-3 4.3 7.2 7.3 9.3 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.8 10.9 10.16 11.5
55PFL6678K/12 2.3 4-3 4.3 7.2 7.3 9.3 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.8 10.9 10.16 11.5
55PFL6678S/12 2.3 4-3 4.3 7.2 7.3 9.3 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.8 10.9 10.16 11.5
55PFL7008H/12 2.3 4-8 4.3 7.2 7.3 9.4 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.8 10.9 10.13 11.6
10.10
10.11
55PFL7008K/12 2.3 4-8 4.3 7.2 7.3 9.4 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.8 10.9 10.13 11.6
10.10
10.11
55PFL7008S/12 2.3 4-8 4.3 7.2 7.3 9.4 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.8 10.9 10.13 11.6
10.10
10.11
55PFL7008S/60 2.3 4-8 4.3 7.2 7.3 9.4 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.8 10.9 10.13 11.6
10.10
10.11
55PFL7108H/12 2.3 4-8 4.3 7.2 7.3 9.4 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.8 10.9 10.13 11.6
10.10
10.11
55PFL7108K/12 2.3 4-8 4.3 7.2 7.3 9.4 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.8 10.9 10.13 11.6
10.10
10.11
55PFL7108S/12 2.3 4-8 4.3 7.2 7.3 9.4 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.8 10.9 10.13 11.6
10.10
10.11
55PFL7108S/60 2.3 4-8 4.3 7.2 7.3 9.4 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.8 10.9 10.13 11.6
10.10
10.11
55PFL8008K/12 2.3
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7.3 - 9.9 9.9 - - 9.10 - 10.2 - 10.5 10.8 10.9 10.15 11.7
 Technical Specs, Diversity, and Connections QFU1.2E LA 2. EN 5

2.3 Connections

Connections
Side Rear
HDMI 4 HDMI 1 HDMI 2 HDMI 3 SCART NETWORK

ARC ARC ARC ARC

1 2 3 4

USB USB USB

Y Pb Pr - L R AUDIO OUT AUDIO IN ANTENNA SATELLITE
OPTICAL L/R

5 6 7 8 9 11
(optional)
COMMON INTERFACE

10

19370_062_130201.eps
130404

Figure 2-1 Connection overview

Note: The following connector colour abbreviations are used 20 - Ground Gnd H
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy=
Grey, Rd= Red, Wh= White, Ye= Yellow. 3 - Video RGB - In, CVBS - In/Out, Audio - In/Out
20 2
2.3.1 Connections
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 EN 6 2. QFU1.2E LA Technical Specs, Diversity, and Connections

4 - RJ45: Ethernet 1 - +5V k

2 - Data (-) jk
3 - Data (+) jk
4 - Ground Gnd H

10000_025_090121.eps 6 - Cinch: Video YPbPr - In, Audio - In

120320 Gn - Video Y 1 VPP / 75 ohm jq
Bu - Video Pb 0.7 VPP / 75 ohm jq
Figure 2-4 Ethernet connector
Rd - Video Pr 0.7 VPP / 75 ohm jq
Rd - Audio - R 0.5 VRMS / 10 kohm jq
1 - TD+ Transmit signal k Wh - Audio - L 0.5 VRMS / 10 kohm jq
2 - TD- Transmit signal k
3 - RD+ Receive signal j
7 - Cinch: S/PDIF - Out
4 - CT Centre Tap: DC level fixation
Bk - Coaxial 0.4 - 0.6VPP / 75 ohm kq
5 - CT Centre Tap: DC level fixation
6 - RD- Receive signal j
7 - GND Gnd H 8 - Cinch: Audio - In (VGA/DVI)
8 - GND Gnd H Rd - Audio R 0.5 VRMS / 10 kohm jq
Wh - Audio L 0.5 VRMS / 10 kohm jq
5 - USB2.0
9 - Aerial - In
- - IEC-type (EU) Coax, 75 ohm D
1 2 3 4
10000_022_090121.eps 10 - Common Interface
090121
68p - See Figure 10-1-35 B06I, CI conditional access jk
Figure 2-5 USB (type A)
11 - SAT - In (optional)
- - F-type Coax, 75 ohm D

2.4 Chassis Overview

Refer to chapter 9. Block Diagrams for PWB/CBA locations.

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 Precautions, Notes, and Abbreviation List
3. Precautions, Notes, and Abbreviation List
Index of this chapter:
3.1 Safety Instructions
3.2 Warnings
3.3 Notes
3.4 Abbreviation List
3.1 Safety Instructions
Safety regulations require the following during a repair:
Connect the set to the Mains/AC Power via an isolation
transformer (> 800 VA).
Replace safety components, indicated by the symbol h,
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard.
Safety regulations require that after a repair, the set must be
returned in its original condition. Pay in particular attention to
the following points:
Route the wire trees correctly and fix them with the
mounted cable clamps.
Check the insulation of the Mains/AC Power lead for
external damage.
Check the strain relief of the Mains/AC Power cord for
proper function.
Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the on position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading
should be between 4.5 M and 12 M.
4. Switch off the set, and remove the wire between the
two pins of the Mains/AC Power plug.
Check the cabinet for defects, to prevent touching of any
inner parts by the customer.
3.2 Warnings
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QFU1.2E LA 3. EN 7
3.3.2 Schematic Notes
All resistor values are in ohms, and the value multiplier is
often used to indicate the decimal point location (e.g. 2K2
indicates 2.2 k).
Resistor values with no multiplier may be indicated with
either an E or an R (e.g. 220E or 220R indicates 220 ).
All capacitor values are given in micro-farads ( 10-6),
nano-farads (n 10-9), or pico-farads (p 10-12).
Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).
An asterisk (*) indicates component usage varies. Refer
to the diversity tables for the correct values.
The correct component values are listed on the Philips
Spare Parts Web Portal.
3.3.3 Spare Parts
For the latest spare part overview, consult your Philips Spare
Part web portal.
3.3.4 BGA (Ball Grid Array) ICs
Introduction
For more information on how to handle BGA devices, visit this
URL: http://www.atyourservice-magazine.com. Select
Magazine, then go to Repair downloads. Here you will find
Information on how to deal with BGA-ICs.
BGA Temperature Profiles
For BGA-ICs, you must use the correct temperature-profile.
Where applicable and available, this profile is added to the IC
Data Sheet information section in this manual.
3.3.5 Lead-free Soldering
Due to lead-free technology some rules have to be respected
by the workshop during a repair:
Use only lead-free soldering tin. If lead-free solder paste is
required, please contact the manufacturer of your soldering
 EN 8 3. QFU1.2E LA Precautions, Notes, and Abbreviation List

result in sets which have the same CTN (Commercial Type 6 = play 16 : 9 format, 12 = play 4 : 3
Number; e.g. 28PW9515/12) but which have a different B.O.M. format
number. AARA Automatic Aspect Ratio Adaptation:
By looking at the third digit of the serial number, one can algorithm that adapts aspect ratio to
identify which B.O.M. is used for the TV set he is working with. remove horizontal black bars; keeps
If the third digit of the serial number contains the number 1 the original aspect ratio
(example: AG1B033500001), then the TV set has been ACI Automatic Channel Installation:
manufactured according to B.O.M. number 1. If the third digit is algorithm that installs TV channels
a 2 (example: AG2B0335000001), then the set has been directly from a cable network by
produced according to B.O.M. no. 2. This is important for means of a predefined TXT page
ordering the correct spare parts! ADC Analogue to Digital Converter
For the third digit, the numbers 1...9 and the characters A...Z AFC Automatic Frequency Control: control
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be signal used to tune to the correct
indicated by the third digit of the serial number. frequency
AGC Automatic Gain Control: algorithm that
Identification: The bottom line of a type plate gives a 14-digit controls the video input of the feature
serial number. Digits 1 and 2 refer to the production centre (e.g. box
SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M. AM Amplitude Modulation
code, digit 4 refers to the Service version change code, digits 5 AP Asia Pacific
and 6 refer to the production year, and digits 7 and 8 refer to AR Aspect Ratio: 4 by 3 or 16 by 9
production week (in example below it is 2010 week 10 / 2010 ASF Auto Screen Fit: algorithm that adapts
week 17). The 6 last digits contain the serial number. aspect ratio to remove horizontal black
bars without discarding video
information
ATSC Advanced Television Systems
Committee, the digital TV standard in
the USA
ATV See Auto TV
Auto TV A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way
AV External Audio Video
AVC Audio Video Controller
AVIP Audio Video Input Processor
B/G Monochrome TV system. Sound
carrier distance is 5.5 MHz
BDS Business Display Solutions (iTV)
BLR Board-Level Repair
BTSC Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
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countries
 Precautions, Notes, and Abbreviation List QFU1.2E LA 3. EN 9

DNR Digital Noise Reduction: noise The SDI signal is self-synchronizing,

reduction feature of the set uses 8 bit or 10 bit data words, and has
DRAM Dynamic RAM a maximum data rate of 270 Mbit/s,
DRM Digital Rights Management with a minimum bandwidth of 135
DSP Digital Signal Processing MHz.
DST Dealer Service Tool: special remote iTV Institutional TeleVision; TV sets for
control designed for service hotels, hospitals etc.
technicians LS Last Status; The settings last chosen
DTCP Digital Transmission Content by the customer and read and stored
Protection; A protocol for protecting in RAM or in the NVM. They are called
digital audio/video content that is at start-up of the set to configure it
traversing a high speed serial bus, according to the customer's
such as IEEE-1394 preferences
DVB-C Digital Video Broadcast - Cable LATAM Latin America
DVB-T Digital Video Broadcast - Terrestrial LCD Liquid Crystal Display
DVD Digital Versatile Disc LED Light Emitting Diode
DVI(-d) Digital Visual Interface (d= digital only) L/L' Monochrome TV system. Sound
E-DDC Enhanced Display Data Channel carrier distance is 6.5 MHz. L' is Band
(VESA standard for communication I, L is all bands except for Band I
channel and display). Using E-DDC, LPL LG.Philips LCD (supplier)
the video source can read the EDID LS Loudspeaker
information form the display. LVDS Low Voltage Differential Signalling
EDID Extended Display Identification Data Mbps Mega bits per second
(VESA standard) M/N Monochrome TV system. Sound
EEPROM Electrically Erasable and carrier distance is 4.5 MHz
Programmable Read Only Memory MHEG Part of a set of international standards
EMI Electro Magnetic Interference related to the presentation of
EPG Electronic Program Guide multimedia information, standardised
EPLD Erasable Programmable Logic Device by the Multimedia and Hypermedia
EU Europe Experts Group. It is commonly used as
EXT EXTernal (source), entering the set by a language to describe interactive
SCART or by cinches (jacks) television services
FDS Full Dual Screen (same as FDW) MIPS Microprocessor without Interlocked
FDW Full Dual Window (same as FDS) Pipeline-Stages; A RISC-based
FLASH FLASH memory microprocessor
FM Field Memory or Frequency MOP Matrix Output Processor
Modulation MOSFET Metal Oxide Silicon Field Effect
FPGA Field-Programmable Gate Array Transistor, switching device
FTV Flat TeleVision MPEG Motion Pictures Experts Group
Gb/s Giga bits per second MPIF Multi Platform InterFace
G-TXT Green TeleteXT MUTE MUTE Line
H H_sync to the module MTV Mainstream TV: TV-mode with
HD High Definition Consumer TV features enabled (iTV)
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HDD Hard Disk Drive NC Not Connected
 EN 10 3. QFU1.2E LA Precautions, Notes, and Abbreviation List

PDP Plasma Display Panel SWAN Spatial temporal Weighted Averaging

PFC Power Factor Corrector (or Pre- Noise reduction
conditioner) SXGA 1280 1024
PIP Picture In Picture TFT Thin Film Transistor
PLL Phase Locked Loop. Used for e.g. THD Total Harmonic Distortion
FST tuning systems. The customer TMDS Transmission Minimized Differential
can give directly the desired frequency Signalling
POD Point Of Deployment: a removable TS Transport Stream
CAM module, implementing the CA TXT TeleteXT
system for a host (e.g. a TV-set) TXT-DW Dual Window with TeleteXT
POR Power On Reset, signal to reset the uP UI User Interface
PSDL Power Supply for Direct view LED uP Microprocessor
backlight with 2D-dimming UXGA 1600 1200 (4:3)
PSL Power Supply with integrated LED V V-sync to the module
drivers VESA Video Electronics Standards
PSLS Power Supply with integrated LED Association
drivers with added Scanning VGA 640 480 (4:3)
functionality VL Variable Level out: processed audio
PTC Positive Temperature Coefficient, output toward external amplifier
non-linear resistor VSB Vestigial Side Band; modulation
PWB Printed Wiring Board (same as PCB) method
PWM Pulse Width Modulation WYSIWYR What You See Is What You Record:
QRC Quasi Resonant Converter record selection that follows main
QTNR Quality Temporal Noise Reduction picture and sound
QVCP Quality Video Composition Processor WXGA 1280 768 (15:9)
RAM Random Access Memory XTAL Quartz crystal
RGB Red, Green, and Blue. The primary XGA 1024 768 (4:3)
color signals for TV. By mixing levels Y Luminance signal
of R, G, and B, all colors (Y/C) are Y/C Luminance (Y) and Chrominance (C)
reproduced. signal
RC Remote Control YPbPr Component video. Luminance and
RC5 / RC6 Signal protocol from the remote scaled color difference signals (B-Y
control receiver and R-Y)
RESET RESET signal YUV Component video
ROM Read Only Memory
RSDS Reduced Swing Differential Signalling
data interface
R-TXT Red TeleteXT
SAM Service Alignment Mode
S/C Short Circuit
SCART Syndicat des Constructeurs
d'Appareils Radiorcepteurs et
Tlviseurs
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SCL Serial Clock I2C
 Mechanical Instructions QFU1.2E LA 4. EN 11

4. Mechanical Instructions
Index of this chapter:
4.1 Cable Dressing-
4.2 Service Positions
4.3 Assy/Panel Removal
4.4 Set Re-assembly
Notes:
Figures below can deviate slightly from the actual situation,
due to the different set executions.

4.1 Cable Dressing-

Figure 4-1 Cable dressing 40" 8000 series

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 EN 12 4. QFU1.2E LA Mechanical Instructions

l e
a i lab
av
ot
N
19210_104_120516.eps
120516

Figure 4-3 Cable dressing 42" - 47" - 55" - 60" 6000 series

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 Mechanical Instructions QFU1.2E LA 4. EN 13

Figure 4-5 Cable dressing 46" 8000 series

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 EN 14 4. QFU1.2E LA Mechanical Instructions

l e
a i lab
av
ot
N
19210_104_120516.eps
120516

Figure 4-7 Cable dressing 46" - 55" 8000 Design series

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 Mechanical Instructions QFU1.2E LA 4. EN 15

Figure 4-9 Cable dressing 55" 8000 series

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 EN 16 4. QFU1.2E LA Mechanical Instructions

19374_027_140110.eps
140110

Figure 4-11 Cable dressing 60" 8000 series

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 Mechanical Instructions QFU1.2E LA 4. EN 17

19374_029_140110.eps
140110

Figure 4-13 Cable dressing 65" 9000 series - Back cover

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 EN 18 4. QFU1.2E LA Mechanical Instructions

19374_031_140110.eps
140110

Figure 4-15 Cable dressing 84" 9000 series - Back cover

4.2 Service Positions Caution: Failure to follow these guidelines can seriously
For easy servicing of a TV set, the set should be put face down damage the display!
on a soft flat surface, foam buffers or other specific workshop Ensure that ESD safe measures are taken.
tools. Ensure that a stable situation is created to perform
measurements and alignments. When using foam bars take 4.3 Assy/Panel Removal
care that these always support the cabinet and never only the
display.
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 Mechanical Instructions QFU1.2E LA 4. EN 19

Click!

3 3

19370_081_130208.eps
130208 LVDS flat foil
Figure 4-17 Rear cover removal Ambilight models -2-

4.3.2 Ambilight units in Rear Cover Click!

The Ambilight units are affixed in the rear cover and will self-
destruct upon removal.
19222_001_120626.eps
120626
Attention: it is of the utmost importance to remove all remains
of any adhesive that might be left on the inside of the rear Figure 4-19 SSB LVDS connector catches (optional) -2-
cover.
4.4 Set Re-assembly
The new units come with double-sided adhesive tape. Ensure To re-assemble the whole set, execute all processes in reverse
a correct mounting to avoid uneven light emission of the units. order.

4.3.3 SSB Notes:

Refer to Figure 4-18 and Figure 4-19 for details.
Some SSBs have a dedicated LVDS connector, requiring
pressing two catches as indicated in the figure, before
removing the LVDS cable.
While re-assembling, make sure that all cables are placed
and connected in their original position.
Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.

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 EN 20 5. QFU1.2E LA Service Modes, Error Codes, and Fault Finding

5. Service Modes, Error Codes, and Fault Finding

Index of this chapter: Digital SDM: use the RC-transmitter and key in the code
5.1 Test Points 062593, directly followed by the MENU (or "HOME")
5.2 Service Modes button.
5.3 Start-up Note: It is possible that, together with the SDM, the main
5.4 Service Tools menu will appear. To switch it off, push the MENU (or
5.5 Error Codes "HOME") button again.
5.6 The Blinking LED Procedure
5.7 Protections
5.8 Fault Finding and Repair Tips
5.9 Software Upgrading

5.1 Test Points

As most signals are digital, it will be difficult to measure
waveforms with a standard oscilloscope. However, several key
ICs are capable of generating test patterns, which can be
controlled via ComPair. In this way it is possible to determine
which part is defective.
SDM
Perform measurements under the following conditions:
Service Default Mode.
Video: Colour bar signal.
Audio: 3 kHz left, 1 kHz right.

5.2 Service Modes

Service Default mode (SDM) and Service Alignment Mode
(SAM) offers several features for the service technician, while 19370_061_130201.eps
the Customer Service Mode (CSM) is used for communication 130507
between the call centre and the customer.
Figure 5-1 Service mode pad
Note: For the new model range, a new remote control (RC) is
used with some renamed buttons. This has an impact on the After activating this mode, SDM will appear in the upper right
activation of the Service modes. For instance the old MENU corner of the screen (when a picture is available).
button is now called HOME (or is indicated by a house icon).
How to Exit SDM
5.2.1 Service Default Mode (SDM) Use one of the following methods:
Switch the set to STANDBY via the RC-transmitter.
Via a standard customer RC-transmitter: key in 00-
Purpose
sequence.
To create a pre-defined setting, to get the same
measurement results as given in this manual.
To override SW protections detected by the standby 5.2.2 Service Alignment Mode (SAM)
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processor and make the TV start up to the step just before
 Service Modes, Error Codes, and Fault Finding
be re-written to NVM. The update can be done via the
NVM editor available in SAM.
Operation hours. Displays the accumulated total of
operation hours (not the standby hours). Every time the TV
is switched on/off, 0.5 hours is added to this number.
Errors (followed by maximum 10 errors). The most recent
error is displayed at the upper left (for an error explanation
see section 5.5 Error Codes).
Reset Error Buffer. When cursor right (or OK button)
pressed here, followed by the OK button, the error buffer
is reset.
Alignments. This will activate the ALIGNMENTS sub-
menu. See Chapter 6. Alignments.
Options numbers. Extra features for Service. For more
info regarding option codes, see chapter 6. Alignments.
Note that if the option code numbers are changed, these
have to be confirmed with pressing the OK button before
the options are stored, otherwise changes will be lost.
Initialise NVM. The moment the processor recognizes a
corrupted NVM, the initialise NVM line will be highlighted.
Now, two things can be done (dependent of the service
instructions at that moment):
Save the content of the NVM via ComPair for
development analysis, before initializing. This will give
the service department an extra possibility for
diagnosis (e.g. when Development asks for this).
Initialise the NVM.
Note: When the NVM is corrupted, or replaced, there is a high
possibility that no picture appears because the display code is
not correct. So, before initializing the NVM via the SAM, a
picture is necessary and therefore the correct display option
has to be entered. Refer to Chapter 6. Alignments for details.
To adapt this option, its advised to use ComPair (the correct
values for the options can be found in Chapter 6. Alignments)
or a method via a standard RC (described below).
Changing the display option via a standard RC: Key in the
code 062598 directly followed by the MENU (or "HOME")
button and XXX (where XXX is the 3 digit decimal display
code as mentioned on the sticker in the set). Make sure to key
in all three digits, also the leading zeros. If the above action is
successful, the front LED will go out as an indication that the
RC sequence wassearch
correct. After the display option is changed
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QFU1.2E LA 5. EN 21
Test settings. For development purposes only.
RF4CE pairing tables. Clear paired remote control. Re-
pairing (coldboot of platform possibly needed) can be done
by pressing the red/blue hot keys simultaneously for a few
seconds.(be sure the distance between the remote control
and TV set RF4CE receiver is less then 30cm). Message
like Pairing successful, confirms the match-make.
Development 1 file versions. Not useful for Service
purposes, this information is mainly used by the
development department.
Development 2 file versions. Not useful for Service
purposes, this information is mainly used by the
development department.
Upload to USB. To upload several settings from the TV to
an USB stick, which is connected to the SSB. The items are
Personal settings, Option codes, Alignments,
Identification data (includes the set type and prod code +
all 12NC like SSB, display, boards), History list. The All
item supports the upload of all several items at once.
A directory repair\ will be created in the root of the
USB stick.
To upload the settings, select each item separately, press
cursor right (or the OK button), confirm with OK and
wait until the message Done appears. In case the
download to the USB stick was not successful, Failure will
be displayed. In this case, check if the USB stick is
connected properly and if the directory repair is present in
the root of the USB stick. Now the settings are stored onto
the USB stick and can be used to download into another TV
or other SSB. Uploading is of course only possible if the
software is running and preferably a picture is available.
This method is created to be able to save the customers
TV settings and to store them into another SSB.
Important remark : to upload the channel list, select
Home => Setup => TV settings => General settings
=> Channel list copy => Copy to USB.The procedure is
also described in the (electronic) user manual.
Download from USB. To download several settings from
the USB stick to the TV, same way of working needs to be
followed as described in Upload to USB. The All item
supports to download all several items at once.
Important remark : to download the channel list, select
Home => Setup => TV settings => General settings
=> Channel list copy => Copy to TV. The procedure is
 EN 22 5. QFU1.2E LA Service Modes, Error Codes, and Fault Finding
5.2.3 Customer Service Mode (CSM)
Purpose
When a customer is having problems with his TV-set, he can
call his dealer or the Customer Helpdesk. The service
technician can then ask the customer to activate the CSM, in
order to identify the status of the set. Now, the service
technician can judge the severity of the complaint. In many
cases, he can advise the customer how to solve the problem,
or he can decide if it is necessary to visit the customer.
The CSM is a read only mode, therefore modifications in this
mode are not possible.
Provided CSM is activated, every menu from CSM can be used
as check for the back end chain video.So for all CSM content
displayed, it could be determined that the back end video chain
is working.
When CSM is activated and there is a USB stick connected to
the TV set, the software will dump the CSM content to the USB
stick.The file (CSM_model number_serial number.xml) will be
saved in the root of the USB stick. This info can be handy if no
information is displayed.
Additional in CSM mode (with USB stick connected), pressing
OK will create an extended CSM dump file on the USB stick.
This file (Extended_CSM_model number_serial number.xml)
contains:
The normal CSM dump information,
All items (from SAM load to USB, but in readable format),
Operating hours,
Error codes,
SW/HW event logs.
To have fast feedback from the field, a flashdump can be
requested by development. When in CSM, push the red
button and key in serial digits 2679 (same keys to form the
word COPY with a cellphone). A file Dump_model
number_serial number.bin will be written on the connected
USB device. This can take 1/2 minute, depending on the
quantity of data that needs to be dumped.
Attention: for every dump
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search data tranfers to USB,
Production code. Displays the production code (the serial
number) of the TV. Note that if an NVM is replaced or is
initialized after corruption, the production code content has
to be re-written to NVM. The update can be done via the
NVM editor available in SAM.
Installed date. Indicates the date of the first installation of
the TV. This date is acquired by time extraction.
Options 1. Displays the option codes numbers of option
group 1 as set in SAM (Service Alignment Mode).
Options 2. Displays the option codes numbers of option
group 2 as set in SAM (Service Alignment Mode).
12NC SSB. Gives an identification of the SSB as stored in
NVM. Note that if an NVM is replaced or is initialized after
corruption, this identification number has to be re-written to
NVM. The update can be done via the NVM editor available
in SAM. This identification number is the 12nc number of
the SSB.
12NC display. Shows the 12NC of the display. Note that if
an NVM is replaced or is initialized after corruption, this
identification number has to be re-written to NVM. The
update can be done via the NVM editor available in SAM.
12NC supply. Shows the 12NC of the power supply. Note
that if an NVM is replaced or is initialized after corruption,
this identification number has to be re-written to NVM. The
update can be done via the NVM editor available in SAM.
12NC sensor board. Shows the 12NC of the sensor
board.
Software versions
Current main software. Displays the build-in main
software version. In case of field problems related to
software, upgrade can be done. As this software is
consumer upgradeable, it will also be published on the
Internet.
Example: QF2xx-1.2.3.4
Standby software. Displays the build-in standby
processor software version. Upgrading this software will be
possible via USB (see section 5.9 Software Upgrading).
Example: STDBY_77.3.11.16
e-UM version. Displays the electronic user manual SW-
version (12NC version number). Most significant number
here is the last digit.
Strings database version. Reflects the latest embedded
 Service Modes, Error Codes, and Fault Finding QFU1.2E LA 5. EN 23

How to Exit CSM 5.3 Start-up

Press MENU (or "HOME") / Back key on the RC-transmitter. As described, the start-up diagrams below, documents which
supplies are present at any certain moment.

Off
Mains Mains
off on

- WakeUp requested WakeUp

- Acquisition needed requested

St by Semi
- stby requested and Active
no data Acquisition St by St by
required requested

GoToProtection
(triggered during startup
by standby P) WakeUp
requested
(SDM)
GoToProtection
GoToProtection

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 EN 24 5. QFU1.2E LA Service Modes, Error Codes, and Fault Finding

Off
AC~ Mains is applied Stand by or
Protection
Standby Supply starts running.
All standby supply voltages become available.

st-by P resets, resulting in a high impedant output

stage of the I/O ports.

Initialise I/O pins of the st-by P

- Keep AVC system in reset (internal signal)
- Switch RESET-FUSION-OUTn LOW
- Switch RESET-HDMI-MUXn LOW
- Switch RESET-ETHERNETn LOW
- Switch AUDIO-MUTEn LOW
- Switch SPLASH-ON LOW
- Switch LCD-PWR-ONn High
If the protection state was left by short circuiting the
SDM pins, detection of a protection condition during
startup shall stall the startup. Protection conditions
occuring in a playing set shall be ignored. The
protection mode shall not be entered.

Switch ENABLE-WOLAN high to power Ethernet PHY

and Wifi dongle
start keyboard scanning, RC detection.
Wake up reasons are off.
Switch ENABLE-WOLANn high to power Ethernet
PHY and internal Wifi dongle if Networked Standby
was Off in the Standby mode.

Switch ON Platform supply by switching High the

STANDBYn line.

Startup shall continue from the

moment a valid detection is received.
12V platform is turned on, automatically enabling the
low voltage DCDC converter outputs

12V error:
Detect2 high received
No Layer1: 3
within 2 seconds?
Layer2: 16

Yes
Enter protection
Wait 300ms

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enginethe supply detection algorithm
All display related I/O lines should be
 Service Modes, Error Codes, and Fault Finding QFU1.2E LA 5. EN 25

Wake up reason
No
coldboot to Active mode?

No yes

AUDIO-MUTEn is switched by MIPS code No Startup screen cfg file

later on in the startup process when audio present?
needs to be released

Standby P monitors MIPS boots yes

boot process and will
init a restart if Boot
process hampers
Reset-lines are switched MIPS sends out startup screen
Boot is failing

TV application starts MIPS starts up the display.

Set was
started with
SDM pin?
Startup screen visible

Wait 4 seconds before restarting

No

Yes

No Switch AVC in reset

Switch RESET-FUSION-OUTn, RESET-

HDMI-MUXn , RESET-ETHERNETn Low
Semi-Standby
3-th try?Switch Standby I/O line LOW

Yes
Ignore boot failure:
Stall the startup process.
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error code
Blink Layer2 error 53.
 EN 26 5. QFU1.2E LA Service Modes, Error Codes, and Fault Finding

Semi Standby
The assumption here is that a fast toggle (<2s) can
Wait until previous on-state is left more than 2
only happen during ON->SEMI ->ON. In these states,
seconds ago. (to prevent LCD display problems)
the AVC is still active and can provide the 2s delay. A
transition ON->SEMI->STB Y->SEMI->ON cannot be
made in less than 2s, because the standby state will
be maintained for at least 4s. Assert RGB video blanking
and audio mute

Display already on?

(cold boot with splash
screen) Yes
Initialize audio and video
No processing IC's and functions
according needed use case.

Startup display
(see separate tab)

Start POWER-OK line

detection algorithm as defined
in the CHS service.
Wait until valid and stable audio and video, corresponding to the
requested output is delivered
AND
the backlight has been switched on for at least the time which is
indicated in the display file as preheat time

return
Release audio mute

unblank the video

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 Service Modes, Error Codes, and Fault Finding QFU1.2E LA 5. EN 27

Active

Mute all sound outputs according

information in the FMS AUDIO

Wait 100ms

Switch off POK line detection

algorithm (see CHS service)

Switch Off LCD backlight

Mute all video outputs switch off Ambilight (see CHS ambilight)

Shut down the display Wait until Ambilight has faded out:
(see separate sheet) Output power Observer should be zero

Semi Standby
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 EN 28 5. QFU1.2E LA Service Modes, Error Codes, and Fault Finding

Semi Stand by

If ambientlight functionality was used in semi-standby

(lampadaire mode), switch off ambient light (see CHS
ambilight)

Delay transition until ramping down of ambient light is *) If this is not performed and the set is
finished. *) switched to standby when the switch off of
the ambilights is still ongoing, the lights will
switch off abruptly when the supply is cut.

transfer Wake up reasons to the Stand by P.

transfer specific Firmware and Wake up reasons to the

Wifi dongle to allow networked standby

Switch AVC system in reset state

Switch reset-USB, Reset-Ethernet and Reset-DVBs
LOW

Switch RESET-FUSION-OUTn, RESET-HDMI-MUXn ,

RESET-ETHERNETn Low

Wait 10ms

Disable all supply related protections and switch off

the DC/DC converters (ENABLE-3V3n)

Switch OFF all supplies by switching HIGH the

Standby I/O line

Important remarks:
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release reset audio 10 sec after entering required?
 Service Modes, Error Codes, and Fault Finding
5.4 Service Tools
5.4.1 ComPair
The ComPair Tool is no longer supported.
5.5 Error Codes
5.5.1 Introduction
The error code buffer contains all detected errors since the last
time the buffer was erased. The buffer is written from left to
right, new errors are logged at the left side, and all other errors
shift one position to the right.
When an error occurs, it is added to the list of errors, provided
the list is not full. When an error occurs and the error buffer is
full, then the new error is not added, and the error buffer stays
intact (history is maintained).
To prevent that an occasional error stays in the list forever, the
error is removed from the list after more than 50 hrs. of
operation.
When multiple errors occur (errors occurred within a short time
span), there is a high probability that there is some relation
between them.
If no errors are there, the LED should not blink at all in
CSM or SDM. No spacer must be displayed as well.
There is a simple blinking LED procedure for board
level repair (home repair) so called LAYER 1 errors
next to the existing errors which are LAYER 2 errors (see
Table 5-2).
LAYER 1 errors are one digit errors.
LAYER 2 errors are 2 digit errors.
In protection mode.
From consumer mode: LAYER 1.
From SDM mode: LAYER 2.
Fatal errors, if I2C bus is blocked and the set reboots,
CSM and SAM are not selectable.
From consumer mode: LAYER 1.
From SDM mode: LAYER 2.
In CSM mode.
When entering CSM: error(s) LAYER 1 will be
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displayed via blinking LED.(attention: any new remote
QFU1.2E LA 5. EN 29
On screen via the SAM (only when a picture is visible).
E.g.:
00 00 00 00 00: No errors detected
23 00 00 00 00: Error code 23 is the last and only
detected error.
37 23 00 00 00: Error code 23 was first detected and
error code 37 is the last detected error.
Note that no protection errors can be logged in the
error buffer.
Via the blinking LED procedure. See section 5.5.3 How to
Clear the Error Buffer.
Via ComPair.
5.5.3 How to Clear the Error Buffer
Use one of the following methods:
By activation of the RESET ERROR BUFFER command
in the SAM menu.
If the content of the error buffer has not changed for 50+
hours, it resets automatically.
5.5.4 Error Buffer
In case of non-intermittent faults, clear the error buffer before
starting to repair (before clearing the buffer, write down the
content, as this history can give significant information). This to
ensure that old error codes are no longer present.
If possible, check the entire contents of the error buffer. In
some situations, an error code is only the result of another error
code and not the actual cause.(e.g. a fault in the protection
detection circuitry can also lead to a protection)
There are several mechanisms of error detection:
Via error bits in the status registers of ICs.
Via polling on I/O pins going to the standby processor.
Via sensing of analog values on the standby processor or
the Mips.
Via a not acknowledge of an I2C communication.
Take notice that some errors need several minutes before they
start blinking or before they will be logged. So in case of
problems wait 2 minutes from start-up onwards, and then
check if the front LED is blinking or if an error is logged.
 EN 30 5. QFU1.2E LA Service Modes, Error Codes, and Fault Finding

Table 5-2 Error code overview

Monitored Error/ Error Buffer/

Description Layer 1 Layer 2 by Prot Blinking LED Device Defective Board
I2CM3 (SSB + SRF bus) 2 13 MIPS E BL / EB SSB SSB
I2CM2 (BE bus) 2 14 MIPS E BL / EB SSB SSB
I2CM1(FE bus) 2 18 MIPS E BL / EB SSB SSB
PNX (Fusion) doesnt boot 2 15 Stby P P BL Fusion SSB
12V 3 16 Stby P P BL / Supply
HDMI mux 2 23 MIPS E EB SII9287 SSB
I2C switch 2 24 MIPS E EB PCA9540 SSB
Channel dec DVB-T2 2 27 MIPS E EB CXD2834 SSB
Channel dec DVB-S2 2 28 MIPS E EB SI2169 SSB
Lnb controller 2 31 MIPS E EB LNBH25 SSB
Hybrid Tuner 2 34 MIPS E EB SUT-RE214Z SSB
Main NVM 2 35 MIPS E EB M24C64 SSB
Tuner DVB-S2 2 36 MIPS E EB STV611X SSB
Class-D 2 37 MIPS E EB TAS 5731 PHP SSB
Processor PQ 2 38 MIPS E EB LPC1114 SSB
IO Expander 2 41 MIPS E EB PCA9554 SSB
T sensor SSB/set 2 42 MIPS E EB LM75 T sensor/SSB
Light sensor 6 43 MIPS E EB TSL2571 Set
P touch control 6 44 MIPS E EB / Set
RF4CE 6 46 MIPS E EB / Set
MIPS doesnt boot (SW cause) 2 53 Stby P P BL FUSION SSB
NT72314 9 61 MIPS E EB NT72314/ QFHD
NT68361 9 62 MIPS E EB NT68361/ QFHD
NT72314 not alive 9 63 MIPS E EB NT72314/ QFHD
NT68361 not alive 9 64 MIPS E EB NT68361/ QFHD

Extra Info
Rebooting. When a TV is constantly rebooting due to
internal problems, most of the time no errors will be logged
or blinked. This rebooting can be recognized via a ComPair
interface and Hyperterminal (for Hyperterminal settings,
see section 5.8 Fault Finding and Repair Tips, 5.8.6
Logging). Its shown that the loggings which are generated
by the main software keep continuing.
Error 13 (I2C bus M3, SSB + SRF bus blocked). Current
situation: when this error occurs, the TV can reboot due to
the blocked bus. The best way for further diagnosis here, is
to check the logging output.
Error 14 (I2C bus manuals
Downloaded from www.Manualslib.com M2, BE bus blocked).
search engine Current situation:
LAYER 2 error = 28 will be logged and displayed via the
blinking LED procedure if SDM is switched on.
Error 31 (Lnb controller). When there is no I2C
communication towards this device, LAYER 2 error = 31
will be logged and displayed via the blinking LED
procedure if SDM is activated.
Error 34 (Tuner). When there is no I2C communication
towards the tuner during start-up, LAYER 2 error = 34 will
be logged and displayed via the blinking LED procedure
when SDM is switched on.
Error 35 (main NVM). When there is no I2C
communication towards the main NVM during start-up,
LAYER 2 error = 35 will be displayed via the blinking LED
 Service Modes, Error Codes, and Fault Finding
displayed via the blinking LED procedure when SDM is
switched on.
Error 46 (RF4CE). When there is no I2C communication
towards the RF4CE driver during start-up, LAYER 2
error = 46 will be logged and displayed via the blinking LED
procedure when SDM is switched on.
Error 53. This error will indicate that the Fusion device has
read his bootscript (when this would have failed, error 15
would blink) but initialization was never completed because
of hardware problems (NAND flash, DDR...) or software
initialization problems. Possible cause could be that there
is no valid software loaded (try to upgrade to the latest main
software version). Note that it can take a few minutes
before the TV starts blinking LAYER 1 error = 2 or in SDM
(maintain grounding continuously), LAYER 2 error = 53.
Error 61 (NT72314). When there is no I2C acknowledge
from the Novatek device (Quad full HD Bolt-on board)
towards the MIPS during start-up, LAYER 2 error = 61 will
be logged.Here, the Novatek device operates as frame rate
convertor.
Error 62 (NT68361). When there is no I2C acknowledge
from the Novatek device (Quad full HD Bolt-on board)
towards the MIPS during start-up, LAYER 2 error = 62 will
be logged.Here, the Novatek device supports the 4K HDMI
to LVDS conversion.
Error 63 (NT72314 not alive).Error generated via I2C by
the device itself, although acknowledge passed and
confirmed.
Error 64 (NT68361 not alive).Error generated via I2C by
the device itself, although acknowledge passed and
confirmed.
5.6 The Blinking LED Procedure
5.6.1 Introduction
The blinking LED procedure can be split up into two situations:
Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM.
This will be only one digit error, namely the one that is
referring to the defective board (see table 5-2 Error code
overview) which causes the failure of the TV. This
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approach will especially be used for home repair and call
QFU1.2E LA 5. EN 31
5. One long blink of 3 s to finish the sequence (spacer).
6. The sequence starts again.
5.6.2 How to Activate
Use one of the following methods:
Activate the CSM. The blinking front LED will show the
layer 1 error(s), this works in normal operation mode or
automatically when the error/protection is monitored by the
standby processor.
In case no picture is shown and there is no LED blinking,
read the logging to detect whether error devices are
mentioned. (see section 5.8 Fault Finding and Repair
Tips, 5.8.6 Logging).
Activate the SDM. The blinking front LED will show the
entire content of the LAYER 2 error buffer, this works in
normal operation mode or when SDM (via hardware pins)
is activated when the tv set is in protection.
5.7 Protections
5.7.1 Software Protections
Most of the protections and errors use either the standby
microprocessor or the MIPS controller as detection device.
Since in these cases, checking of observers, polling of ADCs,
and filtering of input values are all heavily software based,
these protections are referred to as software protections.
There are several types of software related protections, solving
a variety of fault conditions:
Related to supplies: presence of the +5V, +3V3, +2V5,
+1V2 and +1V1 needs to be measured, no protection
triggered here.
Protections related to breakdown of the safety check
mechanism. E.g. since the protection detections are done
by means of software, failing of the software will have to
initiate a protection mode since safety cannot be
guaranteed any more.
Remark on the Supply Errors
The detection of a supply dip or supply loss during the normal
playing of the set does not lead to a protection, but to a cold
 EN 32 5. QFU1.2E LA Service Modes, Error Codes, and Fault Finding
5.8.2 CSM
When CSM is activated and there is a USB stick connected to
the TV, the software will dump the complete CSM content to the
USB stick. The file (Csm.xml) will be saved in the root of the
USB stick. If this mechanism works it can be concluded that a
large part of the operating system is already working (MIPS,
USB...)
5.8.3 Power conversion and distribution.
Description
Input power for the TV platform comes from the main power
supply that delivers +3V5-STANDBY (pin 9 of connector 1M90)
and +12V (pins 11,12 and 25,26 of the same connector). +3V5-
STANDBY (3.5V nominal) is the permanent voltage while +12V
is started by the STANDBY signal (connector 1M90, pin 10)
when going from high to low. +12V is split in few branches via
fuses 1UA0 (+12Va), 1UA1 (+12Vb) and 1UP1(+12-DVBS):
+12Va serves as input voltage for the switching voltage
regulators that deliver +1V1-FD and +1V5.
+12Vb is used as input voltage for the switching voltage
regulators that deliver +3V3 and +5V.
+12V-DVBS (if DVB-S functionality is present) goes to 12V
and +V-LNB switching regulators.
The on board power supply consists of 4 switching voltage
regulators (5 in case of DVB-S version), 8 linear voltage
regulators (9 in case of DVB-S version) and an over-current
protection circuit for 12V (AMBI-POWER) ambilight boards.
All switching voltage regulators have 12V input voltage and
deliver:
+1V1-FD Fusion main core supply voltage (0.95V...1.2V -
depending on DVS1 signal), stabilized close to the point of
load by means of SENSE+1V1-FD signal.
+1V5 supply voltage (1.53V nominal), for the DDR3
memories and DDR3 interface of the Fusion chip and +1V5
to +1V2-MIPS and +1V5 to +1V2-FE linear voltage
regulators.
+3V3 supply voltage (3.32V nominal): overall 3.3V for on
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board ICs and external search engine
ambientlight panels, also used as
Start-up of switching converters is triggered by DETECT12V
signal that becomes high when +12V rises above 10V and
stays above 9V (1V hysteresis).DETECT12V is used as enable
signal by the +12V to +5V switching converter;+12V to +1V1-
FD and +12V to +1V5(and +1V2-MIPS) will start at the same
time with +5V due to ENABLE+1V5+1V1 that is set high by
DETECT12V signal.Tuners are supplied from their respective
linear voltage regulators when +5V starts.The rest of the supply
voltages (+3V3, +2V5, +1V2-FA, +1V2-FE and +1V1-FA) are
switched on a few milliseconds later by signal ENABLE+3V3.
In case of TV sets having ambilight consumption from +12V
higher than 1A, the electronic protection circuit (7UAC or 7UAD
and surrounding components) is used instead of fuse 1UA2.
AMBI-POWER should be available shortly (100 ms) after +12V
starts if there is no load on it. The over-current trigger level is
around 4.1A for 7UAC and 3.5A for 7UAD. Once the over-
current protection is triggered, it can be reset by removing the
shortcircuit cause and keeping it under no load condition for
about 100 ms.
Important remark: for tests, GND-AL must be connected to
platform GND.
+V-LNB value is set via the I2C bus: around 13V for vertical
polarized satellite channels and around 18V for the horizontal
ones. Maximum output current is limited to 400mA
Debugging
The best way to find a failure in the DC/DC converters is to
check their start-up sequence at power on, presuming that
the external supply is operational. Take the STANDBY signal
"high"-to-"low" transition as trigger reference and check the
power start-up sequence as described above.
Tips
Behaviour comparison with a working Fusion R3 platform
can be a fast way to locate failures.
Check first the integrity of fuses 1UA0, 1UA1 and (if
present) 1UA2 and 1UP1.
If a fuse is found interrupted: check the respective +12Va
(or +12Vb or +12V-DVBS) short circuit with all of the
derived supply voltages, for example: a +12Va ->+1V5
 Service Modes, Error Codes, and Fault Finding
in Hyperterminal. The Hyperterminal is available in every
Windows application via Programs, Accessories,
Communications, Hyperterminal. Connect a ComPair UART-
cable (3138 188 75051) from the service connector in the TV to
the multi function jack at the front of ComPair II box.
Required settings in ComPair before starting to log: 5.8.8
- Start up the ComPair application.
- Select the correct database (open file QFUX.X, this will set
the ComPair interface in the appropriate mode).
- Close ComPair
After start-up of the Hyperterminal, fill in a name (f.i. logging)
in the Connection Description box, then apply the following
settings:
1. COMx
2. Bits per second = 115200
3. Data bits = 8
4. Parity = none
5. Stop bits = 1
6. Flow control = none
During the start-up of the TV set, the logging will be displayed.
This is also the case during rebooting of the TV set (the same
logging appears over and over). Also available in the logging is
the Display Option Code (useful when there is no picture),
look for item display number xxx in the beginning of the
logging. Tip: when there is no picture available during rebooting
you are able to check for error devices in the logging (LAYER
2 error) which can be very helpful to determine the failure cause
of the reboot. For protection state, there is no logging.
5.8.7 Guidelines Uart logging
Description possible cases:
Uart loggings are displayed:
When Uart loggings are coming out, the first conclusion we
can make is that the TV set is starting up and
communication with the flash RAM seems to be supported.
The Fusion processor is able to read and write in the
DRAMs.
We can not yet conclude: Flash RAM and DRAMs are fully
operational/reliable.There still can be errors in the data
transfers, DRAM errors, read/write speed and timing
control.
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QFU1.2E LA 5. EN 33
Startup in Jett Mode:
Check Uart logging in Jet mode mentioned as : JETT UART
READY.
Memory test
The memory test is running in the background of the main
TV software.It allocates a memory pool used to write and
read back predefined data, as reference to detect possible
memory corruption.The memory test is enabled by dial-in
of sequence 6636 while the remote control (dedicated) is
in DVD mode and the TV in CSM.Once the red LED in the
front of the TV set starts blinking, exit CSM in order to
display video.As long as the memory test is running and
no error is detected, the standby LED is blinking.Upon
detection of errors, the standby LED stays continuous ON
and details will be shown in the prints of the Uart logging.It
is not possible to stop the memory test once launched
unless the TV is restarted, also increase/decrease the
frequency of the memory interface can not be set.
Startup procedure:
Switch ON the TV set.
Set TV use case (preferably DVBT H264 or HDMI1080p).
Invoke CSM (dial-in 123654on the remote control).
Set the remote control in DVD mode, and enter sequence
6636.
Check the loggings coming from the service connector
(Mips Uart prints) :
**MemoryTest No errors found so far (loop xx)
xx : number of tests done.
As long as the memory test is running and no error is
detected, the standby LED is blinking continuously, upon
detection of errors, the standby LED stays ON.
Get out of CSM in order to see video.
COM port settings:
Baud rate: 115200
Data: 8 bits
Parity: none
Stop: 1 bit
Flow control: none
 EN 34 5. QFU1.2E LA Service Modes, Error Codes, and Fault Finding

5.8.10 Power Supply

In case of no picture when CSM (test pattern) is activated and

backlight doesnt light up, its recommended first to check the
LED drivers on the PSL(S).
Attention point for cable handling: (dis)connection for power
cable (power supply <=> SSB) should always be executed
without any bending or mechanical stress on the outisdes of
the connector 1M90.Risk of double pins inside the connector
should be avoid in this way.

5.8.11 Display option code

Attention: In case the SSB is replaced, always check the

display option code number (group 2, first option number e.g.
44855) in SAM, even when picture is available. Performance
with the incorrect display option code can lead to unwanted
side-effects for certain conditions.

Also supported in this chassis:

The display option code can be changed by 062598 HOME
XXX special SAM command (XXX=display option in 3 digits).

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 Service Modes, Error Codes, and Fault Finding QFU1.2E LA 5. EN 35

5.8.12 SSB Replacement For a more general overview of steps to follow, refer to figure
5-11 SSB replacement flowchart.
Follow the instructions in the flowchart in case a SSB has to be
exchanged. See table 5-3 SSB replacement instructions. Table 5-3 SSB replacement instructions

Step # Action to do Advise / Attention points / Remarks

1 Ensure ESD protection by using a wristband -
2 If SSB is still functional: Go via SAM to upload to USB and copy Personal Upload to USB: a directory repair will be created on the USB, and all data will be copied in this
settings - Option codes - Alignments (Presets) - Set Identification. directory. In case of issues by copying the program map table, it is advised to reinstall the
Advice: because of differences in memory allocation, it is advised to upgrade programs from Virgin mode instead of using copy via USB.
main SW before copying data from existing SSB. Copy of Preset list is
possible from normal user interface.
3 Disconnect set from mains and from antenna. Safety and ESD!
4 Open the set and disconnect LVDS flat cable. Disconnect other cables / Always take care for ESD! Be extra careful when removing connectors!
connections.
5 Dismount the (defective) SSB from the set. Do not damage SSB copper tracks with your tools! Do not scratch bottom of SSB (be very careful
by moving SSB over SSB supports). See Figure 5-9 and Figure 5-10.
6 Place new SSB in the set, and fixate/mount carefully. Do not damage SSB copper tracks with your tools! Do not scratch bottom of SSB (be very careful
by moving SSB over SSB supports). See Figure 5-9 and Figure 5-10.
7 Connect PSU and other connectors. Insert the optional WiFi module. Make sure that the connectors are correctly plugged-in and locked (click). Special attention for the
optional WiFi module: a defective WiFi module can give reboots or no start-up of the SSB. In this
case do a trial without WiFi module.
8 Connect LVDS connector(s). Be very careful: wrong or bad connection can damage the TCON part on the SSB and damage
the LCD display. Check if flat cables are fitted correctly before closing the connector lock.
9 Connect set to mains and switch TV On. Check start-up of the set, backlight switching On.
10 If the set does not start (or reboots) check: Power supply connector must snap into the socket.
- The connectors from the power supply,
- The power supply cable and connection pins,
- LVDS cable connection.
11 Before programming the new SSB, upgrade to latest software. If set is starting Some SSBs will start-up in software upgrade mode, and software needs to be installed before you
up in software upgrade mode, then first install new software via software can program the Display Option codes. Its adviced to use an autorun.upg file for software
Upgrade Menu or via the autorun.upg file. upgrade, this in case you have no OSD on the screen.
12 If set is starting up without picture or menu (OSD), first program the correct Use blind service mode 062598 + Home button, directly followed by the
Display Option codes. Display Option code (3 digits). Set will switch to Standby after Display Option code is entered.
13 Go to SAM and program Set type and Serial number. This is possible via Programming Set type and Serial number is mandatory to have all functionality of the set, like
the NVM editor and virtual keyboard. In case personal settings were DLNA, Net TV For certain sets you may need to use ComPair for this.
recovered from the defective SSB, you can use an Upload from USB.
14 Check if option codes are correct, and keys are present. SSBs with integrated Validity of HDCP, CI+, Marlin, and WDRM keys can be checked via ComPair.
TCON needs TCON alignment in SAM.
15 Update to latest software (Standby and main software). This step is necessary Even when the SSB already has the latest software, it is mandatory to upgrade again the software
to make sure that the (optional) 200 Hz T-CON board has the latest software. to update the 200 Hz T-CON part. At the end of the main software update process, a dedicated
software is loaded, from the main processor via the LVDS connection, to upgrade the
200 Hz T-CON part. For certain LCD displays, a dedicated Display software patch (autoscript) is
available. See General Service info GSC_85590.
16 Once the set is playing, check cable connection between PSU and SSB, by Check the two power connectors on 1M90. Bad contact or bad connection here can give reboots.
moving the cable if there are no bad connections.
17 Fill in the Electronic DDF (Defect Description Form): Fault symptom, TV type It is mandatory to fill in the E-DDF form (see the At Your Service web portal).
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manuals
TV serialsearch
number.engine
 EN 36 5. QFU1.2E LA Service Modes, Error Codes, and Fault Finding

In st ru ct io n n o t e SSB rep lacem en t Q55x.x

Before starting: ST AR T
- prepare a USB memory stick with the latest software
- download the latest Main Software (Fus) from www.p4c.philips.com
- unzip this file
- create a folder upgrades in the root of a USB stick (size > 50 MB) and
save the autorun.upg file in this "upgrades" folder.
Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in Set is still oper ating?
case there are more than one "autorun.upg" files on the USB stick.
No

Yes

C onnect the U SB stick to the set,

go to SAM and save the current TV settings via Upload to USB

1. D ismount the defective SSB.

2. Replace the SSB by a Service SSB.

Start-up the set

Due to a possible wrong display option code in the received Service
SSB (NVM), its possible that no picture is displayed. Due to this
the download application will not be shown either. This tree enables you
to load the main software step-by-step via the UART logging on the PC
(this for visual feedback). Set behaviour?
No pictur e displayed Pictur e displayed
Set is starting up without software
upgrade menu appearing on screen

1) Start up the TV set, equiped with the Service SSB,

and enable the UART logging on the PC. Pictur e displayed
Set is starting up with software
upgrade menu appearing on screen
2) The TV set will start-up automatically in the
download application if main TV software is not loaded.

1) Plug the USB stick into the TV set and select

3) Plug the prepared USB stick into the TV set. Follow the the autorun .upg file in the displayed browser.
instructions in the UART log file, press Right cursor key to enter
the list. Navigate to the autorun.upg file in the UART logging
printout via the cursor keys on the remote control. When the
correct file is selected, press Ok.
2) Now the main software will be loaded automatically,
supported by a progress bar.
4) Press "Down" cursor and Ok to start flashing the main
TV software. Printouts like: L: 1-100%, V: 1-100% and
P: 1-100% should be visible now in the UART logging.

3) Wait until the message Operation successful ! is displayed

5) Wait until the message Operation successful ! is logged in and remove all inserted media. Restart the TV set.
the UART log and remove all inserted media. Restart the TV set.

Set the correct Display code via 062598 -HOME- xxx where
xxx is the 3 digit display panel code (see sticker on the side
or bottom of the cabinet)

After entering the Display Option code, the set is going to

Standby
(= validation of code)

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 Service Modes, Error Codes, and Fault Finding QFU1.2E LA 5. EN 37

Set is st art in g u p in F act o ry m o d e

Set is starting up in F actory m ode?

Noisy picture with bands/lines is visible and the An F is displayed (and the HDMI 1
RED LED is continuous on. input is displayed).

- Press the volume minus button on the TVs local keyboard for 5 ~10
seconds

- Press the SOURCE button for 10 seconds until the F disappears

from the screen or the noise on the screen is replaced by blue mute

The noise on the screen is replaced

with the blue mute or the F is disappeared!

Unplug the mains cord to verify the correct

disabling of the Factory mode.
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 EN 38 5. QFU1.2E LA Service Modes, Error Codes, and Fault Finding

18753_211_100811.eps
110810

Figure 5-13 SSB start-up

5.9 Software Upgrading Automatic Software Upgrade

Downloaded from www.Manualslib.com manuals search engine In normal conditions, so when there is no major problem with
 Service Modes, Error Codes, and Fault Finding QFU1.2E LA 5. EN 39

1. Create a directory UPGRADES on the USB stick.

2. Rename the autorun.upg to something else, e.g. to
software.upg. Do not use long or complicated names,
keep it simple. Make sure that AUTORUN.UPG is no
longer present in the root of the USB stick.
3. Copy the renamed upg file into this directory.
4. Insert USB stick into the TV.
5. The renamed upg file will be visible and selectable in the
upgrade application.

Back-up Software Upgrade Application

If the default software upgrade application does not start (could
be due to a corrupted boot sector) via the above described
method, try activating the back-up software upgrade
application.
How to start the back-up software upgrade application
manually:
1. Disconnect the TV from the Mains/AC Power.
2. Press the CURSOR DOWN-button on a Philips TV
remote control while reconnecting the TV to the Mains/AC
Power.(attention : not supported by use of RF4CE remote
due to the fact this application is not running yet at the time
of the CURSOR-DOWN request).
3. The back-up software upgrade application will start.

5.9.3 Standby Software Upgrade via USB

In this chassis it is possible to upgrade the Standby software

via a USB stick. The method is similar as upgrading the main
software via USB.
Use the following steps:
1. Create a directory UPGRADES on the USB stick.
2. Copy the Standby software (one-zip file StandbyUpgrade,
e.g. StandbyFactory_77.03.12.00_16.00.00.upg) into this
directory.
3. Insert the USB stick into the TV.
4. Start the download application manually (see section
Manual Software Upgrade.
5. Select the appropriate file and press the OK button to
upgrade.

5.9.4 Content and Usage of the One-Zip Software File

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 EN 40 6. QFU1.2E LA Alignments

6. Alignments
Index of this chapter: LATAM models: an NTSC M TV-signal with a signal
6.1 General Alignment Conditions strength of at least 1 mV and a frequency of 61.25 MHz
6.2 Hardware Alignments (channel 3).
6.3 Software Alignments
6.4 Option Settings 6.3.1 White Point
6.5 Reset of Repaired SSB
6.6 Total Overview SAM modes
Choose Home, Setup, TV Settings and then Picture
and set picture settings as follows:
6.1 General Alignment Conditions Picture Setting
Perform all electrical adjustments under the following
Contrast 100
conditions:
Brightness 50
Power supply voltage (depends on region):
Colour 0
AP-NTSC: 120 VAC or 230 VAC / 50 Hz ( 10%).
Light Sensor Off
AP-PAL-multi: 120 - 230 VAC / 50 Hz ( 10%).
Picture format Unscaled
EU: 230 VAC / 50 Hz ( 10%).
US: 120 VAC / 60 Hz ( 10%).
In menu Picture, choose Pixel Precise HD and set
LATAM-NTSC: 120 - 230 VAC / 50 Hz ( 10%).
picture settings as follows:
Connect the set to the mains via an isolation transformer
with low internal resistance. Picture Setting

Allow the set to warm up for approximately 15 minutes. Dynamic Contrast Off

Measure voltages and waveforms in relation to correct Dynamic Backlight Off

ground (e.g. measure audio signals in relation to Colour Enhancement Off

AUDIO_GND). Caution: It is not allowed to use heat sinks Gamma (advanced) 0

as ground.
Test probe: Ri > 10 M, Ci < 20 pF. Go to the SAM and select Alignments-> White point.
Use an isolated trimmer/screwdriver to perform
alignments. White point alignment LCD screens:
Use a 100% white screen (format: 720p50) to the HDMI
6.1.1 Alignment Sequence input and set the following values:
Colour temperature: Cool.
All White point values to: 127.
First, set the correct options:
In SAM, select Option numbers.
In case you have a colour analyser:
Fill in the option settings for Group 1 and Group 2
Measure, in a dark environment, with a calibrated
according to the set sticker (see also paragraph 6.4
contactless color analyser (e.g.Minolta CA-210) in the
Option Settings).
centre of the screen and note the x, y value.
Press OK on the remote control before the cursor is
Apply a 90% full white screen to the HDMI input and select
moved to the left.
this input.Format : 720p50.If a Quantum Data generator is
In submenu Option numbers select Store and press
used, its recommended to select the FLAT predefined
OK on the RC.
setting from the device.
OR:
Adjust the correct x, y coordinates (while holding one of the
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In main menu,manuals search engine
select Store again and press OK on
White point registers R, G or B on 127) by means of
 Alignments QFU1.2E LA 6. EN 41

Select a COLOUR TEMPERATURE (e.g. COOL, White Tone 55PFL8008/x

NORMAL, or WARM). Colour Temp R G B
Set the RED, GREEN and BLUE default values according Normal 127 103 113
to the values in Table 6-5. Cool 122 103 127
When finished press OK on the RC, then press STORE (in Warm 127 90 74
the SAM root menu) to store the aligned values to the NVM.
Restore the initial picture settings after the alignments. Table 6-9 White tone default settings 55" PDL series

Table 6-3 White tone default settings 40" PFL series White Tone 55PDL8908/x
Colour Temp R G B
White Tone 40PFL8008/x Normal 127 96 98
Colour Temp R G B Cool 127 100 116
Normal 127 110 110 Warm 127 88 59
Cool 123 115 127
Warm 127 99 72
Table 6-10 White tone default settings 60" PFL series

Table 6-4 White tone default settings 42" PFL series White Tone 60PFL6008/x
Colour Temp R G B
White Tone 42PFLxxx8/x Normal 127 108 103
Colour Temp R G B Cool 127 115 121
Normal 127 118 116 Warm 127 96 63
Cool 120 120 127
Warm 127 108 74 White Tone 60PFL8708/x
Colour Temp R G B

Table 6-5 White tone default settings 46" PFL series Normal 127 123 91
Cool 124 125 111
Warm 127 118 51
White Tone 46PFL8008/x
Colour Temp R G B
Normal 127 99 108 Table 6-11 White tone default settings 65" PFL series
Cool 124 102 125
Warm 127 87 71 White Tone 65PFL9708/x
Colour Temp R G B

Table 6-6 White tone default settings 46" PDL series Normal 125 123 125
Cool 113 115 127
Warm 127 113 89
White Tone 46PDL8908/x
Colour Temp R G B
Normal 127 92 92 Table 6-12 White tone default settings 84" PFL series
Cool 127 98 110
Warm 127 84 58 White Tone 84PFL9708/x
Colour Temp R G B
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Table 6-7manuals search
White tone enginesettings 47" PFL series
default Normal 127 112 118
 EN 42 6. QFU1.2E LA Alignments

Table 6-13 Overview matrix correction table Diversity

Not all sets with the same Commercial Type Number (CTN)
Matrix # fR fG fB necessarily have the same option code!
Matrix 0 1 1 1 Use of Alternative BOM => an alternative BOM number usually
Matrix 1 1 0.9 0.9 indicates the use of an alternative display or power supply. This
Matrix 2 0.9 1 0.9 results in another display code thus in another Option code.
Matrix 3 0.9 0.9 1 Refer to Chapter 2. Technical Specs, Diversity, and
Matrix 4 0.9 1 1 Connections.
Matrix 5 1 0.9 1
Matrix 6 1 1 0.9 6.5 Reset of Repaired SSB
Matrix 7 0.95 1 1 A very important issue towards a repaired SSB from a Service
Matrix 8 1 0.95 1 repair shop (SSB repair on component level) implies the reset
Matrix 9 1 1 0.95 of the NVM on the SSB.
A repaired SSB in Service should get the service Set type
00PF0000000000 and Production code 00000000000000.
6.4 Option Settings Also the virgin bit needs to be set. To set all this, you can use
the ComPair tool or use the NVM editor and Setup => TV
6.4.1 Introduction
settings => General settings => Reinstall TV (virgin mode).

The microprocessor communicates with a large number of I2C

After a repaired SSB has been mounted in the set (set repair
ICs in the set. To ensure good communication and to make on board level), the type number (CTN) and production code +
digital diagnosis possible, the microprocessor has to know
12NCs (SSB, display and supply) of the TV has to be set
which ICs to address.
according the type plate of the set (no info on 12NCs here). For
this, you can use the NVM editor in SAM. This action also
Notes:
ensures the correct functioning of the Smart TV feature and
After changing the option number(s), save them by
access to the Smart TV portals. The loading of the CTN and
pressing the OK button on the RC before the cursor is production code can also be done via ComPair (Model number
moved to the left, select STORE in the SAM root menu
programming).
and press OK on the RC.
The new option setting is only active after the TV is
switched off / standby and on again with the mains After a SSB repair, the original channel map can be restored,
provided that the original channel map was stored on a USB
switch (the NVM is then read again).
stick before repair was commenced and that basic functionality
of the TV, needed for this procedure, was not hampered as a
6.4.2 (Service) Options result of the defect. The procedure of channel map cloning is
clearly described in the (electronic) user manual.
From 2011 onwards, it is not longer possible to change
individual option settings in SAM. Options can only be changed
all at once by using the option codes as described in section
6.4.4.

6.4.3 Option Code Overview

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Refer to the rearcovermanuals search
sticker in engine
the set for the correct option
 Alignments QFU1.2E LA 6. EN 43

6.5.1 SSB identification

Whenever ordering a new SSB, it should be noted that the

correct ordering number (12nc) of a SSB is located on a sticker
on the SSB. The format is <12nc SSB><serial number>. The
ordering number of the correct Service SSB is the one
preceded by the letter S in case 2 or more ordering numbers
are present on the bar code sticker.

18310_221_090318.eps
090319

Figure 6-1 SSB identification

6.6 Total Overview SAM modes

Table 6-14 SAM mode overview

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description

Hardware Info A. SW version e.g. QF2EU_0.49.1.0 Display TV & Standby SW version and CTN serial
B. Standby processor version e.g. STDBY_77.3.11.16 number
C. Production code e.g. see type plate
Operation hours Displays the accumulated total of operation hours.TV
switched on/off & every 0.5 hours is increase one
Errors Displays the most recent errors
Reset error buffer Clears all content in the error buffer
Alignment White point Colour temperature Normal 3 different modes of colour temperature can be
Warn selected
Cool
White point red LCD White Point Alignment. For values,
White point green see Table 6-5 White tone default settings 46" PFL
series to 6-8 White tone default settings 55" PFL
White point blue
series
Ambilight Select module
Downloaded from www.Manualslib.com manuals search engine Brightness
 EN 44 6. QFU1.2E LA Alignments

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description

RF4CE pairing tables Clear paired remote control
Development file Development 1 file version Display parameters DISPT5.0.9.29 Display information is for development purposes
versions Acoustics parameters SNDPR
5.0.6.20
PQ parameters FUSIO 1.0.27.22
Ambilight parameters PRFAM 5.0.5.2
Temp comp parameters 1.3
Development 2 file version 12NC one zip software Display information is for development purposes
Initial main software
NVM version QF2EU_0.4.5.0
e-Sticker software
Upload to USB Channel list (not) Item Channel list removed from the user interface
Personal settings
Option codes
Alignments
Identification data
History list
All (options included)
Download from USB Channel list (not) Item Channel list removed from the user interface
Personal settings
Option codes
Alignments
Identification data
All (options included)
NVM editor Type number see type plate NVM editor; re key-in type number and production
Production code see type plate code after SSB replacement

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 Circuit Descriptions QFU1.2E LA 7. EN 45

7. Circuit Descriptions
Index of this chapter: 7.1 Introduction
7.1 Introduction The QFU1.2E LA chassis is part of the FUSION platform and
7.2 Power Supply covers sets in the 6xxx, 7xxx, 8xxx and 9xxx range.
7.3 General Power Architecture
It uses the same chipset as the earlier QFU1.1E LA chassis.
Notes:
Only new circuits (circuits that are not published recently) Only circuits that differ from this chassis are described in this
are described. manual. For all other info, refer to the QFU1.1E LA manual.
Figures can deviate slightly from the actual situation, due
to different set executions.
7.1.1 FUSION 2013 Architecture Overview
For a good understanding of the following circuit
descriptions, please use the wiring-, block- (see chapter
9. Block Diagrams) and circuit diagrams (see chapter For details about the chassis block diagrams refer to
chapter 9. Block Diagrams. An overview of the FUSION 2013
10. Circuit Diagrams and PWB Layouts). Where
architecture can be found in Figure 7-1.
necessary, you will find a separate drawing for clarification.

1GB 1GB
DDR FLASH
32 16/32

Hybrid VByOne OR LVDS

Tuner
DVB-T2
#mapping
GPIO

+I2C
Tuner DVB-S2

Fusion
AL

CI+

BL uP

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 EN 46 7. QFU1.2E LA Circuit Descriptions

7.2 Power Supply fuse with one with the correct specifications! This part is
available in the regular market.
7.2.1 Power Supply Unit Consult the Philips Service web portal for the order codes of the
boards.
All power supplies are a black box for Service. When any of
these power supplies is defective, a new board must be 7.3 General Power Architecture
ordered and the defective one must be returned, unless the For the power architecture, refer to figure 7-2
main fuse of the board is broken. Always replace a defective

Fully integrated PSLS

1M09
Ambient
Display interfacing Light
1316, 1319

Platform
Display-power - Power
Control +
With 16 DRV Power Basic-SSB-
1M90
Platform
Low Stby
power

PFC Ac-input +
Mainsfilter
AC-IN
1 power-PCB
1308

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 IC Data Sheets QFU1.2E LA 8. EN 47

8. IC Data Sheets
This chapter shows the internal block diagrams and pin electrical diagrams (with the exception of memory and logic
configurations of ICs that are drawn as black boxes in the ICs).

8.1 Diagram 10-1-8 B02C, DVBT2 channel decoder B02C, CXD2834 (IC7KC0)

Block diagram
MPEG
TUNER Decoder
TAINP (IF)
IF+ 12-bit
TAINM (IF) ADC
IF-

DVB-T2 LDPC/BCH Stream

RFAIN 10-bit TSCLK
(RFAGC-MON) Demodulator Decoder Processor TSCLK
ADC
TSVALID
TSVALID
TSIF
GPIO1 (PWM) TSSYNC
(RFAGC) GPIO TSSYNC
DVB-T
TSDATA7-0
Demodulator TSDATA7-0
TS
RS Decoder
TIFAGC Smoothing
IFAGC AGC DVB-C
Demodulator

TTUSCL SCL
SCL SCL
TTUSDA I2C IF SDA
SDA SDA

41MHz or OSC
20.5 MHz PLL

XTALI
XTALO

Pinning information

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 EN 48 8. QFU1.2E LA IC Data Sheets

Personal Notes:

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 Block Diagrams QFU1.2E LA 9. EN 49

9. Block Diagrams
9.1 Wiring Diagram Series 40"

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 Block Diagrams QFU1.2E LA 9. EN 50

9.2 Wiring Diagram 42" - 47" 6xxx series

Wiring diagram 42"- 47" 6xxx series

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 Block Diagrams QFU1.2E LA 9. EN 51

9.3 Wiring Diagram 55" 6xxx series

Wiring diagram 55" 6xxx series

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 Block Diagrams QFU1.2E LA 9. EN 52

9.4 Wiring Diagram 55" 7xxx series

Wiring diagram 55" 7xx8 series

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 Block Diagrams QFU1.2E LA 9. EN 53

9.5 Wiring Diagram 60" 6xxx series

Wiring diagram 60" 6xxx series

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 Block Diagrams QFU1.2E LA 9. EN 54

9.6 Wiring Diagram 60" 8xxx series

Wiring diagram 60" 8xxx series

8M09 8C27
RF4CE
8016 PSU 8M90
8015

8G50 8G51
SSB
8C31

8C28

8T51 8C29

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 Block Diagrams QFU1.2E LA 9. EN 55

9.7 Wiring Diagram 65" 9xxx series

Wiring diagram 65" 9xxx series

1020 RF4CE
8C27

8319

8316
FRC

8M90 8702

809A
1050 PSU
809B

8M01

8G50
SSB
8G51

8C20

8G52 8G53
TCON

8803

1012 LED-RECEIVER PANEL

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 Block Diagrams QFU1.2E LA 9. EN 56

9.8 Wiring Diagram 84" 9xx8 Series

Wiring diagram 84" 9xx8 series

8L25
8P43 1020 RF4CE

8L26
LED driver 8L25 LED driver
8P42

1051 Standby Board 8C27

8L32
8L21 8L11
8L33
8L24 8G50
8P40

8P41 8G52 1006 FRC Board

1052 PFC-board TCON
8G53

8702 8M90 8G51

8803
8S00 8S01
8M11 1111 SSB
Amplifier board
8M01 1174
8D01
8P50 1050 EMI-board
I
8D02
8C20

5220
1073 Keyboard

5219

5212 5212
1043 WiFi module

1012 LED board

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 Block Diagrams QFU1.2E LA 9. EN 57

9.9 Block Diagram

Skype module
USB 1 camera & mic
USB-HDD-DM
USB-CAM-DM

USB 2 USB USB

USB-PORTA-DM HUB HUB
Wi-Fi Module GPIO for WoWLAN
BCM43235 / MIMO 2x2 11n
USB 3
USB-PORTB-DM

UART for
factory/Service Ethernet
RF4CE module
Ti CC2533
L
I2S
Class D
LNB 1GB
Sat In DVB-S2 R NVM 8 bit SLC
LNBH25 Ethernet 8K8
PHY
NAND Flash
DVB-S + S2 EEPROM
Memory
Analogue Atheros
STV CH DEC TS-DVBS Stereo AR8030
6111B HP
SI2169 10/100Mbit
WoLAN

/2
RF In

RGMI
DVB-T2 PHY PHY
SDIO STANDBY POWER ISLAND
P-

PWM (3)
(2) I2C UART
Analog
FLASH UART
SUT- CH DEC TS-DVBT2 SCART L/R Audio Audio
RE214 10/100/
CXD2834ER YPbPr L/R Audio
AFE
USB USB 1000 I2C
12bit Audio MAC MAC Ethernet
VGA L/R Audio
54MHz
Post- MAC
STANDBY
CEC
processing EJTAG MCU
(8051) Standby
Optical S/PDIF-OUT
S/PDIF
SPI interface NVM
HDMI0_ARC 512KB flash
- RTC
PLF - IR decode GPIO
SmartCard MIPS @ 1GHz - Key pad
Registers - CEC
CA slot (CI+) CA TS In/ Out
Audio-Video - Slow ADC
ADC in

Decoder IR in
CPU APP CPU Graphics Engine
MIPS 74Kf @ 700MHz
MIPS 74kc @700MHz 2D 3D
B1 G1 R1
SCART

1 3 5 7 9 11 13 15 17 19 21 1GB
A A
2 Channel Memory Bus 64/48bit DDR3 L L
2 4 6 8 10 12 14 16 18 20
1 n

Status 1 FBL Display Backlight

OSD Scalers
CPU PWM
H&V Backlight P
TRANSPORT DEMUX

MIPS 24Ke
Meter SPI
@ 400MHz H&V
2D Dimming
Ambilight
Fingerprint BACKEND
MULTI detection
R YPbPr
cf. backend requirements
12bit 54MHz

audio
L/R
VIF/SIF, ATSC, DVB- VIDEO
Main IDP
AFE

T/C, ISDB-B/QAM ENCODER L/R + V-sync 3D IR

1080p@60Hz I/F
L DECODER
YPbPr

DEMODULATOR MAIN MAIN 3D BLENDER

MIPS 4KEc CPU
[...PQ processing...] [...PQ processing...]
Pr YPbPr
YPbPr - Gamma
SC1-DETECTn - White balance
YPBPR-DETECTn - 12bit resolution
Pb PCA9554BS - RGB Halo
IC driven processing Free Watermark
- xvYCC for ME/MC Insertion
Y Analog
SCART RGB Video S main channel FRC Quad 2/4 LVDS 10 bit
- 2x LVDS
DVI
Automatic association with:
SCART CVBS
Mux
AFE: M
E programmable I/F RGB 1080p
audio - HDMI 1/2/3/4 with DVI video
L/R 108MHz U 10bit 3D Video
L OR
colour matrix
- Bitmask Video
10bit X comb
filter
Decoder E PIP PIP PIP Source Select
1080p@60Hz [...PQ processing...] [...PQ processing...] Support for 3D
C
T
VBI Slicer
Analog
Vx1 8 V1 10 bit RGB
I/F 1080p
Video Component / PC RGB
Mux
HDMI Audio Return Channel (ARC)
S2 S1 S0
HDMI
#1

Y4

Y0

Y1 74HCT4051
CVBS Out Mux
HDMI ARC 1:8 demux TV Encoder Video DAC &
Y2 Scaler
HDMI

6dB
HDMI-Rx CVBS Not used
#2

Y3
Gain
EDID

HDMI ARC
HDMI

0
#3

1
2
HDMI ARC 3
HDMI
#4

HDMI mux
SiI9287B (4 inputs)

CEC

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 Block Diagrams QFU1.2E LA 9. EN 58

9.10 Block Diagram Supplylines

+12V-AUDIO +12V-AUDIO (Class-D)

+3V5-STANDBY

pin 9
T 4A 32V
+12V TCON switch +VDISP (TCON)
ENABLE-WOLAN

3,5V to 3,37V
LCD-PWR-ONn +3V3-LAN ((W)LAN)
linear regulator

RT9187GSP (RICHTE)
pins 11, 12,
+12V

25 and 26
3,5V to 3,3V
+3V5-STANDBY +3V3-STANDBY (Fusion, RC,...)
linear regulator

RT9193+33GB (RICHTE)
+12V-AUDIO

over-current protection
+12VAL AMBI-POWER (ambilight)
pins 13 and 14 1A (2A fuse) or 2,8A

+3V3 +3V3AL (ambilight)

+T

+12V detector, DETECT12V

power-up and ENABLE+1V5+1V1
3,3V to 1,1V
power-down ENABLE+2V5 +3V3 +1V1-FA (Fusion)
1M90

linear regulator
+12VAL

pins 21 and 22 sequencer ENABLE+3V3

RT9187BGB (RICHTE)
DVS1

12V to 1,1V DVS2

+1V1-FD
switching converter
1,5V to 1,2V
RT8228DGQW (7UC0)+ ext mosfet +1V5 +1V2-MIPS (Fusion 2nd core voltage)
linear regulator
GND-AL

pins 23 and 24 ENABLE+1V5+1V1 TI TPS7A7001DDA (TI00)

T 3A 32V 12V to 1,5V 3,3V to 1,2V

+12Va +3V3 +1V2-FA (Fusion)
switching converter +1V5 linear regulator
1UA0
NX1117C12Z (NXP0)
TI TPS54527DDA

ENABLE+1V5+1V1
3,3V to 2,5V
pins 7, 8, 15, +3V3 +2V5 (Fusion, PLL)
GND

linear regulator
16, 27 and 28 12V to 3,3V ENABLE+2V5
+3V3 RT9025-12GSP (RICHTE)
switching converter

RT7297CHZSP
Reserved
+12V T 3A 32V 1,5V to 1,1V
+12Vb +1V5 +1V1-DVBT2
ENABLE+3V3 linear regulator
1UA1
STANDBY

RT9025-12GSP (RICHTE)
pin 10
12V to 5V
+5V
switching converter 1,5V to 1,2V
+1V5 +1V2-FE (DVB-T2, DVB-S2)
linear regulator
RT8288AZSP (chanel decoder)
RT9025-12GSP (RICHTE)
DETECT12V

T 3A 32V 5V to 3,3V
12V to +V-LNB +5V VCC-TUNER (DVB-T/T2)
+V-LNB linear regulator
switching converter
1UP1
LNBH25LPQ (ST00) NX1117C33Z (NXP0)

(I2C)

5V to 3,3V
+3V3-DVBS (DVB-S2)
linear regulator

NX1117C33Z (NXP0)

+5V +5V-PORTA,B, C (USB )

+T
1.5A
(0.5A per USB)

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 59

10. Circuit Diagrams and PWB Layouts

10.1 310431366124 SSB
10-1-1 B01A, Power connector

Power connector
B01A +12V B01A
BL-SPI-CS_BL-I-CTRL CUA1 BL-I-CTRL +12V DETECTION

6
7UA0-2

3UAF-3
1M90

22K
BC847BPN(COL)
FUA1 3GY1-2 2 7 100R BL-DIM3 4 RES
1 IUAA 3UG3
FUA4 3GY1-3 3 6 100R BL-DIM4

3
2
FUA3 3GY1-1 1 8 100R BL-DIM5 5
3 1K0

5
3GY1-4 3

100K 1%
FUA6 4 5 100R BL-DIM6

3UAF-4
4
FUA9 3GY5 100R

22K
5 BL-DIM7 IUAF

3UD1
FUAB 3GY6 100R BL-DIM8
6 IUFQ

7
IUF8 3UG4-4

3UAF-2
7 3UA4
FUA2 100K

22K
STANDBY

100K
8 IUAC
9 100R 6
FUAM 7UA0-1

2
10 IUAB
+12V BC847BPN(COL) FUAN DETECT12V
11
FUA5 FUAC 2
12 7UF9-1
1

3UG4-3
13 +12V-AUDIO BC857BS(COL)

3UAE

1% 68K
FUA7
14 3UD0 3UG8
FUAD
15 IUF7
16 1M0 22K

2UF9

100n
1u0 RES
FUA8 3GY7 BL-ON

3UAG RES
17

2UAJ
FUAA 3GY8 100R BL-I-CTRL

100K
18

1
FUAK 3GY9 100R BL-DIM1

3UAF-1
19
FUAL 3GYA 100R

4K7

22K
20 BL-DIM2
+12VAL 100R +3V3-STANDBY
21 IUAD
3GYB POWER-OK BC857BS(COL)

8
22 +3V3-STANDBY
100R 7UF9-2

3UG4-2
23 GND-AL
24
25 +12V ENABLE+3V3

100K
26 FUAV
27
28
30 29 FUAE

3UG4-1
+12V-AUDIO
SMAW200-H28S2

FUAH
10n
10n

1n0

10n

1n0

1n0

1n0

1n0

1n0

1n0

1n0
2UAB RES

2UA3 RES
2UAU RES

16V
2UAA

2UAT

2UA4

2UA2
100n

100n

100p

100n
1u0

1u0

2GYA
2GY1

2GY2

2GY3

2GY4

2GY5

2GY6

2GY7

2GY8

2GY9

2UA5
RES
100u

FUAF

GND-AL +22V +12VAL

+3V5-STANDBY +12VAL +12VAL

RES 2 3UAN-2 7

RES 3 3UAP-3 6

RES 4 3UAP-4 5
RES 3UAN-1

RES 3UAN-3

RES 3UAN-4

RES 3UAP-1

RES 3UAP-2
1

4K7

4K7

4K7

4K7

4K7

4K7

4K7

4K7
2UA9 RES
K

12K 1%

2
6.3V 330u
TS2431

3UAV-3
7UAF

2UA0
2
240R 1%
A

1u0 AMBI-POWER
3UAR

2UAK

IUAL
100p
RES

9UA2-1 RES
3

+12VAL
9UA2-2 RES
9UA2-3 RES
9UA2-4 RES 1 4 FUAP
3UA5 IUAK 2UAN
BC857BS(COL) BC857BS(COL)
7UF8 2 7UAA-1 7UAA-2 5
4K7 1% 100p
RT9193-33GB
3K3 1%

3UAT-4

3UAT-3
2UAM
3UA6

IUAJ 3

10K

10K
1u0
6
1 5 FUAU IUAV
+3V3-STANDBY
12K 1%
3UAV-4

IN OUT

3UAW

0R1
12K 1%
3UAV-1

3UAT-1

FUA0 IUFR
3 4
10K

EN BP 1UA2
+12VAL AMBI-POWER 3UAY
COM
T 2.0A 63V IUAN GND-AL
2UF6

2UF7

2UF8
1u0

22n

1u0

FOR DUAL SIDE AL ONLY 100R

2

5
6
7
8
IUAP
7UAC
4 SI4778DY-GE3
12K 1%
3UAV-2

1UA0 IUA0
PDZ15B(COL)

+12Va
1
2
3

REF 3
3UAT-2

6UAF T 3.0A 32V

6UAC
10K

+3V3-WIFI IUAR 6UAB

+12V 1 7UAB FUAT AMBI-POWER
B230LA-M3
BC847BW
FUAG S1D
9UA1-1 +3V3-WIFI 2 IUAS
1UA1 IUA1
9UA1-2 +12Vb
PDZ15B(COL)
330u 6.3V

9UA1-3
T 3.0A 32V
6UAD
RES 2UAV

9UA1-4
3UAS

2UAL

100p
10K

+12V
5UAA

IUAT 3u0
22u 16V
3UG0-2

3UG0-1

+3V3
RES
2UAP

2UA1
22K

22K

1u0

+3V3-STANDBY +3V3-STANDBY
AMBILIGHT 3-SIDED PROTECTION
IUF0
IUF1
3UA7

4
10K

GND-AL GND-AL
BC847BPN(COL)
3UAL

7UF7-2
RES

5
10K

IUAM IUA2 7UA2 RES

RES 9UA0 3UA8 PMV31XN
RES
3
100K IUF6 CUA0 ENABLE+1V5+1V1 7UAD
IUA3
3UA9
optional SIP32429DN-GE4
STANDBYn 7UA3
2UAD

RES 3UAC

3UAH
RES 3UAB
220K
100n

BC847BW 1 9
1R0

47K

AMBI-POWER
3UG0-3

3UG0-4

10K +12VAL
3UAK

2 VIN VOUT 10
22K

22K
RES
10K

2UAR

IUFS 4
1u0

IUFP EN
8
IUFT FLG
5
RSET
6 7
1X15 IUFU PG
STANDBY 3
REF EMC HOLE IUF3 3UG2 CSS
7UF7-1 2 DETECT12V
BC847BPN(COL) 3UG9 GND-AL GND
22K +3V3
2UAW
3UGA

100n

6
11

1
1K8

10K
2UAS

100n

GND-AL
GND-AL GND-AL

GND-AL

4 2012-11-22

Power connector
3104 313 6612

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 60

10-1-2 B01B, Fusion supply

Fusion supply
B01B B01B
5UC1 IUC0
+12Va
30R
2UCC
2UCA

2UCB

2
3
4
10
22u

22u

22u

5
6
7
8
+12Va
IUC1 IUC2 7UC2 1
3UC0 SI4778DY-GE3
4 9
RES

1
2
3
10R 7UC4
AON7932
8

3UC1
+5V

3R3

5
6
7
2UCE
2K2

10u
3UC2
2UCD
RES 3UC4

1R0

7UC1 IUC3
BC847BW
220p

PDZ5.6B(COL)
IUC4
6UC1

1 3UC3-1 8

2 3UC3-2 7

5
B340A-M3
6UC2

3UC3-3

3UC3-4
2UCP

5
6
7
8

10R

10R

10R

10R
10u

IUC5 7UC3
4 SI4172DY-GE3
270K 5%

4
RES

1
2
3
3UC7

7UC0 2UCF
RT8228DGQW 2UC1
7

VCC IUCB
IUC6 2UCH IUC7 3UC8 1n0 1n0
1 5 5UC2
BOOT
6 3R3
100n
9 NC 4
UGATE 2u0
16
IUC8 5UC0 FUC0
3
IUCP 14 PHASE +1V1-FD
3UC9 DBG 6UC0 DBG TON 2u0

2UCJ RES

2UCK RES

220u 2.5V
+5V 12 2
PGOOD LGATE

2UCW

2UCY
2UCL
22u

22u

22u

22u
2K2 IUCA
LTST-C190CKT 13 8
CS FB

ENABLE+1V5+1V1 11 10
EN MODE
2UCR RES

1%

GND GND_HS
3UCA

150K

15

17
1n0

GND-1V1F
CORE VOLTAGE SUPPLY FUSION
GND-1V1F GND-1V1F

GND-1V1F RES 2UCM

22p
3UCG 3UCB 3UCC FUC1
DVS1 IUC9 SENSE+1V1-FD
180K 1% 22K 1% 10R
120K 1%
12K 1%

22K 1%
3UCR RES

3UCD RES
3UCN +1V1-FD
3UCP

3UCE

3UCF
1M0

10R
220K 1% 2UCN

1u0

GND-1V1F GND-1V1F GND-1V1F

4 2012-11-22

Fusion supply
3104 313 6612

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 61

10-1-3 B01C, LNB supply

LNB supply
B01C B01C

+12V +12V-DVBS
1UP1

T 3.0A 32V
+12V-DVBS
2UPL RES

5UP6
100n

30R

IUPJ
10u 25V
RES 2UPM
2UPC

2UPD

2UPE
100n

10u

10u

5UP5

10u
7UP2
17

LNBH25LPQ
VCC
IUP4 +V-LNB
LX
3
IUPF 2UPJ
16
VBYP
470n

B230LA-M3
21
VUP

RS1D
6UP6

6UP5
6
ADDR FUPA
20 +V-LNB
3UPB VOUT
SCL-FE 7
SCL
B230LA-M3

47R 1 IUPE
3UPD
2UPK

6UP4
220n

SDA-FE 8 DSQ 5
SDA
47R 10
11
47u 25V

47u 25V
2UPG
2UPH
2UPF

NC 12
1u0
F22-DISECQ-TX 22 13
DSQIN
14
24
26
27
28
IUP2 29
3UPE 9 VIA 30
ISEL
22K 31
32
GND_HS

33
PGND

GND
2
15
18
19
23

25

4 2012-11-22

LNB supply
3104 313 6612

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 62

10-1-4 B01D, USB internal

USB internal
B01D 9EHE-1 RES
9EHE-2 RES
9EHE-3 RES
9EHE-4 RES
B01D

2EHL

10u
7EH2
RT9187GSP

1 3
+3V3-LAN
2 VIN VOUT 4

100u 6.3V
33K 1%
+3V5-STANDBY

3EHW

3EHY

RES 2EHY
8 5

1M0
EN BP|ADJ
7
NC

2EHM
10

10u
VIA IEH3
GND

10K 1%
3EM0

3EM1
GND HS

1M0
6

9
ENABLE-WOLAN

7EH4 RES
reserved TPS61200DRCG4
USB1-DM 9EM1 USB-WIFI-DM
5 2
+3V3-WIFI VIN VOUT
2EHV
USB1-DP 9EM2 USB-WIFI-DP 8 1 IEH0 RES
PS VAUX
RES 2EHR

RES 2EHS

2EHT
22u

22u

22u
100n IEH1
6 10
EN FB

RES
22K 1%
9EM3
7
UVLO

3EHR
3EHS
2EHU RES

330K
12

GND_HS
IEH2
RES 5EH0

VIA
3 13

PGND
L

GND

RES

RES
1n0
4u7

11
+3V3
2EM3

100n

+3V5-STANDBY
2EM4

2EM5

2EM6

2EM7
100n

100n

100n

100n

2EH9 IEH4 3EHU

7EHJ
BC847BW
2EM0 47n 22K

3EHT RES

120K 1%
18p

22K
7EM1
27

14

21
1EM0

RES 3EHP
CY7C65632-28LTXCT
12M

5
9
VCC

VCC_A_1
VCC_A_2
VCC_A_3

VCC_D

10 2EHJ IEH6
2EM1 XIN IEH5 3EHV
IEHJ
11
18p XOUT 100n 47K

2EHW

cEH0
1

10n
D- USB1-DM

3EHJ

100K
USB-WIFI-DM 3 2 USB1-DP
DD1- D+
4
RES
USB-WIFI-DP DD1+
3EM6 25
+3V3 OVR1 2EHN
10K RES
+3V3-LAN
USB-CAM-DM 6 26
DD2- SDA 100n
USB-CAM-DP 7 RES 9EH8-1
DD2+
3EM7 24 RES 9EH8-2
+3V3 OVR2
10K RES 9EH8-3
12 RES 9EH8-4
DD3- +3V3
13 18
DD3+ TEST|SCL
3EM8 20
+3V3 OVR3
10K
15
DD4-
16 1C31
DD4+
3EM9 19 FEH1
+3V3 OVR4 1
10K 30 USB-WIFI-DM FEH2
VIA1 2
28 31 USB-WIFI-DP FEH3
VREG VIA2 3
RESET-FUSION-OUTn 17 32 FEH4
RESET VIA3 4
3EM3 IEM1 22 33 IRQ-WOLANn FEH5
+3V3 SELFPWR VIA4 5
10K 23
GND_HS

3EM4 GANG 6
8 8 7
RREF
680R IEM2
A1253WRA
29

+3V3
3EM5

100K

RES 3EHN
+3V3-LAN
2EM2

100n

10K
RES 2EHP

100n

1C30
FEH6
+5V 1
USB-CAM-DM FEH7
2
USB-CAM-DP FEH8
3
FEH9
4
5
7 6

A1253WRA

4 2012-11-22

USB internal
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 63

10-1-5 B01E, Miscellaneous

Miscellaneous
B01E B01E

RES
1T71
FTA1 3TA1 FTA2
SCL-SRF 1
RES 10R
FTA3 3TA2 FTA4 2
SDA-SRF FTA6
3
RES 10R
4
RES 2TA1

RES 2TA2
10p

10p

A1253WRA

RES 5TA1
+3V3 FTA5
30R
RES 2TA3

1u0
T 1.0A 63V
RES
1TA1

RES 5TA2
+12V ITA1
30R
TEMPERATURE
5TA3
SENSOR
+3V3-STANDBY
30R

4 2012-11-22

Miscellaneous
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 64

10-1-6 B02A, Hybrid T/C tuner

Hybrid T/C tuner

B02A B02A
VCC-TUNER

22u 16V
5FA1

2FA5
30R
1FA0 DBG

2FA7

2FA8

100n
10p
2
3 1F00
5 4 SUT-RE214Z

15

14
BM03B-SRSS-TBT
2FAA FFA9 1
5FA7 3FA1 A3.3V
SDA-FE FFA6 10p FFA2 2
IF1_P
SCL-FE FFA7 30R 5FA6 100R 3FA2 FFA3 3
IF1_N
30R 2FA9 4
100R AGC1

TUNER
10p 5
NC1
SOC-IF-N 3FA3 5FA4 6
NC2
SOC-IF-P 47R 3FA4 330n 5FA5 7
IF2_P
47R 330n 8
IF2_N
9
AGC2
10
I2C_SCL
11
I2C_SDA

2FAC
2FAB

12

13

16
10p

10p
FFAA

3KA0 5KA1
7FAA IF-N-DVBT2
LD1117S33 IF-P-DVBT2 47R 3KA1 330n 5KA0
5FAA IFAA 2 330n
FFAE 47R
+5V 3 4 VCC-TUNER
IN OUT

2FAG

2FAH
10p

10p
30R FFA8 FFA4
330u 6.3V

COM
2FA0

2FA1

2FA2

2FA3
100n
10u

1n0

RES
1

FFAD

IF-AGC-DVBT2 3KA3

100R

2FAF

3KA5

22K
10p

RES 3KA4 FFA5 RES 3FA7

IF-AGC-DVBT2 FFAB
100R 100R
SOC-IF-AGC
2FAD

3FAD

2FAE
RES 3KA2

RES 3FA8
6K8

6K8

2K7
22n

10p
IFA6

AGC-SWITCH FFAC
3FA9

2K7

7KA0
PDTA114EU
RES

VCC-TUNER

6 IFA3 3

7FA1-1 2 5 7FA1-2
BC857BS(COL) BC857BS(COL)
1 4

IFA5 IFA4
3FAC
3FAA

3FAB
470R

470R
10K

VCC-TUNER

4 2012-11-22

Hybrid T/C tuner

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 65

10-1-7 B02B, Satellite tuner

Satellite tuner
B02B B02B

IRB0 3RB3 IRB1

+3V3-DVBS * 9RB9
* 4R7

2RBU
2RBK

2RBV
2RBL

2RB2

2RB3

2RB4

2RB5

2RB6

2RB7
100n

100n
22u

10n

1n0

1n0

1n0

4n7

10u

68p
* * *

2RBE
7RB0
STV6110AT 6 8 11 14 22 27 28
10p 3
2 NC 4

LNA LT MIX DIG BB VCO SYN

NX3225JB

2RB8 3RB0
1RB0

30 VSS 32
16M

XTAL_OUT XTAL
XTAL_IN 100p 1K0
1 31 18 4 5 DVBS-IP
2RBF IP
19 3 6 3RB1-4 100R
IN DVBS-IN
1 3RB1-3 100R
10p XTAL_CMD
2RK0 RES SATELLITE 21 1 8 DVBS-QP
QP
SCL-S-TUNER 10p 12 TUNER 20 2 7 3RB1-1 100R DVBS-QN
Diversity Matrix (Satellite Tuner dependant) SDA-S-TUNER 13
SCL
SDA
QN
3RB1-2 100R
2RK1 RES 2RBD I2C-ADDRESS : C6 RF_OUT
7

10p

10p

10p

10p

10p

10p

10p

10p
DVBS-AGC 10p 3n3 2
AGC
34
Position Nr Affected Pin Default Value STV6110 STV6111

2RBW
9RB0 16 35

33n

2RBC

2RBN

2RBR
2RBA

2RBB

2RBP

2RBS
2RB9
AS

- RES 36
2RBY 4,5 100P X 23 37
+3V3-DVBS
NC *
-
24 VIA 38
9RB8 4,5 JUMP X 39

-
1R01 40
2RBM 4,5 27P X 1 * 2RBM
4
RF_IN
41
42
-
6 2
27p
2RB1 4,5 27P X 7 3

-
2RBY

GND
100p

8 4
2RBW 7 33N X 9 5 RF LNA LT MIX DIG BB VCO SYN HS
5RB0

- 10 5 3 9 10 15 17 25 26 2 9 33
27n

9RB6 25 JUMP X *
9RB7 25 JUMP - X FRB0
* 2RB1
RES 2RBG

9RB6

9RB7

-
0p56

+V-LNB
2RB7 27 10U X 27p

- * *
SM15T

2RBH

2RBU
RES 2RBT

6RB0

9RB8
2RBJ

X
100p

27 4N7
47p

1n0

2RBV 27 68P - X
* +3V3-DVBS

9RB9 27 JUMP X -
3RB3 27 4R7 X 2K2

4 2012-11-22

Satellite tuner
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 66

10-1-8 B02C, DVBT2 channel decoder

DVBT2 channel decoder

B02C B02C

+3V3-DVBT2-D

+1V2-DVBT2-C +1V2-DVBT2-P
5KC9

30R
100n 2KC4
2KC7

2KC6

2KC5

IKCA
100n
100n
100n
100n

2KC3

2KC2

2KC1

2KC0
100n

100n

100n
2KCC

2KCB
12p

12p

7KC0 RES 2KCK

10
22
28
44

19
42

32

41M CXD2834ER
7

3 1
IKC0 CVDD DVDD PVDD 3KC1 6p8
35 5 TS-CHDEC-CLK
NC 2 XTALI TSCLK
4 4 47R 8 1 3KC0-1 TS-CHDEC-VALID
5KC0 1KC0 3KC4 IKC1 TSVALID
34 3 7 2 3KC0-2 47R TS-CHDEC-SOP
XTALO TSSYNC
1K0 47R SENSE+1V1-DVBT2 +1V2-DVBT2-C
4u7 2KCD
8 6 3 3KC0-3 TS-CHDEC-DATA
2KCE IKC2 3KCA 0
IF-P-DVBT2 9KC0 47p 38 9 47R
TAINP 1
IF-N-DVBT2 9KC1 100n 2KCF 47R 3KCB 37 12 IKC8
TAINM 2 5KCA
100n 2KCG IKC3 13 +1V2-FE +1V2-DVBT2-C
47R 3
47p TSDATA 14
5KC1 4 30R

AGC-SWITCH 4u7
3KC6
41
RFAIN I2C 5
15
16
RES 5KC5 IKC7 RES 5KC7
6 VCC-TUNER +3V3-DVBT2-D +1V1-DVBT2
1K0 ADDRESS 7
17
30R 30R
2KCH
RES

1
10n

DKC0 GPIO0 = 3KC2 5KC6

2KCR
47 20

1u0
GPIO1 SCL SCL-FE +3V3
2 21 47R 3KC3 SDA-FE
IKC4 GPIO2 0XD8 SDA
47R
30R

2KCP
50

1u0
3KC7 48 51
IF-AGC-DVBT2 TIFAGC
2KCJ 52
10K
100n 53
3KC8 IKC5
+3V3-DVBT2-D 46 54 IKC9
IKC6 TTUSCL 3KCE
3K3 3KC9 45 55 +1V2-DVBT2-C +1V2-DVBT2-P
TTUSDA
3K3 56 22R
57

2KCS
24 58

10u
TESTMODE
59
60
25 61
SLVADR0
VIA 62
63
26 64
DKC1 OSCEN_X
65
66
RESET-FUSION-OUTn 29 67
RST_X
68
69
30 70
SLVADR3
71
RES 72
5KC8
+3V3-DVBT2-D 33 73
NC1
IKCB 40 74
30R NC2
VSS
7KC0 +1V1-DVBT2
GND_HS
2KCL

100n

6
11
18
23
27
31
36
39
43

49

FKC1 CXD2834 +1V2

RES

GAIA3 +1V1

4 2012-11-22

DVBT2 channel decoder

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 67

10-1-9 B02D, DVBS/S2 channel decoder

DVBS/S2 channel decoder

B02D B02D

+3V3-DEMOD +3V3-ANA
5RDD IRD2

100n
100n
+1V2-FE

2RD6

100n
30R

2RD4

2RD5
RES 2RDK

2RDL

2RD0

2RD1

2RD2

2RD3
RES 2RDJ

100n

100n

100n

100n
22u

22u

22u
1RD0
NX3225JB

2 NC 4
1 3

20
28
48

VDD_VIO 22

36
7RD0

9
SI2169-A10-GM

VDD_VANA
16M
VDD_VCORE
RES 2RDD
RES 2RDE

33
10p

10p

XTA_I|CLK_IN
7RDA
LD1117S33 32
XTA_O
IRDA 2
5RDA FRDA
+5V 3 4 +3V3-DVBS 44
IN OUT CLK_IN_OUT
2RDB 13 3RD0-2 2 7 TS-DVBS-SOP
16V

30R 100n TS_SYNC

COM XTAL 3RD6 31 12 3RD0-1 1 8 47R TS-DVBS-VALID
RESETB TS_VAL
2RDP

2RDR
100n

10K 26
+3V3-DEMOD TS_ERR|GPIO_1 47R
22u

1 3 14 3RD1 TS-DVBS-CLK
GPIO_0|JTAG_TMS TS_CLK
RESET-FUSION-OUTn
47R
34 15 3RD0-3 3 6 TS-DVBS-DATA
ADDR TS_DATA0|TS_SER
AGC-SWITCH 9RD3 16
TS_DATA1 47R
43 17
RSSI_ADC TS_DATA2

RES 2RDC
DVBS-QP 2RD7 37 18

6p8
S_ADC_IP TS_DATA3
DVBS-QN 100n 2RD8 38 19
S_ADC_IN TS_DATA4
DVBS-IN 2RDA 100n 39 23
S_ADC_QP TS_DATA5
DVBS-IP 100n 2RD9 40 24
S_ADC_QN TS_DATA6
100n 25
3RD2 TS_DATA7
IRDB IF-AGC-DVBT2 9RD2 1
5RDB MP_A
2RDH 2 11 IRD0 3RD8 SDA-FE
+3V3-DVBS +3V3-DEMOD 10K DRD0 MP_B SDA_HOST
100n 29 10 IRD1 47R 3RD7 SCL-FE
30R 3RD3 DRD1 MP_C SCL_HOST
DVBS-AGC 30 47R
MP_D
2RDS

50
22u

10K
IF-P-DVBT2 9RD0 2RDF 41 51
TC_ADC_P
IF-N-DVBT2 9RD1 100n 2RDG 42 52
TC_ADC_N
100n 53
3RD4 IRD5
SDA-S-TUNER 45 54
SDA_MAST VIA
SCL-S-TUNER 3RD5 47R IRD6 46 55
SCL_MAST
47R 56
+V-LNB 4 57
2RDT 3RD9 IRD3 DISEQC_CMD
5 58
DISEQC_IN
IRDC F22-DISECQ-TX 100p 1K0 6
5RDC DISEQC_OUT
+3V3-DVBS +3V3-ANA
3RDA RES

3RDB RES

8
30R GND1|JTAG_TCLK
21
GND2|JTAG_TDI
2RDM

2RDN

27
4K7

4K7
22u

10n

GND3|JTAG_TDO
47
GND4|JTAG_TRSTB
GND5 GND_HS
35

49

+3V3-DEMOD

4 2012-11-22

DVBS/S2 channel decoder

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 68

10-1-10 B03A, Fusion

Fusion
B03A B03A

7J00-6
FUSION240 7J00-7
FUSION240
AK23
FLASH_CI_GPIO AJ22
CA-D00
AF26
FRD0_PODD0 PODA4
AH22
CA-A04 TS_TSB_MCU AH18
CA-D01 FRD1_PODD1 PODA5 CA-A05 0 MDI0
CA-D02 AE24 AF22 CA-A07 AJ18 MDI1
FRD2_PODD2 POD_A7 1
CA-D03 AK25 AJ23 CA-A08 AK18 MDI2
FRD3_PODD3 POD_A8 2
CA-D04 AH25 AH23 CA-A09 AE19 MDI3
FRD4_PODD4 POD_A9 3
CA-D05 AH27 CA-MDO0 AG20 TS2OD AF19 MDI4
FRD5_PODD5 0 4
CA-D06 AK27 AE27 CA-RDY CA-MDO1 AH20 AG19 MDI5
FRD6_PODD6 PODIREQ 1 5
CA-D07 AJ25 AG30 CA-RST CA-MDO2 AJ20 AH19 MDI6
FRD7_PODD7 PODRST 2 6
CA-A00 AF25 AF30 CA-VS1n CA-MDO3 AK20 AJ19 MDI7
FRD8_PODA0 PODVS1 3 7
CA-A01 AG26 AE28 CA-WAITn CA-MDO4 AE21 TS1D
FRD9_PODA1 PODWAIT 4
CA-A02 AK26 AE30 CA-MDO5 AF21 AK19 MICLK
FRD10_PODA2 POD_DIR FJ16 5 TS2OCLK
CA-A03 AG25 CA-MDO6 AG21 AE20 MISTRT
FRD11_PODA3 6 TS2OSYNC
CA-A10 AE25 AD28 CA-CE1n CA-MDO7 AH21 AF20 MIVAL
FRD12_PODA10 PODCE1 7 TS2ODEN
CA-A11 AH26 AD27 CA-CE2n
FRD13_PODA11 PODCE2 2FZ5
CA-A12 AH28 AF29 CA-CD1n CA-MOCLK AJ21
FRD14_PODA12 PODCD1 TS1CLK 3FZ0
CA-A13 AF24 AD30 CA-CD2n CA-MOSTRT AK21 F27 4n7 SOC-IF-AGC
FRD15_PODA13 POD_CD2 TS1SYNC TAGCO_IF
CA-MOVAL AE22 G26 100R
TS1DEN TAGCO_RF FJ10
AE29
POD_VCC_EN
FRA0 AG29 AD29 T28
FRA0_AD0 POD_VPP_EN DGPIO1
CA-WEn AD26 TS-CHDEC-DATA U28 T29
FRA1_PODWE TSSDI DGPIO2
CA-IORDn AH29 TS-CHDEC-CLK U29
FRA2_PODIORD TSSCLK
CA-IOWRn AJ29 R30 TS-CHDEC-SOP U30
FRA3_PODIOWR HPD TSSSYNC
CA-REGn AF28 TS-CHDEC-VALID T26 M27 STB-GP0
FRA4_PODREG TSSDEN 0
FRA5 AH30 B7 GPIO0 IF-IN-P M26 STB-GP1
FRA5_AD1 GPIO0 10p 1
FRA6 AG28 B10 GPIO1 RES 2FZ6 M25 STB-GP2
FRA6_AD2 GPIO1 2FZ1 2
FRA7 AJ30 C10 GPIO2 IF-IN-N 47p F30 N30 STB-GP3
FRA7_AD3 GPIO2 10p P 3
FRA8 AJ28 C9 GPIO3 F29 IN N29 STB-GP4
FRA8_AD4 GPIO3 2FZ2 N 4
CA-OEn AJ27 B9 N28 STB-GP5
FRA9_PODOE GPIO4 STB_GP 5
FRA10 AF27 B8 GPIO5 100n E28 N27 STB-GP6
FRA10_AD5 GPIO5 2J10 P 6
FRA11 AG27 A7 GPIO6 100n 2FZ3 E27 PD N26 STB-GP7
FRA11_AD6 GPIO6 N 7
FRA12 AG24 B11 GPIO7 2FZ4 N25 STB-GP8
FRA12_AD7 GPIO7 18p 8
NAND-CLE AE23 A11 GPIO8 P25 STB-GP9
FRA13_CLE GPIO8 9
3

AK22 A10 H30 P26

24M

NAND-ALE FRA14_ALE GPIO9 XTLI24M 10 STB-GP10

1J00

CA-A14 AJ26 C11

FRA15_PODA14 GPIO10
A9 GPIO11 2 H29 R28 STB-RXD
GPIO11 2J11 XTLO24M STB_RXD
4 R27 STB-TXD
1

STB_TXD
F-OEn AK29 P27 STB-SDA
FOE 18p STB_SDA
F-WEn AK24 A13 3FZ1 GPIO14 RESET-STANDBYn J26 P28 STB-SCL
FWE GPIO14 RSTN STB_SCL
C12 GPIO15
GPIO15 33R
F-CEn AJ24 D12 GPIO16 J25 LED
BOOTCS GPIO16 LED
TS-DVBS-DATA AE26 C13 GPIO17 TEST-CON P30 M29 IR
FCE2N GPIO17 TESTCON IR
TS-DVBS-VALID AF23 E10 GPIO18 TEST-MOD P29 J30 KYBRD
FINT1 GPIO18 TESTMOD KYBRD
TS-DVBS-SOP AK28 D11 GPIO19 M30 LGSEN
FINT2 GPIO19 LGSEN
TS-DVBS-CLK AH24 E11 GPIO20 ENABLE-STANDBY H25 M28 HDMI-CEC
FCLK GPIO20 STB_EN CEC
CA-A06 AG22 B12 GPIO21 R29 PWRON
FAVD_PODA6 GPIO21 PWRON
F-RDY AG23 A12 GPIO22
FREADY GPIO22
B13 GPIO23 SPI-EN K28 K25 AVLINK1
GPIO23 SPI_EN 1
D10 GPIO24 SF-SDI L28 AVLINK K26 AMBI-TEMP-FUS
GPIO24 SFSI 2
SF-SDO L26
SFSO
SF-WP K30 J27
SFWPN PCVS
SF-HOLDn L27 J28
SFHOLDN PCHS
SF-CS L29
SFCES
SF-CLK L30 J29 STB-RSTO
SFSCK STB_RSTO
K27 HP-DETECT
HP_DETECT
H26 AUDIO-MUTEn
MUTE

4 2012-11-22

Fusion
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 69

10-1-11 B03B, Fusion Umac controller

Fusion Umac controller

B03B 7J00-8
FUSION240
DDR3
B03B
M0-MD0 DB71 AH8 P2 M1-MD0
0 0
M0-MD1 AH5 V2 M1-MD1
1 1
M0-MD2 AH7 R1 M1-MD2
2 2
M0-MD3 AJ5 V1 M1-MD3
3 3
M0-MD4 AK8 R3 DB79 M1-MD4
4 4
M0-MD5 AH6 U1 M1-MD5
5 5
M0-MD6 AJ8 P1 M1-MD6
6 6
M0-MD7 AK5 U3 M1-MD7
7 7
M0-MD8 AK11 L5 DB78 M1-MD8
8 8
M0-MD9 DB72 AF9 R4 M1-MD9
9 9
M0-MD10 AJ11 L4 M1-MD10
10 10
M0-MD11 AG9 P5 M1-MD11
11 11
M0-MD12 AF10 M5 M1-MD12
12 12
M0-MD13 AG8 R5 M1-MD13
13 13
M0-MD14 AH10 M4 M1-MD14
14 14
M0-MD15 AH9 P4 DB77 M1-MD15
15 15
M0-MD16 AG1 MM0DQ MM1DQ W1 M1-MD16
16 16
M0-MD17 AF3 AB1 DB76 M1-MD17
17 17
M0-MD18 AE3 Y3 M1-MD18
18 18
M0-MD19 AH1 AB3 M1-MD19
19 19
M0-MD20 AH2 Y1 M1-MD20
20 20
M0-MD21 AD3 AC2 M1-MD21
21 21
M0-MD22 AD1 Y2 M1-MD22
22 22
M0-MD23 AD2 AC1 M1-MD23
23 23
M0-MD24 AK4 U5 M1-MD24
24 24
M0-MD25 AG3 AA4 M1-MD25
25 25
M0-MD26 AJ3 T5 M1-MD26
26 26
M0-MD27 AK2 Y5 M1-MD27
27 27
M0-MD28 AK3 U4 M1-MD28
28 28
M0-MD29 AJ2 W5 DB75 M1-MD29
29 29
M0-MD30 AG5 V5 M1-MD30
30 30
M0-MD31 DB74 AJ1 Y4 M1-MD31
31 31

M0-DQM0 AJ6 T1 M1-DQM0

0 0
M0-DQM1 AK9 P3 M1-DQM1
1 1
M0-DQM2 AE1 MM0DM MM1DM AA1 M1-DQM2
2 2
M0-DQM3 AH3 W3 M1-DQM3
3 3

M0-DQS0 AK7 T2 M1-DQS0

P P
M0-DQS#0 AK6 MM0DQS0 MM1DQS0 T3 M1-DQS#0
N N
M0-DQS1 DB14 AJ10 N3 DB46 M1-DQS1
P P
M0-DQS#1 DB16 AK10 MM0DQS1 MM1DQS1 N4 DB47 M1-DQS#1
N N
M0-DQS2 AF2 AA3 M1-DQS2
P P
M0-DQS#2 AF1 MM0DQS2 MM1DQS2 AA2 M1-DQS#2
N N
M0-DQS3 AH4 V4 M1-DQS3
P P
M0-DQS#3 AG4 MM0DQS3 MM1DQS3 V3 M1-DQS#3
N N

M0-MA0 AJ12 L2 M1-MA0

0 0
M0-MA1 AJ17 F2 M1-MA1
1 1
M0-MA2 AK15 H1 M1-MA2
2 2
M0-MA3 AH15 H3 M1-MA3
3 3
M0-MA4 AH17 F3 M1-MA4
4 4
M0-MA5 AF15 H5 M1-MA5
5 5
M0-MA6 AF17 F5 M1-MA6
6 6
M0-MA7 AJ15 H2 M1-MA7
7 7
M0-MA8 AH16 MM0A MM1A G3 M1-MA8
8 8
M0-MA9 AG17 F4 M1-MA9
9 9
M0-MA10 AF13 K5 M1-MA10
10 10
M0-MA11 AK16 G1 M1-MA11
11 11
M0-MA12 AK12 L1 M1-MA12
12 12
M0-MA13 AF16 G5 M1-MA13
13 13
M0-MA14 AK17 F1 M1-MA14
14 14
M0-MA15 AJ13 K2 M1-MA15
15 15
+1V5-M0 M0-BA0 AG12 M1 M1-BA0
0 0
M0-BA1 AF14 J5 M1-BA1 +1V5-M1
1 MM0BA MM1BA 1
M0-BA2 AK13 K1 M1-BA2
2 2
M0-CAS# AH12 L3 M1-CAS#
MM0CASN MM1CASN
M0-RAS# AF12 M3 M1-RAS#
MM0RASN MM1RASN
M0-WE# AF11 N2 M1-WE#
MM0WEN MM1WEN
M0-CKE AH13 K3 M1-CKE
MM0CKE MM1CKE
M0-ODT AG11 N1 M1-ODT
MM0ODT MM1ODT
M0-RESET# AG15 H4 M1-RESET#
MM0RESETN MM1RESETN
100n
2J06

3J05

AG14 J4
1K0

M0-CS# MM0CSN MM1CSN M1-CS#

100n
3J03

2J04
1K0
M0-MCLK0 AK14 J1 M1-MCLK0
P P
M0-MCLK0# AJ14 MM0CK MM1CK J2 M1-MCLK0#
N N
FJ05
M0-MVREF0 M0-MVREF0 AE11 U7
0 0 FJ04
AE12 MM0VREF MM1VREF U6 M1-MVREF1 M1-MVREF1
1% 240R 1 1 240R 1%
AE7 T7
MZQ0 MZQ1
3J00 AD18 E1 3J01
MM0ANA_TEST MM1ANA_TEST
100n

100n
2J07

3J06

2J05

AA7
1K0

DDR_RETN
100n

100n
2J02

3J04

2J03
1K0
FJ01 DB73 FJ03
MM0ANA MM0ANA MM1ANA MM1ANA
FJ02
+1V5-M1
3J02

1K0

DDR-RTN
100p
2J00

DB80 DB85

DB81 DB86

DB82 DB87

DB83 DB88

DB89

4 2012-11-22

Fusion Umac controller

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 70

10-1-12 B03C, Umac 1 DDR3

Umac 1 DDR3
B03C B03C
+1V5-M1

+1V5-M1
7J01 +1V5-M1

G7
D9

N1
N9
R1
R9

C1
C9
D2

H2
H9
B2

K2
K8

A1
A8

E9
F1
H5TQ2G63BFR-PBC
VDD VDDQ
M1-MA0 M1-MA0 N3
0
3J18 3J19 M1-MA1 P7
1
M1-MA1 100R 100R M1-MA2 P3 7J02
2

G7
D9

N1
N9
R1
R9

C1
C9
D2

H2
H9
B2

K2
K8

A1
A8

E9
F1
3J1A 3J1B M1-MA3 N2 H5TQ2G63BFR-PBC
3
M1-MA2 100R 100R M1-MA4 P8 D7 M1-MD1 VDD VDDQ
4 0
3J1C 3J1D +1V5-M1 M1-MA5 P2 C3 M1-MD4
5 1
M1-MA3 100R 100R M1-MA6 R8 A C8 DB40 M1-MD3 M1-MA0 N3
6 2 0
3J1E 3J1F M1-MA7 R2 C2 M1-MD6 M1-MA1 P7
7 3 1
M1-MA4 100R 100R M1-MA8 DB31 T8 DQU A7 M1-MD5 M1-MA2 P3
8 4 2
3J1G 3J1H M1-MA9 R3 A2 M1-MD0 M1-MA3 N2
9 5 3
M1-MA5 100R 100R M1-MA10 L7 B8 M1-MD7 M1-MA4 P8 D7 M1-MD21
10 6 4 0
3J1J 3J1K M1-MA11 DB32 R7 A3 DB41 M1-MD2 M1-MA5 P2 C3 DB56 M1-MD22
11 7 5 1
M1-MA6 100R 100R M1-MA12 N7 M1-MA6 R8 A C8 M1-MD23
3J1M 12 6 2
3J1L M1-MA13 DB33 T3 C7 DB42 M1-DQS0 M1-MA7 DB49 R2 C2 M1-MD16
13 DQSU 7 3
100n
2J16

3J11

100R 100R DB34 T7 B7 T8 DQU A7

1K0

M1-MA7 M1-MA14 DB43 M1-DQS#0 M1-MA8 DB50 M1-MD17

3J1P 14 DQSU 8 4
3J1N M1-MA15 M7 M1-MA9 R3 A2 M1-MD18
15 9 5
M1-MA8 100R 100R F3 DB44 M1-DQS1 M1-MA10 L7 B8 DB57 M1-MD19
3J1R BC DQSL 10 6
3J1Y G3 DB45 M1-DQS#1 M1-MA11 R7 A3 M1-MD20
AP DQSL 11 7
M1-MA9 100R 100R M1-MA12 N7
FJ08 12
3J1S 3J1T DDR-MVREF11 DDR-MVREF11 H1 E3 M1-MD14 M1-MA13 DB51 T3 C7 M1-DQS2
VREFDQ 0 13 DQSU
M1-MA10 100R 100R M8 F7 M1-MD15 M1-MA14 DB52 T7 B7 M1-DQS#2
VREFCA 1 14 DQSU
3J1U 3J1V F2 M1-MD12 M1-MA15 M7
2 15
100n

100n
2J14

2J15

M1-MA11 100R 100R L8 F8 M1-MD11 F3 DB58 M1-DQS3

ZQ 3 BC DQSL
100n
2J17

3J12

3J1W 3J1Z DQL H3 G3

1K0

M1-MD8 DB59 M1-DQS#3

4 AP DQSL
240R
3J10

M1-MA12 100R 100R M2 H8 DB48 M1-MD9

BA0 5
3J20 3J21 N8 G2 M1-MD10 DDR-MVREF12 H1 E3 M1-MD28
BA1 6 VREFDQ 0
M1-MA13 100R 100R DB62 M3 H7 M1-MD13 M8 F7 M1-MD31
BA2 7 VREFCA 1
3J22 3J23 DB63 F2 M1-MD30
2

100n

100n
2J18

2J19
M1-MA14 100R 100R M1-BA0 J3 L8 F8 M1-MD27
RAS ZQ 3
3J24 3J25 M1-MCLK0 M1-BA1 DB90 K1 DQL H3 M1-MD26
ODT 4

240R
3J13
M1-MA15 100R 100R M1-BA2 DB35 K3 M2 H8 M1-MD25
CAS BA0 5
3J26 3J27 M1-RAS# DB36 J7 N8 G2 M1-MD24
CK BA1 6
M1-BA0 100R 100R +1V5-M1 M1-ODT DB38 K7 J1 M3 H7 M1-MD29
CK BA2 7
3J28 3J29 M1-CAS# K9 J9
CKE DB64 DB65
3J16

100R 100R L2 L1 J3
75R

M1-BA1 M1-MCLK0 DB91 NC M1-BA0 DB53

3J2B CS RAS
3J2A M1-MCLK0# DB39 L3 L9 M1-BA1 K1
WE ODT
2J12

100R 100R T2 DB54 K3

10n

M1-BA2 RES M1-BA2

3J2D RESET CAS
3J2C M1-RAS# J7
CK
M1-RAS# 100R 100R M1-CKE DB92 E7 M1-ODT K7 J1
3J2F DML CK
3J2E M1-CS# D3 M1-CAS# K9 J9
DMU VSS VSSQ CKE
M1-CAS# 100R 100R M1-WE# M1-MCLK0 L2 NC L1
3J2H CS
2J89

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

3J2G DB55 L3 L9
10n

M1-RESET# M1-MCLK0# WE
3J17

100R 100R T2
75R

M1-WE# RESET
3J2J 3J2K M1-DQM1 DBA8
M1-CS# 100R 100R M1-DQM0 M1-CKE E7
DML
3J2L 3J2M M1-CS# D3
DMU VSS VSSQ
M1-ODT 100R 100R M1-WE#
3J2P

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9
3J2N M1-RESET#
M1-CKE 100R 100R M1-MCLK0#
3J2Q 3J2R M1-DQM3
M1-RESET# 100R 100R M1-DQM2
3J2S 3J2T
DB66
100R 100R +1V5-M1

2J1A
100n
3J14
1K0

FJ09
DDR-MVREF12
2J1B
100n
3J15
1K0

+1V5-M1 +1V5-M1

DB93 DB98 DBA3

DB94 DB99 DBA4

2J1M

2J1G
2J1R

2J1C
2J1P

2J1V

2J1E
100n

100n

100n
2J1T

100n

100n
2J1Z

100n

100n
2J22

2J81

2J82

2J83

2J84

2J21

2J1J
10u

10n

10n

10n

10n

10n

10n

10n

10n

DB95 DB01 DBA5

DB96 DBA1 DBA6

DB97 DBA2 DBA7

+1V5-M1 +1V5-M1
47u 16V

2J1W
2J1Q
2J1N

2J1U

2J1D

2J1H
2J1S

2J1K
100n

100n

100n

100n

100n

100n

100n

2J1F
2J27

2J24

2J25

2J1L

2J85

2J86

2J87

2J88

2J20
10u

10u

10n

10n

10n

10n

10n

10n

10n

10n

4 2012-11-22

Umac 1 DDR3
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 71

10-1-13 B03D, Umac 0 DDR3

Umac 0 DDR3
B03D B03D
+1V5-M0

+1V5-M0
7J03 +1V5-M0

G7
D9

N1
N9
R1
R9

C1
C9
D2

H2
H9
B2

K2
K8

A1
A8

E9
F1
H5TQ2G63BFR-PBC
VDD VDDQ
M0-MA0 M0-MA0 N3
3J35 0
3J34 M0-MA1 P7
M0-MA1
1
100R 100R M0-MA2 P3 7J04
2

G7
D9

N1
N9
R1
R9

C1
C9
D2

H2
H9
B2

K2
K8

A1
A8

E9
F1
3J36 3J37 M0-MA3 N2 H5TQ2G63BFR-PBC
3
M0-MA2 100R 100R M0-MA4 P8 D7 M0-MD0
4 0 VDD VDDQ
3J38 3J39 +1V5-M0 M0-MA5 P2 C3 M0-MD5
5 1
M0-MA3 100R 100R M0-MA6 R8 A C8 DB09 M0-MD4 M0-MA0 N3
6 2 0
3J3A 3J3B M0-MA7 R2 C2 M0-MD7 M0-MA1 P7
7 3 1
M0-MA4 100R 100R M0-MA8 DB61 T8 DQU A7 M0-MD2 M0-MA2 P3
8 4 2
3J3C 3J3D M0-MA9 R3 A2 M0-MD1 M0-MA3 N2
9 5 3
M0-MA5 100R 100R M0-MA10 L7 B8 M0-MD6 M0-MA4 P8 D7 M0-MD16
10 6 4 0
3J3E 3J3F M0-MA11 DB00 R7 A3 DB10 M0-MD3 M0-MA5 P2 C3 DB25 M0-MD18
11 7 5 1
M0-MA6 100R 100R M0-MA12 N7 M0-MA6 R8 A C8 M0-MD20
12 6 2
3J3G 3J3H M0-MA13 DB02 T3 C7 DB11 M0-DQS0 M0-MA7 DB18 R2 C2 M0-MD23
13 DQSU 7 3
2J2A

3J2V
100n

100R 100R DB03 T7 B7 T8 DQU A7

1K0

M0-MA7 M0-MA14 14 DQSU DB12 M0-DQS#0 M0-MA8 DB19 8 4 M0-MD17

3J3J 3J3K M0-MA15 M7 M0-MA9 R3 A2 M0-MD21
15 9 5
M0-MA8 100R 100R F3 DB13 M0-DQS1 M0-MA10 L7 B8 DB26 M0-MD19
BC DQSL 10 6
3J3L 3J3M G3 DB15 M0-DQS#1 M0-MA11 R7 A3 M0-MD22
AP DQSL 11 7
M0-MA9 100R 100R M0-MA12 N7
FJ0A 12
3J3N 3J3P DDR-MVREF01 DDR-MVREF01 H1 E3 M0-MD15 M0-MA13 DB20 T3 C7 M0-DQS2
VREFDQ 0 13 DQSU
M0-MA10 100R 100R M8 F7 M0-MD12 M0-MA14 DB21 T7 B7 M0-DQS#2
3J3R VREFCA 1 14 DQSU
3J3Y F2 M0-MD9 M0-MA15 M7
2 15
100n

100n
2J28

2J29

M0-MA11 100R 100R L8 F8 DB69 M0-MD10 F3 DB27 M0-DQS3

ZQ 3 BC DQSL
3J2W
2J2B

100n

3J3S 3J3T DQL H3 G3

1K0

M0-MD11 DB29 M0-DQS#3

4 AP DQSL
240R
3J2U

M0-MA12 100R 100R DB68 M2 H8 DB17 M0-MD14

1%

3J3V BA0 5
3J3U N8 G2 M0-MD13 DDR-MVREF02 H1 E3 M0-MD29
BA1 6 VREFDQ 0
M0-MA13 100R 100R M3 H7 M0-MD8 M8 F7 M0-MD28
BA2 7 VREFCA 1
3J3W 3J3Z F2 M0-MD25
2

2J2C

2J2D
100n

100n
M0-MA14 100R 100R M0-BA0 J3 L8 F8 DB30 M0-MD26
RAS ZQ 3
3J40 3J41 M0-MCLK0 M0-BA1 DBA9 K1 DQL H3 M0-MD27
ODT 4

240R
3J2Z
M0-MA15 100R 100R M0-BA2 DB04 K3 M2 H8 M0-MD30

1%
CAS BA0 5
3J42 3J43 M0-RAS# DB05 J7 DB67 N8 G2 M0-MD31
CK BA1 6
M0-BA0 100R 100R +1V5-M0 M0-ODT DB07 K7 J1 M3 H7 DB70 M0-MD24
CK BA2 7
3J44 3J45 M0-CAS# DBB0 K9 J9
CKE
3J32

100R 100R L2 L1 J3
75R

M0-BA1 M0-MCLK0 CS NC M0-BA0 DB22 RAS

3J46 3J47 M0-MCLK0# DB08 L3 L9 M0-BA1 K1
WE ODT
DBB1
2J01

100R 100R T2 DB23 K3

10n

M0-BA2 RES RESET M0-BA2 CAS

3J48 3J49 M0-RAS# J7
CK
M0-RAS# 100R 100R M0-CKE DBB2 E7 M0-ODT K7 J1
DML CK
3J4A 3J4B M0-CS# D3 M0-CAS# K9 J9
DMU VSS VSSQ CKE
M0-CAS# 100R 100R M0-WE# M0-MCLK0 L2 NC L1
CS
2J2G

3J4D
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

3J4C DB24 L3 L9
10n

M0-RESET# M0-MCLK0# WE
3J33

100R 100R T2
75R

M0-WE# RESET
3J4E 3J4F M0-DQM1
M0-CS# 100R 100R M0-DQM0 M0-CKE E7
3J4H DML
3J4G M0-CS# D3
DMU VSS VSSQ
M0-ODT 100R 100R M0-WE#
3J4K

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9
3J4J M0-RESET#
M0-CKE 100R 100R M0-MCLK0#
3J4L 3J4M M0-DQM3
M0-RESET# 100R 100R M0-DQM2
3J4N 3J4P
100R 100R +1V5-M0

2J2E
100n
3J30
1K0

FJ0B
DDR-MVREF02
100n

2J2F
3J31
1K0

+1V5-M0 +1V5-M0
47u 16V

2J2M
2J3G

2J2H

2J3C

2J2R
2J3K

2J2K

2J2P

2J3A

2J3E

2J2V
2J3F

100n

100n

100n

100n

100n

100n

100n

2J2T

2J2Z
2J32

2J34

2J36

2J38
10u

10u

10n

10n

10n

10n

10n

10n

10n

10n

DBB3 DBB8 DBC3

DBB4 DBB9 DBC4

DBB5 DBC0 DBC5

DBB6 DBC1 DBC6

+1V5-M0 +1V5-M0
DBB7 DBC2 DBC7
2J2W
2J3H

2J2N

2J3D

2J2U
2J2Y

2J3B

2J2S
100n

100n

100n

100n

100n

100n

100n
2J31

2J33

2J35

2J37

2J2L

2J39

2J30
2J3J

2J2J
10u

10u

10n

10n

10n

10n

10n

10n

10n

10n

4 2012-11-22

Umac 0 DDR3
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 72

10-1-14 B03E, Fusion

Fusion
B03E B03E

7J00-4
FUSION240

A22
AV_IN_OUT B21
AR-1 AR_1 HPHOL HPHOL
AL-1 B22 A21 HPHOR
AL_1 HPHOR
E22
AR_2
D22 C21
AL_2 SUBO
AR-3 A23 7J00-5
AR_3
AL-3 B23 A25 FUSION240
AL_3 SPK_AOR1
AR-4 E23 B25 PANEL_USB
AR_4 SPK_AOL1
AL-4 D23 USB1-DP AB30
AL_4 D1_P LAN_IO
A24 D25 AUD-L USB1-DM AB29
AR_5 AOR2 D1_N
B24 C25 AUD-R AB26
AL_5 AOL2 USBPPON1
E24 USB1-RREF AB27
AR_6 TXRTUNE1
D24 A2 V1-TX0P
AL_6 TX0_P
USB2-DP AC30 B2 V1-TX0N
D2_P TX0_N
SPDIFIN D26 E26 SPDIFO USB2-DM AC29
SPDIFIN SPDIFO D2_N
AB25 C3 V1-TX1P
3J53 USBPPON2 TX1_P
SCKIN C26 Y26 3J07 SCKI2SOUT USB2-RREF AC27 C2 V1-TX1N 7J00-9
SCKIN SCKI2SOUT TXRTUNE2 TX1_N
WSI2SIN 3J54 10R B26 Y27 3J08 10R WSI2SOUT FUSION240
WSI2SIN WSI2SOUT
10R 3J55 A26 AA30 3J09 10R B3
SDI2SIN SDI2SIN 1
AA29 3J50 10R
SDI2SOUT1
W29
TX2_P
A3
V1-TX2P UART_JTAG U26
10R SDI2SOUT2 EN-RXD0 V1-TX2N
SDI2SOUT 2
AB28 3J51 10R SDI2SOUT3 EN-TXD0 V29
GBE_RXD0 TX2_N
RXD-SERVICE Y29 I2C SCLS U27
3 GBE_TXD0 RXD SDAS
Y25 3J52 10R I2SCLK EN-RXD1 W28 A4 V1-TX3P TXD-SERVICE Y28
IJ10 I2SCLK GBE_RXD1 TX3_P TXD
AC28 10R EN-TXD1 V28 B4 V1-TX3N
GPANA1 GBE_TXD1 TX3_N
FJ0F W27 AA28 SCL-M1
GBE_RXD2 SCLM1
FJ0G V27 C5 V1-TX4P EJT-TCK D14 AA27 SDA-M1
GBE_TXD2 TX4_P TCK SDAM1
CVBS C15 FJ0H W26 C4 V1-TX4N EJT-TMS D13
CVBS GBE_RXD3 TX4_N TMS
A15 FJ0J V26 EJT-TDO E12 D1 SCL-M2
CVBS2 GBE_TXD3 TDO SCLM2
CVBS3 B16 B5 V1-TX5P EJT-TDI E13 E2 SDA-M2
CVBS3 TX5_P TDI SDAM2
A16 EN-RXC V25 A5 V1-TX5N EJT-TRSTN C14
CVBS4 GBE_RXC TX5_N TRSTN
EN-TXC U25 AA26 SCL-M3
GBE_TXC SCLM3
C16 A6 V1-TX6P AA25 SDA-M3
C TX6_P SDAM3
EN-RXEN W30 B6 V1-TX6N
GBE_RXEN TX6_N
Y-G1 A20 EN-TXEN V30
Y_G1 GBE_TXEN
PB-B1 A19 C7 V1-TX7P
PB_B1 TX7_P
PR-R1 A18 EN-MDC W25 C6 V1-TX7N
PR_R1 GBE_MDC TX7_N
EN-MDIO Y30
GBE_MDIO
Y-G2 B20 CVBS-OUT2 D4 V1-HTPDn
Y_G2 IJ11 HTPDN
PB-B2 B19 A14 CVBS-OUT1 E5 V1-LOCKn
PB_B2 1 LOCKN
PR-R2 B18 CVBS_OUT B14 CVBS-OUT2 HDMIF-RX0+ A29 D5 9GA2
PR_R2 2 RX0_P IDP_HPD
HDMIF-RX0- B29
RX0_N
Y-G3 C20 HDMIF-RX1+ A28
Y_G3 RX1_P
PB-B3 C19 HDMIF-RX1- B28 A8 BL-SPI-CLK-FUS
PB_B3 RX1_N H_BK_LITE
PR-R3 C18 HDMIF-RX2+ A27 E4 3D-LR-FUS
PR_R3 RX2_P PWM0
HDMIF-RX2- B27 D2 BL-SPI-CS_BL-I-CTRL-FUS
RX2_N PWM1
D20 HDMIF-RXC+ B30 E3 BL-DIM-FUS
IJ12 Y_G4 RXC_P BOOST
D19 HDMIF-RXC- C30 D3
PB_B4 RXC_N BKLGON
IJ13 D18 C8 BL-SPI-SDO-FUS
PR_R4 TCON_ON
HEAC T27
HEAC
SC1-STATUS C17
FS1
FB1 B17 PWR5V T30
FB1 PWR5V
D17 RREF C29
FS2 RREF
A17
FB2

4 2012-11-22

Fusion
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 73

10-1-15 B03F, Fusion power supply

Fusion power supply

B03F +1V2-MIPS
B03F

AE4
AF4
AE5
AF5
AE6
AF6
AG6
AF7
AG7
AD8
AE8
AF8
AD9
AE9
AD10
AE10
W11
Y11
AD11
AD12
AD13
AE13
AD14
AE14
AA10
AA11
AA12

W14
W15
W16
Y15
AA15

2J7F

100u 2.0V
10u
2J6T

2J13

2J26
10n

22u
7J00-3

100n
2J78
FUSION240

VDDM0

VDDM0

VDDM0

VDDM0

VDD_1V2
Y10 SENSE+1V2-MIPS
+1V5 +1V5-M1 W10
V10
P10 +1V5-M0
5J0R IJ0S
V12
P12 +1V5
220u 2V0

120R IJ0R 5J0P

2J7W

2J7V
100n

2J7Z
100n

100n
2J08

2J92
V11

10u
2J95

2J94
P11
10n

10n
120R

2J5D

2J5C

2J5B

2J5A
100n

100n

100n

2J59

2J80

2J93
AC7

10u

10u

10n

10n
AB7
R7
7J00-1 P7
FUSION240 N7

2J7R

2J7U
2J7Y

2J7P

2J7S
100n

2J7T
2J09

2J23

M7
10n

10n

10n

10n

10n

10n

10n
SUPPLY_1 IJ07

VDDM1
5J05
+1V2-FA IJ01 G29 +3V3 H7
5J00
F19 AVDDH_DRX G30 G7
120R

2J5M
2J5G
2J5N

2J5H

2J5K
AA19
100n

2J5F
2J41

2J42

2J5L
G19 AVDDL_CH234 AC6
10u

10n

10n

10n

10n

10n

10n

10n
120R
2J3M
2J3N

100n

E30 AB6 AA18

10u

F20 G27 AA6 AA17

G20 AVSSL_CH234 AVSSH_DRX G28 T6 AA16
+3V3 IJ02 H27 R6 N10
5J01
F17 IJ08 P6 K20
5J07
G17 AVDDH_CH234 E29 +1V2-FA N6 K19
120R
2J3Y

2J3P

100n

AVDDL_DRX F28 M6 K18

10u

120R
100n

2J43

2J44

F18 H6 K14
10u

G18 AVSSH_CH234 G6 K13

D21 AC5 AK30
VREFAU
+1V2-FA IJ03 AB5 A30
5J02
D16 C22 IJ09 AC4 W24
5J08 RES
E16 AVDDL_CH516 C23 +3V3 AB4 V24
120R
2J3R
2J3S

100n

VSS
C24 K4 U24
10u

120R IJ00
100n

2J45

2J46

F15 E25 P24

10u

SGNDAU SENSE+1V1-FD VDDC

F16 AVSSL_CH516 F22 T11 AD21
+3V3 IJ04 F23 AD20
5J03
B15 F24 T10 Y19
AVDDH_CH516
IJ0A AA20 U19
120R 5J09
2J3U

2J3T

100n

G15 G22 AA21 R19

10u

+3V3
G16 AVSSH_CH516 AVDD G23 Y21 N19
120R
100n

2J47

2J48

W21 L19
10u

+3V3-STANDBY IJ05 E21 V21 Y18

5J04
K24 AVSS F21 U21 U18
AVDD33_STB
IJ0B T21 R18
120R 5J0A
2J3W

2J3V

100n

J24 R21 N18

10u

AVSS_STB +3V3
D15 P21 L18
AVDDH 120R
2J4A
100n

2J49

H28 N21 AE17

10u

VDD33_XTAL DAC1
+3V3-STANDBY IJ06 K17 L21 AD17
5J06 AVSSH
L17 K21 Y17
AVSSH
E17 IJ0C M21 U17
120R INN16 5J0B
2J3Z

100n
2J40

M10 R17
10u

+3V3
E18 E15 L10 N17
2 AVDDH 120R
2J4C
2J4B
100n

E19 K10 AJ16

10u

3 INN DAC2
100n
2J90

E20 K16 P14 AG16

4 AVSSH
L16 L25 AE16
AVSSH
100n
2J91

IJ0D M24 AD16

5J0C
+2V5-F L24 Y16
E14 G21 U16
VDD25_LPLL 120R
2J4D

2J4E
100n

Y20 R16
10u
9J03

K15 W20 N16

VSSA_LPLL L15 V20 AE15
VDDC
9J04

U20 AD15
T20

VSS
U15
R20 R15
P20 N15
N20 AH14
PWR_GND

M20 U14
L20 R14
W19 N14
V19 L14
T19 AG13
IJ14 P19 U13
M19 R13
+1V1-FD
W18 N13
2J7G

2J7H
2J7K

2J7E
2J7L

2J7J

V18 L13
10u

10u

10u

10u

10u

10u

+2V5 5J0H IJ0E

7J00-2 T18 U12
FUSION240 P18 R12
120R
2J4S
2J4T

100n

M18 N12
10u

SUPPLY_2 AD6
IJ0L 5J0D
W17 AH11
+2V5-F
VDD2V5_M0P AD7 V17 N11
120R
2J4G
2J4H
100n

2J4F

2J96

2J97

AC26 T17 AG10

1u0
10n

10n

10n

VDD25
+3V3 IJ0F Y12 P17 AJ9
5J0J
2J7D

2J7C

2J7B

2J7A
100n

100n

100n

100n

100n

2J79

AC25 Y13 M17 AJ7

VSSAC_1
Y14 V16 Y7
120R VSS_M0P
VDDC
2J4U
2J4V

100n

AC24 AA13 T16 W7

10u

VDD33
AA14 P16 V7
AB24 M16 L7
VSSAC_2
V15 K7
+2V5 IJ0G AC3 T15 J7
5J0K
B1 AD4 IJ0M +2V5-F P15 Y6
VDD2V5_M1P 5J0E
C1 VDDE2V5 AD5 M15 W6
120R
2J4W

2J6W
2J4Z

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

2J6Z
100n
2J77

2J76

2J75

2J74

2J73

2J72

2J71

2J70

V14 V6
10u

120R
100n

2J4L

2J98

2J99
2J4J

F14 R11 T14 L6

1u0

10n

10n

G14 GNDE2V5 U11 M14 K6

VSS_M1P R10 W13 J6
VSS

+1V1-FA IJ0H U10 V13 AA5

5J0L
C28 T13 N5
VDD11A
N24 P13 AJ4
120R VQPS
100n
2J50

2J51

2J52

D27 M13 W4
10n
10u

VSS11A_1
2J6M
2J6U

2J6N

2J6R
2J6V

2J6P

2J6Y

2J6S

W12 T4
10n

10n

10n

10n

10n

10n

10n

10n

IJ0N 5J0F +2V5-F

D29 G13 T12 G4
AVDD25_HDMI
VDDA2V5 F13 M12 J3
120R
2J4M

2J4N
100n

C27 M11 AG2

10u

+2V5 5J0M IJ0J VSS11A_2

K12 G11 AE2
VDDC

D30 GNDA2V5 L12 F11 AB2

120R VDD33A
100n
2J53

2J54

2J55

G10 W2
10n
10u

D28 IJ0P +1V1-FA F10 U2

VSS11A_3 5J0G
2J6G
2J6D

2J6H
2J6E
2J6F
2J6L

2J6J

G12 G9 R2
10n

10n

10n

10n

10n

10n

10n

VDDA1V1 F12 F9 M2
120R
2J4P

2J4Y
100n

E9 G2
10u

+3V3 5J0N IJ0K

K11 D9 AK1
GNDA1V1 L11 G8 A1
120R
2J56

2J58

F8
10u

1n0

E8
K29 D8
LDO11_CAP
2J6C

2J6A

2J6B
2J67

2J66

2J65

2J68

2J69

E7
10n

10n

10n

10n

10n

10n

10n

10n

D7
2J4R

E6
4n7

D6
VDDF_STB
VDDF1

VDDF2

VDDF2

VDDF2
AG18
AD19
AD22
AD23

AD24

AD25
AE18

AA24
AF18

G24

G25
H24

R24
R25
R26
Y24
T24

F25

T25

F26

+3V3 +3V3-STANDBY
F6
F7
2J5W

2J5U

2J5R
2J5V

2J5S

2J5P

2J5Y
100n

100n

100n

100n

2J5Z
100n

100n

100n

100n

2J5T
100n

100n
2J63

2J64

2J62

2J61

2J60
10u

10u

10u

10n

4 2012-11-22

Fusion power supply

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 74

10-1-16 B04A, Control

Control
B04A +3V3
B04A
+3V3

RES 3GM6
RES 3GM5
7GM1 RES
PCA9540BGD

4K7

4K7

3
VDD
3GM1
4 SDA-DISP SDA-DISP RES
+3V3 SD0 +3V3
SDA-BE 2 5 SCL-DISP SCL-DISP RES 3GM2 100K
SDA SC0
100K 3GM3
SCL-BE 1 7 SDA-BL SDA-BL
SCL SD1
8 SCL-BL SCL-BL 3GM4 100K
SC1
100K
VSS
3CY1-1 1

3CY1-2 2

6
3CY1-3

3CY1-4

3CY2
4K7

4K7

4K7

4K7

4K7

1CV2 DBG
8

SDA-BE RES 9GM1 SDA-DISP SCL-DISP

3CY3-4 1
4 5 EJT-TRSTN 2
47R SCL-BE RES 9GM2 SCL-DISP SDA-DISP 3
5 4
3CY3-3
1CY1 DBG 3 6 EJT-TMS
FCY1 47R BM03B-SRSS-TBT
1
2 FCY2
3CY3-2
FCY3 2 7 EJT-TDO 1CV3 DBG
3 FCVC
4 FCY4 47R SDA-BE RES 9GM3 SDA-BL SCL-BL FCVD 1
5 FCY5 FCVE 2
3CY3-1
FCY6 1 8 EJT-TCK SCL-BE RES 9GM4 SCL-BL SDA-BL
6 3
7 8 47R 5 4

BM06B-SRSS-TBT 3CY4 BM03B-SRSS-TBT

EJT-TDI
47R 3CVF
SCL-M2 SCL-BE 1CV1 DBG
47R SCL-BE FCV2
1
FCV1
3CVG 2
SDA-M2 SDA-BE SDA-BE FCV3
3
47R 5 4
3CV2 FCVB
3D-LR-FUS 3D-LR BM03B-SRSS-TBT
47R

1CV6
FCY7
1 TXD-STANDBY
FCY8
2 FCY9 3GD5
3 RXD-STANDBY BL-SPI-CS_BL-I-CTRL-FUS BL-SPI-CS_BL-I-CTRL
4 5 10R
BM03B-SRSS-TBT
3CV3 FCVN
BL-DIM-FUS BL-DIM 1C27
3CVC FCVF
47R RESET-RF4CEn 1
TXD-RF4CE 10R 3CVD FCVG
2
3GM7 RES 3CVE 10R 3
1CV5 DBG +3V3 RXD-RF4CE FCVH
4
1 SCL-M3 4K7 10R 5
3 3CVW FCVJ
2 TXD-STANDBY RC_IRQ-RF4CEn 6
SDA-M3 3D-LED_3D-RF 3CVY 10R
3 7
RXD-STANDBY 1 7GM2 RES FCVK
4 10R 8
PDTC114EU 9 10
5
2
6

2CVC

2CVB

2CVA

2CV9

2CV8
FH52-8S-0.5SH

10p

10p

10p

10p

10p
7 SCL-FE
8 TXD-SERVICE
9 SDA-FE
3CV8
10 RXD-SERVICE BL-SPI-CLK-FUS AMBI-SPI-CCLK +3V3-STANDBY
11 10R
12 3CV9
13 STANDBYn BL-SPI-SDO-FUS AMBI-SPI-MOSI
14 TXD-RF4CE 10R
DETECT12V 1CV4 DBG
15 3CVM
RXD-RF4CE GPIO0 TXD-RF4CE TXD-RF4CE FCVL
16 1
LCD-PWR-ONn FCVA
17 47R 2
RXD-RF4CE FCVM
18 3CVP 3
19 BL-ON GPIO1 RXD-RF4CE 5 4
20 RC_IRQ-RF4CEn 47R
21 22 BM03B-SRSS-TBT
DC02 3CYC 3CVU
GPIO5 POWER-OK POWER-OK +3V3
BM20B-SRDS-G-TF
DC03 47R 10K
3CVA
GPIO6 +3V3
10K
3CYB 3CVN
GPIO7 IRQ-EXPANDERn TXD-RF4CE RES +3V3-STANDBY
47R 10K
GPIO11 DC06 3CV4 3CVR
GPIO15 RES AMBI-SPI-CCLK RXD-RF4CE
10R 10K
3CV5 3CVB RES
GPIO16 RES AMBI-SPI-MOSI +3V3
10R 10K
3CV7
GPIO20 POWER-OK
47R

GPIO21 DC07

3CVS 3CVT
GPIO23 IRQ-EXPANDERn IRQ-EXPANDERn +3V3
47R 10K

3D-LR 9GM5 RES 3D-LED_3D-RF

9GM6 RES 3D-LR-DISP

4 2012-11-22

Control
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 75

10-1-17 B04B, V-by-One out

V-by-One out
B04B B04B

(CTRL-DISP3) BL-DIM 1G55

GPIO8 20519-051E
+VDISP
FGV5 IGV7 3D-LR 60 61
FGV0 IGV5 58 59

2GWK
100n
FGV6 IGW1 56 57
3GW1 100R RES 54 55
FGV7 IGW2

SHARP
FGV8 IGW3 52 53
3GW2 1K0 RES BGVJ

9GW3-2
9GW3-3
9GW3-4
FGV9 IGW4 51

2GWL

1u0
FGVA IGW5 50
9GW5

RES
FGVB IGW6 49
IGU8
SAMSUNG 48
+3V3 9GW0 IGR0
FGVC IGW7 47
3GW3 100R 3GW4 100R BGVL SAMSUNG IGR1
FGVD IGW8 46
RES 3GW5 100R BGVM
IGW9 45

3GWM

3GW6
9GW4

10K

10K
FGVF IGR2 44
FGVG SHARP SHARP 43
FGVH FGU7 3GW7 42
V1-HTPDn BGVN 41
FGVJ FGVZ
V1-LOCKn 100R 3GW8 BGV1
FGVK FGW0 40
2GW3 100R 9GW1 BGV2
FGVE 39
100n 2GW4
FGVL FGU9 SAMSUNG 38
V1-TX0N 100n 2GR3 BGV3
FGVM FGUF 37
V1-TX0P 100n 2GR4
FGVN FGWA 36
2GW5 100n
FGVP FGU6 BGV4 35
100n 2GW6
FGVQ FGWE BGV5 34
V1-TX1N 100n 2GR5
FGVR FGWB 33
V1-TX1P 100n 2GR6
FGWC 32
2GW7 100n BGV6
FGVS FGWD 31
100n 2GW8
FGVT FGWF BGV7 30
V1-TX2N 100n 2GR7
FGWG 29
V1-TX2P 100n 2GR8
FGVU FGWH 28
2GW9 100n BGV8
FGVV FGWJ 27
100n 2GWA
FGVW FGWK BGV9 26
V1-TX3N 100n 2GR9
FGVY FGWL 25
V1-TX3P 100n 2GRA
FGWM 24
2GWB 100n BGVA
FGU0 FGWN 23
100n 2GWC
FGU1 FGWP BGVB 22
V1-TX4N 100n 2GRB
FGWQ 21
V1-TX4P 100n 2GRC
FGU2 FGWR 20
FGU3 2GWD 100n BGVC
FGWS 19
FGU4 100n 2GWE
BGVD 18
FGU5 V1-TX5N 100n 2GRD
17
FGWT V1-TX5P 100n 2GRE
16
FGWU 2GWF 100n BGVE 15
FGWV 100n 2GWG
BGVF 14
FGWW V1-TX6N 100n 2GRF
13
FGWY V1-TX6P 100n 2GRG
12
2GWH 100n BGVG
FGWZ 11
100n 2GWJ IGR3
BGVH 10
V1-TX7N 100n 2GRH
9
V1-TX7P 100n 2GRJ
8
100n BGVK 7
2GWM 10p
SCL-DISP
SAMSUNG SHARP 3GW9 10R RES
6
5
2GWN 10p RES
4
SDA-DISP 3GWA 10R RES
3
2GWY 1n0
(CTRL-DISP1) 2
GPIO2 3GWN 100R
(CTRL-DISP2) 1
GPIO3 RES 3GWP SAMSUNG
2GW2 100R
(CTRL-DISP3) IGR4
GPIO8 1n0 3GWB 100R SAMSUNG
2GWP 1n0
TO DISPLAY
9GW2
3GWC RES IGR5
SPLASH-ON FGR1
BL-ON FGR2 RES 3GWD 100R IGR6
(CTRL-DISP1)
GPIO2 100R FGR3 RES 3GWE SAMSUNG IGR7
(CTRL-DISP2)
GPIO3 FGR4 100R 3GWF SAMSUNG IGR8
SCL-DISP FGR5 SHARP 3GWG 100R IGR9
SDA-DISP FGR6 10R 3GWH IGRA
(CTRL-DISP3)
10R
FGR7 3GWJ RES SHARP
3D-LED_3D-RF

2GWW
2GWR

2GWU
2GWS

RES 2GWV
2GWT
100p

100p

100n

100n
10p

10p

100R

GPIO8 FGR8 RES 3GWK

100R

3D-LR-DISP FGR9 SAMSUNG 3GWL

100R

4 2012-11-22

V-by-One out
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 76

10-1-18 B04C, Output Vdisp

Output Vdisp
B04C B04C

1 9GS1-1 8
RES
2 9GS1-2 7
RES
3 9GS1-3 6
RES
4 9GS1-4 5
RES
1 9GS2-1 8
RES
2 9GS2-2 7
RES
3 9GS2-3 6
RES FGS1
4 9GS2-4 5
RES

8
3 7
2 6
7GS1 1 5
SI4835DDY-GE3 FGS2
RES 7GS2 6 +VDISP
5
4

1GS1 SI3443CDV
+12V 2
4 1
+3V3 T 4.0A 32V
3GS1

2GS1

2GS2

100n
RES
47R

22u

4
RES
3

2GS3 RES
7GS3-2 2GS5 IGS1
3GS4
3GS3

5
4K7

22n PUMD12
47K IGS2 100n
3
IGS4
6GS1
IGS5 3GS5
DBG DBG
6 4K7 LTST-C190KGKT
3GS6

27K

LCD-PWR-ONn 2 7GS3-1
PUMD12
1

4 2012-11-22

Output Vdisp
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 77

10-1-19 B04D, Tuner CVBS debug

Tuner CVBS debug

B04D B04D

+12V
RES

3FW4 RES
3FW3

470R
10K

4
IFW1 7FW1-2 2FW3
6 RES
BC847BPN(COL)
5
2FW4 7FW1-1 RES 33p
CVBS-OUT1 RES 2 BC847BPN(COL)
IFW2 RES 3
47u
1 3FW5 RES 3FW8 RES IFW3 5FW3 RES DFW1

IFW4 150R IFW5 75R 1u8

3FW6

RES 3FW7

2FW5

RES 2FW6
150R

100p

270p
3K3
RES

RES

DFW2

4 2012-11-22

Tuner CVBS debug

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 78

10-1-20 B04E, Audio - video

Audio - video
B04E B04E
2VW1
CVBS1 CVBS
3VWM 100n
150R 2VW2
SC1-CVBS CVBS3
3VWN 100n
3VWP 2VW3
150R Y-G1
150R 100n
3VWR 2VW4
PB-B1
150R 100n
3VWS 2VW5
PR-R1
150R
100n
2VW6
Y1-IN Y-G2
3VWT 100n
2VW7
PB1-IN 150R PB-B2
3VWU 100n
2VW8
PR1-IN 150R PR-R2
3VWV 100n
150R 2VW9
SC1-G Y-G3
3VWB 100n
150R 2VWA
SC1-B PB-B3
3VWC 100n
2VWB
SC1-R 150R PR-R3
3VWD 100n
150R
3VWW
SC1-BLK FB1
10K
3VW3 IVW1 2VWC
YPBPR-RIN AR-1
8K2 1u0
3VW4

33K

3VW5 IVW2 2VWD

YPBPR-LIN AL-1
8K2 1u0
3VW6

33K

3VW7 IVW3 2VWE

SC-RIN AR-4
8K2 1u0
3VW8

33K

3VW9 IVW4 2VWF

SC-LIN AL-4
8K2 1u0
3VWA

33K

SDI2SIN DVW1

WSI2SIN DVW2

SPDIFIN DVW3

SCKIN DVW4 +3V3

AUD-R DVW5
3VWF

4K7

AUD-L DVW6

AUDIO-MUTEn
3VWG

4K7
RES

3VWH IVW7 2VWJ

VGA-LIN AL-3
8K2 1u0
RES 3VWJ
33K

3VWK IVW8 2VWK

VGA-RIN AR-3
8K2 1u0
3VWL

33K

4 2012-11-22

Audio - video
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 79

10-1-21 B04F, Fusion supply

Fusion supply
B04F +1V5
B04F

2UB0

10u
7UB1
TPS7A7001DDA
3

IN
2
EN
6
OUT
1
100n

4 7
GND_HS

NC FB
2UB6

5
GND

11 VIA
8

10

3UB3 FUB0
RES +1V2-MIPS
27K 1%
3UB4 IUB3 2UB3

2UB4

10u
1K0 100p
47K 1%

220K 1%
100K 1%

22K 1%

3UBF FUB1
IUB4 SENSE+1V2-MIPS
3UB5

RES 3UB6

3UB7

3UB8

12K
1%

DVS2 CORE VOLTAGE SUPPLY MIPS FUSION

10K 1%

IUB5
3UBA
3UB9

1M0
RES

5UB0 IUB6
+12Va
30R
2UB7

100n

IUB7 5UB1 FUB2

2UB8

2UB9
10u

10u

+1V5
2u0
2UBC

2UBA

2UBB
22u

22u

22u

7UB5
TPS54527DDA
8

VIN

RES

IUB9
STEP DOWN IUB8
3UBB 2UBD
2 7 1 3UBE-1 8
+1V5 VFB VBST
22K 1% IUBB 100n 10R
4 6
2UBE RES SS SW 2UBJ 2UBK
470K RES

3UBE-2 IUBC
2 7
22K 1%

1 10R
22p EN IUBA 1n0 1n0
2UBG
3UBC

3UBD

3
10n

VREG5 3UBE-3
2UBH

3 6
1n0

VIA 10R
2UBF

GND_HS GND
1u0

3UBE-4
9

10
11

4 5
10R
GND-1V5 GND-1V5
GND-1V5 GND-1V5

CUB0
DDR3 SUPPLY FUSION
GND-1V5

4 2012-11-22
ENABLE+1V5+1V1
Fusion supply
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 80

10-1-22 B04G, Backlight microcontroller

Backlight microcontroller
B04G B04G
+3V3

+3V3 +3V3
2GE0

2GE1

2GE2
100n

100n
1u0
RES

3GE0

3GE1
4K7

4K7
1GE0
TXD-LPC FGE0
1
FGE1 2 DBG
+3V3 RXD-LPC FGE2
3
5 4
RES

+3V3 BM03B-SRSS-TBT
3GEK
3GE2

RES
1K0

RESET-FUSION-OUTn
100R

LPC-RESETn
7GE0
44

+3V3 LPC1114FBD48/301
8

DBG
2GE3

100n

3GE3 100R IGE1 VDD FGE3 3GE4

6 LPC-RESETn
XTALIN
RES

3GE5 100R
3GE6

7 FGE4
1K0

XTALOUT LPC-ISPn
100R
3 2
PIO0_0|RESET_ PIO2_0|DTR_|SSEL1 DBG

3
4

3
4
LPC-ISPn 4 13 9GE0 AMBI-SPI-CCLK
PIO0_1|CLKOUT|CT32B0_MAT2 PIO2_1|DSR_|SCK1

2GE4

100n
10 26 RES 9GE1 AMBI-SPI-MOSI

SKHUBHE010

SKHUBHE010
PIO0_2|SSEL0|CT16B0_CAP0 PIO2_2|DCD_|MISO1

2GE5

100n
10R 14 38 RES 3D-LED_3D-RF
3GE7 PIO0_3 PIO2_3|RI_|MOSI1

1GE1

1GE2
SCL-SSB 15 19 DBG DBG
PIO0_4|SCL PIO2_4|CT16B1_MAT1|SSEL1
SDA-SSB 3GE8 10R 16 20
PIO0_5|SDA PIO2_5|CT32B0_MAT0
22 1 3D-LR
PIO0_6|SCK0 PIO2_6|CT32B0_MAT1
23 11 LPC-LED1
RES PIO0_7|CTS_ PIO2_7|CT32B0_MAT2|RXD
27 12 LPC-LED2

1
2

1
2
3GE9 10R PIO0_8|MISO0|CT16B0_MAT0 PIO2_8|CT32B0_MAT3|TXD
AMBI-SPI-OUT-MOSI 28 24 LPC-LED3
PIO0_9|MOSI0|CT16B0_MAT PIO2_9|CT32B0_CAP0 FGE5
LPC-SWCLK 29 25 LPC-LED4
PIO0_10|SWCLK|SCK0|CT16B0_MAT2 PIO2_10
BL-DIM1 32 31 RES 3GEA AMBI-SPI-OUT-CCLK
PIO0_11|R|AD0|CT32B0_MAT3 PIO2_11|SCK0|CT32B0_CAP1
10R
BL-DIM2 33 36 BL-DIM5
PIO1_0|R|AD1|CT32B1_CAP0 PIO3_0|DTR_|CT16B0_MAT0|TXD
BL-DIM3 34 37 BL-DIM6
PIO1_1|R|AD2|CT32B1_MAT0 PIO3_1|DSR_|CT16B0_MAT1|RXD
BL-DIM4 35 43 BL-DIM8
PIO1_2|R|AD3|CT32B1_MAT1 PIO3_2|DCD_|CT16B0_MAT2|SCK1
LPC-SWDIO 39 48 3D-LR-DISP +3V3 +3V3 +3V3 +3V3
PIO1_3|SWDIO|AD4|CT32B1_MAT2 PIO3_3|RI_|CT16B0_CAP0
40 18
PIO1_4|AD5|CT32B1_MAT3|WAKEUP PIO3_4|CT16B0_CAP1|RXD
BL-DIM 45 21
PIO1_5|RTS_|CT32B0_CAP0 PIO3_5|CT16B1_CAP1|TXD
RXD-LPC 46

3GEB DBG

3GEC DBG

3GEE DBG

3GEF DBG
PIO1_6|RXD|CT32B0_MAT0
TXD-LPC 47
PIO1_7|TXD|CT32B0_MAT1
BL-SPI-CS_BL-I-CTRL 9
PIO1_8|CT16B1_CAP0

330R

330R

330R

330R
17
3GEL PIO1_9|CT16B1_MAT0|MOSI1
30
PIO1_10|AD6|CT16B1_MAT1|MISO1
10K 42
PIO1_11|AD7|CT32B1_CAP1
3GEM

3GEN
2GE6

RES 100K

RES 100K
1u0

VSS
5
41

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT
DBG

DBG

DBG
DBG
6GE0

6GE1

6GE2

6GE3
+3V3
BL-DIM7 cGE1 AMBI-SPI-CCLK-OUT

AMBI-SPI-CCLK 9GE2 AMBI-SPI-OUT-CCLK LPC-LED1

LPC-LED2
cGE2 AMBI-SPI-MOSI-OUT
LPC-LED3
AMBI-SPI-MOSI 9GE3 AMBI-SPI-OUT-MOSI
LPC-LED4

BL-DIM 9GE4 BL-DIM1

+3V3

+3V3
3GEG

10K

ROW_1
1GE3-1 ROW_2
1GE3-2
1
FGE6 LPC-SWDIO
RES 3 2
FGE7 LPC-SWCLK
3GEJ 5 DEBUG 4
3GEH FGE8 AMBI-SPI-OUT-MOSI
7 DEBUG 6
1K0 RES 100R
9 8
10 LPC-RESETn

FTSH-105-01-L-DV
FTSH-105-01-L-DV

4 2012-11-22

Backlight microcontroller
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 81

10-1-23 B04H, eMMC

eMMC
B04H B04H
+3V3 +3V3

2EJ1

2EJ2

2EJ3

2EJ4

2EJ5

2EJ6
100n

100n

100n

100n

100n

100n
+3V3

+3V3
3EJ1

4K7

7EJ0-1

J10
M4
C6

N4
P3
P5

E6

K9
F5
H26M21001ECR

3EJ4 VCCQ VCC

GPIO14 SDIO2-CLK SDIO2-CMD FEJ2 M5 A3 FEJ3 SDIO2-D0 SDIO2-D0 2 3EJ2-2 7
CMD 0
A4 FEJ4
33R
SDIO2-CLK FEJ1 M6
CLK
MAIN 1
2
A5 FEJ5
SDIO2-D1
SDIO2-D2
47K
3EJ5 3EJ2-3
GPIO15 SDIO2-CMD B2 FEJ6 SDIO2-D3 SDIO2-D1 3 6
3EJ0 3
33R +3V3 FEJ0 K5 RST
DATA
4
B3 FEJ7 SDIO2-D4 47K
SDIO2-RESETn 10K B4 FEJ8 SDIO2-D5
3EJ6-2 5 3EJ2-4
GPIO16 2 7 SDIO2-D0 VDDI C2 B5 FEJ9 SDIO2-D6 SDIO2-D2 4 5
VDDI 6
33R B6 FEJA SDIO2-D7 47K
7
3EJ6-3 VSS VSSQ 3EJ2-1
2EJ7

100n

GPIO17 3 6 SDIO2-D1 SDIO2-D3 1 8

G5
E7
K8
H10

C4
N2
N5
P4
P6

33R 47K
3EJ6-1 FEJB 3EJ3-2
GPIO18 1 8 SDIO2-D3 SDIO2-D4 2 7
33R 47K

GPIO19 4 3EJ6-4 5 SDIO2-D2 SDIO2-CLK SDIO2-D5 1 3EJ3-1 8

33R SDIO2-CMD 47K

GPIO20 1 3EJ7-1 8 SDIO2-D5 +3V3 +3V3 +3V3 SDIO2-D6 4 3EJ3-4 5

33R 47K

GPIO21 4 3EJ7-4 5 SDIO2-D6 SDIO2-D7 3 3EJ3-3 6

M10
M11
M12
M13
M14

N10
N11
N12
N13
N14

P10
P11
P12
P13
P14

33R 7EJ0-2 47K

M3
M7
M8
M9

N1
N3
N6
N7
N8
N9

P1
P2
P7
P8
P9

H26M21001ECR
3EJ7-3
GPIO22 3 6 SDIO2-D7 NC
33R A1 H1
SDIO2-D3 A2 H2
3EJ8
GPIO23 SDIO2-RESETn SDIO2-D6 A6 H3
33R SDIO2-D7 A7 H5
+3V3 A8 H12
3EJ7-2
GPIO24 2 7 SDIO2-D4 A9 H13
A10 H14
33R
A11
A12
NC J1
J2
A13 J3
A14 J5
B1 J12
+3V3 B7 J13 +3V3
B8 J14
B9 K1
B10 K2 SDIO2-RESETn
NC NC
B11 K3
B12 K6
B13 K7
B14 K10
VDDI C1 K12
SDIO2-D4 C3 K13
SDIO2-D5 C5 K14
C7 L1
C8 L2
C9 L3
C10 L12
C11 L13
C12 L14
C13 M1
C14 M2

NC
D1
D2
D3
D4
D12
D13
D14
E1
E2
E3
E5
E8
E9
E10
E12
E13
E14
F1
F2
F3
F10
F12
F13
F14
G1
G2
G3
G10
G12
G13
G14

SDIO2-D4
SDIO2-D5 +3V3

4 2012-11-22

eMMC
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 82

10-1-24 B05A, Class-D amplifier

Class-D amplifier
B05A B05A

3D60 A-STBY
+3V3D +12V-AUDIO +12V-AUDIO
10K
3
RESET-FUSION-OUTn
1 7D70
PDTC144EU
2D97

2D96

2D84

2D92

2D60

2D61

2D62

5D50

2D63

2D66

2D57

2D58

2D59

2D64

2D65

5D51
220n

220n

220n

220n
2 30R

30R
10u

10u

10u

10u

10u

10u

10u

10u

10u

10u
2D49 2D48
3D61
100u 16V ID54 ID55 16V 100u
2D93 RES
100u 16V

100u 16V
10R 5D85
2D67 1u0

1u0

2D5C
2D5A

3D78

3D82
10K

10K
3D62 +3V3D +3V3
2D86

2D68

2D69
100n

100n

AUDIO-MUTE
10u

+3V3D 30R
10K
3 SPEAKER-L- SPEAKER-R-
AUDIO-MUTEn +3V3D 3D58
9D50

ID78
RES

1 7D71 RES
100u 16V

100u 16V
2D5D
2D5B

3D79

3D83
PDTC144EU 1R0
10K

10K
2
+3V3D 3D57 ID77 ID76 ID75 TAS5731P1
7D60
1R0 TAS5711PHP
13

27

32

44
45

40
41

34
35
5

2
3

DBG 2D72
9D52 AVDD DVDD OUT A B C D
RES 3D63 1D03 WSI2SOUT FD67 20 GVDD PVDD
LRCLK 10u
1 SDI2SOUT1 I2SCLK FD63 RES 9D53 FD64 21
SCLK 2D74 ID50 5D70 5D00
9D54 ID79 ID88 ID91
10R 2 SCKI2SOUT FD65 FD66 15
MCLK AUDIO VR_DIG
18 SPEAKER-L+ SPEAKER-L+
SCKI2SOUT SDI2SOUT1 22
3 SDIN AMPLIFIER 31 ID80 2D77 100n 10u 30R
4 WSI2SOUT FD50 VREG
+3V3D

3D73

2D56

2D71

2D99

2D78
220n

220n
+3V3-STANDBY

18R

10n

10n
5 6 3D55 100n
SDA-SSB 23 1
SDA OUT_A
SCL-SSB 3D56 47R 24
SCL ID81 2D79
47R 3D76 RES 4
+3V3D BST_A
3D50

10K
10K

BM04B-SRSS-TBT 33n 2D80 5D71

2D75
9D55

330p
SDI2SOUT3 ID89 ID90 14 43 ID82
A_SEL BST_B FD69
3D54

47K

RES
3D77 33n 30R
ID56 46
OUT_B
D-RESET D-RESET 15K 25
RESET 5D75

2D98

2D70
19 ID93 ID94

10n

10n
PDN SPEAKER-L-
ID87 7D50-2 39 1D01 1D02
OUT_C 30R FD30
PUMH2
2D50 ID66 ID62 ID51 5D74
Left+ 1 1
2D82 FD31

5D81
ID65 12 42 Left- ID57

30R
SPEAKER-L- 2 2
VR_ANA BST_C
11 ID63 10u SPEAKER-R+ Right+ 3 3
4n7 PLL_FLTP 2D85 33n 3D74 2D94
DETECT12V 7D50-1 10
PLL_FLTM BST_D
33 FD32 FD33 Right- 4
PUMH2 3D51
2D51 18R FD70 2041145-3
33n 330p
47n 470R 36 ID52 5D76 5D01 2041145-4
OUT_D ID96
3D52 2D52 SPEAKER-R+
ID58 3D70 RES

2D87

1D52

1D50

1D51
7 ID83

10n
A-STBY 470R 47n ID69 ID97 OC_ADJ 10u 30R
8 16 ID84 3D71 22K
2D53 PBTL OSC_RES
3D75

2D83

2D55
220n

220n
9D51
18R

18K2 1%
ID61 ID70 50
4n7 2D54
2D89

1D53

1D54

1D55

1D56

2D81

2D73
220n

6 51

10n

10n
AUDIO-MUTE SSTIMER ID53
52
2n2
53
2D95

2D76

2D91
26 54

10n

10n
STEST
3D72

55
18R

330p
56
57
5D79 5D80
58 ID98 ID99 SPEAKER-R- SPEAKER-R-
59
VIA 10u 30R
2D88

330p

60
5D83

61
30R

62
63
64
65
66 5D77
67
68
PGND 30R
VSS 69
AB CD
AGND GND A D DO GND_HS
30

29

28

17

47
48

37
38

49
CD00

1X02
REF EMC HOLE

4 2012-11-22

Class-D amplifier
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 83

10-1-25 B05B, Analogue externals

Analogue externals
B05B B05B
3VA7 FVA9
SC-RIN

CDS4C12GTA
RES
1K0

1VAG
2VA8

2VA9
100p

12V

6n8
6VA8
3VA8 FVAA
SC-LIN

CDS4C12GTA
RES
1K0
SCART

1VAH
2VAA

2VAB
100p

12V

6n8
49045-0011

6VA9
25 26
FVA1
24
23
FVAB 22
SC1-B 21

CDS4C12GTA
RES
20
19

3VAG
2VAC

1VAJ
100p

75R
12V
18
17

6VAA
FVA2 16
15
14
IVA0 3VA9 FVAC 13
SC1-STATUS 12
PDZ2.4B(COL)

CDS4C12GTA
RES
12K 11
10
2VAD
6VAB

3VAA

2VAE

1VAK
100p
1K5

12V
1u0

9
8

6VAC
7
6
+3V3 5
FVA4 4
SC1-G 3
CDS4C12GTA
RES

2
1
3VAB
2VAF

1VAL
3D90

100p
1R0

75R
12V

1VA1
6VAD

1J50
3150-831-030-H1 ID95
2
VCC
FD90
1 SPDIFO
VIN FVAD
SC1-R
3
CDS4C12GTA
RES

GND
CDS4C12GTA

MT
1VAM
2VAG

3VAC
100p

75R
12V
V_NOM

5 4
2D0A

RES 2D0B

1D0A

RES 6D0A
100n

100p

12V

6VAE

IVA1 3VAD FVAE

SC1-BLK
PDZ2.4B(COL)

CDS4C12GTA
RES

100R
2VAH

1VAN
3VAE
6VAF

100p
75R

12V
6VAG

FVAF
SC1-CVBS
CDS4C12GTA
RES

1VAP
3VAF
2VAJ

150R
100p

12V
6VAH

3VAK FVAG
SC1-DETECTn
47R
2VAK

100p

4 2012-11-22

Analogue externals
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 84

10-1-26 B05C, Sensor board and AmbiLight

Sensor board and AmbiLight

B05C B05C

FAA0

FH52-11S-0.5SH FH52-25S-0.5SH FH52-40S-0.5SH

FAA1
13 12 27 26 42 41 3CAF SDA-SRF
11 25 40
FAA2 10R
10 24 39 3CAH
3CAE SCL-SRF LED2-OUT
9 23 38 +3V3-STANDBY
IAA0 3CAG 10R
8 22 37 +5V 10K
FAA3 +T 0R3 3CAD RC_IRQ-RF4CEn
7 21 36
FAA4 10R LED2-OUT
6 20 35
3CAC KEYBOARD_IRQ-SRFn
5 19 34
FAA5 10R
4 18 33
3CAB LED2-OUT
3 17 32
FAA6 3CAA 100R 3D-LED_3D-RF SDA-MC
2 16 31
FAA7 3AAA 100R AMBI-TEMP
1 15 30
GND-AL FAA8 100R
14 29
1C20 3AAB AMBI-SPI-MOSI-OUT
13 28
GND-AL FAA9 47R
12 27 +3V3-STANDBY
3AAC AMBI-SPI-CCLK-OUT
11 26
47R
10 25
1u0

GND-AL
100p

100p

100p

100p

9 24
470p

470p
1u0

10p

10p

10p

1u0
8 23
7 22 AMBI-POWER
2CAK

IAA1 1u0
2CAM

6 21
2CAJ

2CAN

2CAR
2CAP

2CAD

2AAW
2CAA

2CAB

2AAC

2AAV

5 20
4 19 2CAS
3 18
9CAA AMBI-POWER
2 17
9CAB +3V3AL
1 16
15 AMBI-POWER
1C25
14
2CAT
13
100n
12
2CAU RES
11
10u
10
9
8 GND-AL
7
6
5 RES
2CAL
4 3AAD FAAZ
3 100n +3V3 +3V3AL
2 +T 0R3
1
2AAD

2AAE
10u

10u
GND-AL
1C26

GND-AL

4 2012-11-22

Sensor board and AmbiLight

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 85

10-1-27 B06A, HDMI

HDMI
B06A +5V +3V3
B06A
pins (9,27,64)

3HA5 RES

PDZ2.4B(COL)
5HA5
FHA8
+3V3 VCC33

6HA1

5HA9

30R
3K3
7HA5 30R

2HAM

2HAN

2HAP
2HAJ

100n

100n

100n
FHB4 RT9715EGB

10u
MICOM-VCC33 RES
IHB0
5 3
VCC33 SBVCC33 VIN FLG

3HAP
2HB4

10K
1u0
I2C ADDRESS

3HA6

2HB5
4 1

2K2

1u0
EN VOUT
SII9287B=OXB2 FHBC
EN

RES 2HAK
2HAL

100n

10u
GND
RES
5HA6
pin (38)
7HA0 FHA7
SBVCC33

27
64

37

38
SII9287B

2
30R

2HAG
2HAF

100n
MICOM_VCC33

SBVCC33

10u
VCC33 RES RES
1H04
FHB7 IHB1
DDRX2+ ARX-HOTPLUG 31
1 3HA0 (CBUS) HPD0
FHAY 32
2 AIN-5V R0PWR5V
3 DDRX2- 10R
2HA5

29
1u0

DDRX1+ ARX-DDC-SDA
3HA1-1

4 DSDA0
100K

ARX-DDC-SCL 30 49 R4PWR5V
5 DSCL0 R4PWR5V
6 DDRX1-
3HBP
DDRX0+ ARXC- 65 48
1

7 N DSCL4 3HBQ
DIN-5V ARXC+ 66 R0XC 47 10K
8 P DSDA4
9 DDRX0- 10K
HDMI CONNECTOR 4 10 DDRXC+ ARX0- 67
N CEC_D
51
7 3HAA-2 2

ARX0+ 68 R0X0
11 P
47K

12 DDRXC-
PCEC-HDMI ARX1- 69
13 N
HARC2 ARX1+ 70 R0X1
14 P
DRX-DDC-SCL DRX-DDC-SCL FHAL
15
DRX-DDC-SDA DRX-DDC-SDA FHAM ARX2- 71
16 N
ARX2+ 72 R0X2
17 P
1 3HAA-1 8

DIN-5V 57 HDMIF-RX2-
18 N
FHB8 35 TX2 56
47K

FHAE 19 DRX-HOTPLUG BRX-HOTPLUG (CBUS) HPD1 P HDMIF-RX2+

FHB0 3HA2
21 20 BIN-5V 36
R1PWR5V
23 22 10R 59 HDMIF-RX1-
N
7

BRX-DDC-SDA 33 TX1 58 HDMIF-RX1+

3HA1-2

DSDA1 P
2HA4

100K

34
1u0

BRX-DDC-SCL DSCL1
DIN-5V 61 HDMIF-RX0-
N
BRXC- 1 TX0 60 HDMIF-RX0+
2

N P
1H03 BRXC+ 2 R1XC
P
CRX2+ 63 HDMIF-RXC-
1 N
BRX0- 3 TXC 62 HDMIF-RXC+ 3HB0 MICOM-VCC33
2 N P
CRX2- BRX0+ 4 R1X0 4K7
3 P
4 CRX1+
5 55 FHA4 3HB1 RES
5 BRX1- N TPWR_CI2CA
CRX1- BRX1+ 6 R1X1
6 P 4K7
7 CRX0+
CIN-5V BRX2- 7 50
8 N CEC_A
CRX0- BRX2+ 8 R1X2
HDMI CONNECTOR 3 9
10 CRXC+
P
+5V
3HAS FHA6 pin (49) R4PWR5V
3 3HAA-3 6

CRX-HOTPLUG FHB9 41 52 3HAY 4K7 +3V3

11 3HA3 (CBUS) HPD2 INT 10R
FHB1 42
47K

12 CRXC- CIN-5V R2PWR5V FHA3 RES

2HAD

3HAR

100K
1u0
13 PCEC-HDMI 10R
6

HARC1 CRX-DDC-SDA 39
3HA1-3

14 DSDA2
2HA2

100K

FHAN 40
1u0

15 CRX-DDC-SCL CRX-DDC-SCL CRX-DDC-SCL DSCL2

CRX-DDC-SDA CRX-DDC-SDA FHAP
16
CRXC- 11
3

17 N
5 3HAA-4 4

CIN-5V CRXC+ 12 R2XC 54 3HAV 47R SCL-SSB

18 P CSCL
53
47K

FHAF 19 CRX-HOTPLUG CSDA 3HAW 47R SDA-SSB

21 20 CRX0- 13
N +5V
23 22 CRX0+ 14 R2X0 +1V5 +3V3
P
10 2HAB
CRX1- 15 RSVDL 28
N
CIN-5V CRX1+ 16 R2X1
P 1u0
7HA1-1
1H02 17 RT9025-12GSP

4
CRX2- N
BRX2+ CRX2+ 18 R2X2 VDD
1 P
3 6 FHB5 +1V2-FE
2 VIN VOUT
BRX2- DRX-HOTPLUG FHBA 45
3 3HA4 (CBUS) HPD3
BRX1+ DIN-5V FHB2 46 74 2 7
4 R3PWR5V EN ADJ

2HAA
75

10u
5 10R
5

BRX1- DRX-DDC-SDA 43 76 1
3HA1-4

6 DSDA3 PGOOD
2HA1

2HA9
100K

44 77
1u0

10u
7 BRX0+ DRX-DDC-SCL DSCL3
BIN-5V 78 5
8 NC
BRX0- DDRXC- 19 79 GND
4

9 N
HDMI CONNECTOR 2

22
23
24
25
26
BRXC+ DDRXC+ 20 R3XC 80 GND HS 7HA1-2
10 P
1 3HAB-1 8

RT9025-12GSP

9
81
11
21 VIA 82
47K

12 BRXC- DDRX0- N VIA

PCEC-HDMI DDRX0+ 22 R3X0 83
13 P
HARC0 84 18 10
14
BRX-DDC-SCL BRX-DDC-SCL FHAR DDRX1- 23 85 19 11
15 N VIA
BRX-DDC-SDA BRX-DDC-SDA FHAS DDRX1+ 24 R3X1 86 20 VIA 12
16 P
87 21 13
17
7 3HAB-2 2

BIN-5V DDRX2- 25 88
18 N
26 R3X2 89
47K

FHAG BRX-HOTPLUG DDRX2+

19 P VIA
21 20
23 22

14
15
16
17
EPAD
73

BIN-5V

1H01
ARX2+
1
2
1V2 DVB-T2 and DVB-S2
3 ARX2-
4 ARX1+
5
6 ARX1-
7 ARX0+
AIN-5V IHB2
8 3HB2
ARX0- RES
9 +3V3-STANDBY
HDMI CONNECTOR 1 10 ARXC+ 22K
3 3HAB-3 6

11 7HA2
47K

12 ARXC- BC847BW
PCEC-HDMI RES
13
14 HARC4
ARX-DDC-SCL ARX-DDC-SCL FHAV
15 IHB3
ARX-DDC-SDA ARX-DDC-SDA FHAW PCEC-QHDMI 9HA1 IHB4
16
17 3HB3 IHB5
5 3HAB-4 4

AIN-5V PCEC-HDMI 9HA0 HDMI-CEC

18
47K

FHAH 19 ARX-HOTPLUG 100R

FHB6
21 20
BC847BW
23 22 7HA3
3HBS

27K
3HAL

1M0

IHB6
AIN-5V
RES

3HB4
+3V3-STANDBY
22K

1X07 1X08 1X09

1X01 EMC HOLE EMC HOLE EMC HOLE 1X14
REF EMC HOLE REF EMC HOLE

4 2012-11-22

HDMI
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 86

10-1-28 B06B, HDMI-ARC

HDMI-ARC
B06B B06B
IHD1 9HD4 IHDF ARC0

3HD4

100R
FHD4 5HD0
HARC0 ARC0
30R
FHD5 5HD1
HARC1 ARC1
30R
FHD6 5HD2
HARC2 ARC2
30R
IHD8 9HD5 IHDG ARC1

FHD8 5HD4
HARC4 ARC4
30R

3HD9

100R
+5V-ARC
2HD0

2HD1

2HD3

2HD5
10p

10p

10p

10p

5HD5
FHD3
+5V
30R
2HDD
2HD6

100n
1u0

7HD0
16

74HC4051PW IHD7 9HD6 IHDH ARC2

VCC
FHD0 11 13
ARC-SEL0 0 MDX 0

3HDE

100R
ARC-SEL1 FHD1 10 0 14
8X 1
7
ARC-SEL2 FHD2 9 15
2 2
FHD7 IHDM
9HD0 6 12 9HD9 ARC3
G8 3
1
4

3HDU

100R
HDMI-ARC 3 5
5
2
6
4
7
VEE GND
7

IHD4 9HD8 IHDK ARC4

3HDS

100R

RES
HDMI-ARC IHDL 9HD2 ARC4
3HDT

100R
RES

4 2012-11-22

HDMI-ARC
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130227

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 87

10-1-29 B06C, USB external

USB external
B06C B06C
+3V3
3EA7
+5V
+T 0R3
3EA8-1
+5V-PORTA
100K
FEAD 3EA8-2
USB-PORTA-OC
2EA3

100n

100K
2EA4

2EA5

2EA6

2EA7
100n

100n

100n

100n

3EA8-3

2EA0 100K
3EA8-4
18p
7EA0 100K
27

14

21
1EA0

CY7C65632-28LTXCT
12M

5
9
VCC

VCC_A_1
VCC_A_2
VCC_A_3

VCC_D

10
2EA1 XIN
11
18p XOUT
1 IEA3 USB2-DM
D-
USB-PORTB-DM 3 2 IEA4 USB2-DP
DD1- D+ 3EAC
USB-PORTB-DP 4
DD1+ +5V
USB-PORTB-OC 25 +T 0R3
OVR1
6 26 3EAD-1
USB-PORTA-DM DD2- SDA +5V-PORTB
USB-PORTA-DP 7
DD2+ 100K
USB-PORTA-OC 24
OVR2 FEAE 3EAD-2
USB-PORTB-OC
USB-PORTC-DM 12
DD3- 100K
USB-PORTC-DP 13 18
DD3+ TEST|SCL 3EAD-3
USB-PORTC-OC 20
OVR3
100K
15
DD4- 3EAD-4
16
DD4+
3EA1 19 100K
+3V3 OVR4
10K 30 1%
VIA1 IEE0 3EE2-1
28 31 USB1-RREF 1 8
VREG VIA2
RESET-FUSION-OUTn 17 32 12K
RESET VIA3
3EA3 IEA1 22 33 1%
+3V3 SELFPWR VIA4 3EE2-2
10K 23 2 7
GND_HS

3EA4 GANG
8
RREF 12K 3EAG
IEA2 1%
680R IEE1 3EE2-3 +5V
100K

USB2-RREF 3 6 +T 0R3
29

+3V3 12K 3EAH-1

1%
+5V-PORTC
4 3EE2-4 5
100K
2EA2

100n
3EA5

12K FEAH 3EAH-2

USB-PORTC-OC
100K
3EAH-3

100K
3EAH-4

100K

1E01 1E02 1E03

+5V-PORTA FEA1 FEA9 +5V-PORTC FEA8
FEA2 1 FEAA +5V-PORTB 1 FEA5 1
USB-PORTA-DM USB-PORTB-DM 2 USB-PORTC-DM 2
2
USB-PORTA-DP USB-PORTB-DP 3 USB-PORTC-DP 3
3
FEA3 4 FEA4 FEAB 4 FEAC FEA6 4 FEA7
5 6 5 6 5 6
2EAB

100n

100n
2EA9

100n

5401 2EAA 5401

5401

4 2012-11-22

USB external
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 88

10-1-30 B06D, Ethernet

Ethernet
B06D B06D
5EF5
2EFS

2EFT
10n

10n

30R
RES 5EF0 VDD33-PHY
+3V3-STANDBY VDD33-PHY FEF9
IEF1
30R
5EF4 AVDDL-1V1
+3V3-LAN

2EFH
2EF0

2EF1

2EF2

2EF3
100n

100n

100n
1u0

10u
30R

FEF0

5EF6
2EF5

2EF6

2EF7

2EF8
100n

100n

100n

100n

30R
2EFA
5EF1

2EF9

2EFJ
100n

100n
4u7

10u

FEF1 7EF0 VDDH-2V5

11
17

14

38

2EFB AR8030-AL1A-R
6

22p
AVDD33

VDD33

DVDDL

AVDDL
3EFY
1EF0

1M0

5 2
XTLI LX
25M

2EFC 4 8 FEF8
22p XTLO VDDH_REG
FEF2
FEFD 23 27
CLK_25M VDDIO_REG

RESET-ETHERNETn FEF3 1 9 TXP

RST TRXP0
2EFG

2EFV
2EFF

2EFZ

100n
10
1u0

1u0

22u
TRXN0 TXN
3EF2 1% FEF4 7 12 RXP
RBBIAS TRXP1
13 RXN
2K37 TRXN1
RES0 26
RES0
RES1 31 33 3EF5 CLK-RMII
RES1 CLK_RMII 2EFP IEF3
30 22R EN-RXEN 1E00
CRS_DV
EN-MDC 40 5450-327-194-H3
MDC 100n
3EF3 1% 39 29 EN-RXD0 1
VDD33-PHY MDIO RXD0
EN-MDIO 1K5 20 28 EN-RXD1 TXP FEFA 2 TX+
INT RXD1
IRQ-WOLANn TXN FEFB 3
FEF5 TX-
15 25 FEF7 RX-ER RXP FEFC
RX_ER
16 RXN FEFE
VDDH-2V5 18 32 EN-TXEN 4 RX+
TX_EN
19 NC 5
36 34 6 RX-
CDA5C16GTH

CDA5C16GTH

CDA5C16GTH

CDA5C16GTH
TXD0 EN-TXD0
1

4
37 35 EN-TXD1 IEF2
RES 6EF2-1

RES 6EF2-2

RES 6EF2-3

RES 6EF2-4
TXD1
RES 2EFK
3EF4

RES 2EFL

VDD33-PHY VDD33-PHY

RES 2EFN
RES 2EFM
10K

16V

16V

16V

16V
15p

15p

15p

15p
LED-RES
50 21 LED-ACT 7 8
RES

LED_ACT
51 22
8

5
LED_RES

2EFU

100n
52 24
LED_10_100
53
10K

3EFT FEF6 54
10K

3EFS VIA
6 55
56
GND_HS

7EF1-1 2 3 57
PUMH2 58
1 5 VIA
7EF1-2
PUMH2
41
42
43
44
45
46
47
48
49

DEF0
4 EN-TXC

CLK-RMII EN-RXC

VDDH-2V5

3EFH 3EFN
RES0 EN-RXD0
10K 10K
3EFJ 3EFP
RES1 EN-RXD1
10K 10K
3EFR
EN-RXEN
10K
3EFL
LED-RES
10K
3EFM 3EFU
LED-ACT RX-ER
10K 10K

4 2012-11-22

Ethernet
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 89

10-1-31 B06E, NAND flash, serial flash and EEPROM

NAND flash, serial flash and EEPROM

B06E B06E
+3V3
+3V3-STANDBY
2JA0

2JA1

2JA2
100n

100n

100n
9JA4

9JA3

3CT1

4K7
7JA0
12
34
37
39

MT29F8G08ABACAWP:C
VCC FCT2 3CTH
1 SF-SDO
1
2
2 47R
3
3
FRA0 DJA0 29 4 +3V3-STANDBY
0 4
FRA5 DJA1 30 5
1 5
FRA6 DJA2 31 6
2 6

8
FRA7 DJA3 32 10 7CT3
3 IO 7
FRA8 DJA4 41 11 M25P05-AVMN6
4 8
FRA10 DJA5 42 14 VCC

5 9 3CTR ICT1 3CT0 FCT3
FRA11 DJA6 43 15 SF-SDI SF-SDI SFB-SI SFB-SI 5 2
6 10 +3V3-STANDBY D Q
FRA12 DJA7 44 20
7 11
21 3CTJ 4K7 270R 3CTU FCT4
6
512K
NC 12 SF-CLK SF-CLK SFB-SCK SFB-SCK C FLASH
22
3JA6 13 4K7 3CTK 3CTZ 270R FCT5
F-RDY DJA8 7 23 SF-CS SF-CS SFB-CS SFB-CS 1
R 14 S
33R B 24
10K 15 3CT3 4K7 270R 3CT2 FCT6
26 SF-WP SF-WP SFB-WPn SFB-WPn 3
+3V3 16 ICT2 W
3JA5 27 47R
17 4K7 3CTB ICT3 3CT9 FCT7
F-OEn DJA9 8 28 SF-HOLDn SF-HOLDn SFB-HOLDn SFB-HOLDn 7
RE 18 HOLD
F-CEn DJAA 9 33 47R
CE 19 4K7
NAND-ALE DJAB 17 35 VSS
ALE 20
NAND-CLE DJAC 16 40
CLE 21
F-WEn DJAD 18 45

4
WE 22
DJAE 19 46
WP 23 FCT8
38
DNU1
3JA0

3JA1

47
4K7

4K7

DNU2
RES

1CTZ
VSS
1
13
25
36

48

RESET-STANDBYn 2
SF-SDO 3
+3V3 SFB-SI 4
9JA5

9JA6

SFB-CS 5
SFB-SCK 6
8 7

1734260-6

+3V3

+3V3 2JA4
IJA1

7JA2 100n
M24C64-WDW6
8

3JA4

10K

(8K 8) 7
WC
EEPROM 3JA2
IJA0
1 6 SCL-SSB
0 SCL
2 47R
1 ADR 3JA3
3 5 SDA-SSB
2 SDA
47R
4

FJA0

4 2012-11-22

NAND flash, serial flash

3104 313 6612
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 90

10-1-32 B06F, Analogue externals

Analogue externals
B06F B06F
3VC6 FVC1
VGA-LIN AUDIO VGA/DVI
CDS4C12GTA

1K0
2VC8

6VC6

2VC9

1VC7
100p

5 1VA6
12V

1n0

4
3
RES

2
1
FVCB
MSJ-035-75C-BL-RF-PBT-BRF

3VC7 FVC2
VGA-RIN
CDS4C12GTA

1K0
2VCA

2VCB
6VC7

1VC8
100p

12V

1n0
RES

3VC8 FVC3
YPBPR-DETECTn
47R
2VCC

100p

FVC4
Y1-IN
CDS4C12GTA
RES
2VC0

3VC0

1VC1
150R
12V
47p

YPBPR
6VC0

5 1VA8
4
FVC5
PB1-IN 3
CDS4C12GTA
RES

2
2VC1

3VC1

1VC2
150R

1
12V
47p

FVCC
MSJ-035-75C-G-RF-PBT-BRF
6VC1

FVC6
PR1-IN
CDS4C12GTA
RES
2VC2

3VC2

1VC3
150R
12V
47p

6VC2

3VC9 FVC7
CVBS-DETECTn
47R
2VCD

100p

YPBPR-RIN
3VC3 FVC8 CVBS +
CDS4C12GTA
RES

1K0
AUDIO CVBS / YPBPR
2VC3

2VC6

1VC4
100p

12V

1n0

5 1VA4
6VC3

4
3

3VC4 FVC9
YPBPR-LIN 2
1
CDS4C12GTA
RES

1K0
FVCD MSJ-035-75C-Y-RF-PBT-BRF
2VC4

2VC7

1VC5
100p

12V

1n0
6VC4

FVCA
CVBS1
CDS4C12GTA
RES
2VC5

3VC5

1VC6
150R
100p

12V
6VC5

4 2012-11-22

Analogue externals
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 91

10-1-33 B06G, DC-DC

DC-DC
B06G 5UR3

30R
B06G
5UR1 IUR0 IUR2
+12Vb 3UR3-1
33R +12Vb
30R
2UR5

2UR6

100n

3UR3-2
10u
2UR7

22
23
24
25
26
33R
10u

2UR0 2UR4 IUR8 5UR2 FUR1 7URA-2

3UR3-3 +5V RT8288AZSP
33R VIA
1n0 1n0 4u7

2UR8

2UR9

2UY5

100n
3UR3-4

22u

22u
IURL
33R 18 10
2UR3
19 11

BAV99 COL
20 VIA VIA 12

3UWJ-1

3UWJ-2

3UWJ-3

3UWJ-4
IUR9 100n
21 13

10R

10R

10R

10R
7URA-1
RT8288AZSP
7

2UY1 2UY2 IURM

6UW2
VCC IUR3 2UR1 VIA
1 4
VIN BOOT 100n 100n
100n
3UR4

14
15
16
17
2
SW 3
1M0
DETECT12V 5 IUR4
EN 3UR5
6 +5V +5V
FB FUW4
120K 1% +22V
GND 2UY8

2UY6

2UY7

2UY3
GND HS

22u

22u

1u0
2UR2

9
1n0

100p
220K 1%
22K 1%
3UR6

3UR7

IURn 3URG-1 RES

5UR5 IURA
+12Vb 33R
3URG-2 RES
30R RES RES
33R
2URK 2URL
2URA

2URB

100n
3URG-3 RES IURB
22u

5UR6 FURA
33R +3V3
1n0 1n0 3URG-4 RES
3u6

B230LA-M3

2URC

2URD
33R

22u

22u
RES 6UW3

RES
7UR6
RT7297CHZSP
2

VIN

STEP DOWN IURC 2URE
1
BOOT
GND-3V3r

2URF IURD 100n

8 3
SS SW
+12Vb +5V +3V3 10n IURE 3URA
7 5 +3V3
EN FB
IURK 68K 1%
6
3UWB DBG

COMP
22K 1%

3URC
3URB

VIA
330R

ENABLE+3V3 GND_HS GND 1M0

4K7 RES

4K7 RES

4K7 RES

4K7 RES

3UWM

2URG
9

10
11
1R0

3n3
3UWA-1

3UWA-2

3UWA-3

3UWA-4

2URJ

CUR5
1n0

RES 2URH

100p
LTST-C190CKT
DBG

IURF
FUW2
6K8 5%
PDZ5.1B(COL)

GND-3V3r
3URF
6UW1
RES 6UW0

GND-3V3r GND-3V3r
GND-3V3r
RES 2UWS

GND-3V3r GND-3V3r
1n0

+2V5
2UWR
100R RES

100R RES

100R RES

RES
8

5
3UWK-1

3UWK-2

3UWK-3

3UWK-4

1u0
100R

7UW2-1
RT9025-12GSP
4

VDD
1

FUW3
+3V3 3 6 +2V5
VIN VOUT

ENABLE+2V5 2 7
EN ADJ
2UWV

22u

3UWL IUWE
2UWT

1
10u

PGOOD +3V3 ENABLE+2V5

2UWU

100n

47K
5
NC
2UWY

100n

GND
GND HS
8

RES

IUWF 3UWC
220K 1%

1% 470K
22
23
24
25
26

2UWW 7UW2-2
3UWD
3UWF

RT9025-12GSP
22K 1n0 VIA

18 10
19 11 +2V5 +2V5-F
20 VIA VIA 12
21 13

VIA
+3V3
14
15
16
17
3UWG-1

3UWG-2

3UWG-3

3UWG-4

3UWH-1

3UWH-2

3UWH-3

3UWH-4
470R

470R

470R

470R

470R

470R

470R

470R
RES

RES

RES

RES

RES

RES

RES

RES

4 2012-11-22

DC-DC
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 92

10-1-34 B06H, DC-DC

DC-DC
B06H 7UU1-1
RT9025-12GSP
B06H
4

VDD
3 IUU2
+1V5 6 +1V1-DVBT2
VIN VOUT
3UU2
+5V 2 7
EN ADJ

2UUA
2UU0

2UU5
IUU7
10u

22u

1n0
1R0

3UU7 RES
1
PGOOD
2UU1

1u0

82K 1%
5 IUU3
NC
GND
GND HS
8

3UU1

22K
3UU6 FUU1
IUU8 SENSE+1V1-DVBT2
82K 1%
*

220K 1%
22
23
24
25
26

680K

3UU4
3UU5

7UU1-2
RT9025-12GSP
VIA

18 10
19 11
20 VIA VIA 12
21 13

VIA
14
15
16
17

7UV0
NX1117C12Z
2
FUV1
+3V3 3 4 +1V2-FA
IN OUT
COM
22u 16V
2UV6

2UV7
100n

Optional
7UV2
RT9030-11GU5

+3V3 1 5 +1V1-FA
VIN VOUT
2UVC

2UVD
3 4
10u

10u
EN NC
7UV1
IUV1 2UV9 RT9187GB GND

10u FUV2 2
+3V3 1 5 +1V1-FA
IN OUT
3UV6 RES

3 4
EN ADJ
2UVB

100R
10u

+1V1-DVBT2 (*) 3UU5 GND

2

3UV1

120K 1%
1.10 V RES IUV3 3UV2
68K 1%

33K 1%
3UV5

1.20 V 680 k

4 2012-11-22

DC-DC
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 93

10-1-35 B06I, CI conditional access

CI conditional access
B06I +3V3
B06I
3PAC
CA-CD1n
10K 3PAD
CA-CD2n
3PAE 10K
CA-VS1n
10K 3PAF
3PA1 CA-WAITn
+5V +5VCA 10K
+T 0R3 +3V3
22u 16V
2PA1

+3V3
2PA2

100n 3PAM
CA-RST
100K 3PAN
7PA1 CA-RDY
20

74LVC245ABQ 10K
3PAP
1 VCC CE2n
3EN2 3PAL
3EN1 REGn 10K 3PAR RES
19 33R CA-CE1n
G3
+3V3 +3V3 10K
3PA3 RES 3PAS
CA-MOVAL 1 CA-IORDn
2 18 MOVAL MOVAL 3PA6 10K
100R 2 10K 3PAT RES
CA-MOSTRT 3PA8-1 8 3 17 MOSTRT MOSTRT 3PAA-1 10K CA-IOWRn
CA-MDO0 3PA8-2 100R 1 4 16 MDO0 MDO0 1 8 3PAA-2 10K RES
RES 3PAU 10K
CA-MDO1 100R 2 7 3PA8-3 6 5 15 MDO1 MDO1 2 7 3PAA-3 10K CE2n 9PAA CA-CE2n CA-OEn
CA-MDO2 100R 3 3PA8-4 5 6 14 MDO2 MDO2 3 6 3PAA-4 10K
10K 3PAV RES
100R 4 7 13 4 5 RES CA-WEn
8 12 REGn 9PAB CA-REGn 10K
9 11
GND GND_HS
10

21

3PAW RES
CA-WP
10K 3PAY RES
CA-INPACKn
10K
+3V3

2PA3

7PA2 100n
20

74LVC245ABQ
1 VCC 1P00
3EN2
3EN1 1
19 CA-D03
G3 2
+3V3 CA-D04
3PA2 3
CA-MOCLK 1 CA-D05
3PA5 10K 4
2 18 MOCLK MOCLK CA-D06
100R 3PA4 2 5
CA-MDO7 100R 3 17 MDO7 MDO7 3PA7 CA-D07 6
CA-MDO6 3PA9-4 5 4 4 16 MDO6 MDO6 10K 3PAB-1 10K CA-CE1n
10K 1 7
CA-MDO5 3PA9-3 100R 5 15 MDO5 MDO5 3PAB-2 8 CA-A10
10K 8
CA-MDO4 3PA9-2 100R 6 3 6 14 MDO4 MDO4 3PAB-3 2 7 CA-OEn
7 3 10K 9
CA-MDO3 3PA9-1 2 100R 7 13 MDO3 MDO3 6 3PAB-4 CA-A11 10
100R 8 1 8 12 4 5 CA-A09 11
9 11 CA-A08 12
GND GND_HS CA-A13 13
10

21

CA-A14 14
CA-WEn 15
CA-RDY 16
+5VCA 17
18
CA-MIVAL 19
CA-MICLK 20
CA-A12 21
CA-A07 22
CA-A06 23
CA-A05 24
CA-A04 25
CA-A03 26
CA-A02 27
CA-A01 28
CA-A00 29
CA-D00 30
CA-D01 31
CA-D02 32
MDI0 1 3PW2-1 8 CA-MDI0 CA-WP 33
33R 34
3PW3 35
MDI1 CA-MDI1 CA-CD1n 36
33R MDO3 37
MDO4 38
3PW4
MDI2 CA-MDI2 MDO5 39
33R MDO6 40
MDO7 41
3PW1-1
MDI3 1 8 CA-MDI3 CE2n 42
33R CA-VS1n 43
CA-IORDn 44
3PW2-4
MDI4 4 5 CA-MDI4 CA-IOWRn 45
33R CA-MISTRT 46
CA-MDI0 47
3PW1-2
MDI5 2 7 CA-MDI5 CA-MDI1 48
33R CA-MDI2 49
CA-MDI3 50
MDI6 3 3PW2-3 6 CA-MDI6
+5VCA 51
33R 52
CA-MDI4 53
MDI7 2 3PW2-2 7 CA-MDI7 CA-MDI5 54
33R CA-MDI6 55
CA-MDI7 56
3PW5
MICLK CA-MICLK MOCLK 57
33R CA-RST 58
CA-WAITn 59
3PW1-4
MIVAL 4 5 CA-MIVAL CA-INPACKn 60
33R REGn 61
MOVAL 62
3PW1-3
MISTRT 3 6 CA-MISTRT MOSTRT 63
33R MDO0 64
MDO1 65
MDO2 66
CA-CD2n 67
68
71 69
72 70

92789-055LF

4 2012-11-22

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 94

10-1-36 B06J, FE

FE
B06J B06J

+3V3

3KW1 3KW2
TS-CHDEC-DATA TS-CHDEC-DATA
560R 470R
3KW3 3KW4
TS-CHDEC-CLK TS-CHDEC-CLK
560R 470R
3KW5 3KW6
TS-CHDEC-VALID TS-CHDEC-VALID
560R 470R
3KW7 3KW8
TS-CHDEC-SOP TS-CHDEC-SOP
560R 470R

RES 2FS3

10p

2FS1 5FS1
SOC-IF-P IF-IN-P
100n 4u7
2FS2 5FS2
SOC-IF-N IF-IN-N
100n 4u7

2FS4 RES

10p

+3V3

3RW1 3RW2
TS-DVBS-DATA TS-DVBS-DATA
560R 470R
3RW3 3RW4
TS-DVBS-CLK TS-DVBS-CLK
560R 470R
3RW5 3RW6
TS-DVBS-VALID TS-DVBS-VALID
560R 470R
3RW7 3RW8
TS-DVBS-SOP TS-DVBS-SOP
560R 470R

4 2012-11-22

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 95

10-1-37 B06K, HDMI

HDMI
B06K B06K

RES
3HW6

390R
3HW1 IHW3
HDMI-ARC HEAC
56R
1%
3HW2

680R
RES

FHW0 3HW3 IHW1

+5V PWR5V
10K
3HW4

2HW1
27K

10n

3HW5 IHW2
+3V3 RREF
12K 1%
2HW2

100n

4 2012-11-22

HDMI
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 96

10-1-38 B06L, Control, temperature sensor and service

Control, temperature sensor and service +3V3

B06L 7CW0
PCA9540BGD B06L

3
VDD
3CWU
4 SDA-SSB SDA-SSB
3CW0 SD0
SDA-M3 SDA-M3 2 5 SCL-SSB SCL-SSB 3CWV 2K2
SDA SC0
4K7 2K2
+3V3 3CW1 3CWW +3V3
SCL-M3 SCL-M3 1 7 SDA-SRF SDA-SRF
SCL SD1
4K7 8 SCL-SRF SCL-SRF 3CWY 4K7
SC1
1CW4
4K7
FCWT SCL-M3 VSS
1

6
FCWU
2
FCWV SDA-M3
3
4 5
3CWJ 3CR6
SCL-M1 SCL-FE SCL-FE +3V3
BM03B-SRSS-TBT
47R 2K2
3CWF 3CR7 BM03B-SRSS-TBT
SDA-M1 SDA-FE SDA-FE +3V3
1CW7
47R 2K2
SCL-SRF FCWB
1
FCW4
2
SDA-SRF FCWC
3
5 4

1CWG +3V3-STANDBY 1CW6

1 SCL-SSB FCW3 1
DCW5 FCWR TEST-MOD FCW2
2 DCW6 FCWS 2
TEST-CON SDA-SSB FCW1 +3V3-STANDBY
3 3
4 F-OEn 5 4
5
6 7 BM03B-SRSS-TBT

3CWR
4K7
BM05B-SRSS-TBT
1CW5
3CU3 BM06B-SRSS-TBT
LED EJTAG-MCU-TDO
47R 1
EJTAG-MCU-TMS FCWD
3CU4 2
STB-GP0 EJTAG-MCU-TDI EJTAG-MCU-TDO FCWF
3
47R EJTAG-MCU-TCK FCWG
4
EJTAG-MCU-TDI FCWE
3CWB 3CU5 5
DVS1 STB-GP4 STB-GP1 EJTAG-MCU-TMS FCWH
6
22K 47R 8 7

3CWS
3CWT
1K0

1K0
3CWC 3CWD
DVS2 STB-GP5 STB-GP2 EJTAG-MCU-TCK
22K 47R
3CU2 3CR8
2CW2

2CW3
100n

100n

STB-GP3 ENABLE-WOLAN ENABLE-WOLAN +3V3-STANDBY

47R 10K
3CWK 3EW0
HP-DETECT IRQ-WOLANn IRQ-WOLANn
+3V3-STANDBY
47R 10K

3CWG
STB-GP6 SPLASH-ON
47R
3CUA
STB-GP7 RESET-ETHERNETn
+3V3
100R
3CWM 3CU0
STB-GP8 RESET-RF4CEn RESET-RF4CEn +3V3-STANDBY
10K
47R
3CWN DCW1
STB-GP9
47R
LCD-PWR-ONn
SDM
3CS0

3CS1
10K

10K

3CWP FCW0 DCW4 3CWE

STB-GP10 SDMn SDMn +3V3-STANDBY
47R 10K
3AW0

2CW1

100n
AMBI-TEMP-FUS AMBI-TEMP
FCS2 10R
2AW0

1E06 5
1u0

FCS0 FCS1 +3V3-STANDBY

4
3CS4-4 3CS4-2 3CS2
3 5 4 2 7 RXD-SERVICE
47R 3CS4-1 47R 3CS4-3 3CS3 47R
2 8 1 3 6 TXD-SERVICE
1
47R 47R 47R

3CRA
3CR9
MSJ-035-75C-B-RF-PBT-BRF
PDZ5.1B(COL)

PDZ5.1B(COL)

10K

10K
3CU1
AVLINK1 DETECT12V
1CS0

1CS1

6CS0

6CS1

47R
3CU6
STB-TXD TXD-STANDBY TXD-STANDBY
47R
RXD-STANDBY
3CU7
STB-RXD RXD-STANDBY
47R
FCW8
STB-SCL

3CU9
STB-SDA SDA-MC
47R
+3V3 3CUC
STB-RSTO RESET-FUSION-OUTn
+3V3 3CTD 47R STANDBYn
PWRON
47R 3CW3
KYBRD KEYBOARD_IRQ-SRFn
+3V3
10R
RES 3CUM
RES 3CUK

3CUL
10K

10K

10K

2CW6

100n

+3V3-STANDBY LGSEN
3CTY
3CW5 3CW2
10K

10K

10K

10K IR RC_IRQ-RF4CEn RC_IRQ-RF4CEn +3V3-STANDBY

3

7CT4 10R 10K

RES 3CUN

3CUR
3CUP

3CUS

NCP803
10K

2CW4

2CW5
100n

100n

VCC +3V3
7CW1 14
RES 3CUU

3CUV

PCA9554BS
3CUT

2 FCT9
10K

10K

10K

RESET RESET-STANDBYn
VDD
15 2 SC1-DETECTn
A0 IO0
2CT4

16 3 GND
1n0

A1 IO1 YPBPR-DETECTn
1 4 CVBS-DETECTn
A2 IO2
2TW0

9TW0

9TW1

9TW2
100n

RES

RES

5
1

3CUW IO3
SCL-SSB 12 7 FCW5 3CR2 100R ARC-SEL0
SCL IO4
8

SDA-SSB 3CUY 47R 13 8 3CR0 ARC-SEL1 7TW0

SDA IO5
9 FCW6 100R 3CR1 ARC-SEL2 LM75BGD
47R IO6
+VS

10
IO7 FCW7 100R
1CT7 3 7
DCW2 OS A0
11 IRQ-EXPANDERn SKHUBHE010
INT 3TW0
1 3 SDA-SSB 1 6
SDA A1
18 22 2 4
3TW1 47R
3CR3

19 23 2 5
10K

SCL-SSB SCL A2
GND

20 VIA VIA 24 DBG 47R

21 25

VSS GND_HS
4

9TW3

9TW4

9TW5
RES
17
6

4 2012-11-22

Control, temperature sensor

3104 313 6612
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 97

10-1-39 B06M, Strap options

Strap options
B06M B06M

+3V3-STANDBY
10K ICW1 10K
SPI-EN SPI-EN
3CUD 3CUE RES

3CL0 ICA1 3CL1 RES

+3V3-STANDBY CA-IOWRn CA-IOWRn
10K 10K

3CL2 ICA2 3CL3 RES

+3V3-STANDBY CA-WEn CA-WEn
10K 10K

ICA3 3CL4
CA-OEn
10K

3CL5 ICA4 3CL6 RES

+3V3-STANDBY CA-IORDn CA-IORDn
10K 10K

3CL7 RES ICA5 3CL8

+3V3-STANDBY CA-A14 CA-A14
10K 10K

ICA6 3CP5
NAND-CLE
10K

3CP8 RES FCP6 3CP6

+3V3-STANDBY F-OEn F-OEn
10K 10K

3CT6 3CTA
+3V3-STANDBY TEST-CON TEST-CON RES
10K 10K
3CT7 RES 3CTC
+3V3-STANDBY TEST-MOD TEST-MOD
10K 10K
3CT8 3CTF
+3V3-STANDBY ENABLE-STANDBY ENABLE-STANDBY RES
10K 10K

4 2012-11-22

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 98

10-1-40 B06N, Headphone

Headphone
B06N B06N

3DH3-1
1 8
68R

IDHN 2DH6 IDHM FDH1

HPHOL 2 3DH3-2 7
2
4V 100u 68R 1DH4
3
1
CDS4C12GTA

CDS4C12GTA

IDHP 2DH7 IDHL FDH2

4 3DH3-4 5
5

HPHOR MSJ-035-12D-B-AG-PBT-BRF
3DH4-4

3DH4-1

1DH2

6DH1

1DH3

6DH2

2DH8

2DH9
1K0

1K0

12V

12V

22n

22n
4V 100u 68R
FDH3
RES

RES
4

3DH3-3
3 6
68R

4 2012-11-22

Headphone
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 99

10-1-41 Layout top

1D01 1D02
1C20 1C251C26 1D56 1D55 1D54 1D53 1D51 1D50 1D52 1G55 1C27
1M90
2AAD
5D85

2CV8
3CVY
3CAG

BGV2

3GM5

3GM6

3GM1
3GM2
2AAC

2GWT
2CAT

3CAF 3AAB 9CAA 2CAS 2CAL 2D76 2D99 2D98

3GWD 3GWE

3CVN

3CVR
BGV9
2CAU
2CAK

5D77

2CAB 9CAB 2D81 2D73 2D70 2GWK

BGVM BGVD 2GWR
3CAH

2CAN
3CAB

5D00

2D91 2GWN 3CVW

2D78

9GW3
2CAJ

2D87

2GWW

3GWC

2GWV
3GWA

2CV9
1CV1 1CV2

3EM8
3EM9
3VWG
5D83 5D80 6GS1 3GS5

9GM1
9GM2

1T71 1C31 1C30

3VWF
1D0A
BGV1

BGVA
3GW1

2D5D
BGVL BGVE
2D0B
2GWU 3GWH
1CV4

BGVF

BGVH9GW2
BGV5

6D0A 9GW0 3GW5 3GWG

2UAT
3CVE

3GWN

2GWY

3GWP
BGVK

2GW2
BGVG
2D5C
BGV6
2D0A 3GW4
BGVN BGVB 2CVA

2UF6
1J50 7EM1
3D90 3CVD

2CVB
BGVC
5D74

BGVJ

2UA9
3D82 2CVC
BGV7
5D70

5D71

3D83 3CVC
BGV3

2D56 BGV8
1CV3
2D55

5D01
2UBC
2D71

BGV4

2D89
5D76 2D83

2UAA
5UB1

2UAM
2D48

3GM3

3GM4

2UAB
2UBA

3UAW
5D79
2VAK 3VAK

9EHE
3GEM
1VAP 2D80 2D82 2GE6
6VAF

3GEJ
2UA0

9GE2
3D74 3D75 9GE3
1VAN 3VAD
2D92 2D66 2J95 3J24
1UA2

3GEL

3GE9
9GE1

7UF8
3GEN
2UBF
2D94

2UF7
2D95

3J25 3GEA
2D62 2D64 5J0R

2EHY
1VAM 2VAG

2J25
2J27
3J1R 9UA1

7EHJ
1VA1

6UAF
2D5B 2D60 7UB5 2J08
2D75
3D72

2D88
3D73

2UBD

1VAL 3J1Y
2VAF 2J92
2D61

2D65

6GE3
1GE3 7UAC 5UAA
6VAB

1VAK 3VAA 2UF8

6GE2

3EHR 9EM3
1VAJ 2VAC 2UB0 3J1W
2UB9
2UB8

2D97
7GE0
2EHU
2D79 2D85

7EH4
3EHS
2UB7

2UB6 3J1Z DB34

3D62
1VAH 2VAA
2D59

2GE2
DB52

2EHR
DB93
2D93

DB31 DB32
2D67

DB50
9D50

3D79 3GEH 3GEG

2J7S DB49 3GE8

2J1E 2J1M 2J14 2J1P 2J20 2J1V

7UB1

7D60
2D54
2D77

1VAG 2VA8
2D96

2EHV
3D78

1GE0
7D71 3GE7
7J02

7J01

3GE0
3D70
2D63

9D51 2D58 9GE0

5D51

2J1N 2J82 2J1H 2J1B 2J1R 2J7T

3D63

2D84 2EHS

3UA8
2D49

2UAD
3UAB
2D53 2D69 6GE1
7D70

3CVF
2D57 2UA1

3CVG

3GE1
3D52 2D52 3D57 3UG9

2D5A
3J10

3UAC
6GE0

9GM5

9GM6

5EH0
3D51

2D50

2UAV
5D50

DB90
3D50 3D60 3D61
3J13
2D51 2GE1
7UA2
7D50

DBA2

DB53
3J1G

3GD5
DB48
3J1H
2D86

2D68
2D72

DBA5
3D58

3D76
3D77
9D55
9D54
3D71
2D74

9D52
9D53
3D55
3D56

3D54 2UB4
1GE2 1GE1

3CV8
3CV9

2UCL
3J1B
1D03

2UCW
2UCY
3J1A 3J20 3J2R 9EH8
3J36 3J3S

2J13
3J37 3J3T

9GW4

2UCK
2UCJ
DB40
3J21 3J2Q
DB57

DB56 DB43 DB41 3GW3

3J3A 3J44 3J4E 3J2E DB42
DB66 2J21 2J1J
3J3V

2J1G
3J3U

3J3Y 3J43
3J42

3J3G 3J3B 3J45 3J4F 3J2F

3J3H
3J48
2J26

2J24
3J3C
3J3D

3J3R
3J47
3J46

3J49
2RB8 3RB0
3J40 2EJ4
2RBF 2RBE2RBU 3RB3 2RBV

5UC0

5UC2
3J41
2RB7 2J2W 2J33 2J2U 2J2D 2J2J 2J37
1RB0 1UA1
2RB6
9RB9

2RDD

2J3J
1RD0
2RDE

2J35

2UPM
9RB7
9RB6
1R01

DRD1

2RDR 3J3L
7RDA

2EJ1
2RBD 3RD3
2RB5
1UP1
7EJ0
3J3M 2EJ6

7J04
DB25
2RBN
2RBP
2RBG

9RB8 2RBY

2GWD

2GWH
2GWB
3EJ4

2GWF
2GW3

2GW5

2GW7

2GW9

2GRD

2GRH
2GRB

2GRG 2GRF
2GR3

2GR5

2GR7

2GWA 2GR9
2RBA

2RD7 3CV2
2RBB 2RB9

2RBM

7RB0
3RB1

3EJ2
3EJ5

2GWG
DB79

2GWC

2GWE
3GW7

2GW4

2GW6

2GW8

2GRC

2GWJ
2GRA

2GRE
2GR4

2GR6

2GR8

2GRJ
DB76
2RD8
2RDJ

2RB1
5RB0

DB26

2RDA 3EJ1
2RBC

DB19
2J31

2EJ5

7RD0
2RBH 2RBW 2RD9
2RBR
2RBS

DB21

2UPF
2EJ3

5UP5
2RBJ 2RB2 2RDC

3EJ3
9RD12RDG
9RD02RDF

3J2Z

3RD1
2RB3

2RB4

9RB0

6UC2

7UC2
7UC3
3RD0

2RDP
1UA0
2RK02RK1

2KCS

DB22
2EJ7 2EJ2 3EJ0
3RD8
6UP6

3EJ8
2J39 2J3D 2J30 2J29 2J2T 2J2V 2J2Z
2KCR3KCE

3RD7
3RD4
3RD5

DRD0

2UPH
2RBK

6RB0
3RDB

9RD3

5KC7

2RBT
7UC4 2UPE
3KC4

DB10

1KC0
2KCC

5KC8
2KCB

2RBL 3RDA

1CV5
7J03 7UP2 2UPG
DB12
2KC0 2KC6
5KC1 2UPD

1CV6
5KA1 3KA0 2KCG DB11
DB71

2UPK
9KC1 2KCF
3KCB
5KA0 3KA1
3VWN
2J59

2VW2
9KC0 2KCE
2KC5

DB03
3KCA 5UP6
2UPJ 2UPC
5KC0 2KCD
3KC3
DB61

DB09 2UCC 2UPL

3CYB 3CVS 3CV4

5KC9

3VWM

7KC0
2KC1 3KC2 2VW1 3UC9
3J2U
2KC3

2J3K

DB00
DB17

2UCA 6UC0

7J00
2KC7

1CY1
3VWD

3VWW
3VWS

3KC9 2VWB 3CVT

3KC8 3VWV 3CY2 2UCB 5UC1

3CY3

3CY1
2VW8 2VW5
3KC6 5KC55KC6
2KCH

2KCP 3CV5 3CY4

3KC7
2KCJ

2KC2 2KC4
3KC1

3KC0

1F00
5FA4 2KCK
3FA3
3VWR 2VW4

5FA5
3FA4 2J3F 2J3H
3FA2 5FA6
3FA1 5FA7
1FA0

3VWP
2VW3
5FA1

3VW5 3VW6
3RW6
3RW4
3RW8
3RW2
3KW2
3KW8
3KW4
3KW6

2VWD

2FA5 2FA0 2VWC 3VW3

3VW4

2VWF3VWA
3VW9
2VWK

3J55 3VW7
2VWJ

3J54 2VWE3VW8
3VWJ

3J53
2FS2

3VWL
2FS1

3UWG 3UWH
5J05
2J42

2FZ6
2FZ3

2PA1
3UU7

3UU6
1J00
3J50
3J09

3VWH
3VWK
7UU1
2UUA 3UU4
3UU1 3UU5
1H01

2J41
3FZ0
2FZ5
2EFL 2EFK

2J10 2J11
3EE2

3CT0
3CTR
3CTD
6EF2

1E00
3UV6

1P00
3CTJ
2EFN 2EFM

3CTU

3CR7 3CTZ
3CUA

3CR6
2UU0

5FS1 5FS2
2UU1
3UU2

3CW2
2FS4

7CT3
3CTK

3CT3 3CT2
2UVC

3HW4 3EW0
3CTA 7UV2
2FS3

3CWK
1EF0
3CT1
3CTH
5EF1

2UVD
2EFB 2EFC
3EFY
3UWM

3CT8 2UV6
3UWA
7HA1

3CTF
6UW0
2EF9
2EFZ

3EF2

2EFA

7UV0
2EFH
3EF3

1CWG
2UWR

2UWT

3HAV
2EFJ
3HAW
2UWV
1H02

2HAB

3EFP
3UWB
3UWL

3CP6 3CP8

7EF0 7UW2
2UWU

7HA0
3UWD 2UWW

2UWY
3UWF 3UWC
3EF5

3UWK

3HBP
2HA9 2UWS
3HBQ
3CWE 2CW1
3HAR 6UW1
2DH7

3EFH 3EFU DCW4

3JA6

2UV7
2HA13HA4

3CS2
3CS1
3CS0

3CS3
3CUE 3CUD
6CS1 6CS0 3CS4 2VC3
3HA3

2URJ

2VC7 2VC9
2VCA

2URH

3URC

2VC4
3URB
2URF

3URF

3VC3 3VC7
1CS0 6VC4 3VC4 6VC7 6VC6 3VC6 2VC8
2HA2 6VC1
1CW7

2VC6 2VCB
2URG

3URA
6VC3

1VC5

1VC7
2VC1 3VC1
1CS1

1VC1

6VC0
2HA43HA2

3UR5
3UR4
3UR7
3UR6
2UR2
1CT7
3HA1

1VC4
2UR3

1VC2 1VC8
1CW4

7UR6

3HA0
2VCC 3VC8

7URA

2HA5 3VC0 3VC9

3CUW

2VC0 2VCD

1E06 1VA8 1VA4 1VA6

3CWW
3CWY

1VC3 1VC6
3CW0
3CW1

2UR7
2UR5
2UR6

3CUY

7CW1 3VC5
1H03

2VC2
6UW3
3TW0
7TW03TW1

2CW6

6VC5 2VC5
2UR0

3CUM 6VC2
1CW6

3VC2
2URE

2URB

5UR3
5UR1

3CUV
2URA
2UR4
3UR3

3CUU 2UR1
2DH6

3CUL
3CR3
3CUN
3CUR
3CUK
3CUS

3CUP

3CUT
9TW2
9TW1
9TW0
9TW5
9TW4
9TW3
2TW0

5UR6

5UR2
3EAC
3EA7

3EAG

7HD0
3EA8

1CW5
3EAD

3EAH
2EAA

6DH2 3DH3 6DH1

1DH2

2EA9 2EAB
3CWS
3CWT

9HD9 3HDU
2DH8
9HA1
5HD5

1DH4
2HDD

2HD6
7EA0
1DH3

2DH9

2URC 2URD 2UR8 2UR9

1H04 1E01 1E02 1E03

4 2012-11-22

SSB layout bottom

3104 313 6612

19370_167_130228.eps
130228

2014-Jan-10 back to
div. table

Downloaded from www.Manualslib.com manuals search engine

 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 100

10-1-42 Layout bottom

3CAA
2CAP
FAA4
2UA5

3AAD
FUAM FAA6
2UA2

FUA4 FGVS FGVQ FGVN FGVL FGVH FGVF FGVC FGVA FGU0 FGWY FGWV FGWT FGWR FGWP FGWL FGWH FAA3
FGVW FGVU FGV8 FGV6 FGU4 FGU2 FGWF FGWC FAAZ

FAA22CAA

3CAE
2GY4
2GY5
3GY6

3GY8
2GY3

2UA3
2GY9

2GY7

2CAM
3CAC
3CAD
2CAD
2CAR
3GYB
3GYA

2AAV
FD30

2AAW
3AAC
FCVD IGR7 3GW6 3GW8 9GW1
FUA6 FUAB 3UA4 FUA5 FUAA FUAL
3AAA
2UAU

FGVJ

IGRA
FGVY FGVV FGV9 FGV7 FGU5 FGU3 FGWG FGWD
FGVT FGVR FGVP FGVM FGVG FGVD FGVB FGU1 FGWZ FGWW FGWU FGWS FGWQ FGWM FGWJ
FCV1

IGR0
FD33 ID99 FAA9

IGR9
9GW5 FAA7 FAA0

2AAE
FCVJ FCVK 3GWM

2GWS
FGWN
IGV7 IGR6 IGR3 2GWL IGR2 FAA1
IGR1

3GW2
ID91

FGWK
IGR8
ID94

3GWF
FGR4
FGVK FGV5 IGW7 FD69 ID57 FD70 FAA8
IAA0

2GWM
FGS22GS2 FGUF IGW6

3GW9
3GWJ IGW4
FGW0 FGVZ FGWB IGV5
FGS1 IGW9
3CVB

3CVA

FAA5
FCVC
7GM1 FCV3
IGR5
FGWE FGU9 IGW1
IAA1
FD90
2GS1
FCV2 FGR3 3GWK

IGW8
FGR5 IGW5 IGW2
FGR7

FGU7
3EM3 9GS1 9GS2 9GM3 FGR2 3GWL 3GWB
FD31

IGU8
FCVE FGR6
2EM5 2EM4 FCVA

5D75
5D81
2EM1 IEM1 FCVH
9GM4 IGR4 2GWP IGW3
FGR8 ID96
1EM0

FGR9
FEH7 3EM5 2GY8 FCVL
FGWA
2EHP 2GYA FUA9 FUA0 FUA7 FUAD FUA8 FUAK
FGR1
ID95
1GS1 FCVG FCVM FGU6 FGVE ID98
2GY6
3GY5

3GY9
2GY2
2UA4

7GS1
3GY7
2GY1

FUA1 FD32 ID93

FEH8 2EM3 FUAE DFW1
2EM6 ID88
3EM6
3EM7

3GY1
DFW2

2EM2 FUA3
FCVF
2FW6
3EM4
IFW1
2EM7
IEM2

5FW3

FEH9
7GS3
IGS4

2EM0 IFW4
2GS3

2FW3

3FW7
3FW4

7FW1 FGV0
7GS2 3GS3

IGS52GS5 3GS1 3FW3 3FW5

9EM2
9EM1

FEH4 3GS4
3GS6 IGS1 3FW6 3FW8 2FW5
IFW5 FUB2
2UBB ID50 FVAG
ID51
2FW4

IGS2 IFW2 IFW3

ID52 ID82

2UBJ
FVAF2VAJ 3VAF 6VAH

2UBK
IUAM
2EHN
7EH2

IUBB IUBC ID62

9UA0

3UA9 IUFR 2UBE

7UA3 3J2S 3J22 3J1N 3J1S 3J1C
IVA1

3UBE
3J18 FVAE 3VAE 2VAH 6VAG FVA1
3UAK

3UBB
2EHL

2EHM

3J2T 3J23 3J1P 3J1T 3J1D 3J19

2UBG
FEH2 IJ0S
3UAS

2UAL

3UA7
3J1K
FVAD 3VAC 6VAE
9UA2

7UAB

IUB7
IEH62EHJ IUAR IUAL
3UA6

FVA4
FJ03 3J1J 3UBD
IUAN 3VAB 6VAD
3EHV

FEH3 IUBA
FUAU 3UAV IUAK3UA5 3GEF 3UBC FVAC
IVA0
6UAB

IUAP FGE7
7UAF

3EHP 3J1M
6VAC

IUB9
3VA9 2VAE
2EHW

3UAY IUAT IUAV 3GEE 3J1F 2UBH

IUB8
ID53 2VAD
3EHT IEH5 3J1L
3EHN FEH5 IEH4 IEHJ 3UAR 3J1E
9GE4

6VAA
6UAC

FGE6 FVAB 3VAG

FUAG
6UAD

FVAA
2EH93EHU
3EHJ

FEH1 2UAK DBA8 3J2A ID63 ID81

3J28 3J2B 6VA9
7UAD

IUB6
IEH1 FGE3 3VA8 2VAB
FCVN

DB33

5UB0
3EHW 3EM1 2UAN DB94
DB51 ID75 ID76
3J29 3J2D FVA9
2UAR

ID70
7UAA

3EHY 3EM0 FUAP ID61 ID80 3VA7 2VA9 6VA8

2J83 2J7P

2J1D
IUAS
IEH0
FUAT
2GE0 3GE6 3GE2 FGE8
DBA1
DBA3 3J2C
IEH3
3J1U
IUAJ

5TA3 IUFT 2GE4 2GE3 3J26 ID97 ID83

DBA4 2J19 FVA2
2EHT

2J7U
FGE2
2UAP

DB64
3J1V

FJ09
IUFS 3GEC 3GE5 2GE5 3GE4 FGE1
DB62 3J27 ID77
2J15DBA7
1TA1

ID69
ITA1 5TA2 DB39 ID55
IUFU
FUAF 3UAP 3UAN 3UAT FGE4 3GEK DB91
DB55
3J2K
IUA2
3GEB FGE0 IUB4
DB38 ID66
2UAW

FUB1
3UGA

3J2J
2UAS

3GE3
DB36 ID58

3UB8
3UB7
2TA1
3GM7

ID56

3UB3 3UBF
FTA2 FUAH DB35 DB54
3TA1 IEH2
3J2L IUB3 ID65 ID54
IGE1

IUB5
2J86

2J1F 2J1U 2J81

2J1A
3J14
DBA6
3CVU
2J17
3J12
2J85

DB98
3CV7

3CVP 3CVM

3J2M

3UB9
3UB5
3CYC

FD50
7GM2

3UBA
3J11
2J16
2J84

2J1Q
2J1S

2J18
3J15

FTA1 IUA3 3UAL 3UB4

3UB6 ID90
2J12
DB45

3TA2 FTA4
FJ08 DB95 DB63 2UB3 ID87

2J89
DB01
3J17 FUB0 FD66 FD64 ID79 ID84 ID78
FTA32TA2 DB44 DB92
DB97 2J1W
DB65
FCVB 3J16
3CV3

2J1C FD65
FTA5 FGE5 2J1K 2J1L
2J1Z

DB58
DB59
3J2G
FTA6 DB99
2TA3 3J2H FD63
FD67
ID89

3J2N 3J4D 2J01 3J4L 3J34

3J3J 3J3P

3J4P 3J3Z
3J3W
3J3K 3J3N
2J2G

3J3F 3J38
3J3E 3J39
3J2P

3J32
3J33
FUC0
3J4C 3J4M 3J35
2J80
5TA1

2J93 5J0P
DC07
3J4A 3J4J 3J4G

3J4N
IJ0R
DB73
3J4B 3J4K 3J4H

IUA1
FJ0BDBC3 DBA9 DBB5
IRB1
2J5A IRB0
2J2K

DBC7
2RDB

2RDM
DB24
FEJ9
2J2F DB23 DBB9 3RD6
IJ0G FJ04

DB27
DB20
FEJ1 FEJA DBB4
3J31 2RD6

DB29
FEJ5 5RDC 2RD1
2J04

2RD0 2RD5
5J0K
3EJ6

DB05DB07
FEJ2
FEJ4 3J03 2J2H 2RDN

2J2C
DB70 IRDC
2J4Z 3J04 3J30

2RDS
FEH6

IRDB5RDB
FEJ6

FEJB FRDA
FEJ3 2J4W 2J02 2J2E DBC0
2J96
2J4H

3J02

2J36
IJ0L

2J38
3EJ7

DB77
IJ14 2J34 2J2L 2J32 5RDA IRDA
FEJ0 IJ00 DBC6
IUA0 IUC8 IJ0M
2J4L

DB85 DB74 DB30

6UP4
6UP5

2J98

FEJ7 2J00 IRD2 FRB0

2RD2
IUC2
2J5K 2J5D

DB86
IUPE IUP4 IUC3 DB80
FEJ8
9GA2 DB75 2J7Z IKC9 IRD0 2RD4 2RD3 IRD3 IRD6
3UPB 2UCE 2UCD 3UC1 DB46 FJ0ADBC2 IRD1
3UC3

2UC1

FUA2 2UCF 2J2M DBB7

3RD9
3UPD

2RDT
DB78

9RD2 3RD2
DB47
2J7Y
2J4J

DB18 IRD5
IUC7 IUCB DB83 DB88 DB89
2J1T

2J2N
2J2P

IJ0P 2J74 2J5U 2J09 2J7V DB04

3UC2

DB68
IUC6 2J23 3J01 DBB1
2RDH
2J88

2J5G
3UC0

2J87

IKC8
2J6A
2UCH

3UC8 2J03
7UC1
3J00

IUPJ
2J4Y

2KCL
IUP23UPE 2J7W
DC03
2J5L 3J2W
2J4F

DB87 DBB6 IKCB

2UCP IJ11 5J0G 2J6S 2J22 DBB3 DB02
DC02

2J65
2J4N 2J7L

2J5M
2J7H 2J2B
5J0E
2J6M

DB13
2J7B
IUC4

DB82
5J0D

DB96
6UC1

2J4G
3UC4

IUC1 2J72 IKC0

IJ0N

DB16
5J0F DB14 DB15
FCY7

DC06
IUAB

IUC5
2J6F

FUPA DB72 DBB2

2J6U

DKC1
2J6Z 2J7J
2J2R IKC1
2J5B

DB67 IKC3
2J28

FCY8 2J6W 2J99

FUAC IUC93UCR 3J2V
2J7R

IUAF 3UAE
2J5N

7UC0
2J6L
2UAJ

2J94
2J05

3FZ1 2J2Y
IUPF

2J68
2J07
3J05
2J06

3J06

2UCR 2J2A
3UD0 3UD1 3UCF 2J4P 2J76 FJ05 DB69 DBC4 DBB8
2RDK IKC2
DBC1

IUF1 2J73
2J3G 2J7F

FCY9
7UA0

3UG8 DBC5
IUF8 3UCE
2J3U 2J6C 2J6R 2J2S 2J3B
3UCG

2J5F
3UCN
3UCP

3UG0 3UCA IJ04 2J4M 2J3A 2J3C2J3E IKCA

3UG4

3UC7

5J03
2J4E

2UCM IUCP 2J75 2J5C DB08

FFA9
2J3T IJ0D 2J4D 2J78
7UF9 2UF9
3UG3

IUF0 IUCA FCY1

2J4A 2J7K
IJ0B

IUF3 3UCB IKC6

2FA8
2FA7
2J7A 2J5H
3UAH

3VWC
5J0A
IUAA

DBB0

2J49 2J6G 2J67 2J6T

2VWA

2J4C
2J70

FUAV IUC0 IJ03

IUFQ 2J4B 2J71 IKC5
IUFP
7UF7 FCY3
2J3S 5J0B
2J3P 2FAG
2J7C

2J3R
IJ02

3UAF IUAC IUF6 3UCD 2J7D FKC1

3UAG

2FAH
2J7G

5J02 5J01
IJ0C

IKC7
2J6V 2J6H
IJ13
FUAN

IUF7 FCY2 FJ01

9J03 2J90 2J77 2J5R DKC0
3UG2 2UCN FCY4 3VWB IJ12 2J5W FFA82FAF
2VW7

2J79
2J3Y
2J6P

2J6Y
2J69

DB81
2J5Z

IKC4
3UCC FUC1
IJ01
9J04 2J91 5J00 2J6J 2J6N
2J3N
FCY5

3VWU
5J0J

FCY6
2J3M 2J6B 2FAB
2J66

2J60

3FAC
FFAC IFA4
2VW9

IUAD
5J09 2J48 2J46 IJ09 5J08 2J63 5J04 2J3W 2J7E
3VWT
2VW6

2J45 2FAC

7KA0
2J62

FJ02 FFAE
2J4U

3FAD
2FAD
2FAE
IJ0A FFAD FFA4

3FA7
2J4V
2J5Y

5J0M IFA3
7FA1
IVW2
2J47
IJ05
2J6D 5J0C 2J64 IJ0F 2J61 IJ0E 3PW4 3FAB FFA7
DVW5

IFA6
3PW2
DVW6

2J97

IFA5
5J0L IJ0H

FFA3
2J40
IVW1

IVW4 FJ0H
2J5S
2J4S

2J5V 2J5T 2J3V 2J6E

2J4T

3PW3 3FA9 3FAA 2FA9

3KA5
3KA3
2RDL
3KW7

3RW1
3RW7
3RW3
3RW5
3KW3

3KW1
3KW5
5J0H

2J54

7FAA
3PW5
DVW3
2J52 2J51 2J50 2J43 3KA2 3FA8

5RDD
5KCA
FFA6
2J44

IJ0J

IFAA
2J5P

IJ0K
3PW1

FFAB 3KA4 FFA5 2FAA

2FA1
FFA2
IVW3 IJ06 2J3Z
5J0N 2J55 2J53
2FZ4

FJ0G FJ0F
DVW1

FJ16 FFAA
5FAA

2FA3
2FZ1
2FZ2

2J4R
DVW4 DVW2

IVW8
IJ10
FJ10 5J07IJ08 2J56 2J58 IJ07
5J06 FJ0J 2FA2
IVW7
3J51
3J08
3J07 3J52

IUU2 2UU5
3PA7
3PA5

IEF3
3PAB
3PA1 FUU1
3PAW
3PAD

IEA3

2EFP
8001
8002 FHD8
2HW2 3HW5

5HD4
2HD5
IUU8
FEFA
ICT1

DEF0

IEA4
3CW3
2UV9

2CW4

3CU4

IHW2
3CTY

IEE0 IEE1
2PA3

7PA2
3CU3

IUU3 3HDS
FEFB
3CWN
ICT3 2AW0

FCT7 3AW0
3PAN FCT5 FCWF
IHDK
3CU1
3CWD
2JA4

FUV1
IUU7 FEFC 9HD8
3CU5

7UV1
FCT2

3CT9 DCW1 3CWF

3PA2
3PA4

3CU0
3CTB

IHD4
3PA9 3CU7 3CW5 2CW5 3CWJ
3PAY

3PAF
3PAL

FEFE
3PAM

FCWD
3CU6 3CWM
3CR9

IUV33UV1
3CRA

FEA4
9PAB FCT6 2CW2
3UV5 3UV2 2HW1 2EFU
3CR8

ICA3
3CWB IHW1
3HW3
2UVB FUV2 IEF2
FEF2

ICA2 ICA5 ICA1 ICA4 3CU2

FCT8
3PAV

3PAS

3PAE
9PAA
3PAP
3CL3

3CL2
3CL7
3CL8

3CL4
3PAT

3CL5
3CL6
3CL1
3CL0

ICT2 2CW3
3PAC
3PAR
3PAU

FCT3 FCT4
3CWG FCWR FCWS FHW0
3CWC
2EFS
5EF4
5EF0

ICW1 FEA7
2CT4

FCW8
3CU9 FEF1
FHB5
5EF6
2PA2

DCW5
7CT4

FCP6
2JA2 FUW2 IEF1 2EF3
2EF8
2EFF

FCT9 IUWE
3CWP 3CT6 DJA8 2HAA FHAG
3JA0 FHBA
7PA1

3PA3
2EF2

FCWE
FEF4
3PA8

3PA6
FEF3

DCW6
9JA5
3PAA

FEF02EF6

2HAP
DJA2 DJA0

3HB1

DJAE
2EFT

FEF8
5EF5
DJA3 DJA1

3HB0
3JA1 2EF5
DJAD FHA4
ICA6 FVCC
9JA4 2EF1

7JA0
DJAB

FUW3
FCW0 DJAC
FEF9
3HAY FHA3
FHD4
2EF7
3CP5

5HD0
2HD0
2JA1
DJA4
2EF0 FHA6 2HAM
2HAD
FEFD

2JA0
3EFT 3EFS

9JA3 2HAJ 3HD4

3HAS

2HAK
DJA5

7EF1
3EFR
2EFV 3EFN

DJAA 3HAA IHDF

DJA6

FHA8
2HAG
2EFG FEF7

DJA7 FHAM FHB4 9HD4

DJA9 IUWF FEF6 2HAL
2HAF
2HAN
3EFJ

6HA1

7HA5
IDHP
9JA6 3CUC
3EFM

FEF5 2HB5
3EFL

3HA5
2HB4

3EF4 FHB2 5HA6

3HAP

FCS0 FHAH
FVC8 FHB7
3JA5 FHA7 FHAY
IURF

5HA5

FVC2

3HAB
FHAP

5HA9

FVC5 FHBC IHB1 3HA6 IHB0

FHAV
FCW4
IURD FVC7
IURK
2UY8

FHB8
IURE FHAN FHAR
FHAW

IUR4 IUR9
FHB1

FCWC
FHAS
FHB0

3CWU
FHAF
7CW0 FCWV FCW1
FCWB
3JA3

3JA2

FCWT
3CWV
7JA2

FHB9
FCW3 FVC9 FVC4
IURB IURC
IUR0
2URK

IUR3 DCW2
FVC1
3URG

FCS1
FVC3
2URL FCW2
FVC6

FHD5
IUR8 FVCD
FVCA FHD2
IDHN
5HD1
2HD1

IURN 5UR5 IURA FCW7 3CR1

FCWH

IUR2
FCW6 3HD9
IURL
IHDG9HD5
3CR0

FHD1
3JA4
3UWJ

IJA0
9HD0

FJA0
IHB4

FCW5

3CWR 3CR2 FHD0

3CT7

IHD8
2UY1

FCWG FEA8
FEAE
3CTC FEAD IHB5 IHD19HD2
3EA5
2UY3
2UY2

IHDM
IEA1

IURM FEA6 FEA5 2EA3 FEAC FEAB FEAA FEA9 FEA3 FEA2 FEA1 IHD7 3HDT
3EA1 3HBS 9HA0 IHB6
3HB2
3HB4

FEAH 3EA3 FCWU 9HD6 FHD7 IHDL

7HA2
2EA2
6UW2

FDH2
FHD65HD2 3HDE
2EA4 7HA3
3DH4

3HW2
3HW1
3HW6

IHB2
2HD3 IHDH
FUW4 IDHL 2EA5 FHD3
FHAL
3HB3

2UY5 IHB3 3HAL

FCS2

FURA
2EA0 IEA2 IHW3
FUR1 FVCB IDHM
FHB6
FDH1

1EA0
3EA4

FHAE

2UY6 2UY7 IUV1

IJA1
2EA1
2EA7 2EA6

FDH3

4 2012-11-22

SSB layout top

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 101

10.2 310431366185 SSB

10-2-1 B01A, Power connector

Power connector
B01A B01A
+12V

BL-SPI-CS_BL-I-CTRL CUA1 BL-I-CTRL +12V DETECTION

6
7UA0-2

3UAF-3
1M90

22K
BC847BPN(COL)
FUA1 3GY1-2 2 7 100R BL-DIM3 4 RES
1 IUAA 3UG3
FUA4 3GY1-3 3 6 100R BL-DIM4

3
2
FUA3 3GY1-1 1 8 100R BL-DIM5 5
3 1K0

5
3GY1-4 3

100K 1%
FUA6 4 5 100R BL-DIM6

3UAF-4
4
FUA9 3GY5 100R

22K
5 BL-DIM7 IUAF

3UD1
FUAB 3GY6 100R BL-DIM8
6 IUFQ

7
IUF8 3UG4-4

3UAF-2
7 3UA4
FUA2 100K

22K
STANDBY

100K
8 IUAC
9 100R 6
FUAM 7UA0-1

2
10 IUAB FUAN
+12V BC847BPN(COL) DETECT12V
11 2
12 FUA5 FUAC 7UF9-1
1

3UG4-3
13 +12V-AUDIO BC857BS(COL)

3UAE

1% 68K
14 FUA7
FUAD 3UD0 3UG8
15 IUF7
16 1M0 22K

2UF9

100n
1u0 RES
FUA8 3GY7 BL-ON

3UAG RES
17

2UAJ
FUAA 3GY8 100R BL-I-CTRL

100K
18

1
FUAK 3GY9 100R BL-DIM1

3UAF-1
19
FUAL 3GYA 100R

4K7

22K
20 BL-DIM2
+12VAL 100R +3V3-STANDBY
21 IUAD
3GYB POWER-OK BC857BS(COL)

8
22 +3V3-STANDBY
100R 7UF9-2

3UG4-2
23 GND-AL
24
25 +12V ENABLE+3V3

100K
26 FUAV
27
28
30 29 FUAE

3UG4-1
+12V-AUDIO
SMAW200-H28S2

FUAH
10n
10n

1n0

10n

1n0

1n0

1n0

1n0

1n0

1n0

1n0
2UAB RES

2UA3 RES
2UAU RES

16V
2UAA

2UAT

2UA4

2UA2
100n

100n

100p

100n
1u0

1u0

2GYA
2GY1

2GY2

2GY3

2GY4

2GY5

2GY6

2GY7

2GY8

2GY9

2UA5
RES
100u

FUAF

GND-AL +22V +12VAL

+3V5-STANDBY +12VAL +12VAL

RES 2 3UAN-2 7

RES 1 3UAP-1 8

RES 2 3UAP-2 7

RES 3 3UAP-3 6

RES 4 3UAP-4 5
RES 3UAN-1

RES 3UAN-3

RES 3UAN-4
1

4K7

4K7

4K7

4K7

4K7

4K7

4K7

4K7
2UA9 RES
K

12K 1%

4
6.3V 330u
TS2431

3UAV-3
7UAF

2UA0
2
240R 1%
A

1u0 AMBI-POWER
3UAR

2UAK

IUAL
100p
RES

9UA2-1 RES
3

+12VAL
9UA2-2 RES
9UA2-3 RES
9UA2-4 RES 1 4 FUAP
3UA5 IUAK 2UAN
BC857BS(COL) BC857BS(COL)
7UF8 2 7UAA-1 7UAA-2 5
4K7 1% 100p
RT9193-33GB
3K3 1%

3UAT-4

3UAT-3
2UAM
3UA6

IUAJ 3

10K

10K
1u0
6
1 5 FUAU IUAV
+3V3-STANDBY
12K 1%
3UAV-4
IN OUT

3UAW

0R1
12K 1%
3UAV-1

3UAT-1

FUA0 IUFR
3 4
10K

EN BP 1UA2
+12VAL AMBI-POWER 3UAY
COM
T 2.0A 63V IUAN GND-AL
2UF6

2UF7

2UF8
1u0

22n

1u0

FOR DUAL SIDE AL ONLY 100R

2

5
6
7
8
IUAP
7UAC
4 SI4778DY-GE3
12K 1%
3UAV-2

1UA0 IUA0
PDZ15B(COL)

+12Va
1
2
3
REF 3
3UAT-2

6UAF T 3.0A 32V

6UAC
10K

+3V3-WIFI IUAR 6UAB

+12V 1 7UAB FUAT AMBI-POWER
B230LA-M3 BC847BW
FUAG S1D
9UA1-1 +3V3-WIFI 2 IUAS
1UA1 IUA1
9UA1-2
PDZ15B(COL)

+12Vb
330u 6.3V

9UA1-3
T 3.0A 32V
6UAD
RES 2UAV

9UA1-4
3UAS

2UAL

100p
10K

+12V
5UAA

IUAT 3u0

22u 16V
3UG0-2

3UG0-1

+3V3
RES
2UAP

2UA1
22K

22K

1u0

+3V3-STANDBY +3V3-STANDBY
AMBILIGHT 3-SIDED PROTECTION
IUF0
IUF1
3UA7

4
10K

GND-AL GND-AL
BC847BPN(COL)
3UAL

7UF7-2
RES

5
10K

IUAM IUA2 7UA2 RES

RES 9UA0 3UA8 PMV31XN
RES
3
100K IUF6 CUA0 ENABLE+1V5+1V1 7UAD
IUA3
3UA9 optional SIP32429DN-GE4
STANDBYn 7UA3
2UAD

RES 3UAC

3UAH
RES 3UAB
220K
100n

BC847BW 1 9
1R0

47K

AMBI-POWER
3UG0-3

3UG0-4

10K +12VAL
3UAK

2 VIN VOUT 10
22K

22K
RES
10K

2UAR

IUFS 4
1u0

IUFP EN
8
IUFT FLG
5
RSET
6 7
IUFU PG
STANDBY 3
IUF3 3UG2 CSS
7UF7-1 2 DETECT12V
BC847BPN(COL) 3UG9 GND-AL GND
22K +3V3
2UAW
3UGA

100n

6
11

1
1K8

10K
1X15
2UAS

100n

REF EMC HOLE

GND-AL
GND-AL GND-AL

GND-AL

5 2012-11-08

Power connector
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 102

10-2-2 B01B, Fusion supply

Fusion supply
B01B B01B

5UC1 IUC0
+12Va
30R
2UCC
2UCA

2UCB

2
3
4
10
22u

22u

22u

5
6
7
8
+12Va
IUC1 IUC2 7UC2 1
3UC0 4 SI4778DY-GE3 9
RES

1
2
3
10R 7UC4
AON7932
8

3UC1
+5V

3R3

5
6
7
2UCE
2K2

10u
3UC2
2UCD
RES 3UC4

1R0

7UC1 IUC3
BC847BW
220p

PDZ5.6B(COL)
IUC4
6UC1

3 3UC3-3 6

4 3UC3-4 5
B340A-M3
6UC2

3UC3-1

3UC3-2
2UCP

5
6
7
8

10R

10R

10R

10R
10u

IUC5 7UC3
4 SI4172DY-GE3
270K 5%

2
RES

1
2
3
3UC7

7UC0 2UCF
RT8228DGQW 2UC1
7

VCC IUCB
IUC6 2UCH IUC7 3UC8 1n0 1n0
1 5 5UC2
BOOT
6 3R3
100n
9 NC 4
UGATE 2u0
16 5UC0
IUC8 FUC0
3
IUCP 14 PHASE +1V1-FD
3UC9 DBG 6UC0 DBG TON 2u0

2UCJ RES

2UCK RES

220u 2.5V
+5V 12 2
PGOOD LGATE

2UCW

2UCY
2UCL
22u

22u

22u

22u
2K2 IUCA
LTST-C190CKT 13 8
CS FB

ENABLE+1V5+1V1 11 10
EN MODE
2UCR RES

1%

GND GND_HS
3UCA

150K

15

17
1n0

GND-1V1F
CORE VOLTAGE SUPPLY FUSION
GND-1V1F GND-1V1F

GND-1V1F RES 2UCM

22p
3UCG 3UCB 3UCC FUC1
DVS1 IUC9 SENSE+1V1-FD
180K 1% 22K 1% 10R
120K 1%
12K 1%

22K 1%
3UCR RES

3UCD RES
3UCN +1V1-FD
3UCP

3UCE

3UCF
1M0

10R
220K 1% 2UCN

1u0

GND-1V1F GND-1V1F GND-1V1F

5 2012-11-08

Fusion supply
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 103

10-2-3 B01C, LNB supply

LNB supply
B01C B01C

+12V +12V-DVBS
1UP1

T 3.0A 32V
+12V-DVBS
2UPL RES

5UP6
100n

30R

IUPJ 10u 25V

RES 2UPM
2UPC

2UPD

2UPE
100n

10u

10u

5UP5

10u
7UP2
17

LNBH25LPQ
VCC
IUP4 +V-LNB
LX
3
IUPF 2UPJ
16
VBYP
470n

B230LA-M3
21
VUP

RS1D
6UP6

6UP5
6
ADDR FUPA
20 +V-LNB
3UPB VOUT
SCL-FE 7
SCL
B230LA-M3

47R 1 IUPE
3UPD
2UPK

6UP4
220n

SDA-FE 8 DSQ 5
SDA
47R 10
11
47u 25V

47u 25V
2UPG
2UPH
2UPF

NC 12 1u0
F22-DISECQ-TX 22 13
DSQIN
14
24
26
27
28
IUP2 29
3UPE 9 VIA 30
ISEL
22K 31
32
GND_HS

33
PGND

GND
2
15
18
19
23

25

5 2012-11-08

LNB supply
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 104

10-2-4 B01D, USB internal

USB internal
B01D 9EHE-1 RES
B01D
9EHE-2 RES
9EHE-3 RES
9EHE-4 RES

2EHL

10u
7EH2
RT9187GSP

1 3 +3V3-LAN
2 VIN VOUT 4

100u 6.3V
33K 1%
+3V5-STANDBY

3EHW

3EHY

RES 2EHY
8 5

1M0
EN BP|ADJ
7
NC

2EHM
10

10u
VIA IEH3
GND

10K 1%
3EM0

3EM1

1M0
GND HS

9
ENABLE-WOLAN

7EH4 RES
reserved TPS61200DRCG4
USB1-DM 9EM1 USB-WIFI-DM
5 2
+3V3-WIFI VIN VOUT
2EHV
USB1-DP 9EM2 USB-WIFI-DP 8 1 IEH0 RES
PS VAUX
2EHR

RES 2EHS

2EHT
22u

22u

22u
100n IEH1
6 10
EN FB
RES

RES
22K 1%
9EM3
7
UVLO

RES 3EHR
RES 3EHS
2EHU RES

330K
12

GND_HS
IEH2
RES 5EH0

VIA
3 13

PGND
L

GND
1n0

4u7

11
+3V3
2EM3

100n

+3V5-STANDBY
2EM4

2EM5

2EM6

2EM7
100n

100n

100n

100n

2EH9 IEH4 3EHU

7EHJ
BC847BW
2EM0 47n 22K

3EHT RES

120K 1%
18p

22K
7EM1
27

14

21
1EM0

RES 3EHP
CY7C65632-28LTXCT
12M

5
9
VCC

VCC_A_1
VCC_A_2
VCC_A_3

VCC_D

10 2EHJ IEH6
2EM1 XIN IEH5 3EHV
IEHJ
11
18p XOUT 2EHW 100n 47K

cEH0
1
10n
D- USB1-DM

3EHJ

100K
USB-WIFI-DM 3 2 USB1-DP
DD1- D+
4
RES

USB-WIFI-DP DD1+
3EM6 25
+3V3 OVR1 2EHN
10K RES
+3V3-LAN
USB-CAM-DM 6 26
DD2- SDA RES 9EH8-1 100n
USB-CAM-DP 7
DD2+
3EM7 24 RES 9EH8-2
+3V3 OVR2 RES 9EH8-3
10K
12 RES 9EH8-4
DD3- +3V3
13 18
DD3+ TEST|SCL
3EM8 20
+3V3 OVR3
10K
15
DD4-
16 1C31
DD4+
3EM9 19 FEH1
+3V3 OVR4 1
10K 30 USB-WIFI-DM FEH2
VIA1 2
28 31 USB-WIFI-DP FEH3
VREG VIA2 3
RESET-FUSION-OUTn 17 32 FEH4
RESET VIA3 4
3EM3 IEM1 22 33 IRQ-WOLANn FEH5
+3V3 SELFPWR VIA4 5
10K 23
GND_HS

3EM4 GANG 6
8 8 7
RREF
680R IEM2
A1253WRA
29

+3V3
3EM5

100K

RES 3EHN
+3V3-LAN
2EM2

100n

10K
RES 2EHP

100n

1C30
FEH6
+5V 1
USB-CAM-DM FEH7
2
USB-CAM-DP FEH8
3
FEH9
4
5
7 6

A1253WRA

5 2012-11-08

USB internal
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 105

10-2-5 B01E, Miscellaneous

Miscellaneous
B01E B01E

RES
1T71
FTA1 3TA1 FTA2
SCL-SRF 1
RES 10R
FTA3 3TA2 FTA4 2
SDA-SRF FTA6
3
RES 10R 4
RES 2TA1

RES 2TA2
10p

10p
A1253WRA

RES 5TA1
+3V3 FTA5
30R
RES 2TA3

1u0
T 1.0A 63V
RES
1TA1

RES 5TA2
+12V ITA1
30R
TEMPERATURE
5TA3
SENSOR
+3V3-STANDBY
30R

5 2012-11-08

Miscellaneous
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 106

10-2-6 B02A, Hybrid T/C tuner

Hybrid T/C tuner

B02A B02A

VCC-TUNER

22u 16V
5FA1

2FA5
30R
7FAA 1FA0 DBG
LD1117S33
1

2FA7

2FA8

100n
2

10p
5FAA IFAA FFAE 2
+5V 3 4 VCC-TUNER 1F00
IN OUT 3
30R 5 4 SUT-RE214Z
330u 6.3V

COM

15

14
2FA0

2FA1

2FA2

2FA3
100n
10u

1n0

RES BM03B-SRSS-TBT
2FAA FFA9 1
1

5FA7 3FA1 A3.3V

SDA-FE FFA6 10p FFA2 2
FFAD IF1_P
SCL-FE FFA7 30R 5FA6 100R 3FA2 FFA3 3
IF1_N
30R 2FA9 4
100R AGC1

TUNER
10p 5
NC1
SOC-IF-N 3FA3 5FA4 6
NC2
SOC-IF-P 47R 3FA4 330n 5FA5 7
IF2_P
47R 330n 8
IF2_N
9
AGC2
10
I2C_SCL
11
I2C_SDA

2FAC
2FAB

12

13

16
10p

10p
FFAA

3KA0 5KA1
IF-N-DVBT2
IF-P-DVBT2 47R 3KA1 330n 5KA0
47R 330n

2FAG

2FAH
10p

10p
FFA8 FFA4

IF-AGC-DVBT2 3KA3

100R

2FAF

3KA5

22K
10p
RES 3KA4 FFA5 RES 3FA7
IF-AGC-DVBT2 FFAB
100R 100R
SOC-IF-AGC
2FAD

3FAD

2FAE
RES 3KA2

RES 3FA8
6K8

6K8

2K7
22n

IFA6 10p

AGC-SWITCH FFAC
3FA9

2K7

7KA0
PDTA114EU
RES

VCC-TUNER

6 IFA3 3

7FA1-1 2 5 7FA1-2
BC857BS(COL) BC857BS(COL)
1 4

IFA5 IFA4
3FAC
3FAA

3FAB
470R

470R
10K

VCC-TUNER

5 2012-11-08

Hybrid T/C tuner

3104 313 6618

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 107

10-2-7 B02B, Satellite tuner

Satellite tuner
B02B B02B
IRB0 3RB3 IRB1
+3V3-DVBS * 9RB9
* 4R7

2RBU
2RBK

2RBV
2RBL

2RB2

2RB3

2RB4

2RB5

2RB6

2RB7
100n

100n
22u

10n

1n0

1n0

1n0

4n7

10u

68p
* * *

2RBE
7RB0
STV6110AT 6 8 11 14 22 27 28
10p 3
2 NC 4

LNA LT MIX DIG BB VCO SYN

NX3225JB

2RB8 3RB0
1RB0

30 VSS 32
16M

XTAL_OUT XTAL
XTAL_IN 100p 1K0
1 31 18 4 5 DVBS-IP
2RBF IP
19 3 6 3RB1-4 100R
IN DVBS-IN
1 3RB1-3 100R
2RK0 10p XTAL_CMD
RES SATELLITE QP
21 1 8 DVBS-QP
SCL-S-TUNER 10p 12 TUNER 20 2 7 3RB1-1 100R DVBS-QN
SCL QN
SDA-S-TUNER 13 3RB1-2 100R
SDA 2
2RK1 RES 2RBD I C-ADDRESS: C6 RF_OUT
7

10p

10p

10p

10p

10p

10p

10p

10p
DVBS-AGC 10p 3n3 2
AGC
34

2RBW
9RB0 16 35

33n

2RBC

2RBN

2RBR
2RBA

2RBB

2RBP

2RBS
2RB9
AS
RES 36
23 37
+3V3-DVBS
24 NC VIA 38
39
*
1R01 40

6
1
2
* 2RBM
4
RF_IN
41
42
27p
7 3
2RBY

GND
100p

8 4
9 5 RF LNA LT MIX DIG BB VCO SYN HS
5RB0

10 5 3 9 10 15 17 25 26 29 33
27n

*
FRB0
* 2RB1
RES 2RBG

9RB6

9RB7
0p56

+V-LNB
27p

* *
SM15T

2RBH
RES 2RBT

6RB0

9RB8
2RBJ

100p
47p

1n0

+3V3-DVBS
*

Diversity Matrix (Satellite Tuner dependant)

Position Nr Affected Pin Default Value STV6110 STV6111

2RBY 4,5 100P - X

9RB8 4,5 JUMP X -
2RBM 4,5 27P X -
2RB1 4,5 27P - X
2RBW 7 33N - X
9RB6 25 JUMP X -
9RB7 25 JUMP - X
2RB7 27 10U X -
2RBU 27 4N7 - X
2RBV 27 68P - X
9RB9 27 JUMP X -
3RB3 27 4R7 X 2K2 5 2012-11-08

Satellite tuner
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 108

10-2-8 B02C, DVBT2 channel decoder

DVBT2 channel decoder

B02C B02C

+3V3-DVBT2-D

+1V2-DVBT2-C +1V2-DVBT2-P
5KC9

30R
100n 2KC4
2KC7

2KC6

100n 2KC5

IKCA
100n
100n
100n

2KC3

2KC2

2KC1

2KC0
100n

100n

100n
2KCC

2KCB
12p

12p

7KC0 RES 2KCK

10
22
28
44

19
42

32

41M CXD2834ER
7

3 1
IKC0 CVDD DVDD PVDD 3KC1 6p8
35 5 TS-CHDEC-CLK
NC 2 XTALI TSCLK
4 4 47R 8 1 3KC0-1 TS-CHDEC-VALID
5KC0 1KC0 3KC4 IKC1 TSVALID
34 3 7 2 3KC0-2 47R TS-CHDEC-SOP
XTALO TSSYNC
1K0 47R SENSE+1V1-DVBT2 +1V2-DVBT2-C
4u7 2KCD
8 6 3 3KC0-3 TS-CHDEC-DATA
2KCE IKC2 3KCA 0
IF-P-DVBT2 9KC0 47p 38 9 47R
100n TAINP 1
IF-N-DVBT2 9KC1 2KCF 47R 3KCB 37 12 5KCA IKC8
TAINM 2
100n 2KCG IKC3 13 +1V2-FE +1V2-DVBT2-C
47p 47R 3
5KC1 TSDATA 14
4 30R

AGC-SWITCH 4u7
3KC6
41
RFAIN I 2C 5
15
16
RES 5KC5 IKC7 RES 5KC7
6 VCC-TUNER +3V3-DVBT2-D +1V1-DVBT2
1K0 ADDRESS 7
17
30R 30R
2KCH
RES

1
10n

DKC0 GPIO0 = 3KC2 5KC6

2KCR
47 20

1u0
GPIO1 SCL SCL-FE +3V3
2 21 47R 3KC3 SDA-FE
IKC4 GPIO2 0XD8 SDA
47R
30R

2KCP
50

1u0
3KC7 48 51
IF-AGC-DVBT2 TIFAGC
2KCJ 52
10K
100n 53
3KC8 IKC5
+3V3-DVBT2-D 46 54 IKC9
IKC6 TTUSCL 3KCE
3K3 3KC9 45 55 +1V2-DVBT2-C +1V2-DVBT2-P
TTUSDA
3K3 56 22R
57

2KCS
24 58

10u
TESTMODE
59
60
25 61
SLVADR0
VIA 62
63
26 64
DKC1 OSCEN_X
65
66
RESET-FUSION-OUTn 29 67
RST_X
68
69
30 70
SLVADR3
71
RES 5KC8 72
+3V3-DVBT2-D 33 73
NC1
IKCB 40 74
30R NC2
VSS
7KC0 +1V1-DVBT2
GND_HS
2KCL

100n

6
11
18
23
27
31
36
39
43

49

FKC1 CXD2834 +1V2

RES

GAIA3 +1V1

5 2012-11-08

DVBT2 channel decoder

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 109

10-2-9 B02D, DVBS/S2 channel decoder

DVBS/S2 channel decoder

B02D B02D

+3V3-DEMOD +3V3-ANA
5RDD IRD2

100n
100n
+1V2-FE

2RD6

100n
30R

2RD4

2RD5
RES 2RDK

2RDL

2RD0

2RD1

2RD2

2RD3
RES 2RDJ

100n

100n

100n

100n
22u

22u

22u
1RD0
NX3225JB

2 NC 4
1 3

20
28
48

VDD_VIO 22

36
7RD0

9
SI2169-A10-GM

VDD_VANA
16M VDD_VCORE
RES 2RDD
RES 2RDE

33
10p

10p

XTA_I|CLK_IN
7RDA
LD1117S33 32
XTA_O
5RDA 2
IRDA FRDA
+5V 3 4 +3V3-DVBS 44
IN OUT CLK_IN_OUT
2RDB 13 3RD0-2 2 7 TS-DVBS-SOP
16V

30R 100n TS_SYNC

COM XTAL 3RD6 31 12 3RD0-1 1 8 47R TS-DVBS-VALID
RESETB TS_VAL
2RDP

2RDR
100n

10K 26
+3V3-DEMOD TS_ERR|GPIO_1 47R
22u

1 3 14 3RD1 TS-DVBS-CLK
GPIO_0|JTAG_TMS TS_CLK
RESET-FUSION-OUTn
47R
34 15 3RD0-3 3 6 TS-DVBS-DATA
ADDR TS_DATA0|TS_SER
AGC-SWITCH 9RD3 16
TS_DATA1 47R
43 17
RSSI_ADC TS_DATA2

RES 2RDC
DVBS-QP 2RD7 37 18

6p8
S_ADC_IP TS_DATA3
DVBS-QN 100n 2RD8 38 19
100n S_ADC_IN TS_DATA4
DVBS-IN 2RDA 39 23
S_ADC_QP TS_DATA5
DVBS-IP 100n 2RD9 40 24
100n S_ADC_QN TS_DATA6
25
3RD2 TS_DATA7
5RDB IRDB IF-AGC-DVBT2 9RD2 1
MP_A IRD0 3RD8
+3V3-DVBS +3V3-DEMOD 2RDH 10K DRD0 2 11 SDA-FE
MP_B SDA_HOST
100n 29 10 IRD1 47R 3RD7 SCL-FE
30R 3RD3 DRD1 MP_C SCL_HOST
DVBS-AGC 30 47R
MP_D
2RDS

50
22u

10K
IF-P-DVBT2 9RD0 2RDF 41 51
TC_ADC_P
IF-N-DVBT2 9RD1 100n 2RDG 42 52
TC_ADC_N
100n 53
3RD4 IRD5
SDA-S-TUNER 45 54
SDA_MAST VIA
SCL-S-TUNER 3RD5 47R IRD6 46 55
SCL_MAST
47R 56
+V-LNB 4 57
2RDT 3RD9 IRD3 DISEQC_CMD
5 58
100p DISEQC_IN
5RDC IRDC F22-DISECQ-TX 1K0 6
DISEQC_OUT
+3V3-DVBS +3V3-ANA
3RDA RES

3RDB RES

8
30R GND1|JTAG_TCLK
21
GND2|JTAG_TDI
2RDM

2RDN

27
4K7

4K7
22u

10n

GND3|JTAG_TDO
47
GND4|JTAG_TRSTB
GND5 GND_HS
35

49

+3V3-DEMOD

5 2012-11-08

DVBS/S2 channel decoder

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 110

10-2-10 B03A, Fusion

Fusion
B03A B03A

7J00-6 7J00-7
FUSION120 FUSION120
FLASH_CI_GPIO TS_TSB_MCU
CA-D00 AK23 AJ22 CA-A04 AH18 MDI0
FRD0_PODD0 PODA4 0
CA-D01 AF26 AH22 CA-A05 AJ18 MDI1
FRD1_PODD1 PODA5 1
CA-D02 AE24 AF22 CA-A07 AK18 MDI2
FRD2_PODD2 POD_A7 2
CA-D03 AK25 AJ23 CA-A08 AE19 MDI3
FRD3_PODD3 POD_A8 3
CA-D04 AH25 AH23 CA-A09 CA-MDO0 AG20 TS2OD AF19 MDI4
FRD4_PODD4 POD_A9 0 4
CA-D05 AH27 CA-MDO1 AH20 AG19 MDI5
FRD5_PODD5 1 5
CA-D06 AK27 AE27 CA-RDY CA-MDO2 AJ20 AH19 MDI6
FRD6_PODD6 PODIREQ 2 6
CA-D07 AJ25 AG30 CA-RST CA-MDO3 AK20 AJ19 MDI7
FRD7_PODD7 PODRST 3 7
CA-A00 AF25 AF30 CA-VS1n CA-MDO4 AE21 TS1D
FRD8_PODA0 PODVS1 4
CA-A01 AG26 AE28 CA-WAITn CA-MDO5 AF21 AK19 MICLK
FRD9_PODA1 PODWAIT 5 TS2OCLK
CA-A02 AK26 AE30 FJ16 CA-MDO6 AG21 AE20 MISTRT
FRD10_PODA2 POD_DIR 6 TS2OSYNC
CA-A03 AG25 CA-MDO7 AH21 AF20 MIVAL
FRD11_PODA3 7 TS2ODEN
CA-A10 AE25 AD28 CA-CE1n
FRD12_PODA10 PODCE1 2FZ5
CA-A11 AH26 AD27 CA-CE2n CA-MOCLK AJ21
FRD13_PODA11 PODCE2 TS1CLK 3FZ0
CA-A12 AH28 AF29 CA-CD1n CA-MOSTRT AK21 F27 4n7 SOC-IF-AGC
FRD14_PODA12 PODCD1 TS1SYNC IF
CA-A13 AF24 AD30 CA-CD2n CA-MOVAL AE22 TAGCO G26 100R
FRD15_PODA13 POD_CD2 TS1DEN RF FJ10
AE29 T28
POD_VCC_EN 1
FRA0 AG29 AD29 TS-CHDEC-DATA U28 DGPIO T29
FRA0_AD0 POD_VPP_EN TSSDI 2
CA-WEn AD26 TS-CHDEC-CLK U29
FRA1_PODWE TSSCLK
CA-IORDn AH29 R30 TS-CHDEC-SOP U30
FRA2_PODIORD HPD TSSSYNC
CA-IOWRn AJ29 TS-CHDEC-VALID T26 M27 STB-GP0
FRA3_PODIOWR TSSDEN 0
CA-REGn AF28 E1 GPIO0 IF-IN-P M26 STB-GP1
FRA4_PODREG GPIO0 10p 1
FRA5 AH30 F3 GPIO1 RES 2FZ6 M25 STB-GP2
FRA5_AD1 GPIO1 47p 2FZ1 2
FRA6 AG28 F4 GPIO2 IF-IN-N F30 N30 STB-GP3
FRA6_AD2 GPIO2 10p IN_P 3
FRA7 AJ30 F2 GPIO3 F29 N29 STB-GP4
FRA7_AD3 GPIO3 2FZ2 IN_N 4
FRA8 AJ28 F1 N28 STB-GP5
FRA8_AD4 GPIO4 STB_GP 5
CA-OEn AJ27 G6 GPIO5 100n E28 N27 STB-GP6
FRA9_PODOE GPIO5 P 6
FRA10 AF27 G5 GPIO6 100n 2FZ3 E27 PD N26 STB-GP7
FRA10_AD5 GPIO6 N 7
FRA11 AG27 G4 GPIO7 2FZ4 N25 STB-GP8
FRA11_AD6 GPIO7 8
FRA12 AG24 G3 GPIO8 P25 STB-GP9
FRA12_AD7 GPIO8 2J10 9
NAND-CLE AE23 G2 H30 P26 STB-GP10
FRA13_CLE GPIO9 XTLI24M 10
3

AK22 G1
24M

NAND-ALE FRA14_ALE GPIO10 18p

1J00

CA-A14 AJ26 H6 GPIO11 H29 R27 STB-TXD

FRA15_PODA14 GPIO11 XTLO24M TXD
2 R28 STB-RXD
2J11 RXD
J6 3FZ1 GPIO14 4 STB P27 STB-SDA
1

GPIO14 18p SDA

F-OEn AK29 J5 33R GPIO15 RESET-STANDBYn J26 P28 STB-SCL
FOE GPIO15 RSTN SCL
F-WEn AK24 J4 GPIO16
FWE GPIO16
J3 GPIO17 J25 LED
GPIO17 LED
F-CEn AJ24 J2 GPIO18 TEST-CON P30 M29 IR
BOOTCS GPIO18 TESTCON IR
TS-DVBS-DATA AE26 J1 GPIO19 TEST-MOD P29 J30 KYBRD
FCE2N GPIO19 TESTMOD KYBRD
TS-DVBS-VALID AF23 H1 GPIO20 M30 LGSEN
FINT1 GPIO20 LGSEN
TS-DVBS-SOP AK28 H2 GPIO21 ENABLE-STANDBY H25 M28 HDMI-CEC
FINT2 GPIO21 STB_EN CEC
TS-DVBS-CLK AH24 H3 GPIO22 R29 PWRON
FCLK GPIO22 PWRON
CA-A06 AG22 H4 GPIO23
FAVD_PODA6 GPIO23
F-RDY AG23 H5 GPIO24 SPI-EN K28 K25 AVLINK1
FREADY GPIO24 SPI_EN 1
SF-SDI L28 AVLINK K26 AMBI-TEMP-FUS
SFSI 2
SF-SDO L26
SFSO
SF-WP K30 J27
SFWPN PCVS
SF-HOLDn L27 J28
SFHOLDN PCHS
SF-CS L29
SFCES
SF-CLK L30 J29 STB-RSTO
SFSCK STB_RSTO
K27 HP-DETECT
HP_DETECT
H26 AUDIO-MUTEn
MUTE

5 2012-11-08

Fusion
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 111

10-2-11 B03B, Fusion Umac controller

Fusion Umac controller

B03B B03B
7J00-8
FUSION120
DDR3
M0-MD0 DB71 AH8
0
M0-MD1 AH5
1
M0-MD2 AH7
2
M0-MD3 AJ5
3
M0-MD4 AK8
4
M0-MD5 AH6
5
M0-MD6 AJ8
6
M0-MD7 AK5
7
M0-MD8 AK11
8
M0-MD9 DB72 AF9
9
M0-MD10 AJ11 W2 M1-MD0
10 0
M0-MD11 AG9 AC2 M1-MD1
11 1
M0-MD12 AF10 Y1 M1-MD2
12 2
M0-MD13 AG8 AC1 M1-MD3
13 3
M0-MD14 AH10 Y3 M1-MD4
14 4
M0-MD15 AH9 AB1 M1-MD5
15 5
M0-MD16 AG1 MM0DQ W1 M1-MD6
16 6
M0-MD17 AF3 AB3 DB79 M1-MD7
17 7
M0-MD18 AE3 MM1DQ T5 DB77 M1-MD8
18 8
M0-MD19 AH1 Y4 M1-MD9
19 9
M0-MD20 AH2 T4 M1-MD10
20 10
M0-MD21 AD3 W5 M1-MD11
21 11
M0-MD22 AD1 U5 M1-MD12
22 12
M0-MD23 AD2 Y5 DB76 M1-MD13
23 13
M0-MD24 AK4 U4 M1-MD14
24 14
M0-MD25 AG3 W4 M1-MD15
25 15
M0-MD26 AJ3
26
M0-MD27 AK2 AA1 DB78 M1-DQM0
27 0
M0-MD28 AK3 MM1DM W3 DB75 M1-DQM1
28 1
M0-MD29 AJ2
29
M0-MD30 AG5 AA2 M1-DQS0
30 P
M0-MD31 DB74 AJ1 MM1DQS0 AA3 M1-DQS#0
31 N
V3 M1-DQS1
P
M0-DQM0 AJ6 MM1DQS1 V4 DB47 M1-DQS#1
0 N
M0-DQM1 AK9
1
M0-DQM2 AE1 MM0DM T2 M1-MA0
2 0
M0-DQM3 AH3 L2 M1-MA1
3 1
N1 M1-MA2
2
M0-DQS0 AK7 N3 M1-MA3
P 3
M0-DQS#0 AK6 MM0DQS0 L3 M1-MA4
N 4
M0-DQS1 DB14 AJ10 N5 M1-MA5
P 5
M0-DQS#1 DB16 AK10 MM0DQS1 L5 M1-MA6
N 6
M0-DQS2 AF2 N2 M1-MA7
P 7
M0-DQS#2 AF1 MM0DQS2 MM1A M3 M1-MA8
N 8
M0-DQS3 AH4 L4 M1-MA9
P 9
M0-DQS#3 AG4 MM0DQS3 R5 M1-MA10
N 10
M1 M1-MA11
11
M0-MA0 AJ12 T1 M1-MA12
0 12
M0-MA1 AJ17 M5 M1-MA13
1 13
M0-MA2 AK15 L1 M1-MA14
2 14
M0-MA3 AH15 R2 M1-MA15
3 15
M0-MA4 AH17
4
M0-MA5 AF15 U1 M1-BA0
5 0
M0-MA6 AF17 P5 M1-BA1
6 MM1BA 1
M0-MA7 AJ15 R1 M1-BA2
7 2
M0-MA8 AH16 MM0A T3 M1-CAS#
8 MM1CASN
M0-MA9 AG17 V2 M1-RAS#
9 MM1RASN
M0-MA10 AF13 U3 M1-WE#
10 MM1WEN
M0-MA11 AK16 R3 M1-CKE
11 MM1CKE
M0-MA12 AK12 V1 M1-ODT
12 MM1ODT
M0-MA13 AF16 N4 M1-RESET#
13 MM1RESETN
M0-MA14 AK17 P4 M1-CS#
14 MM1CSN
M0-MA15 AJ13
15
+1V5-M0 P1 M1-MCLK0
P
M0-BA0 AG12 MM1CK P2 M1-MCLK0# +1V5-M1
0 N
M0-BA1 AF14
1 MM0BA
M0-BA2 AK13 U7
2 0
M0-CAS# AH12 MM1VREF U6 M1-MVREF1
MM0CASN 1 3J01 240R 1%
M0-RAS# AF12 AA5
MM0RASN MZQ1
M0-WE# AF11 K6 MM1ANA
MM0WEN MM1ANA_TEST
M0-CKE AH13 AB4
MM0CKE DDR_RETN
M0-ODT AG11 +1V5-M1
MM0ODT
100n
2J06

3J05

AG15
1K0

M0-RESET# MM0RESETN

100n
3J03

2J04
AG14

1K0
M0-CS# MM0CSN
3J02

AK14
1K0

M0-MCLK0 P
M0-MCLK0# AJ14 MM0CK
FJ05 N
M0-MVREF0 FJ04
M0-MVREF0 AE11 DDR-RTN M1-MVREF1
0
AE12 MM0VREF
3J00 240R 1% 1
100p
2J00

AE7
MZQ0
100n

100n
2J07

3J06

2J05

AD18
1K0

MM0ANA MM0ANA_TEST
100n

100n
2J02

3J04

2J03
1K0

FJ01 DB73 FJ03

MM0ANA MM1ANA
FJ02

DB80 DB85

DB81 DB86

DB82 DB87

DB83 DB88

DB89

5 2012-11-08

Fusion Umac controller

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 112

10-2-12 B03C, Umac 1 DDR3

Umac 1 DDR3
B03C B03C
+1V5-M1

+1V5-M1
+1V5-M1

M10
A10

K10

B10

E10
7J01

M2
G3
G9
D8

C2
A3

K2

E3
H5TQ2G83BFR
M1-MA0 VDD VDDQ
3J18 3J19 M1-MA0 K4
M1-MA1
0
100R 100R M1-MA1 L8
3J1B 1
3J1A M1-MA2 L4
2
100R 100R K3

M10
A10

K10

B10

E10
M1-MA2 M1-MA3 7J02

M2
G3
G9
3

D8

C2
A3

K2

E3
3J1C 3J1D +1V5-M1 M1-MA4 L9 H5TQ2G83BFR
4
M1-MA3 100R 100R M1-MA5 L3 A8 VDD VDDQ
5 TDQS
3J1E 3J1F M1-MA6 M9 B8 DB56 M1-DQM0 M1-MA0 K4
6 TDQS 0
M1-MA4 100R 100R M1-MA7 M3 M1-MA1 L8
7 DM 1
3J1G 3J1H M1-MA8 DB31 N9 A M1-MA2 DB50 L4
8 2
M1-MA5 100R 100R M1-MA9 M4 C4 DB42 M1-DQS0 M1-MA3 K3
9 DQS 3
3J1J 3J1K M1-MA10 H8 D4 DB43 M1-DQS#0 M1-MA4 L9
10 DQS 4
M1-MA6 100R 100R M1-MA11 DB32 M8 M1-MA5 L3 A8
11 5 TDQS
3J1L 3J1M M1-MA12 K8 M1-MA6 M9 B8 DB58 M1-DQM1
12 6 TDQS
100n
2J16

3J11

100R 100R DB33 N4 B4 M3

1K0

M1-MA7 M1-MA13 13 0 M1-MD0 M1-MA7 DB49 7 DM

3J1N 3J1P M1-MA14 DB34 N8 C8 M1-MD5 M1-MA8 N9 A
14 1 8
M1-MA8 100R 100R C3 DB40 M1-MD6 M1-MA9 M4 C4 DB90 M1-DQS1
3J1R BC 2 9 DQS
3J1Y C9 M1-MD1 M1-MA10 DB52 H8 D4 DB91 M1-DQS#1
AP 3 10 DQS
M1-MA9 100R 100R DQ E4 M1-MD2 M1-MA11 M8
FJ08 4 11
3J1S 3J1T DDR-MVREF11 DDR-MVREF11 E2 E9 M1-MD7 M1-MA12 K8
VREFDQ 5 12
M1-MA10 100R 100R J9 D3 M1-MD4 M1-MA13 DB51 N4 B4 M1-MD14
3J1V VREFCA 6 13 0
3J1U E8 DB41 M1-MD3 M1-MA14 N8 C8 M1-MD15
7 14 1
100n

100n
2J14

2J15

M1-MA11 100R 100R H9 C3 M1-MD10

ZQ BC 2
100n

3J1Z
2J17

3J12

3J1W C9
1K0

AP 3 M1-MD11
240R
3J10

M1-MA12 100R 100R J3 A1 DQ E4 M1-MD12

3J21 BA0 4
3J20 K9 A4 DDR-MVREF12 E2 E9 M1-MD13
BA1 VREFDQ 5
M1-MA13 100R 100R DB62 J4 A11 J9 D3 M1-MD8
3J23 BA2 VREFCA 6
3J22 F2 E8 M1-MD9
7

100n

100n
2J18

2J19
M1-MA14 100R 100R M1-BA0 F4 F10 H9
3J25 RAS ZQ
3J24 M1-BA1 G2 NC H2
ODT

240R
3J13
M1-MA15 100R 100R M1-BA2 DB35 G4 H10 DB06 J3 A1
3J27 CAS BA0
3J26 M1-MCLK0 M1-RAS# DB36 F8 J8 DB57 M1-MA15 K9 A4
CK BA1
M1-BA0 100R 100R M1-ODT DB38 G8 N1 J4 A11
3J29 CK BA2
3J28 M1-CAS# G10 N11 DB64 F2
CKE
M1-BA1 100R 100R +1V5-M1 M1-MCLK0 DB01 H3 M1-BA0 DB53 F4 F10
3J2B CS RAS
3J2A M1-MCLK0# DB39 H4 M1-BA1 G2 NC H2
WE ODT
3J16
RES

100R 100R N3 G4 H10

75R

M1-BA2 RESET M1-BA2 DB54 CAS

3J2C 3J2D M1-RAS# F8 J8 M1-MA15
VSS VSSQ CK
2J12

100R 100R G8 N1
10n

M1-RAS# M1-CKE M1-ODT CK

3J2F
A2
A9
B2
D9
F3
F9
J2
J10
L2
L10
N2
N10

B3
B9
C10
D2
D10

3J2E M1-CS# M1-CAS# G10 N11

CKE
M1-CAS# 100R 100R M1-WE# M1-MCLK0 H3
3J2H CS
3J2G M1-RESET# M1-MCLK0# DB55 H4
WE
M1-WE# 100R 100R N3
RESET
2J89

3J2J 3J2K
10n

VSS VSSQ
3J17

100R 100R
75R

M1-CS# M1-CKE
3J2M

A2
A9
B2
D9
F3
F9
J2
J10
L2
L10
N2
N10

B3
B9
C10
D2
D10
3J2L M1-CS#
M1-ODT 100R 100R M1-WE#
3J2N 3J2P M1-RESET#
M1-CKE 100R 100R
3J2Q 3J2R
M1-RESET# 100R 100R M1-MCLK0#
3J2S 3J2T
100R 100R +1V5-M1
2J1A
100n
3J14
1K0

FJ09
DDR-MVREF12
2J1B
100n
3J15
1K0

+1V5-M1 +1V5-M1
2J1G
2J1R

2J1C
2J1V

2J1E
100n
2J1T

100n

100n
2J1Z

100n

100n
2J22

2J81

2J82

2J83

2J84

2J21

2J1J
10u

10n

10n

10n

10n

10n

10n

10n

10n

DB93 DB98 DBA3

DB94 DB99 DBA4

DB95 DB59 DBA5

DB96 DBA1 DBA6

DB97 DBA2 DBA7

+1V5-M1 +1V5-M1
47u 16V

2J1W
2J1U

2J1D

2J1H
2J1S

2J1K
100n

100n

100n

100n

2J1F
2J27

2J24

2J25

2J85

2J86

2J87

2J88

2J20
10u

10u

10n

10n

10n

10n

10n

10n

10n

10n

5 2012-11-08

Umac 1 DDR3
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 113

10-2-13 B03D, Umac 0 DDR3

Umac 0 DDR3
B03D B03D
+1V5-M0

+1V5-M0
7J03 +1V5-M0

G7
D9

N1
N9
R1
R9

C1
C9
D2

H2
H9
B2

K2
K8

A1
A8

E9
F1
H5TQ2G63BFR-PBC
VDD VDDQ

M0-MA0 M0-MA0 N3
3J35 0
3J34 M0-MA1 P7
1
M0-MA1 100R 100R M0-MA2 P3 7J04

G7
2

D9

N1
N9
R1
R9

C1
C9
D2

H2
H9
B2

K2
K8

A1
A8

E9
F1
3J36 3J37 M0-MA3 N2 H5TQ2G63BFR-PBC
3
M0-MA2 100R 100R M0-MA4 P8 D7 M0-MD0 VDD VDDQ
3J39 4 0
3J38 +1V5-M0 M0-MA5 P2 C3 M0-MD5
5 1
M0-MA3 100R 100R M0-MA6 R8 A C8 DB09 M0-MD4 M0-MA0 N3
3J3B 6 2 0
3J3A M0-MA7 R2 C2 M0-MD7 M0-MA1 P7
7 3 1
M0-MA4 100R 100R M0-MA8 DB61 T8 DQU A7 M0-MD2 M0-MA2 P3
3J3D 8 4 2
3J3C M0-MA9 R3 A2 M0-MD1 M0-MA3 N2
9 5 3
M0-MA5 100R 100R M0-MA10 L7 B8 M0-MD6 M0-MA4 P8 D7 M0-MD16
3J3F 10 6 4 0
3J3E M0-MA11 DB00 R7 A3 DB10 M0-MD3 M0-MA5 P2 C3 DB25 M0-MD18
11 7 5 1
M0-MA6 100R 100R M0-MA12 N7 M0-MA6 R8 A C8 M0-MD20
12 6 2
3J3G 3J3H M0-MA13 DB02 T3 C7 DB11 M0-DQS0 M0-MA7 DB18 R2 C2 M0-MD23
13 DQSU 7 3
2J2A

3J2V
100n

100R 100R DB03 T7 B7 T8 DQU A7

1K0

M0-MA7 M0-MA14 14 DQSU DB12 M0-DQS#0 M0-MA8 DB19 8 4 M0-MD17

3J3J 3J3K M0-MA15 M7 M0-MA9 R3 A2 M0-MD21
15 9 5
M0-MA8 100R 100R F3 DB13 M0-DQS1 M0-MA10 L7 B8 DB26 M0-MD19
BC DQSL 10 6
3J3L 3J3M G3 DB15 M0-DQS#1 M0-MA11 R7 A3 M0-MD22
AP DQSL 11 7
M0-MA9 100R 100R M0-MA12 N7
FJ0A 12
3J3N 3J3P DDR-MVREF01 DDR-MVREF01 H1 E3 M0-MD15 M0-MA13 DB20 T3 C7 M0-DQS2
VREFDQ 0 13 DQSU
M0-MA10 100R 100R M8 F7 M0-MD12 M0-MA14 DB21 T7 B7 M0-DQS#2
3J3R VREFCA 1 14 DQSU
3J3Y F2 M0-MD9 M0-MA15 M7
2 15
100n

100n
2J28

2J29

M0-MA11 100R 100R L8 F8 DB69 M0-MD10 F3 DB27 M0-DQS3

ZQ 3 BC DQSL
3J2W
2J2B

100n

3J3S 3J3T DQL H3 G3

1K0

M0-MD11 DB29 M0-DQS#3

1%

4 AP DQSL
240R
3J2U

M0-MA12 100R 100R DB68 M2 H8 DB17 M0-MD14

3J3V BA0 5
3J3U N8 G2 M0-MD13 DDR-MVREF02 H1 E3 M0-MD29
BA1 6 VREFDQ 0
M0-MA13 100R 100R M3 H7 M0-MD8 M8 F7 M0-MD28
3J3Z BA2 7 VREFCA 1
3J3W F2 M0-MD25
2

2J2C

2J2D
100n

100n
M0-MA14 100R 100R M0-BA0 J3 L8 F8 DB30 M0-MD26
3J41 RAS ZQ 3
3J40 M0-BA1 DB60 K1 DQL H3 M0-MD27

1%
ODT 4

240R
3J2Z
M0-MA15 100R 100R M0-BA2 DB04 K3 M2 H8 M0-MD30
3J43 CAS BA0 5
3J42 M0-MCLK0 M0-RAS# DB05 J7 DB67 N8 G2 M0-MD31
CK BA1 6
M0-BA0 100R 100R M0-ODT DB07 K7 J1 M3 H7 DB70 M0-MD24
3J45 CK BA2 7
3J44 M0-CAS# K9 J9
CKE
M0-BA1 100R 100R +1V5-M0 M0-MCLK0 DB65 L2 NC L1 M0-BA0 DB22 J3
3J47 CS RAS
3J46 M0-MCLK0# DB08 L3 L9 M0-BA1 K1
WE ODT
3J32

100R 100R T2 K3
75R

M0-BA2 RESET M0-BA2 DB23 CAS

3J48 3J49 M0-RAS# J7
CK
2J01

100R 100R DB66 E7 K7 J1

10n

M0-RAS# RES M0-CKE DML M0-ODT CK

3J4A 3J4B M0-CS# D3 M0-CAS# K9 J9
DMU VSS VSSQ CKE
M0-CAS# 100R 100R M0-WE# M0-MCLK0 L2 NC L1
3J4D CS
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

3J4C M0-RESET# M0-MCLK0# DB24 L3 L9

WE
M0-WE# 100R 100R T2
RESET
2J2G

3J4E 3J4F
10n

M0-DQM1
3J33

100R 100R E7
75R

M0-CS# M0-DQM0 M0-CKE DML

3J4G 3J4H M0-CS# D3
DMU VSS VSSQ
M0-ODT 100R 100R M0-WE#
3J4K

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9
3J4J M0-RESET#
M0-CKE 100R 100R
3J4L 3J4M M0-DQM3
M0-RESET# 100R 100R M0-MCLK0# M0-DQM2
3J4N 3J4P
100R 100R +1V5-M0

2J2E
100n
3J30
1K0

FJ0B
DDR-MVREF02
100n

2J2F
3J31
1K0

+1V5-M0 +1V5-M0
47u 16V

2J2M
2J3G

2J2H

2J3C

2J2R
2J3K

2J2K

2J2P

2J3A

2J3E

2J2V
2J3F

100n

100n

100n

100n

100n

100n

100n

2J2T

2J2Z
2J32

2J34

2J36

2J38
10u

10u

10n

10n

10n

10n

10n

10n

10n

10n

DBB3 DBB8 DBC3

DBB4 DBB9 DBC4

DBB5 DBC0 DBC5

+1V5-M0 +1V5-M0
DBB6 DBC1 DBC6

DBB7 DBC2 DBC7

2J2W
2J3H

2J2N

2J3D

2J2U
2J2Y

2J3B

2J2S
100n

100n

100n

100n

100n

100n

100n
2J31

2J33

2J35

2J37

2J2L

2J39

2J30
2J3J

2J2J
10u

10u

10n

10n

10n

10n

10n

10n

10n

10n

5 2012-11-08

Umac 0 DDR3
3104 313 6618

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 114

10-2-14 B03E, Fusion

Fusion
B03E B03E

7J00-5
FUSION120
7J00-4 PANEL_USB
FUSION120 B3 TX1-A-
AV_IN_OUT LAN_IO TA1_P A3 TX1-A+
TA1_N
AR-1 A22 B21 HPHOL C3 TX1-B-
AR_1 HPHOL TB1_P
AL-1 B22 A21 HPHOR C4 TX1-B+
AL_1 HPHOR TB1_N
E22 A4 TX1-C-
AR_2 TC1_P
D22 C21 B4 TX1-C+
AL_2 SUBO TC1_N
AR-3 A23 B5 TX1-CLK-
AR_3 TCLK1_P
AL-3 B23 A25 A5 TX1-CLK+
AL_3 SPK_AOR1 TCLK1_N
AR-4 E23 B25 C5 TX1-D-
AR_4 SPK_AOL1 TD1_P
AL-4 D23 USB1-DP AB30 C6 TX1-D+
AL_4 D1_P TD1_N
A24 D25 AUD-L USB1-DM AB29 A6 TX1-E-
AR_5 AOR2 D1_N TE1_P
B24 C25 AUD-R AB26 B6 TX1-E+
AL_5 AOL2 USBPPON1 TE1_N
E24 USB1-RREF AB27
AR_6 TXRTUNE1
D24 B9 TX2-A-
AL_6 TA2_P
USB2-DP AC30 A9 TX2-A+
D2_P TA2_N
SPDIFIN D26 E26 SPDIFO USB2-DM AC29 C9 TX2-B-
SPDIFIN SPDIFO D2_N TB2_P
AB25 C10 TX2-B+
3J53 USBPPON2 TB2_N
SCKIN C26 Y26 3J07 SCKI2SOUT USB2-RREF AC27 A10 TX2-C- 7J00-9
SCKIN SCKI2SOUT TXRTUNE2 TC2_P
WSI2SIN 3J54 10R B26 Y27 3J08 10R WSI2SOUT B10 TX2-C+ FUSION120
WSI2SIN WSI2SOUT TC2_N
SDI2SIN 10R 3J55 A26 AA30 3J09 10R SDI2SOUT1 B11 TX2-CLK- JTAG_I2C
SDI2SIN 1 TCLK2_P
10R AA29 3J50 10R SDI2SOUT2 EN-RXD0 W29 A11 TX2-CLK+ U26
SDI2SOUT 2
AB28 3J51 10R SDI2SOUT3 EN-TXD0 V29
GBE_RXD0 TCLK2_N
C11 TX2-D- RXD-SERVICE Y29
UART SCLS U27
3 GBE_TXD0 TD2_P RXD SDAS
IJ11 Y25 3J52 10R I2SCLK EN-RXD1 W28 C12 TX2-D+ TXD-SERVICE Y28
I2SCLK GBE_RXD1 TD2_N TXD
AC28 10R EN-TXD1 V28 A12 TX2-E-
GPANA1 GBE_TXD1 TE2_P
FJ0F W27 B12 TX2-E+ AA28 SCL-M1
GBE_RXD2 TE2_N SCLM1
CVBS C15 FJ0G V27 EJT-TCK K2 AA27 SDA-M1
1 GBE_TXD2 TCK SDAM1
A15 FJ0H W26 E3 TX3-A- EJT-TMS K3
2 GBE_RXD3 TA3_P TMS
CVBS3 B16 CVBS FJ0J V26 D3 TX3-A+ EJT-TDO K1 E2 SCL-M2
3 GBE_TXD3 TA3_N TDO SCLM2
A16 E4 TX3-B- EJT-TDI K5 D1 SDA-M2
4 TB3_P TDI SDAM2
EN-RXC V25 D4 TX3-B+ EJT-TRSTN K4
GBE_RXC TB3_N TRSTN
C16 EN-TXC U25 F5 TX3-C- AA26 SCL-M3
C GBE_TXC TC3_P SCLM3
F6 TX3-C+ AA25 SDA-M3
TC3_N SDAM3
Y-G1 A20 EN-RXEN W30 D5 TX3-CLK-
Y_G1 GBE_RXEN TCLK3_P
PB-B1 A19 EN-TXEN V30 E5 TX3-CLK+
PB_B1 GBE_TXEN TCLK3_N
PR-R1 A18 D6 TX3-D-
PR_R1 TD3_P
EN-MDC W25 E6 TX3-D+
GBE_MDC TD3_N
Y-G2 B20 EN-MDIO Y30 D7 TX3-E-
Y_G2 GBE_MDIO TE3_P
PB-B2 B19 A14 CVBS-OUT1 E7 TX3-E+
PB_B2 1 TE3_N
PR-R2 B18 CVBS_OUT A13
PR_R2 2
HDMIF-RX0+ A29 E10 TX4-A-
IJ10 RX0_P TA4_P
Y-G3 C20 HDMIF-RX0- B29 D10 TX4-A+
Y_G3 RX0_N TA4_N
PB-B3 C19 HDMIF-RX1+ A28 F10 TX4-B-
PB_B3 RX1_P TB4_P
PR-R3 C18 HDMIF-RX1- B28 F11 TX4-B+
PR_R3 RX1_N TB4_N
HDMIF-RX2+ A27 D11 TX4-C-
RX2_P TC4_P
D20 HDMIF-RX2- B27 E11 TX4-C+
IJ12 Y_G4 RX2_N TC4_N
D19 HDMIF-RXC+ B30 E12 TX4-CLK-
PB_B4 RXC_P TCLK4_P
IJ13 D18 HDMIF-RXC- C30 D12 TX4-CLK+
PR_R4 RXC_N TCLK4_N
F12 TX4-D-
TD4_P
SC1-STATUS C17 HEAC T27 F13 TX4-D+
FS1 HEAC TD4_N
FB1 B17 D13 TX4-E-
FB1 TE4_P
PWR5V T30 E13 TX4-E+
PWR5V TE4_N
D17
FS2
A17 RREF C29
FB2 RREF
D2 BL-SPI-CLK-FUS
H_BK_LITE
B2 3D-LR-FUS
PWM0
C1 BL-SPI-CS_BL-I-CTRL-FUS
PWM1
B1 BL-DIM-FUS
BOOST
A2
BKLGON
C2 BL-SPI-SDO-FUS
TCON_ON
E9 9GA2 RES
NC_IDP_HPD
F9 IJ0T
NC_LOCKN
G9 IJ0U
NC_HTPDN

5 2012-11-08

Fusion
3104 313 6618

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 115

10-2-15 B03F, Fusion power supply

Fusion power supply

B03F B03F
+3V3-STANDBY +3V3

2J5Y

2J5P
10n

10u

2J5W
2J5R

2J5U
2J5S

2J5V
100n

100n
2J5T

100n

100n

100n

100n
2J5Z

100n

100n

100n

100n
2J60

2J61

2J62

2J64

2J63
10u

10u
R26
R25
R24

F26
AD25
T25
G25
F25
AD24
AA24
Y24
T24
H24
G24
AD23
AD22
AD19
AG18
AF18
AE18

J7
H7
G7
F7
7J00-3
FUSION120

VDDF_STB

VDDF2

VDDF1
IJ14
M11 +1V1-FD
G12

2J7G
2J7H
2J7E

2J7K

2J7L
2J7J
M12

10u

10u

10u

10u

10u

10u
7J00-1
FUSION120 T12
SUPPLY_1 IJ07 5J05 A1 W12

VDDC
G29 +3V3 AK1 G13
IJ01 AVDDH_DRX G30 M2 M13
5J00 120R
100n

2J41

2J42

F19 E30 U2 P13

10u

+1V2-FA
G19 AVDDL_CH234 G27 Y2 T13
120R
2J3M
2J3N

100n

AVSSH_DRX G28 AB2 V13

10u

2J7C

2J7D
2J7A

2J7B
100n

100n

100n

100n

100n
AE2

2J79
F20 H27 W13
G20 AVSSL_CH234 IJ08 AG2 D14
5J07
IJ02 E29 P3 E14
5J01 +1V2-FA
+3V3 F17 AVDDL_DRX F28 M4 F14
120R
100n

2J43

2J44

VSS
G17 AVDDH_CH234 AA4 G14
10u

120R
2J3Y

2J3P

100n

AJ4 M14
10u

F18 D21 V5 P14

VREFAU
G18 AVSSH_CH234 L6 T14
5J02 IJ03 C22 IJ09 P6 V14

2J6W

100n
2J6Z

100n

100n

100n

100n

100n

100n

100n

100n

100n
2J70

2J71

2J72

2J73

2J74

2J75

2J76

2J77
+1V2-FA F22 R6 D15
D16 C23 T6 E15
120R
2J3R
2J3S

100n

100n

2J45

2J46

E16 AVDDL_CH516 F23 K7 F15

10u

10u

SGNDAU
C24 L7 M15
F16 F24 P7 P15
AVSSL_CH516
5J03 IJ04 E25 R7 T15

VDDC
+3V3 B15 IJ0A T7 V15
AVDDH_CH516 5J09
G22 +3V3 AJ7 M16
120R

2J6M
2J3U

2J6R

2J6N

2J6U
2J6S

2J6Y

2J6P

2J6V
2J3T

100n

G16 AVDD G23 AJ9 P16

10u

10n

10n

10n

10n

10n

10n

10n

10n
AVSSH_CH516 120R
100n

2J47

2J48

AG10 T16
10u

E21 N11 V16

5J04 IJ05
+3V3-STANDBY K24 AVSS F21 AH11 M17
AVDD33_STB
IJ0B N12 P17
120R 5J0A
2J3W

2J3V

100n

J24 R12 T17

10u

AVSS_STB +3V3
B14 U12 V17
AVDDH 120R
2J4A
100n

2J49

H28 N13 W17

10u

VDD33_XTAL DAC1

2J6G
2J6H

2J6D

2J6E

2J6F

2J6L
2J6J
C14 R13 M18

10n

10n

10n

10n

10n

10n

10n
5J06 IJ06 AVSSH
+3V3-STANDBY U13 P18
E17 B13 IJ0C 5J0B AG13 T18
120R INN16 AVDDH
2J3Z

100n
2J40

L14 V18
10u

DAC2 +3V3
E18 C13 N14 W18
2 AVSSH 120R
2J4C
2J4B
100n

E19 R14 M19

10u

3 INN
E20 G15 U14 P19
4 VDD25_LPLL PWR_GND
100n
2J90

AH14 T19

2J6C
2J6B

2J6A

2J69

2J68

2J65

2J66

2J67
K16 L15 V19

10n

10n

10n

10n

10n

10n

10n

10n
IJ0D 5J0C
100n

VSSA_LPLL
2J91

VSS

L16 +2V5-F N15 W19

R15 L20
120R
2J4D

2J4E
100n

U15 M20
10u

AD15 N20
9J03

AE15 P20

VDDC
N16 R20
9J04

R16 T20
U16 U20
Y16 V20
AD16 W20
AE16 Y20
AG16 G21
AJ16 L24
L17 M24
N17 L25 IJ00
R17 T11 SENSE+1V1-FD
7J00-2 U17 K10
FUSION120 Y17 K21
SUPPLY_2 IJ0L 5J0D AD17 L10
5J0H IJ0E AG6 +2V5-F AE17 L21
+2V5 VDD2V5_M0P AG7 L18 M10
120R
2J4G
2J4H
100n

2J4F

2J96

2J97

N18 M21
1u0
10n

10n

10n

120R
2J4S
2J4T

100n

Y12 R18 N21

10u

Y13 U18 P21

Y14 Y18 R21
VSS_M0P
AA13 L19 T10
5J0J IJ0F AC26 AA14 N19 T21
VDD25 R19
+3V3 U21
VDDC
VSS

AC25 IJ0M 5J0E U19 V21

120R VSSAC_2
2J4U
2J4V

100n

AC3 Y19 W21

10u

+2V5-F
AC24 VDD2V5_M1P AC4 AD20 Y21
VDD33 120R
100n

2J4L

2J98

2J99
2J4J

AA20
1u0

10n

10n

AD21
AB24 R10 P24 AA21
VSSAC_1
5J0K IJ0G R11 U24
+2V5 VSS_M1P U10 V24
G10 U11 W24 R4
120R AVDD25
2J4W
2J4Z

100n

A30 AB5
10u

REF_BG
K12 AK30 AC5
AVSS25
L12 N24 K14 M6
AVSS25 VQPS
5J0L IJ0H K15 N6
+1V1-FA C28 K17 V6
VDD11A +1V5-M1
A7 K18 W6 +1V5
120R
100n
2J50

2J51

2J52

D27 B7 K19 Y6
10n
10u

VSS11A_2
C7 K20 AA6 IJ0S 5J0R
VSS

D29 D8 IJ0N N10 AB6

AVDD25_HDMI LVDSVDD 5J0F
E8 AA16 AC6
220u 2V0
+2V5-F 120R
2J7W
2J7V

100n

100n
2J7Z

100n
2J92

C27 F8 AA17 M7 2J08

10u

5J0M IJ0J VSS11A_1 120R

2J4M

2J4N
100n

2J94

2J95

G8 AA18 N7
10u

10n

10n

+2V5
VDDM1

D30 AA19 V7
120R VDD33A
100n
2J53

2J54

2J55

A8 W7
10n
10u

D28 B8 Y7
VSS11A_3
C8 AA7
LVDSGND D9 AB7
2J7U

2J7R
2J7S

2J7P

2J7Y
2J7T

100n
2J23

2J09

K11 AC7
10n

10n

10n

10n

10n

10n

10n

5J0N IJ0K
+3V3 L11 P11
V11
120R
2J56

2J58

P12
10u

1n0

IJ0P 5J0G
G11 +1V1-FA V12
VDDP +1V5-M0
P10
120R
2J4P

2J4Y
100n

K13 V10
10u

GNDP L13 W10 IJ0R +1V5

5J0P
Y10
100n

2J78

120R
VDD_1V2

2J5D

2J5C

2J5B

2J5A
100n

100n

100n

2J59

2J80

2J93
K29
10u

10u

10n

10n
VDDM0

VDDM0

LDO11_CAP
SENSE+1V2-MIPS
2J4R

4n7

AD14

AD13
AD12
AD11

AD10
AA15

AA12
AA11
AA10
AE14

AE13

AE10
W15
W16
W14

W11

AD9

AD8

AD7

AD6

AD5

AD4
AE9

AE8

AE6

AE5

AE4

+1V2-MIPS
AF8

AF7

AF6

AF5

AF4
Y15

Y11
100u 2.0V

2J5M
2J5G
2J5N

2J5H

2J5K
2J7F

2J6T

2J5F
2J13

2J26

2J5L
22u

10u

10n

10n

10n

10n

10n

10n

10n

10n

5 2012-11-08

Fusion power supply

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 116

10-2-16 B04A, Control

Control
B04A B04A
+3V3

+3V3

7GM1

3GM5

3GM6
PCA9540BGD

4K7

4K7

3
VDD
3GM1
4 SDA-DISP SDA-DISP RES +3V3
+3V3 SD0
SDA-BE 2 5 SCL-DISP SCL-DISP RES 3GM2 100K
SDA SC0
100K 3GM3
SCL-BE 1 7 SDA-BL SDA-BL
SCL SD1
8 SCL-BL SCL-BL 3GM4 100K
SC1
100K
VSS
1

3CY1-2 2

3CY1-3 3

3CY1-4 4

6
3CY1-1

3CY2
4K7

4K7

4K7

4K7

4K7

1CV2 DBG
8

SDA-BE RES 9GM1 SDA-DISP SCL-DISP 1

4 3CY3-4 5 EJT-TRSTN 2
47R SCL-BE RES 9GM2 SCL-DISP SDA-DISP 3
5 4
1CY1 DBG 3 3CY3-3 6 EJT-TMS
FCY1 47R BM03B-SRSS-TBT
1
2 FCY2
FCY3 2 3CY3-2 7 EJT-TDO 1CV3 DBG
3 FCVC
4 FCY4 47R SDA-BE RES 9GM3 SDA-BL SCL-BL FCVD 1
5 FCY5 FCVE 2
3CY3-1
FCY6 1 8 EJT-TCK SCL-BE RES 9GM4 SCL-BL SDA-BL
6 3
7 8 47R 5 4

BM06B-SRSS-TBT 3CY4 BM03B-SRSS-TBT

EJT-TDI
47R 3CVF
SCL-M2 SCL-BE 1CV1 DBG
47R SCL-BE FCV2 1
FCV1
3CVG 2
SDA-M2 SDA-BE SDA-BE FCV3 3
47R 5 4
3CV2 FCVB
3D-LR-FUS 3D-LR BM03B-SRSS-TBT
47R

1CV6
FCY7
1 TXD-STANDBY
FCY8
2 FCY9 3GD5
3 RXD-STANDBY BL-SPI-CS_BL-I-CTRL-FUS BL-SPI-CS_BL-I-CTRL
4 5 10R

BM03B-SRSS-TBT
3CV3 FCVN
BL-DIM-FUS BL-DIM 1C27
3CVC FCVF
47R RESET-RF4CEn 1
TXD-RF4CE 10R 3CVD FCVG
2
3GM7 RES 3CVE 10R 3
1CV5 DBG +3V3 RXD-RF4CE FCVH
4
1 SCL-M3 4K7 10R 5
3 3CVW FCVJ
2 TXD-STANDBY RC_IRQ-RF4CEn 6
SDA-M3 3D-LED_3D-RF 3CVY 10R
3 7
RXD-STANDBY 1 7GM2 RES FCVK
4 10R 8
PDTC114EU 9 10
5
2
6

2CVC

2CVB

2CVA

2CV9

2CV8
FH52-8S-0.5SH

10p

10p

10p

10p

10p
7 SCL-FE
8 TXD-SERVICE
9 SDA-FE
3CV8
10 RXD-SERVICE BL-SPI-CLK-FUS AMBI-SPI-CCLK +3V3-STANDBY
11 10R
12 3CV9
13 STANDBYn BL-SPI-SDO-FUS AMBI-SPI-MOSI
14 TXD-RF4CE 10R
DETECT12V 1CV4 DBG
15 3CVM FCVL
16 RXD-RF4CE GPIO0 TXD-RF4CE TXD-RF4CE 1
LCD-PWR-ONn 47R FCVA
17 2
RXD-RF4CE FCVM
18 3CVP 3
19 BL-ON GPIO1 RXD-RF4CE 5 4
20 RC_IRQ-RF4CEn 47R
21 22 BM03B-SRSS-TBT
DC02 3CYC 3CVU
GPIO5 POWER-OK POWER-OK +3V3
BM20B-SRDS-G-TF
DC03 47R 10K
3CVA
GPIO6 +3V3
10K
3CYB 3CVN RES
GPIO7 IRQ-EXPANDERn TXD-RF4CE +3V3-STANDBY
47R 10K
GPIO11 DC06 3CV4 3CVR
GPIO15 RES AMBI-SPI-CCLK RXD-RF4CE
10R 10K

RES 3CV5 3CVB RES

GPIO16 AMBI-SPI-MOSI +3V3
10R 10K
3CV7
GPIO20 POWER-OK
47R

GPIO21 DC07

3CVS 3CVT
GPIO23 IRQ-EXPANDERn IRQ-EXPANDERn +3V3
47R 10K

3D-LR 9GM5 RES 3D-LED_3D-RF

9GM6 RES 3D-LR-DISP

5 2012-11-08

Control
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 117

10-2-17 B04B, LVDS

LVDS
B04B B04B
1G50
10p

10p

10p

10p

10p 20519-041E AMBI-SPI-DO-QFHD

3GVJ
RES
50 51
48 49 100R
46 47 3GVK
2GVN

2GVR
2GVP

2GVS

2GVT

AMBI-SPI-CLK-QFHD RES +3V3

44 45
FGV0 100R
SPDIFIN 3GVL 42 43
3GVF
100R 9GV4 GPIO2 RES
3GVB 41
GPIO8 RES IGV7 100R

1n0
1n0
1n0

1n0
40

3GVC RES
10p
10p
10p
10p

10p
10p
100R 9GV5
39 3GVG
3GVM IGV6 RES

1K0
ARC3 38 GPIO2 1G51
100R 9GV6 20519-051E
37 100R 60 61

RES 2GVC
IGV2

RES 2GVA
RES 2GVB

RES 2GVK
RES 2GV9

RES 2GVL
RES 2GVG
RES 2GVD

RES 2GVH
3GVN

RES 2GVF
PCEC-QHDMI 36 BL-ON
AMBI-TEMP 3GVP 100R IGV1 58 59
35 56 57
FGR1 BL-SPI-CS_BL-I-CTRL 3GVR 100R IGV0
34 SPLASH-ON 9GV1
100R FGV5 54 55
FGR2 33 52 53
FGR3 TX3-A- FGV6
32
FGR4 TX3-A+ FGV7 GPIO8 FGU7 RES 3GV0 100R IGW1
31 51
FGR5 TX3-B- FGV8 SDA-DISP FGVZ RES 3GVE 10R IGW2
30 50
FGR6 TX3-B+ FGV9 SCL-DISP FGW0 RES 3GVD 10R IGW3
29 49
FGR7 TX3-C- FGVA BL-ON FGVE RES 3GV3 10R IGW4
28 48
FGR8 TX3-C+ FGVB BL-DIM RES 3GV4 100R IGW5
27 47
FGR9 GPIO3 RES 3GV5 100R IGW6
26 46
TX3-CLK- FGVC 3D-LED_3D-RF FGU9 RES 3GV6 100R FGU8
25 45
IGR0 TX3-CLK+ FGVD 3D-LR-DISP FGUF RES 3GV7 100R IGW7
24 44
IGR1 GPIO3 FGWA RES 3GV8 100R FGW8
23 43
IGR2 TX3-D- FGVF SPLASH-ON FGU6 RES 3GV9 100R IGW9
22 42
IGR3 TX3-D+ FGVG GPIO2 FGWE RES 3GVA 100R FGWB
21 41
IGR4 TX3-E- FGVH TX1-A- FGWC
20 40
IGR5 TX3-E+ FGVJ TX1-A+ FGWD
19 39
IGR6 FGVK TX1-B- FGWF
18 38
IGR7 TX1-B+ FGWG
17 37
IGR8 TX4-A- FGVL TX1-C- FGWH
16 36
IGR9 TX4-A+ FGVM TX1-C+ FGWJ
15 35
IGRA TX4-B- FGVN FGWK
14 34
TX4-B+ FGVP TX1-CLK- FGWL
13 33
TX4-C- FGVQ TX1-CLK+ FGWM
12 32
TX4-C+ FGVR FGWN
11 31
TX1-D- FGWP
10 30
TX4-CLK- FGVS TX1-D+ FGWQ
9 29
TX4-CLK+ FGVT TX1-E- FGWR
8 28
TX1-E+ FGWS
7 27
TX4-D- FGVU RES 2GVJ 10p IGV3
6 26
TX4-D+ FGVV RES 2GVM 10p IGV4
5 25
TX4-E- FGVW TX2-A- FGWT
4 24
TX4-E+ FGVY TX2-A+ FGWU
3 23
TX2-B- FGWV
2 22
+3V3 TX2-B+ FGWW
1 21
TX2-C- FGWY
RES 2GVU 20
TX2-C+ FGWZ
19
100n TO DISPLAY TX2-CLK- FGU0
18
17
7GV0-1 FGU1
1

TX2-CLK+ 16
NX3L4684TK VCC
15
AMBI-SPI-OUT-MOSI 9GVD 2 TX2-D- FGU2
Y1 14
3 AMBI-SPI-MOSI-OUT TX2-D+ FGU3
Z 13
AMBI-SPI-DO-QFHD 5 TX2-E- FGU4
Y0 12
TX2-E+ FGU5
11
GPIO2 4 1 3GVH-1 8
S 10
2 3GVH-2 7
9
GND 3 3GVH-3 6
8
6

4 3GVH-4 5
7
6
+3V3-STANDBY RES 9GV3 IGV5
+3V3 AMBI-SPI-OUT-MOSI 5
7GV0-2 AMBI-SPI-MOSI-OUT 9GV7 +VDISP 4
NX3L4684TK
1

3
VCC AMBI-SPI-DO-QFHD 9GV8 1M01
2
2GV2

100n

AMBI-SPI-OUT-CCLK 10
Y1 AMBI-SPI-OUT-CCLK 1 1
9 9GVB AMBI-SPI-CCLK-OUT AMBI-SPI-CCLK-OUT 9GV9 KEYBOARD_IRQ-SRFn
Z 2
AMBI-SPI-CLK-QFHD 7
Y0 3
AMBI-SPI-CLK-QFHD 9GVA 4 5 TO DISPLAY
9GVC 7GV0-3
GPIO2 8 NX3L4684TK
S
A1253WVA
11

GND_HS
GND
6

1X03 1X05
EMC HOLE REF EMC HOLE

5 2012-11-08

LVDS
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 118

10-2-18 B04C, Output Vdisp

Output Vdisp
B04C B04C

1 9GS1-1 8
RES
2 9GS1-2 7
RES
3 9GS1-3 6
RES
4 9GS1-4 5
RES
1 9GS2-1 8
RES
2 9GS2-2 7
RES
3 9GS2-3 6
RES FGS1
4 9GS2-4 5
RES

8
3 7
2 6
7GS1 1 5
SI4835DDY-GE3 FGS2
RES 6 +VDISP
7GS2
5
4

1GS1 SI3443CDV
+12V 2
4 1
+3V3 T 4.0A 32V
3GS1

2GS1

2GS2

100n
RES
47R

22u

4
RES
3

2GS3 RES
7GS3-2 2GS5 IGS1
3GS4
3GS3

5
4K7

22n PUMD12
47K IGS2 100n
3
IGS4
6GS1
IGS5 3GS5 DBG
DBG
6 4K7 LTST-C190KGKT
3GS6

27K

LCD-PWR-ONn 2 7GS3-1
PUMD12
1

5 2012-11-08

Output Vdisp
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 119

10-2-19 B04D, Tuner CVBS debug

Tuner CVBS debug

B04D B04D

+12V
RES

3FW4 RES
3FW3

470R
10K

4
IFW1 7FW1-2 2FW3
6 RES
BC847BPN(COL)
5
2FW4 7FW1-1 RES 33p
CVBS-OUT1 RES 2 BC847BPN(COL)
IFW2 RES 3
47u
1
3FW5
RES
3FW8
RES IFW3 5FW3 RES DFW1

IFW4 150R IFW5 75R 1u8

3FW6

RES 3FW7

2FW5

2FW6
150R

100p

270p
3K3

RES
RES

RES

DFW2

5 2012-11-08

Tuner CVBS debug

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 120

10-2-20 B04E, Audio - video

Audio - video
B04E B04E
2VW1
CVBS1 CVBS
3VWM 100n
150R 2VW2
SC1-CVBS CVBS3
3VWN 100n
3VWP 2VW3
150R Y-G1
150R 100n
3VWR 2VW4
PB-B1
150R 100n
3VWS 2VW5
PR-R1
150R
100n
2VW6
Y1-IN Y-G2
3VWT 100n
2VW7
PB1-IN 150R PB-B2
3VWU 100n
150R 2VW8
PR1-IN PR-R2
3VWV 100n
150R 2VW9
SC1-G Y-G3
3VWB 100n
150R 2VWA
SC1-B PB-B3
3VWC 100n
150R 2VWB
SC1-R PR-R3
3VWD 100n
150R
3VWW
SC1-BLK FB1
10K
3VW3 IVW1 2VWC
YPBPR-RIN AR-1
8K2 1u0
3VW4

33K

3VW5 IVW2 2VWD

YPBPR-LIN AL-1
8K2 1u0
3VW6

33K

3VW7 IVW3 2VWE

SC-RIN AR-4
8K2 1u0
3VW8

33K

3VW9 IVW4 2VWF

SC-LIN AL-4
8K2 1u0
3VWA

33K

SDI2SIN DVW1

WSI2SIN DVW2

SPDIFIN FVW0

SCKIN DVW4 +3V3

AUD-R DVW5
3VWF

4K7

AUD-L DVW6

AUDIO-MUTEn
RES 3VWG
4K7

3VWH IVW7 2VWJ

VGA-LIN AL-3
8K2 1u0
RES 3VWJ
33K

3VWK IVW8 2VWK

VGA-RIN AR-3
8K2 1u0
3VWL

33K

5 2012-11-08

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 121

10-2-21 B04F, Fusion supply

Fusion supply
B04F B04F
+1V5

2UB0

10u
7UB1
TPS7A7001DDA
3

IN
2
EN
6
OUT
1
2UB6

100n

4 7
GND_HS

NC FB
5
GND

11 VIA
8

10

3UB3 FUB0
RES +1V2-MIPS
27K 1%
3UB4 IUB3 2UB3

2UB4

10u
1K0 100p
47K 1%

220K 1%
100K 1%

22K 1%

3UBF FUB1
IUB4 SENSE+1V2-MIPS
3UB5

RES 3UB6

3UB7

3UB8

27K
1%

DVS2 CORE VOLTAGE SUPPLY MIPS FUSION

10K 1%

IUB5
3UBA
3UB9

1M0
RES

5UB0 IUB6
+12Va
30R
2UB7

100n

IUB7 5UB1 FUB2

2UB8

2UB9
10u

10u

+1V5
2u0
2UBB RES
2UBC

2UBA
22u

22u

22u

7UB5
TPS54527DDA
8

VIN

IUB9
STEP DOWN IUB8
3UBB 2UBD
2 7 1 3UBE-1 8
+1V5 VFB VBST
22K 1% IUBB 100n 10R
4 6
2UBE RES SS SW 2UBJ 2UBK
470K RES

2 3UBE-2 7 IUBC
22K 1%

1 10R
22p EN IUBA 1n0 1n0
2UBG
3UBC

3UBD

3
10n

VREG5 3UBE-3
2UBH

3 6
1n0

VIA 10R
2UBF

GND_HS GND
1u0

4 3UBE-4 5
9

10
11

10R
GND-1V5 GND-1V5
GND-1V5 GND-1V5

CUB0
DDR3 SUPPLY FUSION
GND-1V5

ENABLE+1V5+1V1

5 2012-11-08

Fusion supply
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 122

10-2-22 B04G, Backlight microcontroller

Backlight microcontroller
B04G B04G
+3V3

+3V3 +3V3
RES 2GE0

2GE1

2GE2
100n

100n
1u0

3GE0

3GE1
4K7

4K7
1GE0
TXD-LPC FGE0
1
FGE1 2 DBG
+3V3 RXD-LPC FGE2
3
5 4
RES

+3V3 BM03B-SRSS-TBT
3GEK RES
3GE2

1K0

RESET-FUSION-OUTn
100R

LPC-RESETn
7GE0
44

+3V3 LPC1114FBD48/301
8

DBG
2GE3

100n

3GE3 100R IGE1 VDD FGE3 3GE4

6 LPC-RESETn
XTALIN
RES

FGE4 3GE5 100R

7 LPC-ISPn
XTALOUT
3GE6

1K0

100R
3 2
PIO0_0|RESET_ PIO2_0|DTR_|SSEL1 DBG

3
4

3
4
LPC-ISPn 4 13 9GE0 AMBI-SPI-CCLK
PIO0_1|CLKOUT|CT32B0_MAT2 PIO2_1|DSR_|SCK1

2GE4

100n
10 26 RES 9GE1 AMBI-SPI-MOSI

SKHUBHE010

SKHUBHE010
PIO0_2|SSEL0|CT16B0_CAP0 PIO2_2|DCD_|MISO1

2GE5

100n
10R 14 38 RES 3D-LED_3D-RF
3GE7 PIO0_3 PIO2_3|RI_|MOSI1

1GE1

1GE2
SCL-SSB 15 19 DBG DBG
PIO0_4|SCL PIO2_4|CT16B1_MAT1|SSEL1
SDA-SSB 3GE8 10R 16 20
PIO0_5|SDA PIO2_5|CT32B0_MAT0
22 1 3D-LR
PIO0_6|SCK0 PIO2_6|CT32B0_MAT1
23 11 LPC-LED1
RES PIO0_7|CTS_ PIO2_7|CT32B0_MAT2|RXD
27 12 LPC-LED2

1
2

1
2
3GE9 10R PIO0_8|MISO0|CT16B0_MAT0 PIO2_8|CT32B0_MAT3|TXD
AMBI-SPI-OUT-MOSI 28 24 LPC-LED3 FGE5
PIO0_9|MOSI0|CT16B0_MAT PIO2_9|CT32B0_CAP0
LPC-SWCLK 29 25 LPC-LED4
PIO0_10|SWCLK|SCK0|CT16B0_MAT2 PIO2_10 3GEA
BL-DIM1 32 31 RES AMBI-SPI-OUT-CCLK
PIO0_11|R|AD0|CT32B0_MAT3 PIO2_11|SCK0|CT32B0_CAP1
10R
BL-DIM2 33 36 BL-DIM5
PIO1_0|R|AD1|CT32B1_CAP0 PIO3_0|DTR_|CT16B0_MAT0|TXD
BL-DIM3 34 37 BL-DIM6
PIO1_1|R|AD2|CT32B1_MAT0 PIO3_1|DSR_|CT16B0_MAT1|RXD
BL-DIM4 35 43 BL-DIM8
PIO1_2|R|AD3|CT32B1_MAT1 PIO3_2|DCD_|CT16B0_MAT2|SCK1
LPC-SWDIO 39 48 3D-LR-DISP +3V3 +3V3 +3V3 +3V3
PIO1_3|SWDIO|AD4|CT32B1_MAT2 PIO3_3|RI_|CT16B0_CAP0
40 18
PIO1_4|AD5|CT32B1_MAT3|WAKEUP PIO3_4|CT16B0_CAP1|RXD
BL-DIM 45 21
PIO1_5|RTS_|CT32B0_CAP0 PIO3_5|CT16B1_CAP1|TXD
RXD-LPC 46

3GEB DBG

3GEC DBG

3GEE DBG

3GEF DBG
PIO1_6|RXD|CT32B0_MAT0
TXD-LPC 47
PIO1_7|TXD|CT32B0_MAT1
BL-SPI-CS_BL-I-CTRL 9
PIO1_8|CT16B1_CAP0

330R

330R

330R

330R
17
3GEL PIO1_9|CT16B1_MAT0|MOSI1
30
PIO1_10|AD6|CT16B1_MAT1|MISO1
10K 42
PIO1_11|AD7|CT32B1_CAP1
3GEM

3GEN
2GE6

RES 100K

RES 100K
1u0

VSS
5
41

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT

LTST-C190KGKT
DBG

DBG

DBG
DBG
+3V3

6GE0

6GE1

6GE2

6GE3
BL-DIM7

AMBI-SPI-CCLK 9GE2 AMBI-SPI-OUT-CCLK LPC-LED1

LPC-LED2

LPC-LED3
AMBI-SPI-MOSI 9GE3 AMBI-SPI-OUT-MOSI
LPC-LED4

BL-DIM 9GE4 BL-DIM1

+3V3

+3V3
3GEG

10K

ROW_1
1GE3-1 ROW_2
1GE3-2
1
RES 3 2 FGE6 LPC-SWDIO
FGE7 LPC-SWCLK
3GEJ 5 DEBUG 4
DEBUG 6 3GEH FGE8 AMBI-SPI-OUT-MOSI
7
1K0 RES 100R
9 8
10 LPC-RESETn

FTSH-105-01-L-DV
FTSH-105-01-L-DV

5 2012-11-08

Backlight microcontroller
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 123

10-2-23 B04H, eMMC

eMMC
B04H +3V3 +3V3 B04H

2EJ1

2EJ2

2EJ3

2EJ4

2EJ5

2EJ6
100n

100n

100n

100n

100n

100n
+3V3

3EJ1 +3V3

4K7
7EJ0-1

J10
M4
C6

N4
P3
P5

E6

K9
F5
H26M21001ECR
3EJ4 VCCQ VCC 3EJ2-2
GPIO14 SDIO2-CLK SDIO2-CMD FEJ2 M5 A3 FEJ3 SDIO2-D0 SDIO2-D0 2 7
CMD 0
A4 FEJ4
33R
SDIO2-CLK FEJ1 M6
CLK
MAIN 1
2
A5 FEJ5
SDIO2-D1
SDIO2-D2
47K
3EJ5 3EJ2-3
GPIO15 SDIO2-CMD B2 FEJ6 SDIO2-D3 SDIO2-D1 3 6
3EJ0 3
33R +3V3 FEJ0 K5 DATA B3 FEJ7 SDIO2-D4 47K
RST 4
SDIO2-RESETn 10K B4 FEJ8 SDIO2-D5
3EJ6-2 5 3EJ2-4
GPIO16 2 7 SDIO2-D0 VDDI C2 B5 FEJ9 SDIO2-D6 SDIO2-D2 4 5
VDDI 6
33R B6 FEJA SDIO2-D7 47K
7
3EJ6-3 VSS VSSQ 3EJ2-1
2EJ7

100n

GPIO17 3 6 SDIO2-D1 SDIO2-D3 1 8

G5
E7
K8
H10

C4
N2
N5
P4
P6
33R 47K
3EJ6-1 FEJB 3EJ3-2
GPIO18 1 8 SDIO2-D3 SDIO2-D4 2 7
33R 47K
3EJ6-4 3EJ3-1
GPIO19 4 5 SDIO2-D2 SDIO2-CLK SDIO2-D5 1 8
33R SDIO2-CMD 47K
3EJ7-1 +3V3 +3V3 +3V3 3EJ3-4
GPIO20 1 8 SDIO2-D5 SDIO2-D6 4 5
33R 47K
3EJ7-4 3EJ3-3
GPIO21 4 5 SDIO2-D6 SDIO2-D7 3 6
M10
M11
M12
M13
M14

N10
N11
N12
N13
N14

P10
P11
P12
P13
P14
33R 7EJ0-2 47K
M3
M7
M8
M9

N1
N3
N6
N7
N8
N9

P1
P2
P7
P8
3EJ7-3
H26M21001ECR P9
GPIO22 3 6 SDIO2-D7 NC
33R A1 H1
SDIO2-D3 A2 H2
3EJ8
GPIO23 SDIO2-RESETn SDIO2-D6 A6 H3
33R SDIO2-D7 A7 H5
+3V3 A8 H12
3EJ7-2
GPIO24 2 7 SDIO2-D4 A9 H13
33R A10 H14
A11
A12
NC J1
J2
A13 J3
A14 J5
B1 J12
+3V3 B7 J13 +3V3
B8 J14
B9 K1
B10 K2 SDIO2-RESETn
NC NC
B11 K3
B12 K6
B13 K7
B14 K10
VDDI C1 K12
SDIO2-D4 C3 K13
SDIO2-D5 C5 K14
C7 L1
C8 L2
C9 L3
C10 L12
C11 L13
C12 L14
C13 M1
C14 M2
NC
D1
D2
D3
D4
D12
D13
D14
E1
E2
E3
E5
E8
E9
E10
E12
E13
E14
F1
F2
F3
F10
F12
F13
F14
G1
G2
G3
G10
G12
G13
G14

SDIO2-D4
SDIO2-D5 +3V3

5 2012-11-08

eMMC
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 124

10-2-24 B05A, Class-D amplifier

Class-D amplifier
B05A B05A

3D60 A-STBY
+3V3D +12V-AUDIO +12V-AUDIO
10K
3

RESET-FUSION-OUTn 1 7D70
PDTC144EU
2D97

2D96

2D84

2D92

2D60

2D61

2D62

5D50

2D63

2D66

2D57

2D58

2D59

2D64

2D65

5D51
220n

220n

220n

220n
2
30R

30R
10u

10u

10u

10u

10u

10u

10u

10u

10u

10u
2D49 2D48
3D61
100u 16V ID54 ID55 16V 100u
2D93 RES
100u 16V

100u 16V
1u0

10R
1u0

5D85

2D5C
2D5A

3D78

3D82
10K

10K
3D62 +3V3D +3V3
2D86

2D68

2D69
100n

100n

2D67

AUDIO-MUTE
10u

+3V3D 30R
10K
3 SPEAKER-L- SPEAKER-R-
AUDIO-MUTEn +3V3D 3D58
9D50

ID78
RES

1 7D71 RES
100u 16V

100u 16V
2D5D
2D5B

3D79

3D83
PDTC144EU 1R0
10K

10K
2
+3V3D 3D57 ID77 ID76 ID75 TAS5731P1
7D60
1R0 TAS5711PHP
13

27

32

44
45

40
41

34
35
5

2
3

DBG 2D72
9D52 AVDD DVDD OUT A B C D
RES 3D63 1D03 WSI2SOUT FD67 20 GVDD PVDD
LRCLK 10u
1 SDI2SOUT1 I2SCLK FD63 RES 9D53 FD64 21
SCLK 2D74 ID50 5D70 5D00
9D54 ID79 ID88 ID91
10R 2 SCKI2SOUT FD65 FD66 15
MCLK AUDIO VR_DIG
18 SPEAKER-L+ SPEAKER-L+
SCKI2SOUT SDI2SOUT1 22
3 SDIN AMPLIFIER 31 ID80 2D77 100n 10u 30R
4 WSI2SOUT FD50 VREG
+3V3D

3D73

2D56

2D71

2D99

2D78
220n

220n
+3V3-STANDBY

18R

10n

10n
5 6 3D55 100n
SDA-SSB 23 1
SDA OUT_A
SCL-SSB 3D56 47R 24
SCL ID81 2D79
47R 3D76 RES 4
+3V3D BST_A
3D50

10K
10K

BM04B-SRSS-TBT 33n 2D80 5D71

9D55 2D75

330p
SDI2SOUT3 ID89 ID90 14 43 ID82
A_SEL BST_B FD69
3D54

47K

RES 33n 30R

3D77 46
ID56 OUT_B
D-RESET D-RESET 15K 25
RESET 5D75

2D98

2D70
19 ID93 ID94

10n

10n
PDN SPEAKER-L-
ID87 7D50-2 39 1D01 1D02
OUT_C 30R FD30
PUMH2
2D50 ID66 ID62 ID51 5D74 Left+ 1 1
2D82 FD31

5D81
ID65 12 42 Left- ID57

30R
VR_ANA BST_C SPEAKER-L- 2 2
11 ID63 10u SPEAKER-R+ Right+ 3 3
4n7 PLL_FLTP 2D85 33n 3D74 2D94
DETECT12V 7D50-1 10 33 FD32 FD33 Right- 4
PUMH2 3D51 PLL_FLTM BST_D
2D51 18R FD70 2041145-3
33n 330p
47n 470R 36 ID52 5D76 5D01 2041145-4
3D52 OUT_D ID96
ID58 2D52 SPEAKER-R+
3D70 RES

2D87

1D52

1D50

1D51
7 ID83

10n
A-STBY 470R 47n ID69 ID97 OC_ADJ 10u 30R
8 16 ID84 3D71 22K
2D53 PBTL OSC_RES
3D75

2D83

2D55
220n

9D51 220n
18R

18K2 1%
ID61 ID70 50
4n7 2D54
2D89

1D53

1D54

1D55

1D56

2D81

2D73
220n

6 51

10n

10n
AUDIO-MUTE SSTIMER ID53
52
2n2 53
2D95

2D76

2D91
26 54

10n

10n
STEST
3D72

55
18R

330p
56
57 5D79 5D80
58 ID98 ID99 SPEAKER-R- SPEAKER-R-
59
VIA 10u 30R
2D88

330p

60
5D83

61
30R

62
63
64
65
66 5D77
67
68
PGND 30R
VSS 69
AGND GND A D DO AB CD GND_HS
30

29

28

17

47
48

37
38

49
CD00

1X02
REF EMC HOLE

5 2012-11-08

Class-D amplifier
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 125

10-2-25 B05B, Analogue externals

Analogue externals
B05B B05B

3VA7 FVA9
SC-RIN

CDS4C12GTA
RES
1K0

1VAG
2VA8

2VA9
100p

12V

6n8
6VA8
3VA8 FVAA
SC-LIN

CDS4C12GTA
RES
1K0
SCART

1VAH
2VAA

2VAB
100p

12V

6n8
49045-0011

6VA9
25 26
FVA1
24
23
FVAB 22
SC1-B 21

CDS4C12GTA
RES
20
19

3VAG
2VAC

1VAJ
100p

75R
12V
18
17

6VAA
16
FVA2
15
14
IVA0 3VA9 FVAC 13
SC1-STATUS 12
PDZ2.4B(COL)

CDS4C12GTA
RES
12K 11
10
2VAD
6VAB

3VAA

2VAE

1VAK
100p
1K5

12V
1u0

9
8
6VAC

7
6
+3V3 5
FVA4 4
SC1-G 3
CDS4C12GTA
RES

2
1
3VAB
2VAF

1VAL
3D90

100p
1R0

75R
12V

1VA1
6VAD

1J50
3150-831-030-H1 ID95
2
VCC
FD90
1 SPDIFO
VIN FVAD
SC1-R
3
CDS4C12GTA
RES

GND
CDS4C12GTA

MT
1VAM
2VAG

3VAC
100p

75R
12V
V_NOM

5 4
2D0A

RES 2D0B

1D0A

RES 6D0A
100n

100p

12V

6VAE

IVA1 3VAD FVAE

SC1-BLK
PDZ2.4B(COL)

CDS4C12GTA
RES

100R
2VAH

1VAN
3VAE
6VAF

100p
75R

12V
6VAG

FVAF
SC1-CVBS
CDS4C12GTA
RES

1VAP
3VAF
2VAJ

150R
100p

12V
6VAH

3VAK FVAG
SC1-DETECTn
47R
2VAK

100p

5 2012-11-08

Analogue externals
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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 126

10-2-26 B05C, Sensor board and AmbiLight

Sensor board and AmbiLight

B05C B05C

FAA0

FH52-11S-0.5SH FH52-25S-0.5SH FH52-40S-0.5SH

FAA1
13 12 27 26 42 41 3CAF SDA-SRF
11 25 40
FAA2 10R
10 24 39 3CAH
3CAE SCL-SRF LED2-OUT
9 23 38 +3V3-STANDBY
IAA0 3CAG 10R
8 22 37 +5V 10K
FAA3 +T 0R3 3CAD RC_IRQ-RF4CEn
7 21 36
FAA4 10R LED2-OUT
6 20 35
3CAC KEYBOARD_IRQ-SRFn
5 19 34
FAA5 10R
4 18 33
3CAB LED2-OUT
3 17 32
FAA6 3CAA 100R 3D-LED_3D-RF SDA-MC
2 16 31
FAA7 3AAA 100R AMBI-TEMP
1 15 30
GND-AL FAA8 100R
14 29
1C20 3AAB AMBI-SPI-MOSI-OUT
13 28
GND-AL FAA9 47R
12 27 +3V3-STANDBY
3AAC AMBI-SPI-CCLK-OUT
11 26
47R
10 25
1u0

GND-AL
100p

100p

100p

100p

9 24
470p

470p
1u0

10p

10p

10p

1u0
8 23
7 22 AMBI-POWER
2CAK

IAA1 1u0
2CAM

6 21
2CAJ

2CAN

2CAR
2CAP

2CAD

2AAW
2CAA

2CAB

2AAC

2AAV

5 20
4 19 2CAS
3 18
9CAA AMBI-POWER
2 17
9CAB +3V3AL
1 16
15 AMBI-POWER
1C25
14
2CAT
13
100n
12
2CAU RES
11
10u
10
9
8 GND-AL
7
6
5 2CAL RES
4 3AAD FAAZ
3 100n +3V3 +3V3AL
2 +T 0R3
1
2AAD

2AAE
10u

10u
GND-AL
1C26

GND-AL

5 2012-11-08

Sensor board and AmbiLight

3104 313 6618

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 Circuit Diagrams and PWB Layouts QFU1.2E LA 10. EN 127

10-2-27 B06A, HDMI

HDMI +5V +3V3

B06A pins (9,27,64) B06A

3HA5 RES

PDZ2.4B(COL)
5HA5
FHA8
+3V3 VCC33

6HA1

5HA9

30R
3K3
7HA5 30R

2HAM

2HAN

2HAP
2HAJ

100n

100n

100n
FHB4 RT9715EGB

10u
MICOM-VCC33 RES
IHB0
5 3
VCC33 SBVCC33 VIN FLG

3HAP
2HB4

10K
1u0
I2C ADDRESS

3HA6

2HB5
4 1

2K2

1u0
EN VOUT
SII9287B=OXB2 FHBC
EN

RES 2HAK
2HAL

100n

10u
GND
RES
5HA6
pin (38)
7HA0 FHA7
SBVCC33

27
64

37

38
SII9287B

2
30R

2HAG
2HAF