Cortex M3权威指南CnR2（电子书）

Cortex-M3
Cortex-M3
Joseph Yiu

www.ouravr.com
1
Cortex-M3
2
Cortex-M3
ARM 4
Cortex-M3
ARM
150
1.

2.

3.

4.
error fault
:retarget, fault, region
both
5.

200%
6.
.text

7. ARM
40%
^_^
2008.05.10-2008.06.07 28
rock.song@hotmail.comQQ:9471202/9312500
bugs
Y
2008.07.02
3
Cortex-M3
4 /
CM3 STM32
CM3
CM3
16 DSP CM3
www.ouravr.com
Cortex-M3
ouravr
watercat

RTOS
ARM
32

Cortex-M3
4
Cortex-M3
5
Cortex-M3
ARM7TDMIARMCPU
ARM7TDMI
ARM Cortex-M3
ARM32ARMv7
Thumb-2
Cortex-M3
ARM
Wayne Lyons
6
Cortex-M3
ARMCortex-M3
Cortex-M3
Cortex-M3Cortex-M3 Technical Reference Manual,
Cortex-M3 TRM
ARMv7-M
ARMv7-M Application Level Architecture
Reference Manual
SoC
Cortex-M3
Cortex-M3
ARMGNUARM7TDMI
Cortex-M3
7
Cortex-M3

Alan Tringham, Dan Brook, David Brash, Haydn Povey, Gary Campbell, Kevin McDermott,Richard
Earnshaw, Samin Ishtiaq, Shyam Sadasivan, Simon Axford, Simon Craske, Simon Smith, Stephen Theobald
and Wayne Lyons.
CodeSourceryLuminary Micro
Elsevier
Peter ColeIvan Yardley
8
Cortex-M3
ADK AMBA
AHB
AHB-AP AHB
AMBA
APB
ARM ARM ARM
ASIC
ATB
BE8
CPI
CPU
DAP
DSP
DWT
ETM
FPB
FSR Fault
HTM CoreSight AHB
ICE
IDE
IRQ
ISA
ISR
ITM
JTAG
JTAG-DP JTAG
LR
LSB
LSU /
MCU
MMU
MPU
MSB
MSP
NMI
NVIC
OS
PC
PSP
PPB
9
Cortex-M3

MOV R0, R1 ; R1R0

MRS <reg>, <special_reg> ;
C
for (i=0;i<3;i++) { func1(); }

if (a > b) { ...
:
1. 4'hC , 0x123 16
2. #33 (e.g., IRQ #3 3)
3. #immed_1212
4.
bit[15:12] 1512

1. R
2. W
3. RW 3
4. R/Wc 0
10
Cortex-M3
1 Cortex-M3 Technical Reference Manual (TRM) (Cortex-M3)

www.arm.com/documentation/ARMProcessor_Cores/index.html
2 ARMv7-M Architecture Application Level Reference Manual(ARMv7-M)

www.arm.com/products/CPUs/ARM_Cortex-M3_v7.html
3CoreSight Technology System Design GuideCoreSight

www.arm.com/documentation/Trace_Debug/index.html
4 AMBA Specification (AMBA)

www.arm.com/products/solutions/AMBA_Spec.html
5 AAPCS Procedure Call Standard for the ARM Architecture(AAPCS ARM)

www.arm.com/pdfs/aapcs.pdf
6 RVCT 3.0 Compiler and Library Guide(RVCT 3.0)

www.arm.com/pdfs/DUI0205G_rvct_compiler_and_libraries_guide.pdf
7 ARM Application Note 179: Cortex-M3 Embedded Software Development(ARM179

Cortex-M3)
www.arm.com/documentation/Application_Notes/index.html
34
11
Cortex-M3
12
Cortex-M3 [] 1
ARM Cortex-M3
ARM

Thumb-2(ISA)
Cortex-M3

1.1 ARM Cortex-M3

201020G
USB
ARM Cortex-M3
Cortex32
32
DSPCM332
CM38051
dreams come true
CM3

8/1632

328/16Cortex-M3
1

Cortex-M3
device aggregation
13
Cortex-M3 [] 1
34
CM3
CC
CM3
ARM7/ARM9
NXPphilipsTIAtmelOKISTARM32
MCUARM73210
CM3ARM7
CM3
-
ARM
1.1.1 Cortex-M3 Cortex-M3 MCU
Cortex-M3CPUCM3MCU
CM3CM3
I/O
1.1.2 ARM ARM
1.1.2.1
ARMARMARM
ARM1990Advanced RISC Machines Ltd.,
14
Cortex-M3 [] 1
AcornVLSI1991ARMARM6
VLSITI, NEC, Sharp, ST
ARMARMARMPDA
ARM20ARM
ARM
ARM
(SoC)
ARMIPIPARM
1.2 ARM
ARMARM7TDMI
ARM1176TZ(F)-S
ARM
ARM7TDMIARMv4TTThumbARMv5TE
ARM9EARM9EARM926E-SARM946E-SARMv5TE
DSP
ARM11ARM11ARMv6ARMv6
ARM1136J(F)-SARM1156T2(F)-S ARM1176JZ(F)-SARMv6ARM
SIMDv6Thumb-2
ARMv6MCU
ARMv6
ARMv6ARMCPU
ARMv73
A
R
M
3
AARMv7-A[ 1]

SymbianLinuxWindows CE
Windows MobileMMU
Java

1
PC
1
RARMv7-R
15
Cortex-M3 [] 1

MARMv7-M

Cortexv7Cortex-M3M
1
deadlineARM
Cortex-M3Cortex-M3M
CortexACortex-A8RCortex-R4
1.2 ARM
ARMv7-MThe ARMv7-M Architecture Application Level Reference Manual

System LevelARMCortex M3 Technical
Reference Manualv7-M v7M
CM3CM3
1.2.1
ARM1990s
ARM7TDMITThumbDJTAG
(Debugging)MIICE4
4
TCM
16
Cortex-M3 [] 1
1.1 ARM

ARM7TDMI v4T
ARM7TDMI-S v4T
DSP,Jazelle[
3]
ARM7EJ-S v5E
ARM920T v4T MMU
ARM922T v4T MMU
ARM926EJ-S v5E MMU DSP,Jazelle
ARM946E-S v5E MPU DSP
ARM966E-S v5E DSP
ARM968E-S v5E DMA,DSP
ARM966HS v5E MPU DSP
ARM1020E v5E MMU DSP
ARM1022E v5E MMU DSP
[ 2]
ARM1026EJ-S v5E MMU MPU DSP, Jazelle
ARM1136J(F)-S v6 MMU DSP, Jazelle
ARM1176JZ(F)-S v6 MMU+TrustZone DSP, Jazelle
ARM11 MPCore v6 MMU+ DSP

ARM1156T2(F)-S v6 MPU DSP
Cortex-M3 v7-M MPU NVIC
Cortex-R4 v7-R MPU DSP
Cortex-R4F v7-R MPU DSP+
Cortex-A8 v7-A MMU+TrustZone DSP, Jazelle
2JazelleARMJava
3MMU
MMUMMU
safety-critical
MPUMPUMMU
7ARM
ARMv7Cortex
ARMARM7TDMIARMv7
v4T
1.3
ARM
ARM7TDMIARM
17
Cortex-M3 [] 1
32ARMARM
16ThumbThumb

ThumbARM
1.3
1: Thumb-2v7v6
ARM and Thumb-2 Instruction Set Quick Reference Card
ARMThumb2
ThumbThumb-22003Thumb
both 1632
The ARM Architecture Reference ManualARMARM
ARMv73
3Corex-M3ARMv7-MARMv7-M Architecture Application
Level Reference Manual(Ref2)
1.4 Thumb-2 ISA

Thumb-2Thumb-216Thumb
Thumb-21632Thumb
18
Cortex-M3 [] 1
1.4 Thumb-2Thumb
Cortex-M332ARM
Thumb-2Cortex-M3
Thumb-2
Cortex-M3
ARM7ARMCM3CM3Thumb
Thumb
both 1632ThumbARM
ARM7ARM9
Cortex-M3ARMv7ARM7Cortex-M3
CM3
data-crunchingCM3ARM
1.5 Cortex-M3
3CM3
CM3
CM3816CM3
ARM32
CM3CM3
CM3240
MPU

CM3Thumb-2sCM3
Ad-HocZigBee
CM3
fault-handingfault

19
Cortex-M3 [] 1
CM3MPU

Cortex-M31ARM
8
Chpt 12 Cortex-M3
Chpt 3-6 Cortex-M3
Chpt 7-9
Chpt 1011 Cortex-M3
Chpt 12-14 Cortex-M3
s
1.6
Cortex-M3Cortex-M3
CM3ARM
The Cortex-M3 Technical Reference Manual
The ARMv7-M Architecture Application Level Reference Manual2
CM3
AMBA Specification 2.0 4AMBA
CARM Application Note 179: Cortex-M3 Embedded Software Development

7

2
Cortex-M3
20
Cortex-M3 2
Cortex-M3
2.1
Cortex-M3 32 32 32
32 CM3
CM3
8GB
CM3 MPU
cache CM3 Both
CM3
21
Cortex-M3 2
2.1 Cortex-M3
2.1
1. Debug SystemTrace System

2. MPU
2.2
Cortex-M3 R0-R15 R13 SPSP
banked
22
Cortex-M3 2
2.2.1 R0-R12
R0-R12 32 16 Thumb
R0-R7 32 Thumb-2
2.2.2 Banked R13:

Cortex-M3 banked
MSP

PSP
0 4
ARM (exception)
fault
2.2.3 R14
R14
ARM 3 MMU
cache 1
1 R14 ARM
RISC
23
Cortex-M3 2
2.2.4 R15

2.2.5
Cortex-M3
PSRs
PRIMASK, FAULTMASK, BASEPRI
CONTROL
2.3 Cortex-M3
2.1

xPSR ALU 0

PRIMASK NMI
FAULTMASK faultNMI faults

BASEPRI
CONTROL
3
2.3
Cortex-M3
(handler mode handler )
thread mode
Cortex-M3
24
Cortex-M3 2

userUnprivileged

2.4 Cortex-M3
CM3
MPU MPU

CONTROL
(SVC) SVC
CONTROL
2.5

MPU
MPU
25
Cortex-M3 2
2.4
Cortex-M3 NVIC(Nested
Vectored Interrupt Controller)

NVIC

2.4.1

xPSR
2.4.2
CM3 ISR
ARM
2.4.3
ISR
pending(reentry)
7

7

2.4.4
Cortex-M3
ISR
2.4.5
/ 8(BASEPRI)(
PRIMASKFAULTMASK)time-critical
26
Cortex-M3 2
(deadline)
8
2.5
Cortex-M3 4GB 2.6
ARM Cortex-M3
Cortex-M3
CM3
RAM
CM3 MPU
5
27
Cortex-M3 2
2.6
Cortex-M3 CM3

I-Code D-Code
SRAM RAM
2.7 MPU
Cortex-M3
violatedMPU fault
fault
MPU MPU
MPU ( region
) region
MPU
2.8
Cortex-M3 Thumb-2 32 16
ARM 32
ARM 16 Thumb ARM 32
NOP Thumb 16
thumb ARM
ARM Thumb
overheadARM
Thumb
28
Cortex-M3 2
2.7 ARM7
Thumb-2
Cortex-M3 ARM Thumb
ARM ARM CM3
ARM
both
ARM Thumb

Cortex-M3
UBFXBFIBFC C

CLZRBIT
UDIVSDIV
SEVWFEWFI

MSR,MRS
CM3 Thumb-2 C
CM3
CM3 (unified assembler framework)
CM3 Thumb-2 ARMv7-M Thumb-2
CM3
SIMD Thumb v6
SETEND A
2.9
ARMv7-M CM3
ARM
29
Cortex-M3 2
16-4-1=11 4+1 240 CM3 FIQ

v7 ARM FIQ
CM3
FIQ
CM3 NVIC 240 NVIC 16-4-1=11
fault CM3 256 2.2
2.2 Cortex-M3

0 N/A N/A
1 -3
2 NMI -2 NMI
3 (hard) fault -1 fault fault
4 MemManage faultMPU
fault
5 fault Abort
6 (usage)
Fault
7-10 N/A N/A
11 SVCall
12
13 N/A N/A
14 PendSV pendable request
15 SysTick
16 IRQ #0 #0
17 IRQ #1 #1
255 IRQ #239 #239
30
Cortex-M3 2
CM3 240 CM3

NMIassertNMI
2.9b ( r2p0 )
Cortex-M3
CM3
CM3
Cortex-M3
8 16
2.10
Cortex-M3
(halting)(stepping)
profiling
Cortex-M3 ARM CoreSight ARM
JTAG CPU (DAP)
(DP)DPs CM3
DPs SWJ-DP( JTAG
) SW-DP JTAG ARM CoreSignt JTAG-DP
3 DPs
SWJ-DP
CM3 ETM ETM
TPIU
TIPU
PC
Cortex-M3 fault
Cortex-M3
handler
ITM
ITM
JTAG
DAP CM3 DAP
TPIU
31
Cortex-M3 2
2.11 Cortex-M3
Cortex-M3
Cortex-M3
2.11.1
Cortex-M3

Thumb-2 32 ARM
16 Thumb
Thumb-2
Cortex-M3
32
Cortex-M3 100MHz
CM3 (CPI) MHz
CM3
2.11.2
240

Cortex-M3 R0-R3, R12, LR, PSR PC

8
NVIC
8

LDMSTM
PUSH POP
NMI
-(safety-critical)NMI

2.11.3
Cortex-M3 0.19mW/MHz
32
Cortex-M3 2
SLEEPING SLEEPDEEP WFI

WFE

CM3
CM3

2.11.4
8051

fault faults
banked
MPU
2.11.5
JTAG
CoreSight

6 4
ETM DWT
fault fault
patch
ITM
33
Cortex-M3 2
34
Cortex-M3 3
Cortex-M3
3.1
CM3 R0-R15 R0-R12
16 R0-R7 32 Thumb-2
3.1.1 R0-R7
R0-R7 32
3.1.2 R8-R12
R8-R12 16 Thumb 32
thumb-2 32
35
Cortex-M3 3
3.1.3
3.1 Cortex-M3
3.1.4 R13
R13 CM3 R13
SPMRS,MSR
MSP SP_main OS

PSP SP_process

ISR
ESR
MSP
36
Cortex-M3 3
PUSH POP SP
PUSH POP

1.2
PUSH POP SP

Cortex-M3 PUSH POP
PUSH {R0} ; *(--R13)=R0R13 long*

POP {R0} ; R0= *R13++
C
Cortex-M3 PUSH
PUSH
POP PUSH PUSH POP
subroutine_1
PUSH {R0-R7, R12, R14} ;
;
POP {R0-R7, R12, R14} ;
BX R14 ;
R13 SPboth MSP PSP

R13/SP MRS/MSR
MSP SP_main
PSP SP_process
37
Cortex-M3 3
PUSH POP 4
0x4,0x8,0xc,R13 0, 0Read As Zero
3.1.5 R14
R14 LR both LR R14LR
BL(Branch and Link) LR
main ;

BL function1 ; function1
; PC= function1 LR=main

Function1
; function1
BX LR ; function1 LR PUSH
;
PC LSB 0LR LSB

0 ARM/Thumb ARM ARM Thumb
CM3 LSB
3.1.6 R15
R15 PC CM3

PC +4
0x1000: MOV R0, PC ; R0 = 0x1004
PC LR CM3
PC LSB 0 PC
PC LSB=1 Thumb
0 ARM CM3 fault
3.2
Cortex-M3
PSRs xPSR
PRIMASK, FAULTMASK, BASEPRI
CONTROL
MSR/MRS
MRS <gp_reg>, <special_reg> ;
38
Cortex-M3 3
MSR <special_reg>, <gp_reg> ;
3.2.1 PSRs PSR

PSRAPSR
PSRIPSR
PSREPSR
MRS/MSR 3 PSRs 2 3
xPSRPSR
3.3 Cortex-M3 xPSR
3.4 (xPSR)
3.2.2 PRIMASK, FAULTMASK BASEPRI

3.2 Cortex-M3

PRIMASK 1
NMI fault 0
FAULTMASK 1 1 NMI
fault 0
BASEPRI 9

00
- PRIMASK BASEPRI
FAULTMASK OS fault
faults fault
FAULTMASK OS
PRIMASK, FAULTMASK BASEPRI MRS/MSR ,
39
Cortex-M3 3
MRS R0, BASEPRI ; BASEPRI R0

MRS R0, FAULTMASK ;
MRS R0, PRIMASK ;
MSR BASEPRI, R0 ; R0 BASEPRI
MSR FAULTMASK, R0 ;
MSR PRIMASK, R0 ;
3

CM3 CPS 4
CPSID I ;PRIMASK=1 ;
CPSIE I ;PRIMASK=0 ;
CPSID F ;FAULTMASK=1, ;
CPSIE F ;FAULTMASK=0 ;
3.2.3 CONTROL
3.3 Cortex-M3 CONTROL

CONTROL[1]
0= MSP
1= PSP
PSP handler

MSP 1
CONTROL[0] 0=
1=
Handler
CONTROL[1]
Cortex-M3 handler CONTROL[1] 0 0 1

LR 2 LR
LR 5
CONTROL[0]

40
Cortex-M3 3
CONTROL MRS MSR

MRS R0, CONTROL
MSR CONTROL, R0
3.3
Cortex-M3 2
3.6
handler
SCS
MRS/MSR APSR
SCS
fault
fault( If a program running at the user access level tries
to access SCS or special registers, a fault exception will occur)Keil MDK
STM32 fault
SCS 0xE000E100
STM32 STM32 faultfault
MDK 3.20
CONTROL[0]
CONTROL[0] handler
handler CONTROL[0]
3.7
CM3
NVIC
MPU
41
Cortex-M3 3

PSP
MSP CM3
8
CONTROL CONTROL[0]=0
3.8
CONTROL[0]=1+both
3.9
CONTROL0
SVC SVC CONTROL[0]
3.4
Cortex-M3 16-4-1=11 240 IRQ
240 SysTick
NVIC 16 32
42
Cortex-M3 3
NVIC NMI NMI

NMI
NMI
3.4 Cortex-M3 fault

NVIC fault fault
3.4 Cortex-M3

0 N/A N/A
1 -3
2 NMI -2 NMI
3 (hard) fault -1 fault fault
PRIMASK BASPRI
fault fault
5 fault Abort

6 (usage)
Fault ARM
7-10 N/A N/A
11 SVCall SVC
12
13 N/A N/A
14 PendSV
pendable request
15 SysTick
16 IRQ #0 #0
17 IRQ #1 #1

255 IRQ #239 #239
7-9
3.5
CM3 (ESR) ESR
CM3 WORD32
ESR
NVIC
0 0
3.5

43
Cortex-M3 3
0 0x00 MSP
1 0x04
2 0x08 NMI
3 0x0C fault
4 0x10 MemManage fault
5 0x14 fault
6 0x18 fault
7-10 0x1c-0x28
11 0x2c SVC
12 0x30
13 0x34
14 0x38 PendSV
15 0x3c SysTick
16 0x40 IRQ #0
17 0x44 IRQ #1
18-255 0x48-0x3FF IRQ #2 - #239
11SVC NVIC 11x4=0x2C
0
MSP
3.6
Cortex-M3 PUSH POP
PUSH POP 9
3.6.1
SP PUSH
POP PUSH POP SP
PUSH PUSH

PUSH POP
PUSH/POP SP /

; R0=X, R1=Y, R2=Z
BL Fx1
Fx1
PUSH {R0 } ; R0 & SP
PUSH {R1} ; R1 & SP
PUSH {R2} ; R2 & SP
; Fx1 R0-R2
44
Cortex-M3 3
POP {R2} ; R2 & SP

POP {R1} ; R1 & SP
POP {R0} ; R0 & SP
BX LR ;
;
;R0=X, R1=Y, R2=Z Fx1 R0-R2
3.10

PUSH POP PUSH/POP

PUSH {R0-R2} ; R0-R2
PUSH {R3-R5,R8, R12} ; R3-R5,R8 R12
POP
POP {R3-R5,R8, R12} ; R3-R5R8 R12
POP {R0-R2} ; R0-R2

push pop

PUSH/POP
PUSH {R0-R3, LR}
POP {R0-R3, PC}
POP PC PUSH LR
LR LR PC LR
PC LR LR

PC
PUSH R13 STMDB POP
R13 LDMIA STMDB/LDMIA
4
3.7 Cortex-M3
Cortex-M3 SP 32
SP 4
45
Cortex-M3 3
3.13 Cortex-M3 PUSH
POP SP SP 4
3.14 Cortex-M3 POP
POP PUSH
ESR CM3 SP
MSP PSP ESR ESR CONTROL[1]
SP
3.7.1 Cortex-M3
CM3 CONTROL[1]
CONTROL[1]=0 MSP handler
3.15 CONTROL[1]=0
CONTROL[1]=1 MSP PSPhandler MSP

OS OS handler
OS
handler MSP
PSP
46
Cortex-M3 3
3.16 CONTROL[1]=1

MRS R0, MSP ; R0
MSR MSP, R0 ; R0
MRS R0, PSP ; R0
MSR PSP, R0 ; R0
PSP OS
STMDB LDMIA
OS PSP
3.8
CM3 32
0x0000,0000 MSP
0x0000,0004 PC LSB 1

3.17
ARM ARM
0 0 CM3 0
MSP
32
47
Cortex-M3 3
3.18 MSP PC
CM3 MSP 1
0x20007C00-0x20007FFF MSP 0x20008000
MSP 2 CM3 Thumb
LSB 1 3.18
0x101 0x100 0x100
MSP 1 NMI faultMSP
MSP
10 20 ARM 19 GCC
48
Cortex-M3 4

Cortex-M3
Cortex-M3
A ARMv7-M
Architecture Application Level Reference Manual(Ref2)
ARM 20 Keil RVMDK
RVMDK
4
4.1
ARM
ARM 19 GCC AS
4.1.1

1, 2, ;

Tab
1
#
MOV R0, #0x12 ; R0 0x12
MOV R1, #A ; R1 A ASCII
;
EQU
NVIC_IRQ_SETEN0 EQU 0xE000E100 ;
NVIC_IRQ0_ENABLE EQU 0x1

LDR R0, =NVIC_IRQ_SETEN0 ; LDR
; PC
MOV R1, #NVIC_IRQ0_ENABLE ; R1
49
Cortex-M3 4
STR R1, [R0] ; *R0=R1 IRQ #0

DCI BKPT 0xBE00
DCI 0xBE00 ; (BKPT) 16

( DCI )
DCB
DCD 32
LDR R3, =MY_NUMBER ; R3= MY_NUMBER
LDR R4, [R3] ; R4= *R3

LDR R0, =HELLO_TEXT ; R0= HELLO_TEXT
BL PrintText ; PrintText R0

MY_NUMBER
DCD 0x12345678
HELLO_TEXT
DCB Hello\n,0
ARM
4.1.2
ARM 4.1

S APSR
ADDS R0, R1 ; APSR
EQ,NE,LT,GT EQ=Euqal, NE= Not Equal, LT= Less Than, GT= Greater Than

BEQ <Label> ; EQ
4
Cortex-M3 B
CM3 IF-THEN IF-THEN
IT S 15
4.1.3
Thumb-2ARM
UAL 16 32
32 Thumb-2 Thumb-2 32 ARM

16 32 Thumb ARM
50
Cortex-M3 4
UAL
ADD R0, R1 ; Thumb
ADD R0, R0, R1 ; UAL R0=R0+R1
UAL Thumb
Thumb APSR S UAL
S
AND R0, R1 ; Thumb
ANDS R0, R0, R1 ; UAL S
Thumb-2 16 32
R0=R0+1 16 32 ADD UAL
16 32
ADDS R0, #1 ; 16
ADDS.N R0, #1 ; 16 NNarrow
ADDS.W R0, #1 ; 32 W=Wide
.W(Wide) 32 16
32 .N
ARM
C C
32 32
32 Thumb-2 ARM 32
0x1000: LDR r0, [r1] ; 16

0x1002: RBIT.W r0 ; 32 0x1002
16 R0-R7
32 Thumb-2 R0-R15 R15(PC)

PC
ARMv7-M
4.2
Cortex-M3 4.2 4.9
ARMv6T2
Cortex-M3 v7
51
Cortex-M3 4

Cortex-M3

APSR 5
N: (Negative)
Z (Zero)
C: /(Carry)
V: (oVerflow)
S: (Saturation)
52
Cortex-M3 4
4.2.1
4.2 16

ADC
ADD
AND
C &
ASR
BIC 0
CMN
CMP
CPY
EOR
LSL 31
LSR
MOV
MUL
MVN NOT
NEG
ORR
ROR
SBC
SUB
TST Z
REV 32
REVH 32 16 16
REVSH 32 16 32
SXTB 32
SXTH 32
UXTB 32
UXTH 32
4.3 16

B
B<cond>
BL LR
BLX #im BLXCM3
CBZ 0
CBNZ 0
53
Cortex-M3 4
IT If-Then
4.4 16

LDR
LDRH
LDRB
LDRSH
LDRSB
STR
STRH
STRB
LDMIA
STMIA
PUSH
POP
16 Thumb v4T
4.5 16

SVC
BKPT

fault
NOP
CPSIE PRIMASK(CPSIE i)/ FAULTMASK(CPSIE f) 0
CPSID PRIMASK(CPSID i)/ FAULTMASK(CPSID f)
4.6 32

ADC
ADD
ADDW 12
AND C |
ASR
BIC
BFC
BFI
54
Cortex-M3 4
CMN
CMP
CLZ
EOR
LSL
LSR
MLA
MLS
MOVW 16 16 16 0
MOV 16 MOVW
MOVT 16 16 16
MVN
MUL
ORR
ORN
RBIT 32 2 180
REV 32
REVH/ 32
REV16
REVSH 32 32
ROR
RRX C C
SFBX 32 32
SDIV
SMLAL 32 64
64
SMULL 32 64
SSAT
SBC
SUB
SUBW 12
SXTB 32
TEQ
TST Z
UBFX
UDIV
UMLAL 32 64
64
UMULL 32 64
USAT
UXTB 32 24 0
55
Cortex-M3 4
UXTH 32 16 0
4.7 32

LDR
LDRB
LDRH
LDRSH 32
LDM
LDRD 64 2
STR
STRB
STRH
STM
STRD 2
PUSH
POP
4.8 32

B
BL
TBB 8
TBH 16
4.9 32
LDREX
LDREXH
LDREXB
STREX
STREXH
STREXB
CLREX LDREX/LDREXH/LDREXB
MRS
MSR
NOP
SEV
WFE
WFI
56
Cortex-M3 4
ISB MPU
DSB MPU cache
DMB MPU cache
4.2.2
Thumb Cortex-M3
4.10
BLX #im BLX ARM Cortex-M3 Thumb

ARM fault
SETEND ARMv6 Cortex-M3
fault
CM3 ARMv7-M ARMv7M Thumb2

CM3 4.11
faultNVIC NOCPNo CoProcessor

4.11
MCR
MCR2
MCRR
MRC
MRC2
MRRC
LDC
STC
CPS PSRs
ARMv6 CM3
4.12 CPS

CPS<IE/ID>.W A CM3 A
57
Cortex-M3 4
CPS.W #mode CM3 PSR mode
hint CM3 NOP
4.13 hint

DBG hint
PLD cache hint CM3 cache
NOP
PLI cache hint CM3 cache
NOP
YIELD
swapped out
4.3
ARM
4.3.1
CM3

MOV R3 R8
MOV R8, R3
MOV MVN
LoadStore
LDR
STR
4.14

LDRB Rd, [Rn, #offset] Rn+offset Rd
LDRH Rd, [Rn, #offset] Rn+offset Rd
LDR Rd, [Rn, #offset] Rn+offset Rd
LDRD Rd1, Rd2, [Rn, #offset] Rn+offset (64 ) Rd1
32 Rd2 32
58
Cortex-M3 4
STRB Rd, [Rn, #offset] Rd Rn+offset

STRH Rd, [Rn, #offset] Rd Rn+offset
STR Rd, [Rn, #offset] Rd Rn+offset
STRD Rd1, Rd2, [Rn, #offset] Rd1 32 Rd2 32
Rn+offset
LDM/STM LDR/STR
4.15
4.15

LDMIA Rd!, {} Rd
Rd 16
STMIA Rd!, {} Rd
Rd 16
LDMIA.W Rd!, {} Rd
Rd 32
LDMDB.W Rd!, {} Rd
Rd 32
STMIA.W Rd!, {} Rd
Rd 32
STMDB.W Rd!, {} Rd Rd 32

CM3 LDM/STM Rd R13 SP

POP/PUSH
(LDMIA->POP, STMDB -> PUSH)
STMDB SP!, {R0-R3, LR} PUSH {R0-R3, LR}
LDMIA SP!, {R0-R3, PC} PUSH {R0-R3, PC}
Rd(I ncrement )D ecrement Rd

(Before)(A fter )/4 R8=0x8000
STMIA.W R8!, {r0-R3} ; R8 0x8010

STMDB.W R8, {R0-R3} ; R8 R8
LDR/STR (Pre-indexing)
LDR STR
LDR.W R0, [R1, #20]! ;
R1+offset R0R1 R1+ 20offset
R1
R0
4.16
59
Cortex-M3 4

LDR.W Rd, [Rn, #offset] ///
LDRB.W Rd, [Rn, #offset] 0
LDRH.W Rd, [Rn, #offset]
LDRD.W Rd1, Rd2, [Rn, #offset]
LDRSB.W Rd, [Rn, #offset] /
LDRSH.W Rd, [Rn, #offset] 32
STR.W Rd, [Rn, #offset] ///
STRB.W Rd, [Rn, #offset]
STRH.W Rd, [Rn, #offset]
STRD.W Rd1, Rd2, [Rn, #offset]
CM3 (Post-indexing)
offset Rd
Rd Rd+offsetoffset
STR.W R0, [R1], #-12 ;
R0 R1 R1 R1+(-12)
[R1]

4.17

LDR.W Rd, [Rn], #offset ///
LDRB.W Rd, [Rn], #offset 0
LDRH.W Rd, [Rn], #offset
LDRD.W Rd1, Rd2, [Rn], #offset
LDRSB.W Rd, [Rn], #offset] /
LDRSH.W Rd, [Rn], #offset] 32
STR.W Rd, [Rn], #offset ///
STRB.W Rd, [Rn], #offset
STRH.W Rd, [Rn], #offset
STRD.W Rd1, Rd2, [Rn], #offset
60
Cortex-M3 4

LDR/STR
CM3 #offset

ldr r2, [r0, r3] ;
ldr r2, [r0], r3 ;
C
ldr r2, [r0, r3, lsl #2]

PUSH/POP
PUSH/POP PC LR
;
PUSH {R0-R3, LR}

;
POP {R0-R3, PC}
LR
MRS/MSR 3 CM3
MRS/MSR
CM3
APSR
CM3
faultMemManage fault
fault OSC
MRS APSR xPSR

C xPSR.30 MRS R0, APSR R0.30=C C
R0.30 C STM32 PSR fault
APSR

32
CM3 MOV/MVN
16 MOV 8
61
Cortex-M3 4
MOV R0, #0x12

32 MOVW MOVT 16
32
MOVW MOVT 32 MOVW MOVT
MOVW 16
LDR Rd, = imm32
LDR, r0, =0x12345678
LDR 32
LDR PC

32 32
LDR Rd, [PC, #offset] offset
LDR offset
LDR offset
literal pool(
LTORG )
LDR vs. ADR

Both LDR ADR LDR
LSB
LDR r0, =address1 ; R0= 0x4000 | 1

address1
0x4000: MOV R0, R1
address1 LSB
LDR R0, =address1 ; 0x4000 R0

address1
0x4000: DCD 0x0 ;0x4000
ADR LSB
ADR r0, address1 ; R0= 0x4000=

address1
0x4000: MOV R0, R1
ADR 0x4000=
LDR PC
ADR PC ADR
ADR LDR 32
ADR LDR
62
Cortex-M3 4
4.3.2
CM3
ADD R0, R1 ; R0 += R1
ADD R0, #0x12 ; R0 += 12
ADD.W R0, R1, R2 ; R0 = R1+R2
ADD
16 APSR .W 32
S APSR
ADD.W R0, R1, R2 ;
ADDS.W R0, R1, R2 ;
ADD CM3 SUB, MUL, UDIV/SDIV 4.18
63
Cortex-M3 4
4.18

ADD Rd, Rn, Rm ; Rd = Rn+Rm
ADD Rd, Rm ; Rd += Rm imm im816 im1232
ADD Rd, #imm ; Rd += imm
ADC Rd, Rn, Rm ; Rd = Rn+Rm+C

ADC Rd, Rm ; Rd += Rm+C imm im816 im1232
ADC Rd, #imm ; Rd += imm+C
ADDW Rd, #imm12 ; Rd += imm12 12

SUB Rd, Rn ; Rd -= Rn
SUB Rd, Rn, #imm3 ; Rd = Rn-imm3
SUB Rd, #imm8 ; Rd -= imm8
SUB Rd, Rn, Rm ; Rd = Rm-Rm
SBC Rd, Rm ; Rd -= Rm+C
SBC.W Rd, Rn, #imm12 ; Rd = Rn-imm12-C
SBC.W Rd, Rn, Rm ; Rd = Rn-Rm-C
RSB.W Rd, Rn, #imm12 ; Rd = imm12-Rn
RSB.W Rd, Rn, Rm ; Rd = Rm-Rn
MUL Rd, Rm ; Rd *= Rm
MUL.W Rd, Rn, Rm ; Rd = Rn*Rm
MLA Rd, Rm, Rn, Ra ; Rd = Ra+Rm*Rn
MLS Rd, Rm, Rn, Ra ; Rd = Ra-Rm*Rn
UDIV Rd, Rn, Rm ; Rd = Rn/Rm
SDIV Rd, Rn, Rm ; Rd = Rn/Rm
CM3 / 64 4.19
4.19 64

SMULL RL, RH, Rm, Rn ;[RH:RL]= Rm*Rn 64
SMLAL RL, RH, Rm, Rn ;[RH:RL]+= Rm*Rn
UMULL RL, RH, Rm, Rn ;[RH:RL]= Rm*Rn 64
SMLAL RL, RH, Rm, Rn ;[RH:RL]+= Rm*Rn
64
Cortex-M3 4
4.20 CM3
4.20
AND Rd, Rn ; Rd &= Rn
AND.W Rd, Rn, #imm12 ; Rd = Rn & imm12
AND.W Rd, Rm, Rn ; Rd = Rm & Rn
ORR Rd, Rn ; Rd |= Rn
ORR.W Rd, Rn, #imm12 ; Rd = Rn | imm12
ORR.W Rd, Rm, Rn ; Rd = Rm | Rn
BIC Rd, Rn ; Rd &= ~Rn
BIC.W Rd, Rn, #imm12 ; Rd = Rn & ~imm12
BIC.W Rd, Rm, Rn ; Rd = Rm & ~Rn
ORN.W Rd, Rn, #imm12 ; Rd = Rn | ~imm12
ORN.W Rd, Rm, Rn ; Rd = Rm | ~Rn
EOR Rd, Rn ; Rd ^= Rn

EOR.W Rd, Rn, #imm12 ; Rd = Rn ^ imm12
EOR.W Rd, Rm, Rn ; Rd = Rm ^ Rn
65
Cortex-M3 4
3 32 3 Rn
DataOp Rd, Rm, Rn, LSL #imm5 ; Rn imm5

DataOp Rd, Rm, Rn, LSR #imm5 ; Rn imm5
DataOp Rd, Rm, Rn, ASR #imm5 ; Rn imm5
DataOp Rd, Rm, Rn, ROR #imm5 ; Rn imm5
DataOp Rd, Rm, Rn, ROL #imm5 ; Rn imm5
DataOp Rd, Rm, Rn, RRX ; Rn
Rn Rn Rn
CM3
4.21
66
Cortex-M3 4
4.21

LSL Rd, Rn, #imm5 ; Rd = Rn<<imm5
LSL Rd, Rn ; Rd <<= Rn
LSL.W Rd, Rm, Rn ; Rd = Rm<<Rn
LSR Rd, Rn, #imm5 ; Rd = Rn>>imm5
LSR Rd, Rn ; Rd >>= Rn
LSR.W Rd, Rm, Rn ; Rd = Rm>>Rn
ASR Rd, Rn, #imm5 ; Rd = Rn imm5

ASR Rd, Rn ; Rd = Rn
ASR.W Rd, Rm, Rn ; Rd = Rm Rn
ROR Rd, Rn ; Rd >> = Rn
ROR.W Rd, Rm, Rn ; Rd = Rm >> Rn
RRX.W Rd, Rn ; Rd = (Rn>>1)+(C<<31)
RRX{S} Rd Rd
( RRX S ) Rn
RRXS.W Rd, Rn ; tmpBit = Rn & 1
; Rd = (Rn>>1)+(C<<31)
; C= tmpBit
S C 16 Thumb
C 4.1
4.1
67
Cortex-M3 4
32
n 32-n
n 32-n

2 1
1
8 16 32
1 0
4.22
4.22

SXTB Rd, Rm ; Rd = Rm 32
SXTH Rd, Rm ; Rd = Rm 32
32 4 2
4.23
4.23

REV.W Rd, Rn
REV16.W Rd, Rn
REVSH.W

4.2
68
Cortex-M3 4
4.2

4.24
4.24

BFC.W Rd, Rn, #<width>
BFI.W Rd, Rn, #<lsb>, #<width>
CLZ.W Rd, Rn 0
RBIT.W Rd, Rn 180
SBFX.W Rd, Rn, #<lsb>, #<width> 32
SBFX.W Rd, Rn, #<lsb>, #<width> 32
4.3.3

B Label ; Label
BX reg ; reg
BX reg ARM(LSB=0) Thumb(LSB=1)

CM3 Thumb reg LSB=1 fault

BL Label ; Label LR
BLX reg ; reg REG LSB
; LR
LRR14BX LR
BLX reg LSB 1
ARM LSB fault
PC MOV LDR
MOV PC, Rn ; Rn
LDR PC, [Rn] ; Rn
POP {,PC} ; PC
;
LDMIA SP!, {, PC} ;POP
PC LSB1

ARM BL

LR
69
Cortex-M3 4
4.3.4
5 4 ARM
4.25
4.25 Cortex-M3 APSR 4

PSR
N 31 N= MSB
Z 30 0 0,
/ 0 Z
C 29 C
C C
v7M
V 28
ADD MSB 1
V
ARM 4
If-Then
C
4 15
4.26
4.26

EQ (EQual) Z==1
NE NotEqual Z==0
CS/HS (CarrySet) C==1

CC/LO (CarryClear) C==0

MI (MInus) N==1
PL N==0
VS V==1
VC V==0
HI C==1 && Z==0
LS C==0 || Z==1
GE N==V
LT N!=V
GT Z==0 && N==V
70
Cortex-M3 4
LE Z==1 || N!=V
AL -
15 AL B
BEQ label ; Z=1

.W Thumb-2 32

BEQ.W label
If-Then
CMP R0, R1 ; R0,R1
ITTET GT ;If R0>R1 ThenTThenEElse
MOVGT R2, R0
MOVGT R3, R1
MOVLE R2, R0
MOVGT R3, R1
IT If-Then
CM3 PSR
16
32 S
CMP/CMN TST/TEQ
PSR/APSR (MSR )
16 16 ADD.N Rd, Rn,
Rm 16 32 S
ADDS.W R0, R1, R2 ; 32 Thumb-2
ADD.W R0, R1, R2 ; 32 Thumb-2
ADD R0, R1 ; 16 Thumb
ADDS R0, #0xcd ; 16 Thumb
UAL
ARM
S UAL
S 16 Thumb
S
CM3
CMP CMP CMP
CMP R0, R1 ; R0-R1

CMP R0, 0x12 ; R0-0x12
CMN CMN CMP
71
Cortex-M3 4

CMN R0, R1 ; R0+R1
CMN R0, 0x12 ; R0+0x12
TST TST AND
CMP
TST R0, R1 ; R0 & R1
TST R0, 0x12 ; R0 & 0x12
TEQ TEQ EOR
CMP
TEQ R0, R1 ; R0 ^ R1
TEQ R0, 0x12 ; R0 ^ 0x12
4.3.5 (barrier)
CM3

race condition

.
MPU

DSB MPU
fault
CM3
CM3 3 4.27
4.27

DMB DMB
(commit)
DSB DMB

ISB

DMB RAM RAM

DMB RAM
DSB DMB
DMB DSB
DMB/DSB ISB

72
Cortex-M3 4
(self-mofifying)
ISB

4.3.6

CM3

MSB
4.3
4.3
4.28
4.28

SSAT.W Rd, #imm5, Rn, {,shift}

SSAT.W Rd, #imm5, Rn, {,shift}

Q
APSR
Q 0 APSR
APSR
73
Cortex-M3 4
Rn
Rn 32

Rn

Rd
#imm5

132 32 12 -2048 2047

SSAT
SSAT{.W} R1, #12, R0
R0 4.29
4.29
(R0) (R1) Q
0x2000(8192) 0x7FF(2047) 1
0x537(1335) 0x537(1335)
0x7FF(2047) 0x7FF(2047)
0 0
0xFFFFE000(-8192) 0xFFFFF800(-2048) 1
0xFFFFFB32(-1230) 0xFFFFFB32(-1230)
32 12 0-4095
USAT
USAT{.W} R1, #12, R0
4.4
4.4
4.30
(R0) (R1) Q
0x2000(8192) 0xFFF(4095) 1
0xFFF(4095) 0xFFF(4095)
0x1000(4096) 0xFFF(4095) 1
0x800(2048) 0x800(2048)
0 0
74
Cortex-M3 4
0x80000000(-2G) 0 1
0xFFFFFB32(-1230) 0 1
4.4 CM3
v6 v7
4.4.1 MRS MSR

ARM
APSR

MRS <Rn>, <SReg> ; Rn
MSR <Sreg>,<Rn> ; Rn
SReg
4.31 MRS/MSR

IPSR
EPSR 0 T CM3 T 1, EPSR

APSR
IEPSR IPSR+EPSR
IAPSR IPSR+APSR
EAPSR EPSR+APSR
PSR xPSR = APSR+EPSR+IPSR
MSP
PSP
PRIMASK
BASEPRI
BASEPRI_MAX BASEPRI
FAULTMASK fault PRIMASK fault
CONTROL
PSP
LDR R0, =0x20008000
MSR PSP, R0
BX LR ; PSP
4.4.2 IF-THEN
IF-THEN(IT) 4
IT T 3 TE T E

T E If-Then
T IT E IT
75
Cortex-M3 4
IT
IT <cond> ; 1 IF-THEN
IT<x> <cond> ; 2 IF-THEN
IT<x><y> <cond> ; 3 IF-THEN
IT<x><y><z> <cond> ; 4 IF-THEN
<x>, <y>, <z>TE <cond> 4.26 AL
17
IT CM3

C if ?:
IT C
if (R0==R1)
{
R3 = R4 + R5;
R3 = R3 / 2;
}
else
{
R3 = R6 + R7;
R3 = R3 / 2;
}

CMP R0, R1 ; R0 R1
ITTEE EQ ; R0 == R1, Then-Then-Else-Else
ADDEQ R3, R4, R5 ;
ASREQ R3, R3, #1 ;
ADDNE R3, R6, R7 ;
ASRNE R3, R3, #1 ;
4.4.3 CBZ CBNZ

CBZ <Rn>, <label>
CBNZ <Rn>, <label>
0-126

while (R0!=0)
{
Function1();
}

Loop
CBZ R0, LoopExit
BL Function1
76
Cortex-M3 4
B Loop
LoopExit:
CBZ/CBNZ
4.4.4 SDIV UDIV

32
SDIV.W Rd, Rn, Rm
UDIV.W Rd, Rn, Rm
Rd= Rn/Rm
LDR r0, =300
MOV R1, #7
UDIV.W R2, R0, R1
R2= 300/7 =44
NVIC DIVBYZERO
fault Rd
4.4.5 REV, REVH,REV16 REVSH
REV 32 REVH
REV Rd, Rm
REVH Rd, Rm
REV16 Rd, Rm
REVSH Rd, Rm
R0=0x12345678
REV R1, R0
REVH R2, R0
REV16 R3, R0
R1=0x78563412R2=0x12347856R3=0x34127856
REVSH REVH R0=0x33448899,

REVSH R1, R0
R1=0xFFFF9988
4.4.6 RBIT
RBIT REV 32
180
RBIT.W Rd, Rn

R1=0xB4E10C23 1011,0100,1110,0001,0000,1100,0010,0011
RBIT.W R0, R1
77
Cortex-M3 4
R0=0xC430872D 1100,0100,0011,0000,1000,0111,0010,1101

4.4.7 SXTB, SXTH, UXTB, UXTH

4 C 32
SXTB Rd, Rn
SXTH Rd, Rn
SXTB Rd, Rn
UXTH Rd, Rn
SXTB/SXTH 32 UXTB/UXTH
R0=0x55aa8765,
SXTB R1, R0 ; R1=0x00000065
SXTH R1, R0 ; R1=0xffff8765
UXTB R1, R0 ; R1=0x00000065
UXTH R1, R0 ; R1=0x00008765
4.4.8 BFC/BFIUBFX/SBFX
CM3 C
BFC 32 2 s 0
BFC.W Rd, #lsb, #width
lsb width lsb

LDR R0, =0x1234FFFF
BFC R0, #4, #10
R0= 0x1234C00F
BFC R0, #27, #9
BFI LSB
BFI.W Rd, Rn, #lsb, #width

LDR R0, =0x12345678
LDR R1, =0xAABBCCDD
BFI.W R1, R0, #8, #16
R1= 0xAA5678DD Rn #lsb Rd
78
Cortex-M3 4
UBFX/SBFX
UBFX.W Rd, Rn, #lsb, #width
SBFX.W Rd, Rn, #lsb, #width
UBFX Rn Rd BFI
LDR R0, =0x5678ABCD
UBFX.W R1, R0, #12,#16
R0=0x0000678A
SBFX
LDR R0, =0x5678ABCD
SBFX.W R1, R0, #8,#4
R0=0xFFFFFFFB
4 #lsb #width
4.4.9 LDRD/STRD
CM3 64 LDRD/STRD 64
LDRD.W RL, RH, [Rn, #+/-offset] {!}; 64

LDRD.W RL, RH, [Rn],#+/-offset ; 64
STRD.W RL, RH, [Rn, #+/-offset] {!}; 64
STRD.W RL, RH, [Rn],#+/-offset ; 64
(0x1000)= 0x1234_5678_ABCD_EF00
LDR R2, =0x1000 ;
LDRD.W R0, R1, [R2]
R0= 0xABCD_EF00, R1=0x1234_5678
STRD 64
STRD.W R1, R0, [R2]
(0x1000)=0xABCD_EF00_1234_5678
4.4.10 TBB,TBH
C switchBasic Select Case
case TBB/TBH
51 MOVC
TBB TBH
TBH
switch switch TBH
CM3
PC +4 TBB 255*2+4=514TBH
65535*2+4=128KB+2Both TBB TBH
79
Cortex-M3 4
TBB
TBB.W [Rn, Rm] ; PC+= Rn[Rm]*2
Rn Rm 4.5
4.5 TBB
Rn R15Rn PC+4
ARM armasm.exe
TBB
TBB.W [pc, r0] ; PC branchtable

branchtable
DCB ((dest0 branchtable)/2) ; 8 DCB
DCB ((dest1 branchtable)/2)
dest0
... ; r0 = 0
dest1
... ; r0 = 1
dest2
... ; r0 = 2
dest3
... ; r0 = 3
TBH TBB 16 Rm
Rn+2*Rm 4.6
80
Cortex-M3 4
4.6 TBH
TBH TBB
TBH.W [pc, r0, LSL #1] ; PC branchtable
branchtable
DCI ((dest0 branchtable)/2) ; 16 DCI
DCI ((dest1 branchtable)/2)
dest0
... ; r0 = 0
dest1
... ; r0 = 1
dest2
... ; r0 = 2
dest3
... ; r0 = 3
81
Cortex-M3 4
82
Cortex-M3 5
5.1
CM3 ARM

CM3 bit-band

CM3 v7M
CM3 both
5.2
CM3 CM3
CM3 NVIC MPU
CM3
(FPB)
(DWT)
(ITM)
(ETM)
(TPIU)
ROM

CM3 4GB, SRAM RAM
83
Cortex-M3 5
4GB
5.1 Cortex-M3
SRAM 512MB SRAM

1MB 32MB
(alias) 8M 8051 128
1MB
512MB 32MB
SRAM
1GB RAM
RAM
84
Cortex-M3 5
0.5GB CM3
s s

AHB CM3 AHB NVIC, FPB, DWT ITM
APB CM3 APB
CM3 APB APB
APB
NVIC SCS SCS NVIC SysTickMPU
5.2
5.2 (SCS)
CM3 MPU

RAM ROM
5.3
CM3 4
(Bufferable)
(Cacheable)
(Executable)
(Sharable)
MPUCM3
RAM
8 512MB
1. 0x0000_0000- 0x1FFF_FFFF WT
Write Through
D-Code System

2. SRAM 0x2000_0000 0x3FFF_FFFF SRAM
WB-WA(Write Back, Write Allocated)

3. (0x4000_0000 0x5FFF_FFFF)
eXecute Never, XNARM
4. RAM 0x6000_0000 - 0x7FFF_FFFF RAM RAM
WB-WA
85
Cortex-M3 5
5. RAM 0x8000_0000 0x9FFF_FFFF(WT)

6. (0xA000_0000 0xBFFF_FFFF)

7. (0xC000_0000 0xDFFF_FFFF)
8. (0xE000_0000 0xFFFF_FFFF)

CM3
MPU

(Write Back)
cache
(Write Through)
cache
C
volatile volatile
(Write Allocate)~
5.4
CM3 NVICMPU
MPU
MPU MPU
MPU MPU regions region
5.1
5.1

0000_0000 1FFF_FFFF
SRAM 2000_0000 3FFF_FFFF
4000_0000 5FFF_FFFF
RAM 6000_0000 9FFF_FFFF
A000_0000 DFFF_FFFF
ITM E000_0000 E000_0FFF
stimulus
DWT E000_1000 E000_1FFF fault
FPB E000_2000 E000_3FFF fault
86
Cortex-M3 5
NVIC E000_E000 E000_EFFF fault

PPB E000_F000 E003_FFFF fault
TPIU E004_0000 E004_0FFF fault
ETM E004_1000 E004_1FFF fault
PPB E004_2000 E004_2FFF fault
ROM E00F_F000 E00F_FFFF fault
E010_0000 FFFF_FFFF
fault
5.5
/ CM3
SRAM 1MB 1MB
RAM
32
5.3A A
87
Cortex-M3 5
5.3B B
0x2000_0000 2
5.4
5.5
5.5
88
Cortex-M3 5
5.6
5.7
30 8051 CM3
8051
CM3

LSB
LSB LSB

0x2000_0000-0x200F_FFFFSRAM 1MB
0x4000_0000-0x400F_FFFF 1MB
SRAM A, n(0<=n<=7)
AliasAddr 0x22000000+((A-0x20000000)*8+n)*4 =0x22000000+ (A-0x20000000)*32 +

n*4
A, n(0<=n<=7)
AliasAddr 0x42000000+((A-0x40000000)*8+n)*4 =0x42000000+ (A-0x40000000)*32 +

n*4
*4 4 *8 8
SRAM 5.2
5.2 SRAM

0x20000000.0 0x22000000.0
0x20000000.1 0x22000004.0
89
Cortex-M3 5
0x20000000.2 0x22000008.0
0x20000000.31 0x2200007C.0
0x20000004.0 0x22000080.0
0x20000004.1 0x22000084.0
0x20000004.2 0x22000088.0
0x200FFFFC.31 0x23FFFFFC.0
5.3

0x40000000.0 0x42000000.0
0x40000000.1 0x42000004.0
0x40000000.2 0x42000008.0
0x40000000.31 0x4200007C.0
0x40000004.0 0x42000080.0
0x40000004.1 0x42000084.0
0x40000004.2 0x42000088.0
0x400FFFFC.31 0x43FFFFFC.0

1. 0x20000000 0x3355AACC
2. 0x22000008 0x20000000 2 1
3. 0x22000008 0 0x20000000
2 0
4. 0x20000000 0x3355AAC8bit[2]
LSB
//
5.5.1
GPIO LED
74HC165,CD4094
I/O
CM3 bit-bangbit-band
bit-bang

90
Cortex-M3 5
ISR
5.8
5.8
ISR
CM3 CM3
5.9
91
Cortex-M3 5
5.9
5.5.2

LDRB/STRB LDRH/STRH
5.5.3 C
C C
LSB C
#define
#define DEVICE_REG0 ((volatile unsigned long *) (0x40000000))
#define DEVICE_REG0_BIT0 ((volatile unsigned long *) (0x42000000))
#define DEVICE_REG0_BIT1 ((volatile unsigned long *) (0x42000004))
...
*DEVICE_REG0 = 0xAB; //
...
*DEVICE_REG0 = *DEVICE_REG0 | 0x2; // bit1
...
*DEVICE_REG0_BIT1 = 0x1; // bit1
92
Cortex-M3 5
//
#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &
0xFFFFF)<<5)+(bitnum<<2))
//
#define MEM_ADDR(addr) *((volatile unsigned long *) (adr))
MEM_ADDR(DEVICE_REG0) = 0xAB; //
MEM_ADDR(DEVICE_REG0)= MEM_ADDR(DEVICE_REG0) | 0x2; //
MEM_ADDR(BITBAND(DEVICE_REG0,1)) = 0x1; //
volatile C
volatile
GCC RealView MDK ( Keil)

volatile unsigned long bbVarAry[7] __attribute__(( at(0x20003014) ));
volatile unsigned long* const pbbaVar= (void*)(0x22000000+0x3014*8*4);
0x20003014 7 32*7=224
long*const
at() 4

pbbaVar[136]=1; // 136

bbaVarAry[224]
bbVarAry[7] 224*4

bbVarAry
volatile
volatile
5.6
CM3
ARM
0 LSB 0
0x1001,0x1002 0x1003 ARM
Data abort CM3 fault
5.12-5.16 5
93
Cortex-M3 5
4 2
5.12 1
5.13 2
5.14 3
5.15 4
5.16 5
CM3 LDR/LDRH/LDRSH
/(LDM/STM)
PUSH/POP
(LDREX/STREX) fault
LSB

94
Cortex-M3 5
ARM
NVIC fault
UNALIGN_TRP
5.7
CM3 SWP ARM SWP
CM3 SWP
ARM SWP SWP

ARM / SWP
/
SWP
master CM3
LDREX/STREX, LDREXH/STREXH,
LDREXB/STREXB// LDREX/STREX
LDREX/STREX
LDREX Rxf, [Rn, #offset]
STREX Rd, Rxf, [Rn, #offset]
LDREX LDR STREX STREX

STREX Rxf (Rn+offset) Rd
0 STREX Rd 1

STREX LDREX LDREX
STR/STREX STREX LDREX
STREX
STREX
STR
STREX
CM3
95
Cortex-M3 5
4GB
LDREX 16 4K
LDREX/STREX

(R0)(R0).5
(R0) 0
MainProgram
;
TryInc1st
LDREX r2, [R0]
ADD r2, #1
; 3 ISREx3
STREX R1, R2, [R0] ; STREX R1=1(R0)=0x20
TryInc2nd
;
LDREX r2, [R0]
ADD r2, #1
STREX R1, R2, [R0] ; STREX R1=0(R0)=0x21

ISREx3
; R0-R3, R12, LR, PC, PSR
LDR R2, [R0]
ORR R2, #0x20
STR R2, [R0] ; ISREx3 (r0) Bit2
BX LR ; R0-R3,R12,LR,PC,PSR
STREX #3
ISREx3(R0)(STR) ISRExt3 STREX
LDREX ISREx3 (R0)
STREX STREX
STR R2=1(R0)=1
(R0)
2
TryInc
LDREX r2, [R0]
ADD r2, #1
STREX R1, R2, [R0]
CMP R1, #1 ; STREX
BEQ TryInc ; STREX
LDREX/STREX LDREX
R0
4 4KB 4GB
96
Cortex-M3 5
STR/STREX
4GB LDREX
LDREX
STREX
STREX STREX
CM3 MPU
(master)
So
LDREX/STREX
LDREXTestRecursive
ldr r3, =N ; N
LoopWrapper
push {r0-r2, lr}
ldr r0, =0x20003000
sub r3, #1
TryInc
ldrex r1, [r0]
add r1, #1
ldr lr, =DoSTREXRcsv
cmp r3, #0
bne LoopWrapper
DoSTREXRcsv
strex r2, r1, [r0]
cmp r2, #1
beq TryInc
pop {r0-r2, pc}
(0x20003000)=0(0x20003000)N N

5.8
CM3 both
CM3
97
Cortex-M3 5
CM3 ARM7 ARM7

CM3 5.4
5.4 CM3
Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0
0x1000 D[7:0] D[15:8] D[23:16] D[31:24]
0x1000 D[7:0] D[15:8] - -
0x1002 D[7:0] D[15:8]
0x1000 D[7:0]
0x1001 D[7:0]
0x1002 D[7:0]
0x1003 D[7:0]
5.5 CM3 AHB

0x1000 D[7:0] D[15:8] D[23:16] D[31:24]
0x1000 D[7:0] D[15:8]
0x1002 D[7:0] D[15:8]
0x1000 D[7:0]
0x1001 D[7:0]
0x1002 D[7:0]
0x1003 D[7:0]
AHB BE-8 lane

ARM7TDMI lane 5.6
5.6 ARM7 AHB

0x1000 D[7:0] D[15:8] D[23:16] D[31:24]
0x1000 D[7:0] D[15:8] - -
0x1002 D[7:0] D[15:8]
0x1000 D[7:0]
0x1001 D[7:0]
0x1002 D[7:0]
0x1003 D[7:0]
CM3
NVIC, FPB
0xE0000000 0xE00FFFFF
So REV/REVH
98
Cortex-M3 6
Cortex-M3

Cortex-M3
Cortex-M3

[] ARM
NVIC
15 16
6.1
Cortex-M3 3 3
6.1
6.1 Cortex-M3
4
3
16CM3
3216
16

CM3ARMv7M4IF-THEN
99
Cortex-M3 6
ThumbPC+4
41632ThumbThumb2

32
penalty
6.2 32
100
Cortex-M3 6
6.2
CM3
6.3 Cortex-M3
MPU ETM CM3 MCU

6.1
6.1

NVIC
SYSTICK Timer
MPU
CM3BusMatrix AHB
AHB to APB AHB APB
SW-DP/SWJ-DP / JTAG
JTAG SWJ-DP
AHB-AP AHB /SWJ AHB
ETM

DWT
ITM
TPIU
101
Cortex-M3 6

FPB Flash
ROM
Cortex-M3 CPU NVIC
CM3CoreCortex-M3
NVICNVIC CM3
NVIC CPU NVIC
CM3 NVIC

SysTick
OS CM3
SysTick
NVIC
MPU CM3
regions regions

BusMatrixBusMatrix CM3 AHB

BusMatrix
(bit-band)
AHB to APB Bridge APB CM3
APB CM3
APB APB APB

SW-DP/SWJ-DPSW-DP/ JTAG SWJ-DP AHB
AHB-AP AHB
JTAG NVIC
AHB SWJ-DP both JTAG SW-DP

AHB-AP AHBCM3
SW-DP/SWJ-DPDAP[ ]

SW-DP/SWJ-DPAHB-APAHB-APAHB
DAP SW-DP/SWJ-DP AHB-AP 15 15.1
ETMETM
CM3 ETM
DAP
DWT DWT

ETM

ITMITM TPIU
102
Cortex-M3 6
printf DWT ITM

TPIUTIPU
CM3 ATBTPIU

FPBFPBflashFlashCPU
FPB FPB
flash
SRAMFlash
Flash
FPBsuch
as adding diagnosis program code to a device that cannot be used in normal situations unless
the FPB is used to change the program control.
ROM
CM3

CM3

CM3
ROM

6.3 Cortex-M3
SoC
hook up
CM3
AHB-Lite APB AMBA 4
6.3.1 I-Code
I-Code AHB-Lite 32 0x0000_0000 0x1FFF_FFFF
16 CPU
16 Thumb
6.3.2 D-Code
D-Code AHB-Lite 32 0x0000_0000 0x1FFF_FFFF
CM3
D-Code
AHB-Lite
6.3.3
AHB-Lite 32 0x2000_0000 0xDFFF_FFFF
103
Cortex-M3 6
0xE010_0000 0xFFFF_FFFF D-Code
6.3.4
APB 32 0xE004_0000 0xE00F_FFFF
APB TPIUETM ROM
0xE004_2000-E00F_F000
6.3.5
APB 32
SWJ-DP SW-DP
15 ARM CoreSight
Technology System Design Guide (Ref 3)
6.4 Cortex-M3
CM3
SoC
Cortex-M3 Technical Reference Manual(TRM)(Ref1) 6.2
6.2

TXEV, RXEV

(SLEEPING, SLEEPDEEP)
ETM
(ETMINTNUM, ETMINTSTATE, CURRPRI)
(SYSRESETREQ) NVIC
(Lockup) (Halted) fault
(LOCKUP, HALTED) NMI

(ENDIAN)
ETM
ITM ATB ATBARM CoreSight

ITM
TPIU
12 Lockup
6.5
CM3 (PPB) PPB (APB)
CoreSight
PADDR31 0 CM3
104
Cortex-M3 6
MPU regions
PPB 32 APB
PPB
6.6
CM3
6.4
6.4 Cortex-M3
(I-Code)
D-Code
AHB SRAM
both I-CodeD-CodeARMAMBAADKADKAMBA
VHDL/Verilog
CM3 CM3
AHB

105
Cortex-M3 6
AHB
flash SRAM
CM3 SRAM SRAM

SRAM CM3
EMI
AHB
AHB
6.4
/
AHB-to-APBI/O
UARTARMIPCM3
6.7
CM3Cortex-M3 Technical Reference
Manual(Ref1)
12
CM3
6.3
6.3 Cortex-M3
assert
nPORESET
NVICMPU
nSYSRESET
nTRST
106
Cortex-M3 6
6.5 Cortex-M3
107
Cortex-M3 6
108
Cortex-M3 7

Fault
SVC PendSV
7.1
Cortex-M3
115 16
240 CM3
CM3 CM3 CM3
CM3
CM3
240
115 7.1 0 16
7.2
7.1

0 N/A N/A
1 -3
2 NMI -2 NMI
3 (hard)fault -1 fault(escalation) fault
FAULTMASK fault Fault
PRIMASK/BASEPRI
FAULTMASK fault
fault fault
5 fault Abort
fault
6 (usage)
109
Cortex-M3 7
Fault ARM
7-10 N/A N/A
11 SVCall SVC
12
13 N/A N/A
14 PendSV
pendable request
15 SysTick
7.2

16 IRQ #0 #0
17 IRQ #1 #1

255 IRQ #239 #239
NVIC VECTACTIVE
IPSR
NVIC
IRQ #
NVIC
(pending) fault
ARM CM3 NVIC
7.2
CM3
CM3
(preempt) 3 NMI fault

CM3 3 256 128
128
CM3
8 16 32
MSB
3 7.1
110
Cortex-M3 7
7.1 3
[4:0] 3
8 0x000x200x400x600x800xA0
0xC0 0xE0

CM3 3 8
3 vs. 4
7.3 3 vs. 4
MSB 4
3 LSB
MSB 7
7 8 MSB 0 15
7 0-6
111
Cortex-M3 7
3 5 8 7.3
7.3 3 5 8
3 5 8
-3 -3 -3 -3
-2 NMI -2 -2 -2
-1 fault -1 -1 -1
0, 0x00, 0x00 0x00,0x01
1, 0x20 0x08 0x02,0x03

0xFF 0xE0 0xF8 0xFE,0xFF
256 128
CM3 256
NVIC 7.5

2
MSB LSB
74
7.4

0 [7:1] [0:0]
1 [7:2] [1:0]
2 [7:3] [2:0]
3 [7:4] [3:0]
4 [7:5] [4:0]
5 [7:6] [5:0]
6 [7:7] [6:0]
7 [7:0]
7.5 (AIRCR)0xE000_ED00

31:16 VECTKEY RW -
0x05FA
0xFA05
15 ENDIANESS R - 1(BE8)0

10:8 PRIGROUP R/W 0
2 SYSRESETREQ W -
112
Cortex-M3 7
1 VECTCLRACTIVE W -
OS
0 VECTRESET W - CM3

L H
H L
1 7
128
CM3 7
CM3
NMI fault

3 [7:5] 5 5
4 2 7.4
7.4 3 5
7.4 7.5
113
Cortex-M3 7
7.5 5
[4:0] 1 8
7.6 7.7
7.6 3 1
114
Cortex-M3 7
7.7 3 1
IRQ #3
IRQ #5 IRQ #3 IRQ #5

AIRCR
7.5
7.3
CM3
CM3 4
4 7.6
115
Cortex-M3 7
7.6
32
0x0000_0000 - MSP
0x0000_0004 1 PC
0x0000_0008 2 NMI
0x0000_000C 3 fault

0 Flash ROM
CM3
RAM RAM
NVIC
0xE000_ED08
2
32 32+16=48
2 64 64*4=256
0x0, 0x100, 0x200 7.7
7.7 (VTOR)0xE000_ED08

7-28 TBLOFF RW 0
29 TBLBASE R - Code 0 RAM 1
MSP

NMI
fault

SRAM
7.4
NMI NMI
NMI CPU
(halted)CPU Lock up NMI
lock up NMI 12
116
Cortex-M3 7
7.8
assert
PRIMASK FAULTMASK
7.9
7.9

7.10
117
Cortex-M3 7
7.10

7.11 CM3 ARM7TDMI
7.11
7.12
118
Cortex-M3 7
7.12
CM3
7.13
7.13 ISR
7.5 Fault
fault CM3 Faults
faults
faults
faults
119
Cortex-M3 7
fault
7.5.1 Faults
AHB (error response)
faults
prefetch abort
/data abort
CM3
PUSH fault
POP fault
(sequence)
fault
AHB
AHB fault
region
SDRAM
SDRAM

faults
fault fault
fault fault
fault fault
fault fault NMI
fault fault fault
12
fault NVIC Handler

BUSFAULTENA fault
fault fault NVIC

fault fault (BFSR) fault
fault
fault BFSR
BFARVALID 1 fault
fault BFAR fault
fault
120
Cortex-M3 7
fault vs. fault

fault fault
fault faults fault

fault
CM3
fault fault
fault
fault

BFSR 8
0xE000_ED28 2
0xE000_ED29 7.8
7.8 fault (BFSR)0xE000_ED29

7 BFARVALID - 0 =1 BFAR
6:5 - - - -
4 STKERR R/Wc 0
3 UNSTKERR R/Wc 0
2 IMPRECISERR R/Wc 0 violation
1 PRECISERR R/Wc 0
0 IBUSERR R/Wc 0
7.5.2 faults
faults MPU MPU
MemManage fault
MPU MemMange fault
MemManage faults
MPU regions

region

MemManage fault
MemManage MemMange
fault MemManage fault fault
fault fault fault NMI
MemManage fault
121
Cortex-M3 7
fault MemManage fault MemManage fault

NVIC handler MEMFAULTENA RAM
MemManage fault
MemManage fault NVIC fault
MFSR MemManage fault DACCVIOL
IACCVIOL MMARVALID
fault NVIC
MMAR
MFSR 8
0xE000_ED28 1
7.9
7.9 fault (MFSR)0xE000_ED28

7 MMARVALID - 0 =1 MMAR
6:5 - - - -
4 MSTKERR R/Wc 0
3 MUNSTKERR R/Wc 0
2 - - - -
1 DACCVIOL R/Wc 0
0 IACCVIOL R/Wc 0
7.5.3 faults
faults
Cortex-M3 fault

Cortex

ARM CM3 ARM fault
ARM
LR /
/
CM3
fault NVIC
fault fault
fault fault
fault fault fault MemManage fault
fault fault fault fault NMI
fault
fault MemManage fault fault
fault NVIC handler USGFAULTENA
RAM fault fault
122
Cortex-M3 7
fault NVIC fault UFSR

fault fault
ARM
fault ARM PC
LSB ARM
BX RnRn LSB=0
LSB=0
POP {,PC} LSB=0
fault UFSR INVSTATE (INValid STATE)
UFSR 7.10 2
0xE000_ED28 0xE000_ED2A FAULT
1
7.10 fault (UFSR)0xE000_ED2A

9 DIVBYZERO R/Wc 0 DIV_0_TRP

8 UNALIGNED R/Wc 0 fault
7:4 - - - -
3 NOCP R/Wc 0
2 INVPC R/Wc 0 EXC_RETURN
PC
EXC_RETURN The return PC
PC

1 INVSTATE R/Wc 0 ARM
0 UNDEFINSTR R/Wc 0
7.5.4 fault
fault fault fault fault
fault escalation fault
fault fault NVIC
fault HFSR fault
fault fault
HFSR 7.11
7.11 fault 0xE000_ED2C

123
Cortex-M3 7

31 DEBUGEVT R/Wc 0 fault
30 FORCED R/Wc 0 fault
fault fault fault
29:2 - - - -
1 VECTBL R/Wc 0 fault
0 - - - -
7.5.5 faults
fault
E faults
Faults
fault
RTOS
fault
fault
NVIC VECTRESET
CM3
SYSRESETREQ
fault
RTOS
fault (FSRs)Fault
fault fault
fault fault fault
FSRs 1
FSR fault
7.6 SVC PendSV
SVC PendSV
SVC
SVC
SVC SVC

OS
OS
SVC
124
Cortex-M3 7
SVC
API
SVC
7.14
7.14 SVC
SVC SVCSVC
SVC 0x3 ; 3
SVC SVC
SVC SVC
PSP MRS Rn, PSP
LR SVC 8

SVC vs. SWI

ARM ARM7
SWI SVC SWI
CM3
ARM7 CM3

CM3 SVC SVC

fault NMI
SVC fault
PendSV SVC SVC

SVC SVC
fault SVC
PendSV
SVC OS
PendSV NVIC PendSV 1
PendSV
125
Cortex-M3 7

SYSTICK

SysTick 7.15
7.15 SysTick
SysTick
SysTick ISROS
CM3 OS
fault
7.16 IRQ
OS
IRQ SysTick
SysTick SysTick

PendSV PendSV
ISR PendSV
126
Cortex-M3 7
OS IRQ SysTick PendSV

7.17
7.17 PendSV

1. A SVC
2. OS PendSV
3. CPU SVC PendSV
4. PendSV B
5.
6. ISR SysTick ISR
7. OS PendSV
8. SysTick ISR ISR
9. ISR PendSV
10. PendSV A
127
Cortex-M3 7
128
Cortex-M3 8
NVIC
NVIC

SysTick
8.1 NVIC
NVIC Cortex-M3
CM3 NVIC CM3
NVIC
NVIC MPUSysTick
NVIC MPU
NVIC 1 240 IRQs

NVIC NMINMI
NMI
NVIC 0xE000_E000 NVIC /
MRS/MSR CPS
8.2
NVIC

PRIMASK, FAULTMASK BASEPRI

129
Cortex-M3 8
8.3

CM3 240 (SETENA /CLRENA )
240 8 32
1 SETENA 1 CLRENA
0
1
0 0
--
SETENA CLRENA 240 32 8
SETENA0, SETENA1SETENA7 8.1
32
SETENA0/CLRENA0 SETENA/CLRENA //
16 0 16 7 7.2
8.1 SETENA/CLRENA
SETENAs: xE000_E100 0xE000_E11C ; CLRENAs:0xE000E180 - 0xE000_E19C

SETENA0 R/W 0xE000_E100 0 0-31 32
[n]#n 16+n
SETENA1 R/W 0xE000_E104 0 32-63 32

SETENA7 R/W 0xE000_E11C 0 224-239 16
CLRENA0 R/W 0xE000_E180 0 0-31 32

[n]#n 16+n
CLRENA1 R/W 0xE000_E184 0 32-63 32

CLRENA7 R/W 0xE000_E19C 0 224-239 16
8.4

(SETPEND)
(CLRPEND)
8 /
130
Cortex-M3 8
8.2
8.2 SETPEND/CLRPEND
SETPENDs:0xE000_E200 0xE000_E21C ; CLRPENDs:0xE000E280 - 0xE000_E29C

SETPEND0 R/W 0xE000_E200 0 0-31 32
[n]#n 16+n
SETPEND1 R/W 0xE000_E204 0 32-63 32

SETPEND7 R/W 0xE000_E21C 0 224-239 16
CLRPEND0 R/W 0xE000_E280 0 0-31 32

[n]#n 16+n
CLRPEND1 R/W 0xE000_E284 0 32-63 32

CLRPEND7 R/W 0xE000_E29C 0 224-239 16
8.4.1
8 CM3
3 4 32
/
D D.18
8.3 0xE000_E400 0xE000_E4EF

PRI_0 R/W 0xE000_E400 08 #0
PRI_1 R/W 0xE000_E401 08 #1

PRI_239 R/W 0xE000_E4EF 08 #239
131
Cortex-M3 8
8.3B 0xE000_ED18 0xE000_ED23

0xE000_ED18 PRI_4 fault
0xE000_ED1A PRI_6 fault
0xE000_ED1B - - - -
0xE000_ED1C - - - -
0xE000_ED1D - - - -
0xE000_ED1E - - - -
0xE000_ED1F PRI_11 SVC
0xE000_ED20 PRI_12
0xE000_ED21 - - - -
0xE000_ED22 PRI_14 PendSV
0xE000_ED23 PRI_15 SysTick
8.4.2
ISR
1 ISR ISR
1 ISR
//
8.4
8.4 ACTIVE 0xE000_E300_0xE000_E31C
ACTIVE0 RO 0xE000_E300 0 0-31 32

[n] #n 16+n
ACTIVE1 RO 0xE000_E304 0 32-63 32

132
Cortex-M3 8
ACTIVE7 RO 0xE000_E31C 0 224-239 16

8.4.3 PRIMASK FAULTMASK

PRIMASK NMI fault 0
MRS MSR
1.
MOV R0, #1
MSR PRIMASK, R0
2.
MOV R0, #0
MSR PRIMASK, R0
CPS
CPSID i ;
CPSIE i ;
FAULTMASK-1fault
PRIMASKFAULTMASK
NMINMI
NMI
NMI
8.4.4 BASEPRI

BASEPRI
BASEPRI0BASEPRI
0x60
MOV R0, #0x60
MSR BASEPRI, R0
BASEPRI
MOV R0, #0
MSR BASEPRI, R0
BASEPRI_MAXBASEPRI
BASEPRI
BASEPRI_MAX
MOV R0, #0x60

MSR BASEPRI_MAX, R0 ; 0x60
MOV R0, #0xf0
133
Cortex-M3 8
MSR BASEPRI_MAX, R0 ; 0xf0 0x60

MOV R0, #0x40
MSR BASEPRI_MAX, R0 ;Ok 0x40
BASEPRI
0xf0BASEPRIBASEPRI
BASEPRI
3BASEPRI0x00, 0x20, 0x40,
0x60, 0x80, 0xA0, 0xC00xE0
8.4.5
faultfaultfault
Handler(SHCSR)0xE000_ED24
faults8.5
8.5 HandlerSHCSR0xE000_ED24

18 USGFAULTENA R/W 0 fault
17 BUSFAULTENA R/W 0 fault
16 MEMFAULTENA R/W 0 fault
15 SVCALLPENDED R/W 0 SVC SVC

14 BUSFAULTPENDED R/W 0 fault
13 MEMFAULTPENDED R/W 0 fault
12 USGFAULTPENDED R/W 0 fault
11 SYSTICKACT R/W 0 SysTick
10 PENDSVACT R/W 0 PendSV
9 - - - -
8 MONITORACT R/W 0 Monitor
7 SVCALLACT R/W 0 SVC
6:4 - - - -
3 USGFAULTACT R/W 0 fault
2 - - - -
1 BUSFAULTACT R/W 0 fault
0 MEMFAULTACT R/W 0 fault

CM3
fault
Cortex-M3 Technical Reference Manual, pg8-29
134
Cortex-M3 8
fault
ICSRNMISysTickPendSV
8.6
8.5 ICSR0xE000_ED04

31 NMIPENDSET R/W 0 1 NMI NMI
NMI
28 PENDSVSET R/W 0 1 PendSV PendSV

27 PENDSVCLR W 0 1 PendSV
26 PENDSTSET R/W 0 1 SysTick PendSV

25 PENDSTCLR W 0 1 SysTick
23 ISRPREEMPT R 0 =1

22 ISRPENDING R 0 1= NMI
21:12 VECTPENDING R 0 ISR

11 RETTOBASE R 0 (base level)
1

fault
0
9:0 VECTACTIVE R 0 ISR
ISRNMI
fault

16,
/
8.5

1. 071
2. faultNMI
3.
4.
135
Cortex-M3 8
ROM
5.
6.

LDR R0, =0xE000ED0C ;
LDR R1, =0x05FA0500 ; 5 (2/6)
STR R1, [R0] ;
...
MOV R4, #8 ; ROM
LDR R5, =(NEW_VECT_TABLE+8)
LDMIA R4!, {R0-R1} ; NMI fault
STMIA R5!, {R0-R1} ;

...
LDR R0, =0xE000ED08 ;
LDR R1, =NEW_VECT_TABLE
STR R1, [R0] ;
...
LDR R0, =IRQ7_Handler ; IRQ #7
LDR R1, =0xE000ED08 ;
LDR R1, [R1]
ADD R1, R1,#(4*(7+16)); IRQ #7
STR R0, [R1] ; IRQ #7

...
LDR R0, =0xE000E400 ;
MOV R1, #0xC0
STRB R1, [R0,#7] ; IRQ #7 0xC0
...
LDR R0, =0xE000E100 ; SETEN
MOV R1, #(1<<7) ; IRQ #7
STR R1, [R0] ; IRQ #7

MSP

ROM
ROM00,
ROM3
1.
2.
3.
I/O

136
Cortex-M3 8
CM3NVIC
32 8.7SETENA
SETENA10
10 SETPEND
8.7 ICTR0xE000_E004

4:0 INTLINESUM R - 32
0=1 32
1=33 64
2=65 96

0xFFMSB13
0xE0
8.6
SETPEND
STIR8.8
8.8 STIR0xE000_EF00

8:0 INTID W - INTID
8 IRQ #8
NMIfaultsPendSV
NVICNVIC(0xE000_ED14)
1USERSETMPENDNVICSTIR
8.7 SysTick
SysTickNVICSysTick15
137
Cortex-M3 8
Cortex-M3CM3
CM3FCLKCM3
CM3STCLKSTCLK
SysTickCM3
CM3CM3
SysTick
4SysTick8.98.12
8.9 SysTick0xE000_E010

16 COUNTFLAG R 0 SysTick
0 1

2 CLKSOURCE R/W 0 0=(STCLK)
1=(FCLK)
1 TICKINT R/W 0 1=SysTick 0 SysTick

0= 0
0 ENABLE R/W 0 SysTick

23:0 RELOAD R/W 0

23:0 CURRENT R/Wc 0
SysTick
COUNTFLAG
8.10 SysTick0xE000_E01C

31 NOREF R - 1=STCLK
0=
30 SKEW R - 1= 10ms
0= 10ms
23:0 TENMS R/W 0 10ms
Cortex-M3

138
Cortex-M3 8
CM3
SysTickTENMS
10ms SysTickSysTick
TENMSCM3
TENMSCM3TENMS
SysTick
haltSysTick
139
Cortex-M3 8
140
Cortex-M3 9

/

faults
9.1
CM3
8

MSP/PSPSPLRPC
9.1.1
xPSR, PC, LR, R12R3-R0
PSPPSP
MSP
SPN9.1AHB
9.19.13
141
Cortex-M3 9
9.1

SP (N-0) -

(N-4) xPSR 2
(N-8) PC 1
(N-12) LR 8
(N-16) R12 7
(N-20) R3 6
(N-24) R2 5
(N-28) R1 4
SP (N-32) R0 3
9.1
Cortex-M3 r2p0
r2p0
SP89.19.1
SP8
4PCN-8N-12

8exception
stack frameCM32
2
AAPCSCM31
1NVIC
STKALIGN
12
CM3PCxPSR
PC
xPSRIPSR
R0-R3R12R4-R11ARM
CC/C++ Procedure Call Standard for the ARM ArchitectureAAPCS,
Ref5C
142
Cortex-M3 9
R4-R11push
ISR
R0-R3, R12
SPLDMLDM
R0-R3, R12
R0-R3SVCPendSV
9.1.2
I-Code
9.1.3

SPPSPMSPMSP

PSRIPSRPSR
PCPC
LRISRLREXC_RETURN
LREXC_RETURN
4149.39.4
NVIC
9.2

3
9.2LREXC_RETURN
9.2
BX <reg> LREXC_RETURNBX LR
POP {PC} LRPOP

LREXC_RETURNPC
POP {,PC}

LDRLDM PC
143
Cortex-M3 9
8051reti CM3
EXC_RETURNPCC
__interrupt

1.
2. NVIC
9.3
CM3NVIC
(wrapper code)
NVICCM3
832
ISR
SVCSVC
fault
9.4
CM3Tail-Chaining

POP
POPPUSHCPU
CM3POPPUSH
9.2
144
Cortex-M3 9
9.2
9.2B ARM7TDMI
9.5
CM3CM3
#1#2#2
ISR #29.3#2
ISR #132
ISR #2ISR #1
145
Cortex-M3 9
9.3
9.6
LREXC_RETURN
281[3:0]9.3PC
LRCM3
9.3 EXC_RETURN

[31:4] EXC_RETURN1
3 0=Handler
1=
2 0=MSP
1=PSP
1 0
0 0=ARM
1=ThumbCM31
9.3EXC_RETURN39.4
9.4 EXC_RETURN
EXC_RETURN
0xFFFF_FFF1 handler
0xFFFF_FFF9 (SP=MSP)
0xFFFF_FFFD (SP=PSP)
MSPLR=0xFFFF_FFF9
LR
PSPLR=0xFFFF_FFFD
146
Cortex-M3 9
LR
9.4 LREXC_RETURN
HandlerLR=0xFFFF_FFF1LR
ISRLR0xFFFF_FFF19.5
9.5 LREXC_RETURN
147
Cortex-M3 9
EXC_RETURN0xFFFF_FFF0-0xFFFF_FFFF
CM3
9.7

CM3
1212
CM3
6
LDRD/STRD
(LDM/STM)
CM3
LDM/STM
LDR/STRCM3LDM/STM
LDR/STR
CM3xPSRICILDM/STM
xPSRCM3ICI bits
LDM/STM
IF-THEN(IT)
xPSRICICunionboth ICI bitsIT
EPSRIF-THENLDM/STMLDM/STM
LDM/STM
xPSR
(outstanding)
fault
9.8 faults
Faults
faults
148
Cortex-M3 9
9.8.1
fault
faultfaultfault
fault
(stacking error)fault(BFSR
0xE000_ED29)STKERR4
MPUfaultMemFault
faultfault(MFSR
:0xE000_ED28)MSTKERR4fault
fault
9.8.2
fault
faultfault
fault
unstacking errorBFSR.3UNSTKERR
MPUMemManage faultMFSR.3MUNSTKERR
MemManage faultfault
9.8.3
faultfault
MPUfaultHFSR
0xE000_ED2CVECTTBL1
9.8.4
LREXC_RETURN9.4ARM
faultfaultfaultFault(UFSR,0xE000_ED2A)
INVPC2INVSTATE1
149
Cortex-M3 9
150
Cortex-M3 10
10
Cortex-M3

C

10.1
CM3 C
C C C

19 20
10.1.1

bug
C
NMI

10.1.2 C
CC
151
Cortex-M3 10
main
RealViewRVDS KEIL RealView(RVMDK)

ARMGNU19
CodeSourcery GNU
C
C
CARMThumb-2
RealView C3.0
Thumb-2C
__asm void SetFaultMask(unsigned int new_value)

{
//
MSR FAULTMASK, new_value // new_valueFAULTMASK
BX LR //
}
RealView C RVCT 3.0 Compiler and Library
Guide(Ref6)
CM3
MRS/MSR WFI/WFE
ARM ARM/Thumb interworking

CM3 Thumb
C CM3 NVIC
STKALIGN
#define NVIC_CCR ((volatile unsigned long *)(0xE000ED14))

*NVIC_CCR *NVIC_CCR | 0x200; //STKALIGN
AAPCS 12
10.2 C
C
C GNU
C
C

ARMARM Architecture Procedure
Call Standard(AAPCS, Ref5)
R0-R3
R0R12R0
152
Cortex-M3 10
R0-R3R129PUSHR4-R11
PUSHPOP
R0-R3, R12C
R0-R3, R12
R4-R11R0-R3,R12PUSHC
POPR4-R11
AAPCS
10.3
CM3

CARMRVDSRealView
RVCT10.1
10.1 ARM
RVDS(IDE)
ARMwww.arm.com
10.4
C
CM3C
ARM(armasm)
STACK_TOP EQU 0x20002000 ; SP

AREA |Header Code|, CODE
153
Cortex-M3 10
DCD STACK_TOP ; MSP

DCD Start ;
ENTRY ;
Start ;
;
MOV r0, #10 ;
MOV r1, #0 ;
; 10+9+8+...+1
loop
ADD r1, r0 ; R1 += R0
SUBS r0, #1 ; R0S
BNE loop ; if (R0!=0) goto loop;
; R1
deadloop
B deadloop ;
END ;
SPPC
ARM
$> armasm --cpu cortex-m3 -o test1.o test1.s
-otest1.o
ELF
$> armlink --rw_base 0x20000000 --ro_base 0x0 --map -o test1.elf test1.o

--ro_base 0x0ROM0
--rw_base 0x200000000x20000000
RAM
--map

$> fromelf --bin --output test1.bin test1.elf

$> fromelf -c --output test1.list test1.elf

ELF
10.5

LED
UARTWindows
CM3UARTCM3
UARTUART
154
Cortex-M3 10
UARTUART
MAX3232I/ORS-232
UARTCM3
SemihostingNVIC
Semihostingprintf15
Cprintf
STDOUT15
CM3
TPAUARTITMprintf
UART
CM3TPIU
SWV TPAITM
SWV

10.5.1 Hello World

UART
retargeting
~

UART0_BASE EQU 0x4000C000
UART0_FLAG EQU UART0_BASE+0x018
UART0_DATA EQU UART0_BASE+0x000
Putc ; UART
; R0 =
PUSH {R1,R2, LR} ;
LDR R1, =UART0_FLAG
PutcWaitLoop
LDR R2, [R1] ;
TST R2, #0x20 ;
BNE PutcWaitLoop ; UART
LDR R1, =UART0_DATA ; UART
STRB R0, [R1] ;
POP {R1,R2, PC} ;
UART
UARTUART
UART
20

155
Cortex-M3 10
Puts ; UART
; R0 =
; C
PUSH {R0 ,R1, LR} ;
MOV R1, R0 ; R1Putc
; R0
PutsLoop
LDRB R0, [R1], #1 ;
CBZ R0, PutsLoopExit ;
BL Putc ; UART
B PutsLoop ;
PutsLoopExit
POP {R0, R1, PC} ;
PutsHello World
UART0_BASE EQU 0x4000C000
UART0_FLAG EQU UART0_BASE+0x018
UART0_DATA EQU UART0_BASE+0x000
AREA | Header Code|, CODE
DCD STACK_TOP ; MSP
DCD Start ;
ENTRY
Start ;
MOV r0, #0 ;
MOV r1, #0
MOV r2, #0
MOV r3, #0
MOV r4, #0
BL Uart0Initialize ; UART0
LDR r0, =HELLO_TXT ; R0
BL Puts
deadend
B deadend ;
;-------------------------------------------------------------
;
;-------------------------------------------------------------
Puts ; UART
; R0 =
; C
PUSH {R0 ,R1, LR} ;
MOV R1, R0 ; R1Putc
; R0
PutsLoop
156
Cortex-M3 10
LDRB R0, [R1], #1 ;

CBZ R0, PutsLoopExit ;
BL Putc ; UART
B PutsLoop ;
PutsLoopExit
POP {R0, R1, PC} ;
;-------------------------------------------------------------
Putc ; UART
; R0 =
PUSH {R1,R2, LR} ;
LDR R1, =UART0_FLAG
PutcWaitLoop
LDR R2, [R1] ;
TST R2, #0x20 ;
BNE PutcWaitLoop ; UART
LDR R1, =UART0_DATA ; UART
STRB R0, [R1] ;
POP {R1,R2, PC} ;
;-------------------------------------------------------------
Uart0Initialize
;
BX LR ;
;-------------------------------------------------------------
HELLO_TXT
DCB Hello world\n,0 ; Hello world
END ;
CM3
Uart0InitializePutcPutcPuts
16
PutHex ; 16
; R0=
PUSH {R0-R3,LR}
MOV R3, R0 ; R0R3R0Putc
MOV R0, #0 ; 0x
BL Putc
MOV R0, #x
BL Putc
MOV R1, #8 ;
MOV R2, #28 ;
PutHexLoop
ROR R3, R2 ; 284
157
Cortex-M3 10
AND R0, R3, #0xF ; 44

CMP R0, #0xA ; ASCII
ITE GE
ADDGE R0, #55 ; 10,A-F
ORRLT R0, #0x30 ; 0-9ADDLT
BL Putc ; hex
SUBS R1, #1 ;
BNE PutHexLoop ; 08
POP {R0-R3,PC} ;

10
32CM3
0x7B(123)321
Puts
C
PutDec ; 10
; R0=
; 320xffff_ffff101011
PUSH {R0-R5, LR} ;
MOV R3, SP ; R3
SUB SP, SP, #12 ; 11
MOV R1, #0 ; NULL
STRB R1, [R3, #-1]! ; NULL
;
MOV R5, #10 ; R5

PutDecLoop
UDIV R4, R0, R5 ; R4 = R0 / 10
MUL R1, R4, R5 ; R1 = R4 * 10
SUB R2, R0, R1 ; R2 = R0-(R0/10)*10
ADD R2, 0x30 ; ASCIIR20-9ORR
STRB R2, [R3, #-1]! ; ascii
MOVS R0, R4 ; R0 =
BNE PutDecLoop ; 10
MOV R0, R3 ; R0
BL Puts ; Puts
ADD SP, SP, #12 ; SP
POP {R0-R5, PC} ;

158
Cortex-M3 10
10.6
/
0x2000_0000(SRAM)

$> armlink --rw_base 0x20000000 --ro_base 0x0 --map -o test1.elf test1.o

AREA |Header Code|, CODE
DCD STACK_TOP ; MSP
DCD Start ;
ENTRY ;
Start ;
;
MOV r0, #10 ;
MOV r1, #0 ;
; 10+9+8+...+1
loop
ADD r1, r0 ; R1 += R0
SUBS r0, #1 ; R0S
BNE loop ; if (R0!=0) goto loop;
; R1
LDR r0, =MyData1
STR r1, [r0] ;MyData1
deadloop
B deadloop ;
;
AREA | Header Data|, DATA
ALIGN 4
MyData1
DCD 0 ; Destination of calculation result
MyData2
DCD 0
END ;
DATA/MyData1
0x2000_0000
10.7

159
Cortex-M3 10
DeviceALockedR/WA
A
ADeviceALocked1A
ADeviceALockedA
A
1DeviceALocked1
22
A2A11
AAA
AA
DeviceALocked5STREX
#1#2STREX#1
STREX11A
10.3
10.3

STREX
LockDeviceA
; A
; R0=0R0=1
; DeviceALocked1
160
Cortex-M3 10
PUSH {R1, R2, LR}

TryToLockDeviceA
LDR R1, =DeviceALocked
LDREX R2, [R1] ;
CMP R2, #0 ;
BNE LockDeviceAFailed
DeviceAIsNotLocked
MOV R0, #1 ; A
STREX R2, R0, [R1] ;
CMP R2, #0
BNE LockDeviceAFailed ; STREXA
LockDeviceASucceed
MOV R0, #0 ;
POP {R1, R2, PC} ;
LockDeviceAFailed
MOV R0, #1 ;
POP {R1, R2, PC} ;
1
ISR
PRIMASK

CM3
10.8
locked transfers
CM3C

--
10.4
161
Cortex-M3 10
10.4
10.4
10.9
4UBFXTBB/TBH
162
Cortex-M3 10
10.5
DecodeA
LDR R0,=A ; A
LDR R0, [R0]
UBFX R1, R0, #6, #2 ; R1=R0[7:6]
TBB [PC, R1]
BrTable1
DCB ((P0 -BrTable1)/2) ; A[7:6] = 00 P0
DCB ((DecodeA1-BrTable1)/2) ; A[7:6] = 01 DecodeA1
DCB ((P1 -BrTable1)/2) ; A[7:6] = 10 P1
DCB ((DecodeA2-BrTable1)/2) ; A[7:6] = 10 DecodeA2
DecodeA1
UBFX R1, R0, #3, #2 ; R1=R0[4:3]
TBB [PC, R1]
BrTable2
DCB ((P2 -BrTable2)/2) ; A[4:3] = 00 P2
DCB ((P3 -BrTable2)/2) ; A[4:3] = 01 P3
DCB ((P4 -BrTable2)/2) ; A[4:3] = 10 P4
DCB ((P4 -BrTable2)/2) ; A[4:3] = 11 P4
DecodeA2
TST R0, #4 ; UBFX
BEQ P5
B P6
P0 ... ; P0
P1 ... ; P1
P2 ... ; P2
P3 ... ; P3
P4 ... ; P4
P5 ... ; P5
P6 ... ; P6
Cswitch
TBH
163
Cortex-M3 10
164
Cortex-M3 11
11

/

SVC
SVC
C SVC
NMIFaultsSVCPendSVIRQ #0, IRQ #1

CM3 /
CM3
11.1
CM3 NVIC
/ NVIC
11.1.1
MSP
MSP

8 32 ISR
CM3 SP SP
SRAM
11.1
165
Cortex-M3 11
10.1
10.1
11.1.2

ROM

fault NMI SVC
166
Cortex-M3 11
; IRQ=+16
; R0=
; R1=
PUSH {R2, LR}
LDR R2, =0xE000ED08 ;
LDR R2, [R2] ;
STR R1, [R2, R0, LSL #2] ; VectTblOffset+ExcpType*4
; ExcpType*4
POP {R2, PC} ; Return
11.1.3
0NMIfault
-2-1
; IRQ #40xC0
LDR R0, =0xE000E400 ;
LDR R1, =0xC0 ;
STRB R1, [R0, #4] ; IRQ #4
CM338
0xFF1
RBITCLZ
;
LDR R0, =0xE000E400 ; IRQ #0
LDR R1, =0xFF
STRB R1, [R0] ; 0xFF
LDRB R1, [R0] ; 30xE0
RBIT R2, R1 ; LSB
CLZ R1, R2 ; 315
MOV R2, #8
SUB R2, R2, R1 ;
MOV R1, #0x0
STRB R1, [R0] ;
3
0x00, 0x20, 0x40, 0x60, 0x80, 0xA0, 0xC00xE0CM3
3
faults
NMI
11.1.4

1. RAMRAM
167
Cortex-M3 11
(DSB)4

2.

UART
NVIC(SETENA/CLRENA)
10
--
SETENACLRENA
1.
; IRQ
EnableIRQ
; R0=
PUSH {R0-R2, LR}
AND.W R1, R0, #0x1F ; IRQ
MOV R2, #1
LSL R2, R2, R1 ; = (0x1 << (N & 0x1F))
AND.W R1, R0, #0xE0 ; IRQ>31
LSR R1, R1, #3 ; = (N/32)*4IRQ
LDR R0, =0xE000E100 ; SETENA
STR R2, [R0, R1] ;
POP {R0-R2, PC} ;
2.

DisableIRQ
; R0=
PUSH {R0-R2, LR}
MOV R2, #1
LSL R2, R2, R1 ; = (0x1 << (N & 0x1F))
AND.W R1, R0, #0xE0 ; IRQ>31
LSR R1, R1, #3 ; = (N/32)*4IRQ
LDR R0, =0xE000E180 ; CLRENA
STR R2, [R0, R1] ;
POP {R0-R2, PC} ;
NVIC
NVIC//

/--
168
Cortex-M3 11
11.2 /
CM3CARM7
CM3
ISR
irq1_handler
;
...
; IRQ
...
;
BX LR
ISRR4-R11CM3
PUSH
irq1_handler
PUSH {R4-R11, LR} ;
;
...
; IRQ
...
;
POP {R4-R11, PC}
POPPOP
ISR
ARM7 []
CM3
NVIC
NVIC
ISR
ARM7
11.3

NVIC8
NVICSTIR8
169
Cortex-M3 11
SVC
NVICUSERSETMPENDSTIR
DD.17
SVC
ISR
NVIC STIR

DSB
MOV R0, #SOFTWARE_INTERRUPT_NUMBER
LDR R1,=0xE000EF00 ; NVIC
STR R0, [R1] ;
DSB ;
...

USERSETMPEND
SVC
11.4
7
NMIfault
SRAMSRAM
STACK_TOP EQU 0x20002000 ; MSP

NVIC_SETEN EQU 0xE000E100 ; SETENA
NVIC_VECTTBL EQU 0xE000ED08 ;
NVIC_AIRCR EQU 0xE000ED0C ;
NVIC_IRQPRI EQU 0xE000E400 ;
AREA | Header Code|, CODE

DCD STACK_TOP ; MSP
DCD Start ;
DCD Nmi_Handler ; NMI
DCD Hf_Handler ; fault
170
Cortex-M3 11
ENTRY
Start ;
;
MOV r0, #0
MOV r1, #0
...
;
LDR r0, =0
LDR r1, =VectorTableBase
LDMIA r0!, {r2-r5} ; 4MSP, Reset, NMI, fault
STMIA r1!, {r2-r5}
DSB ;
;
LDR r0, =NVIC_VECTTBL
LDR r1, =VectorTableBase
STR r1, [r0]
...
;
LDR r0, =NVIC_AIRCR
LDR r1, =0x05FA0500 ; 52
STR R1, [r0]
; IRQ0
MOV r0, #0 ; IRQ#0
LDR r1, =Irq0_Handler
BL SetupIrqHandler
; IRQ #0
LDR r0, =NVIC_IRQPRI
LDR r1, =0xC0 ; IRQ#0
STRB r1, [r0,#0] ;
DSB ;
MOV r0, #0 ; IRQ #0
BL EnableIRQ
...
;------------------------
;
SetupIrqHandler
; R0 = IRQ
; R1 = IRQ
PUSH {R0, R2, LR}
LDR R2, =NVIC_VECTTBL ;
LDR R2, [R2]
ADD R0, #16 ; = IRQ + 16
171
Cortex-M3 11
LSL R0, R0, #2 ; 4 (4)

ADD R2, R0 ;
STR R1, [R2] ;
POP {R0, R2, PC} ;
EnableIRQ
; R0=
PUSH {R0-R2, LR}
MOV R2, #1
LSL R2, R2, R1 ; = (0x1 << (N & 0x1F))
AND.W R1, R0, #0xE0 ; IRQ>31
LSR R1, R1, #3 ; = (N/32)*4IRQ
LDR R0, =NVIC_SETEN ; SETENA
STR R2, [R0, R1] ;
POP {R0-R2, PC} ;
;------------------------
;
Hf_Handler
... ; fault
BX LR
Nmi_Handler
... ; NMI
BX LR
Irq0_Handler
... ; IRQ #0
BX LR ; Return
;------------------------
AREA | Header Data|, DATA
ALIGN 4
;
VectorTableBase SPACE 256 ; 256
VectorTableEnd ; (256 / 4 = 64)
MyData1 DCD 0 ;
MyData2 DCD 0
END ;
SPACE
25664256
MyData1
0x2000_0100 MyData20x2000_0104

172
Cortex-M3 11
NVIC
NMIfault
BX LRPOP ,PC
LDMIA
LDM/STM
LDM/STMLDM/STM
NVIC
DSB

SetupIrqHandlerEnableIRQ
NVIC
DisableIRQSETENACLRENA
11.5 SVC
SVCOSAPIOSAPI
SVC8
SVC 3 ;3
3SVCSVCSVCSVC
811.2
11.2 SVC

173
Cortex-M3 11
svc_handler
TST LR, #0x4 ; EXC_RETURN2
ITE EQ ; 0,
MRSEQ R0, MSP ; MSP
MRSNE R0, PSP ; , MSP
LDR R1, [R0,#24] ; PC
LDRB R0, [R1,#-2] ; SVCR0
; PCLR(EXC_RETURN)OS
BX LR ; OS
OSTBB/TBH
OS
SVCSVCSVC
BL
11.6 SVC

BL
OS
OSSVC
LDR R0, =HELLO_TXT

SVC 0 ; 0
MOV R0, #A
SVC 1 ; 1
LDR R0, =0xC123456
SVC 2 ; 162
MOV R0, #1234
SVC 3 ; Display decimal value in R0
SVCSVCIRQ
11Thumb-2
SetupExcpHandler
; R0 =
; R1 =
PUSH {R0, R2, LR}
LDR R2, =NVIC_VECTTBL
LDR R2, [R2] ;
STR.W R1, [R2, R0, LSL #2] ; [R2+R0<<2]
POP {R0, R2, PC} ;
SVC
R0-R3SVCR0-R3
SVC
174
Cortex-M3 11
svc_handler
;
TST LR, #0x4 ; EXC_RETURN2
ITE EQ ; 0,
MRSEQ R0, MSP ; MSP
MRSNE R0, PSP ; , MSP
LDR R0, [R1,#0] ; R0
LDR R1, [R1,#24] ; PC
LDRB R1, [R1,#-2] ; SVC8
; R0R1
PUSH {LR} ; LRBL
CBNZ R1, svc_handler_1
BL Puts ; Puts
B svc_handler_end
svc_handler_1
CMP R1, #1
BNE svc_handler_2
BL Putc ; Putc
B svc_handler_end
svc_handler_2
CMP R1, #2
BNE svc_handler_3
BL PutHex ; PutHex
B svc_handler_end
svc_handler_3
CMP R1, #3
BNE svc_handler_4
BL PutDec ; PutDec
B svc_handler_end
svc_handler_4
B error ;
...
svc_handler_end
POP {PC} ; Return

3R0R1-R3
svc_handler
R0-R3
SVC
+SVCR0-R3
175
Cortex-M3 11
1. R0SVC
2. CM3SVCxPSR, PC, LR, R12, R3-R0
3.
4.

5. SVCR0
R0-R3

LDR/STR
SetupIrqhandler SetupExcpHandler
SetupIrqHander3
SetupExcpHandler
31
CM3

CLZRBIT
both
uC/OS-II256

11.7 C SVC
SVC
SVCSVCC
ARM(armcc)(armasm)RVDSKeil RVMDK
// R0SVC
__asm void svc_handler_wrapper(void)
{
IMPORT svc_handler
TST LR, #4
ITE EQ
MRSEQ R0, MSP
MRSNE R0, PSP
B svc_handler
}
// BX LRsvc_handler
SVCCR0
R0-R3
176
Cortex-M3 11
CC
// CSVCpwdSF
// pwdSF[0] = R0 , pwdSF[1] = R1
// pwdSF[2] = R2 , pwdSF[3] = R3
// pwdSF[4] = R12, pwdSF[5] = LR
// pwdSF[6] = PC
// pwdSF[7] = xPSR
unsigned long svc_handler(unsigned int* pwdSF)
{
unsigned int svc_number;
unsigned int svc_r0;
int retVal; //
svc_number = ((char *) pwdSF[6])[-2]; // C
svc_r0 = ((unsigned long) pwdSF[0]);
printf (SVC number = %xn, svc_number);
printf (SVC parameter 0 = %x\n, svc_r0);
//retVal
pwdSF[0]=retVal;
return 0;
}
0
retVal
SVCCunsigned int func(),
return xx;ARMR0
R0return
R0pwdSF[0]=retVal

return xx
C//
177
Cortex-M3 11
RVDSKeil RVMDK__svc
34
unsigned long __svc(0x03) CallSvc3(unsigned long svc_r0, unsigned long
svc_r1, unsigned long svc_r2, unsigned long svc_r3);
CSVC
int Func(void)
{
unsigned long p0, p1, p2, p3; //SVC4
unsigned long svcRet; //
. . .
svcRet=CallSvc3(p0, p1, p2, p3); // 34p1,p2,p3,p4
svcRet
. . .
return;
}
__svcRVCT 3.0 Compiler and Library Guide(Ref6)
GNU__svcGCC
3R0
SVC
int MyDataIn 0x123;
__asm __volatile (mov R0, %0\n
svc 3 \n : : r (MyDataIn) );
r(MyDataIn)
__asm ( assembler_code : output_list : input_list )

19GNU
GNU
178
Cortex-M3 12
12
12.1
CM3 v7-M
/(kernel)
MPU
CM3 CM3
MSP
MSP
PSP
SysTick

PSP
MSP MPU MSP

12.1 SRAM MPU regions
CM3
SP regions
179
Cortex-M3 12
12.1 /
0 MSP
;
BL MpuSetup ; MPU regions
LDR R0, =PSP_TOP ;
MSR PSP, R0 ;
BL SystickSetup ; SysTickSysTickOS
MOV R0, #0x3 ; CONTROLPSP
MSR CONTROL,R0 ;
B UserAppStart ;
C C C
Cortex-M3 TRM
Ref1 SVC ISR EXC_RETURN
12.2 OS
180
Cortex-M3 12
EXC_RETURN
SysTick
12.3
12.3 SysTick
PendSV

MSP CM3 MSP process
stack MSP
; MSP
MpuSetup(); // MPU regions
SystickSetup(); // SysTick
SwitchStackPointer(); // PSP
/*; ------ SwitchStackPointer -----

PUSH {R0, R1, LR}
MRS R0, MSP ; MSPR0
LDR R1, =MSP_TOP
MSR MSP, R1 ; MSPMSP_TOP
MSR PSP, R0 ; MSPPSP
MOV R0, #0x3
MSR CONTROL,R0 ; PSP
POP {R0, R1, PC}
; ------ C -----*/
; PSP
UserApplicationStart(); //
12.2
AAPCS primitive
1,2,4 8 CM3 NVIC
STKALIGN D D.17
181
Cortex-M3 12
LDR R0, =0xE000ED14 ; R0=NVIC CCR

LDR R1, [R0]
ORR.W R1, R1, #0x200 ; STKALIGN
STR R1, [R0] ; NVIC CCR
C
*NVIC_CCR= *NVIC_CCR | 0x200; /* STKALIGN*/
STKALIGN 1 xPSR 9 SP
xPSR.9 SP
STKALIGN
CM3 1 0
AAPCS C
2 C
double, long long / INT64
12.3
CM3 handler
NVIC NONBASETHRDENA
0
CM3
redirect_handler
PUSH {LR}
SVC #0 ;
BL User_IRQ_Handler
SVC #1 ;
POP {PC} ;
182
Cortex-M3 12
+PSP
SVC #0 8
PSP EXC_RETURN.+PSP
SVC #1 PSP EXC_RETURN
redirect_handler
5

12.4 SVC
svc_handler
;
TST LR, #0x4 ; EXC_RETURN.2
ITE EQ ;
MRSEQ R0, MSP ; MSPR0
MRSNE R0, PSP ; PSPR0
LDR R1, [R0, #24] ;
LDRB R0, [R1, #-2] ; 8
CBZ r0, svc_service_0
CMP r0, #1
BEQ svc_service_1
B.W Unknown_SVC_Request
svc_service_0 ; 0+PSP
MRS R0, PSP ; PSP
SUB R0, R0, #0x20 ; 328
MSR PSP, R0 ; PSP
MOV R1, #8*4 ; R18
svc_service_0_copy_loop
SUBS R1, R1, #1*4
LDR R2, [SP, R1]
STR R2, [R0, R1]
CMP R1, #0
BNE svc_service_0_copy_loop
STRB R1, [R0, #0x1C] ; IPSR

LDR R0, =0xE000ED14 ; NVICCCR
LDR r1, [r0]
ORR r1, #1
STR r1, [r0] ;
ORR LR, #0xC ; EXC_RETURN +PSP
BX LR ;
svc_service_1 ; 1+PSPhandler
MRS R0, PSP ; PSPR0
LDR R1, [R0, #0x18] ; PSPsvc #1
; POP {PC}
STR R1, [SP, #0x18] ; handlerMSP
ADD R0, R0, #0x20 ; PSP
MSR PSP, R0 ; PSP
183
Cortex-M3 12
LDR R0, =0xE000ED14 ; NVICCCR

LDR r1, [r0] ; NVICCCR
BIC r1, #1
STR r1, [r0] ; NONBASETHRDENA
BIC LR, #0xC ; EXC_RETURNhandlerMSP
BX LR
SVC IPSR
12.4
12.4
PSPSVC0IRQ
PSPsvc #1
IRQPSPPSP
MSPMSP
MSPPSP
184
Cortex-M3 12
12.4
CM3
MCU/SoC
32
I-CodeSystemD-Code
(I-Code)
(System)RAM
SRAMCodeD-Code
SRAM
CM3
ARMALIGNGNU AS
LDR/STRLSL
/

LDM/STMLDM/STM14LDM
14LDR
if then
IF-THENITxxxIT4
ThumbThumb-2
Thumb-2
CM3ARMv6
RBITCLZ
12.5 (Lockup)
faultfault
faultfaultfault
CM3
-mission-critical
185
Cortex-M3 12
12.5.1
PC0xFFFF_FFFx
CM3LOCKUP

faultfaultsfault
NMIfaults
MSPPCfault
faultNMINMI
-1NMINMI-2

haltPC
-
NMIfault/fault
fault12.5
12.5 fault/NMI fault
12.5.2
NMI
fault
NMI
NMI
faultSP
fault
hard_fault_handler
PUSH {R4-R7,LR} ;
...
faultfaultfault
186
Cortex-M3 12
SPNMI
I/O
R0-R3R12
faultNMIPendSV
PendSV
NMI/faultSVCSVC
NMIfaultfault
NMI/fault
SVC
SVC
187
Cortex-M3 12
188
Cortex-M3 13
13
Cortex-M3
SysTick

CM3
13.1 SysTick
8 NVIC SysTick SysTick
24 0 RELOAD
SysTick 13.1 SysTick
13.1 SysTick
CM3 SysTick FCLK

HCLK FCLK
FCLK
FCLK
[31](NOREF)
SysTick 1 0 COUNTFLAG
SysTick STCSR
SysTick STCVR
SysTick OS
189
Cortex-M3 13
SysTick STCSR.TICKINT
SRAM SysTick
; SysTick
MOV R0, #0xF ; 15
LDR R1, =systick_handler ;
LDR R2, =0xE000ED08 ;
LDR R2, [R2] ;
STR R1, [R2, R0, LSL #2] ;
SysTick
; SysTickSysTick
LDR R0, =0xE000E010 ; STCSR
MOV R1, #0
STR R1, [R0] ; SysTick
LDR R1, =0x3FF ; SysTick10241023
; 010240x3FF
STR R1, [R0,#4] ;
STR R1, [R0,#8] ; STCVRCOUNTFLAG
MOV R1, #0x7 ; FCLKSysTick
STR R1, [R0] ;
SysTick 10ms (TENMS )
CM3 24 10ms
STCR TENMS
SysTick 300
SysTick
SysTick CURRENT RELOAD 300
LDR r0, =15

LDR r1, =SysTickAlarm ; SysTickSetupExcpHanler
BL SetupExcpHandler ;
LDR R0, =0xE000E010 ; SysTick
MOV R1, #0 ; SysTick
STR R1, [R0]
STR R1, [R0,#0x8] ; CURRENT
LDR R1, =(300-12) ; 12
STR R1, [R0,#0x4] ; RELOAD
LDR R4, =SysTickFired ; RAM
MOV R5, #0 ; 0
STR R5, [R4]
MOV R1, #0x7 ; FCLKSysTickSysTick
STR R1, [R0] ;
LDR R4, SysTickFired
190
Cortex-M3 13
WaitLoop
LDR R5, [R4] ;
CMP R5, #0
BEQ WaitLoop
... ; SysTickFired
SetupExcpHandler RAM
SetupExcpHandler
; R0 =
; R1 =
PUSH {R0, R2, LR}
LDR R2, =NVIC_VECTTBL
LDR R2, [R2] ;
STR.W R1, [R2, R0, LSL #2] ; [R2+R0<<2]
POP {R0, R2, PC} ;
0 300-12 CURRENT12
12 one shot SysTick

SysTick SysTick
SysTickAlarm ; SYSTICK exception handler

PUSH {LR}
LDR R0, =0xE000E010 ; SYSTICK
MOV R1, #0
STR R1, [R0] ; SysTick
LDR R0, =0xE000ED04
LDR R1, =0x02000000 ; NVICSysTick
STR R1, [R0]
... ;
LDR R2, SysTickFired
LDR R1, [R2]
ORR R1, #1
STR R1, [R2] ;
POP {PC} ;
SysTickFired
13.2
CM3
FCLK SysTick
CM3 SLEEPING
191
Cortex-M3 13
CM3 SLEEPDEEP
NVIC
13.1 CM3
13.1 0xE000_ED10

4 SEVONPEND RW - WFE
CM3 WFE

3 - - -
2 SLEEPDEEP R/W 0 SLEEPDEEP

1 SLEEPONEXIT R/W - SleepOnExit
0 - - -
WFI/WFE CM3 CM3
sleep/slpWFI Wait-For-Interrupt WFE Wait-For-Event
event RXEV
event
WFE 13.2
13.2

SRAM STM32
WFI/WFE
WFI
WFI BASEPRI
ISR PRIMASK ISR
WFE SETONPEND
ISR WFI
192
Cortex-M3 13
CM3 13.2A 13.2B

WFI/WFE
13.2AWFI +
ISR
PRIMASK=0 BASEPRI + +
PRIMASK=0 BASEPRI
PRIMASK=1 BASEPRI +
PRIMASK=1 BASEPRI
13.2BWFE +
ISR
PRIMASK=0SEVONPEND=0 BASEPRI + +
PRIMASK=0SEVONPEND=0 BASEPRI
PRIMASK=0SEVONPEND=1 BASEPRI + +
+
PRIMASK=1SEVONPEND=0 BASEPRI +
PRIMASK=1SEVONPEND=1 BASEPRI +
+
1. PRIMASK=0 ISR
2. WFE SEVONPEND=1
3. PRIMASK BASEPRI
4. PRIMASK=0
CM3 SleepOnExit
SLEEPONEXIT 13.3
193
Cortex-M3 13
13.3 SleepOnExit
13.3
CM3
TXEVTransmit Event
RXEVReceive Event
13.4
13.4
WFE RXEV CM3
SEV Send EVent TXEV
13.5
194
Cortex-M3 13
13.5
WFE
WFE 13.6
195
Cortex-M3 13
13.6 WFE
WFE

WFE
SEV SEV WFE
13.3.1
13.6 WFE
WFE WFE
WFE

spin lock Linux
RTOS
RTOS spin_lock() spin_unlock():Linux
196
Cortex-M3 13

spin_lock ; r0
MOVS r2, #1 ; r2
spin_lock_loop
LDREX r1, [r0]
CMP r1, #0
BNE spin_lock_loop ;
STREX r1, r2, [r0] ; STREX Lock_Variable 1
CMP r1, #0 ; STREX
BNE spin_lock_loop ; STREX
DMB ;
BX LR ;
spin_unlock ; r0
MOVS r1, #0
DMB ;DMB
STR r1, [r0] ; Clear lock
DMB ;
BX LR ;

WFE/SEV
WFE
SEV
spin_lock_with_WFE ; WFE r0
MOVS r2, #1 ; r2
spin_lock_loop
LDREX r1, [r0]
CBNZ r1, lock_is_set ; r1!=0
STREX r1, r2, [r0] ; STREX Lock_Variable 1
CMP r1, #0 ; STREX
BNE spin_lock_loop ; STREX
DMB ;
BX LR ;
lock_is_set
WFE ; SEV
B spin_lock_loop ; SEV

SEV
spin_unlock_with_SEV ; r0
MOVS r1, #0
DMB ;DMB
197
Cortex-M3 13
STR r1, [r0] ; Clear lock

DMB ;
SEV
BX LR ; Return

WFE WFE
spin_unlock_with_SEV
RTOS
CPU 100%
CM3 RXEV
Cortex-M3 r2p0
SLEEPONEXIT CM3 WFI/WFE
WFI/WFE
SLEEPONEXIT
Cortex-M3 2 2008
WFI/WFE

2
cells

SysTick 2

13.4
CM3 CM3
NVIC (AIRCR)
VECTRESET 0
LDR R0, =0xE000ED0C ; NVIC AIRCR address
LDR R1, =0x05FA0001 ; VECTRESET0x05FA
STR R1, [R0] ;
deadloop
198
Cortex-M3 13
B deadloop ;
CM3
CM3
SYSRESETREQ
CM3
CM3
STM32
SYSRESETREQ
LDR R0, =0xE000ED0C ; NVIC AIRCR address
LDR R1, =0x05FA0004 ; SYSRESETREQ0x05FA
STR R1, [R0] ;
deadloop
B deadloop ;
SYSRESETREQ CM3
(SYSRESETn)SYSRESETREQ
SYSRESETREQ
FAULTMASK
199
Cortex-M3 13
200
Cortex-M3 14
14
MPU
MPUCM3CM3
MPU
MPU
MPU
MPU
14.0
MPU
1 C
unsigned int

bug

C C
C Super StarC
C

[]
C

bug 0
u r my super star
201
Cortex-M3 14
C
C C C
C
2-

/
MPU

MPU
MMU MMU cache RAM RAM MB

MMU MMU

14.1 MPU
Cortex-M3MPU
MPU
MPUMPUMPU

MPUregions
MPUregionregion
CM3MPU8regions
regionregion
regionMPU
MPUregion
MemManage fault
MPUregionsregion
region1region4region4region
14.2 MPU
MPU
202
Cortex-M3 14
Cortex-M3 TRM

MPU MPUTR RO 0xe000,ed90 A
MPU MPUCR RW 0xe000,ed94 0x0000,0000
MPU regionMPURNR RW 0xe000,ed98 -
MPU regionMPURBAR RW 0xe000,ed9c -
MPU region(s) MPURASR RW 0xed00,eda0 -
MPU region1 D9C 0xed00,eda4 -
MPU region1 DA0 0xed00,eda8 -
MPU region2 D9C 0xed00,edac -
MPU region2 DA0 0xed00,edb0 -
MPU region3 D9C 0xed00,edb4 -
MPU region3 DA0 0xed00,edb8 -
MPUMPUTR14.1
14.1 MPU MPUTR 0xE00_ED90

23:16 IREGION R 0 MPU region ARMv7-M
MPU
15:8 DREGION R 0 MPU MPU 8,

0 SEPARATE R 0
DREGIONMPU
MPUMPUCR14.2
14.2 MPU MPUCR 0xE00_ED94

2 PRIVDEFENA RW 0
203
Cortex-M3 14
region
1= region
0= region
region fault
1 HFNMIENA RW 0 1= NMI fault MPU
0= NMI fault MPU
0 ENABLE RW 0 MPU
PRIVDEFENAregionMPU
regionMPU
regionregionregion
PRIVDEFENA14.1
14.1 PRIVDEFENA
ENABLE
regionMemManage fault
MPUMPUMPU
MPU(system
partition)
SCS
When the MPU is enabled, only the system partition and vector table loads are always
accessible.
regionMPUregionregionMPU
region(MPURNR)14.3
204
Cortex-M3 14
14.3 MPU region MPURNR 0xE00_ED98

7:0 REGION RW - region 8
region[2:0]
regionregion
regionsMPU region(MPURBAR)
VALIDREGIONMPURNRMPURBAR14.4
14.4 MPU region MPURBAR 0xE00_ED9C

31:N ADDR RW - Region N region
MPU region
SZENABLE ADDR
4 VALID RW - REGION
1=MPU regionREGION
0=MPU region
3:0 REGION RW - MPU region
regionregion
64KB64KB0x0001,00000x0002,0000
160
REGIONregionVALID0VALID=1
REGION=nregionMPU region
regionMPU
14.5
205
Cortex-M3 14
14.5 MPU regionMPURASR0xE000_EDA0

31:29 3 -
28 1 XN 1=
2=
27 1 -
26:24 3 AP

0b000
0b001 RW OS
0b010 RW RO
0b011 RW RW
0b100 n/a n/a n/a
0b101 RO OS
0b110 RO RO
0b111 RO RO
23:22 2
21:19 3 TEX
18 1 S Sharable
1=
0=
17 1 C Cachable
1=
0=
16 1 B Buffable
1=
0=
15:8 8 SRD regionSRDregion
128region8region
128regionRegion
7:6 2 -
5:1 5 REGIONSIZE Region1<<(REGIONSIZE+1)32
0 1 SZENABLE 1=region 0=region
region[15:8]8region
regionregionregion
region8regionregionregion
regionregionSRD8
regionSRD.3=03regionregion
regionregionfault
region256128regionregion
206
Cortex-M3 14
APAP
[28]XNeXecute Neverregion
MemManage fault
TEX, S, BC[21:16]CM3
(cache)CM3v7-Mv7-ML2
v7-M
v6ARMx86
(policy)
14.6 TEX,C,B
TEX C B
000 0 0
000 0 1
000 1 0 allocate S
000 1 1 allocate S
001 0 0 S
001 0 1 n/a n/a n/a
001 1 0
001 1 1 allocate S
010 1 x
010 0 1 n/a n/a n/a
010 1 x n/a n/a n/a
1BB A A BB=, AA= S

TEXMSB=1regionCB
AATEX[1:0]BBAA
BB
14.7
(AA and BB)

00
01 allocate
10 allocate
11 allocate
ARM Architecture Application Level Reference
Manual(Ref2)
8431
Cortex-M3 TRM
207
Cortex-M3 14
9.2.3 (alias)MPU
STMregions
43
(STM)1-4region
region/region/retgion

4region
; R1 = RTOS4region8
MOV R0, #NVIC_BASE
ADD R0, #MPU_REG_CTRL
LDM R1, [R2-R9] ; 4region
STM R0, [R2-R9] ; 4region

regionsregion
C/C++memcpy()CRT
memcpy()long* char*,
short*

14.3 MPU
MPU
MPUregions
OS

data_stack
data_stack
SRAM
NVICMPU
UARTADC
CM3regionTEX=0C=1B=1NVIC
strongly orderedregionsTEX=0, C=0, B=1
regionfaultregionTEX=0, C=0, B=0
14.2MPUMPURAM
MemManage faultNVIChandlerSHCSR
MemManage faultMPUMemManage fault
208
Cortex-M3 14
14.2 MPU
4region
LDR R0, =0xE000ED98 ; Region
MOV R1, #0 ; region 0
STR R1, [R0]
LDR R1, =0x00000000 ; = 0x00000000
STR R1, [R0, #4] ; MPU Region
LDR R1, =0x0307002F ; R/W, TEX=0,S=1,C=1,B=1, 16MB, Enable=1
STR R1, [R0]
209
Cortex-M3 14
LDR R1, =0x08000000 ; = 0x08000000

LDR R1, =0x0307002B ; R/W, TEX=0,S=1,C=1,B=1, 4MB, Enable=1

STR R1, [R0]
LDR R1, =0x40000000 ; = 0x40000000
LDR R1, =0x03050039 ; R/W, TEX=0,S=1,C=0,B=1, 512MB, Enable=1

STR R1, [R0]
LDR R1, =0xE0000000 ; = 0xE0000000
MOV R1, #1 ; MPU

STR R1, [R0,#-4] ; MPU(0xE000ED98-4=0xE000ED94)
4regions:
0x0000_0000-0x00FF_FFFF(16MB)
0x0800_0000-0x0803_FFFF(4MB)
0x4000_0000-0x5FFF_FFFF(512MB)
0xE000_0000-0xE00F_FFFF(1MB) XN
VALIDREGIONregion
LDR R0, =0xE000ED9C ; MPU region

LDR R1, =0x00000010 ; =0x00000000, region=0, valid=1
STR R1, [R0, #0] ; region 0
LDR R1, =0x0307002F ; R/W, TEX=0,S=1,C=1,B=1, 16MB, Enable=1

LDR R1, =0x0307002B ; R/W, TEX=0,S=1,C=1,B=1, 4MB, Enable=1

210
Cortex-M3 14
LDR R1, =0xE0000013 ; =0xE0000000, region=3, valid=1

MOV R1, #1 ; MPU

STR R1, [R0,#-8] ; MPU(0xE000ED9C-8=0xE000ED94)
MPU
MPU(MPUASR)3MPU(MPUBAR)
MPUMPUBARMPUASR48
LDM/STM
LDR R0, =0xE000ED9C ; MPU reigon
LDR R1, =MPUconfigTab ; MPU
LDMIA R1!, {R2-R9} ; 8
STMIA R0!, {R2-R9} ; 4region
B MPUconfigEnd
ALIGN 4 ;
MPUconfigTab ; LDM/STM
DCD 0x00000010 ; =0x00000000, region=0,valid=1

DCD 0x0307002F ; R/W, TEX=0,S=1,C=1,B=1, 16MB, Enable=1
DCD 0x0307002B ; R/W, TEX=0,S=1,C=1,B=1, 4MB, Enable=1
DCD 0x03050039 ; R/W, TEX=0,S=1,C=0,B=1, 512MB, Enable=1
DCD 0xE0000013 ; =0xE0000000, region=0,valid=1
DCD 0x03040027 ; R/W, TEX=0,S=1,C=0,B=0, 1MB, Enable=1
MPUconfigEnd
LDR R0, =0xE000ED94 ; MPU
MOV R1, #1 ; MPU
STR R1, [R0]
region
regionMpuRegionSetup
/region
region

BFIUBFX
MpuSetup ; MPU
PUSH {R0-R6,LR}
MOV R1, #0
STR R1, [R0] ; MPU
; --- Region #0 ---
LDR R0, =0x00000000 ; Region 0: = 0x00000000
211
Cortex-M3 14
MOV R1, #0x0 ; Region 0: Region = 0

MOV R2, #0x17 ; Region 0: = 0x17 (16MB)
MOV R3, #0x3 ; Region 0: AP = 0x3 ( )
MOV R4, #0x7 ; Region 0: MemAttrib = 0x7
MOV R5, #0x0 ; Region 0: region=0
MOV R6, #0x1 ; Region 0: {XN, Enable} = 0,1
BL MpuRegionSetup
; --- Region #1 ---
LDR R0, =0x08000000 ; Region 1: = 0x08000000
MOV R2, #0x15 ; Region 1: = 0x15 (4MB)
MOV R3, #0x3 ; Region 1: AP = 0x3 ()
MOV R4, #0x7 ; Region 1: MemAttrib = 0x7
MOV R5, #0x0 ; Region 1: region= 0
BL MpuRegionSetup
... ; region #2region #3
; --- Region #4-#7 ---
MOV R0, #4
BL MpuRegionDisable
MOV R0, #5
BL MpuRegionDisable
MOV R0, #6
BL MpuRegionDisable
MOV R0, #7
BL MpuRegionDisable
MOV R1, #1
STR R1, [R0] ; MPU
POP {R0-R6,PC} ;
MpuRegionSetup
; MPU region
; :
; R0 =
; R1 = Region
; R2 =
; R3 = AP ()
; R4 = MemAttrib ({TEX[2:0], S, C, B})
; R5 = region
; R6 = {XN,Enable}
PUSH {R0-R1, LR}

BIC R0, R0, #0x1F ;
BFI R0, R1, #0, #4 ; regionR0[3:0]
ORR R0, R0, #0x10 ; VALID
LDR R1, =0xE000ED9C ; MPU Region
STR R0, [R1] ;
AND R0, R6, #0x01 ;
UBFX R1, R6, #1, #1 ; XN
BFI R0, R1, #28, #1 ; XN R0[28]
BFI R0, R2, #1 , #5 ; region(R2[4:0])R0[5:1]
BFI R0, R3, #24, #3 ; AP(R3[2:0])R0[26:24]
BFI R0, R4, #16, #6 ; memattrib(R4[5:0])R0[21:16]
BFI R0, R5, #8, #8 ; SRD(R5[7:0])R0[15:8]
LDR R1, =0xE000EDA0 ; MPU Region
STR R0, [R1] ;
POP {R0-R1, PC} ;
212
Cortex-M3 14
MpuRegionDisable
; region
; R0 = region
PUSH {R1, LR}
AND R0, R0, #0xF ; region4
ORR R0, R0, #0x10 ; VALID
LDR R1, =0xE000ED9C ; MPU Region
STR R0, [R1] ;
MOV R0, #0
LDR R1, =0xE000EDA0 ; MPU Region
STR R0, [R1] ;
POP {R1, PC} ;
regionregion
14.4 MPU
MPUMPU
regionsregions
1. region
a)
b)
2. SRAM region
a)
b)
c)
d)
3.
a)
b)
c)
d)
4. NVIC
a)
11regionMPU8
region14.1regionsregion
PRIVDEFENA=1regions53
RAMregions
RAM
14.4.1 region

213
Cortex-M3 14
regions
regionregion
regionregion
8region
3region
regionregionregion14.3
14.3 regionSRDregions
regions
region0
MOV R5, #0x64 ; Region 1: region 2, 5, 6
MpuSetup ; MPU
PUSH {R0-R6,LR}
MOV R1, #0
STR R1, [R0] ; MPU
; --- Region #0 ---
LDR R0, =0x00004000 ; Region 0: = 0x00004000
214
Cortex-M3 14

MOV R2, #0x0D ; Region 0: = 0x0D (16KB)
MOV R3, #0x3 ; Region 0: AP = 0x3 ( )
MOV R4, #0x2 ; Region 0: TEX=0,S=0,C=1,B=0
MOV R5, #0x0 ; Region 0: region=0
BL MpuRegionSetup
; --- Region #1 ---
LDR R0, =0x20000000 ; Region 1: = 0x20000000
MOV R2, #0x0B ; Region 1: = 0x0B (4KB)
MOV R3, #0x3 ; Region 1: AP = 0x3 ()
MOV R4, #0xB ; Region 1: TEX=1,S=0,C=1,B=0
MOV R6, #0x1 ; Region 1: {XN, Enable} =0,1
BL MpuRegionSetup
; --- Region #2 ---
LDR R0, =0x22000000 ; Region 2: = 0x22000000
MOV R2, #0x10 ; Region 2: = 0x010 (128KB)
MOV R3, #0x3 ; Region 2: AP = 0x3 ()
BL MpuRegionSetup
; --- Region #3 ---
LDR R0, =0x40000000 ; Region 3: = 0x40000000
MOV R2, #0x13 ; Region 3: = 0x013 (1MB)
MOV R3, #0x3 ; Region 3: AP = 0x3 ()
MOV R5, #0x64 ; Region 3: region 2,5,6
BL MpuRegionSetup
; --- Region #4 ---
LDR R0, =0x42000000 ; Region 4: = 0x42000000
MOV R2, #0x18 ; Region 4: = 0x018 (32MB)
MOV R3, #0x3 ; Region 4: AP = 0x3 ()
MOV R5, #0x64 ; Region 4: region 2,5,6
BL MpuRegionSetup
; --- Region #5 --- RAM
215
Cortex-M3 14
LDR R0, =0x60000000 ; Region 5: = 0x60000000

MOV R2, #0x17 ; Region 5: = 0x010 (16MB)
MOV R3, #0x3 ; Region 5: AP = 0x3 ()
BL MpuRegionSetup
; --- Region #6 ---
MOV R0, #6
BL MpuRegionDisable
; --- Region #7 ---
MOV R0, #7
BL MpuRegionDisable
SRD0x9B~0x64SRDregion
14.3ARMARM
regions32KB flash, 8KB RAM
216
Cortex-M3 14
14.8 regions
MPU region
C,B,A,S,XN
0000_0000 16KB RO C,-,A,-,-
0000_3FFF
0000_4000 16KB RO C,-,A,-,- Region #0
0000_7FFF
2000_0000 4KB RW C,B,A,-,- Region #1
2000_0FFF
2000_1000 4KB C,B,A,-,-
2000_1FFF RW
2200_0000 128KB RW C,B,A,-,- Region #2
2001_FFFF
2202_0000 128KB C,B,A,-,-
2203_FFFF RW
4000_0000 1MB RW -,B,-,-,XN Region #3
400F_FFFF
4004_0000 128KB -,B,-,-,XN
4005_FFFF RW Region #3
region 2
400A_0000 128KB -,B,-,-,XN
400B_FFFF RW Region #3
region 5
400C_0000 128KB -,B,-,-,XN
400D_FFFF RW Region #3
region 6
4200_0000 32MB RW -,B,-,-,XN Region #4
43FF_FFFF
4280_0000 4MB -,B,-,-,XN
42BF_FFFF RW Region #4
region 2
4340_0000 4MB -,B,-,-,XN
437F_FFFF RW Region #4
region 5
4380_0000 4MB -,B,-,-,XN
43BF_FFFF RW Region #4
region 6
6000_0000 16MB RW C,B,A,-,- Region #5 RAM
60FF_FFFF
E000_0000 1MB -,-,-,-,XN NVIC,
E00F_FFFF
217
Cortex-M3 14
218
Cortex-M3 15
15

CoreSight

Cortex-M3

15.1

JTAG AVR
bug
CM3
CM3
CM3
a)
b)
c) BKPT
d)
e)
f)
g) ROM (flash patching)
h)
i) ETM
j)
k) ITM
l) profiling

219
Cortex-M3 15
CM3 CM3 ARM

CoreSight
15.2 CoreSight
CoreSight
CoreSight Technology System Design Guide(Ref3)
CoreSight Cortex-M3 TRM CM3
15.2.1
CM3 ARM7/ARM9 CoreSight
ARM JTAG CM3
(DAP)
DAP AMBA APB CM3 JTAG DAP
DAP
CM3 DAP APB
CM3 NVIC FPB,

DWT, ITM NVIC
CM3 debug host interface :

JTAG (Serial Wire, SW) SW
ARM DP DP
CM3 DAP
CM3 JTAG
4 SW
15.2.2 DP AP DAP
CM3 15.1
DP SWJ-DP SW-DP 32
DAP SWJ-DP SW JTAG SW-DP SW
CoreSight JTAG-DP JTAG DAP
220
Cortex-M3 15
32 8 DAP 256
CM3
255 AP
DAP
15.1 Cortex-M3
DAP CM3 AHB-AP AP
DAP AHB CM3
CM3 NVIC
CoreSight AP APB-AP
JTAG-APAPB-AP APB JTAG-AP
JTAG ARM7
15.2.3
CoreSight CM3 3
1. ETM
2. DWT
3. ITM printf GUI
ATB
CoreSight SoC
ATB merger ATB CoreSight

ATB funnel TPIU TPIU
PC PC
CM3 CM3 ATB funnel

CM3 TPIU PC
15.2.4 CoreSight
CoreSight
221
Cortex-M3 15

JTAG
TAP

PC

CM3 CoreSight
CM3 CM3 ATB 8 CoreSight
32
CM3 TrustZoneARM

CoreSight
CoreSight 15.2

15.2 CoreSight
CM3 15.3
222
Cortex-M3 15
15.3 Cortex-M3
CM3 CoreSight
CoreSight CoreSight CoreSight
CM3 CoreSight TPIU
CM3
CoreSight CoreSight Technology System Design

Guide(Ref3)
15.3
CM3 halt
debug monitor exception
12
1.

SysTick

2.
12
SysTick

NVIC DHCSR C_DEBUGEN

CM3 C_DEBUGEN
DHCSR.C_HALT C_HALT
DHCSR
[31:16]
15.1
15.1 DHCSR 0xE00_EDF0

223
Cortex-M3 15
31:15 KEY W -
A05F
25 S_RESET_ST R -
24 S_RETIRE_ST R -
19 S_LOCKUP R - 1=
18 S_SLEEP R - 1=
17 S_HALT R - 1=
16 S_REGRDY R - 1=
15:6 - -
5 C_SNAPSTALL RW 0* stalled
4 - -
3 C_MASKINTS RW 0*
2 C_STEP RW 0* C_DEBUGEN=1
1 C_HALT RW 0* C_DEBUGEN=1
0 C_DEBUGEN RW 0*
*DHCSR NVIC
DHCSR
NVIC NVIC
DEMCR 15.2
15.2 DEMCR 0xE00_EDFC

24 TRCENA RW 0* DWT,ETM,ITM TPIU

23:20
19 MON_REQ RW 0 1=

18 MON_STEP RW 0 MON_EN=1
17 MON_PEND RW 0
16 MON_EN RW 0
15:11
10 VC_HARDERR RW 0* fault
9 VC_INTERR RW 0* /
8 VC_BUSERR RW 0* fault
7 VC_STATERR RW 0* fault
6 VC_CHKERR RW 0* fault

5 VC_NOCPERR RW 0* fault
4 VC_MMERR RW 0* fault
3:1
224
Cortex-M3 15
0 VC_CORERESET RW 0*
*DEMCR NVIC
TRCENA
Vector Catch, VCVC
VC
TRCENA VC
15.4
CM3 both

15.4
15.4
225
Cortex-M3 15
CM3 EDBGREQ
/SoC
C_HALT
15.5

15.5
15.5 Cortex-M3
CM3

FPB
BKPT #im816Thumb0xBExx8
#im8C_DBGEN
NMI
226
Cortex-M3 15
faultBKPT
BKPTBKPT
BKPT
BKPTBKPTBKPT
BKPT
()
BKPTC_DEBUGENMON_EN0
faultfault(HFSR)DEBUGEVT1fault
DFSRBKPT1
FPB6
FPB
BKPTFPB
15.6
NVIC
DCRSRDCRDR15.315.4
15.3 DCRSR0xE00_EDF4

16 REGWnR W - 1=
0=
15:5 - - -
4:0 REGSEL W - 00000= R0
00001=R1

01111=R15
10000=xPSR
10001=MSP
10010=PSP
10100=
[31:24]: CONTROL
[23:16]: FAULTMASK
[15:8]: BASEPRI
[7:0]: PRIMASK
15.4 DCRDR0xE00_EDF8

31:0 DATA R/W -
227
Cortex-M3 15
DCRSR

1.
2. DCRSR160
3. DHCSR.S_REGRDY=1
4. DCRDR

1.
2. DCRDR
3. DCRSR161
4. DHCSR.S_REGRDY=1
DCRSRDCRDR
DCRDRsemihosting
printfputc()putc()
DCRDR
ITM
15.7
NVIC
NVICCM3

faultCM3DFSR

VECTRESETNVIC
0xE000_ED0C

C_MASKINTS0xE000_EDF0

Stalledstall
C_SNAPSTALL

228
Cortex-M3 16
16

(DWT)
(ITM)
(ETM)
(TPIU)
(FPB)
AHB
ROM
16.1
CM3
w

Cortex-M3 Technical Reference Manual(Ref1)
FPB CM3
ITM stimulus

16.1.1 Cortex-M3
CM3 CoreSight
ATB TPIUTPIU
TPA 16.1
16.1 Cortex-M3
CM3 3 ETM, ITM DWTETM
CM3 7 ID ATID
229
Cortex-M3 16
ATID
CoreSight CM3 ATB
CoreSight ATB
ATB funnel
DEMCR.TRCENA 15.2 D.37
TRCENA
16.2 (DWT)
DWT
1. 4
a)

b) ETM ETM
c) PC
d)
e) CYCCNT
2. DWT
a) CYCCNT
b) Folded
c) /LSU
d)
e) CPI
f) overhead
3. PC
4.
ETM PC
3
COMP
MASK
FUNCTION
COMP 32 MASK
16.1
16.1 MASK
MASK
1 [0]
230
Cortex-M3 16
2 [1:0]
3 [2:0]
15 [14:0]
FUNCTION
MASK COMP RUNCTION FUNCTION
FUNCTION
DWT profiling
CYCCNT
CPU

16.3 ITM
ITM
ITM stimulus
DWT ITM
ITM

ITM TPIU
ITM TPIU NVIC
UART
ITM DEMCR.TRCENA ITM
ITM ITM 0xC5AC_CE55
CoreSight ACCESS ITM
ITM ITM
ATID ITM ATB ID ID

ID
16.3.1 ITM
ITM printf ITM 32
(stimulus)
/
UART ITM ITM

FIFO FIFO
TPIU
TRCENA ITM
231
Cortex-M3 16
live
16.3.2 ITM DWT

ITM DWT ITM
16.2 DWT ITM DWTEN DWT
DWT
16.2 ITM TPIU
16.3.3 ITM
ITM ITM FIFO ITM
16.4
ETM
CM3 ETM FIFO
ETM
ETM DWT DWT

ETM
ARM ETM CM3 ETM DWT
CM3 ETM ARM ETM
ETM
1. DEMCR.TRCENA DEMCR 15.2 D.37

2. ETM ETMLOCK_ACCESS 0xC5AC_CE55
3. ATBID ATID ETM

4. ETM NIDEN

232
Cortex-M3 16
5. ETM
16.5 TPIU
ITM, DWT ETM TPIU TPIU
CM3 TPIU
(Clocked mode)4
SWVSWVCM3

TPIU
SWVSWV
TPIUDECMR.TRCENA
Cortex-M3 r2p0
SWV SWV 1
SWV
TDO JTAG
DWT ITM
16.6 FPB
FPB

(literal data)SRAM
FPB8
6
2
233
Cortex-M3 16

LDR R0, =0xE000E400
32
PC

LDR R0, [PC, #<immed_8>*4]
; immed_8 = ( PC)/4
...
;
...
DCD 0xE000E400
...
LDRThumb-232
LDR.W R0, [PC, #+/-<offset_12>]

; offset_12 = -PC
...
;
...
DCD 0xE000E400
...

CM3
D-CodeRAM

FPBFPB
1
SRAM
REMAPREMAP3[31:29]
0b0010x2000_0000-0x3FFF_FF80
SRAM
REMAP
... what if
ROMflash

flashSRAM
(BL)SRAMBL
234
Cortex-M3 16
ROMSRAM

16.3
16.7 AHB
AHB-APCM3SWJ-DP/SW_DP
CM3AHB-AP3
CSW
TAR
/DRW
AHB-AP16.4
235
Cortex-M3 16
16.4 Cortex-M3AHB-AP
CSW/ TAR
DRWDRW
LSB0x1002DRW[31:16]AHB-AP
AHB-APAHB-AP4bannked
CSWMasterType1AHB-AP
AHB
FIFO
16.8 ROM
CM3ROMCM3
v7-MCM3
Cortex-MCM3
ROMNVIC
ROM0xE00F_F000ROM
ID
CM3ROMNVICROM
ROM0xFFF0F003[1:0]
NVIC2NVIC
0xE00F_F000+0xFFF0_F000=0xE000_E000
ROM16.2
CoreSigthROM
16.2 Cortex-M3ROM
236
Cortex-M3 16

0xE00F_F000 0xFFF0_F003 NVIC NVIC0xE000_E000
0xE00F_F004 0xFFF0_2003 DWT DWT0xE000_1000
0xE00F_F008 0xFFF0_3003 FPB FPB 0xE000_2000
0xE00F_F00C 0xFFF0_1003 ITM ITM 0xE000_0000
0xE00F_F010 0xFFF4_1003/ TPIU TPIU 0xE004_0000
0xFFF4_1002
0xE00F_F014 0xFFF4_2003 ETM ETM 0xE004_1000
0xFFF4_2002
0xE00F_F018 0 End End-Of-Table
0xE00F_F0CC 1 MEMTYPE
0xE00F_F0D0 0 PID4 ID
0xE00F_F0DC 0 PID7 ID
0xE00F_F0E0 0 PID0 ID
0xE00F_F0EC 0 PID3 ID
0xE00F_F0F0 0 CID0 ID
0xE00F_F0FC 0 CID3 ID
(bit[1])(bit[0])
NVIC, DWTFPB1TPIUETM
CoreSight
ROM
NVIC= 0xE00F_F000 + 0xFFF0_F000 = 0xE000_E000
ROMCM3
ROMROM
237
Cortex-M3 16
238
Cortex-M3 17
17
Cortex-M3
Cortex-M3
Cortex-M3 0 1
Cortex-M3 1 2

17.1 Cortex-M3
CM3
CM3 CM3

MPU
ETM
SW, JTAG

1.

2. CM3 KB MB RAM

3. CM3 0.18um 100MHz

4. CM3 CM3

17.2 Cortex-M3 0 1
Cortex-M3 Cortex-M3 0
2006 3 CM3
1 CM3 1
1
1
CM3 Luminary ST
1 CM3 0

1
NVIC_CCR.STKALIGN
NVIC_CCR STKALIGN
1 AUXFAULT fault
239
Cortex-M3 17
DWT
ID

allocated
I-Code AHB D-Code AHB
I-Code AHB D-Code AHB
I-Code D-Code (merge)
ADK
AHB (HTM)AHB CoreSight

NVIC_ICSR.VECTPENDING NVIC_DHCSR.C_MASKINTS
C_MASKINTS VECTPENDING
JTAG-DP SWJ-DP JTAG-DP
CoreSight
0 CM3 ARM RVDS
Keil RVMDK
EABI EABI-
CM3 NVIC CPUID
revison CM3 17.1
17.1 CPUID
17.1 CPUID 0xE000_ED00
PartNo Revision
[31:24] [23:20] [19:16] [15:4] [3:0]
0(r0p0) 0x41 0x0 0xF 0xC23 0
1(r1p0) 0x41 0x0 0xF 0xC23 1
1 (r1p1) 0x41 0x1 0xF 0xC23 1
2(r2p0) 0x41 0x2 0xF 0xC32 0
ST STM32 r1p1
17.2.1 1 JTAG-DP SWJ-DP

JTAG SWJ-DP SW-DP JTAG-DP
CM3 both SW JTAG LM ST
SWJ-DP
240
Cortex-M3 17
17.1 SWJ-DP JTAG-DP SW-DP
17.3 Cortex-M3 1 2
2008 Cortex-M3 2 2008
2 2
17.3.1
2
1 C
NVIC STKALIGN
17.3.2 Auxiliary Control Register

Cortex-M3 faults
faults

0xE000_E008

2 DISFOLD R/W 0 IT (folding) IT

(execution phase)
1 DISDEFWBUF R/W 0
MPU regions

241
Cortex-M3 17
0 DISMCYCINT R/W 0
LDM, STM, 64

17.3.3 ID
NVIC ID NVIC CPUID
CPUID 0xE000_ED00
PartNo Revision
[31:24] [23:20] [19:16] [15:4] [3:0]
2 0x41 0x2 0xF 0xC23 0x0
(r2p0)
17.3.4
2
DWT

17.3.5
r2p0

CM3

WIC NVIC
CM3
2
WIC PMU
2 CM3
2
17.3.6 2

242
Cortex-M3 17
WIC
faults LDM/STM
Cortex-M3
2 2
CM3

0/1

PSR 9
STKALIGN EABI
C EABI
SysTick
CM3
SysTick RTOS

17.4
Cortex-M3
/ C C

ICEprobe
JTAG SW

DWT ITM

243
Cortex-M3 17
17.4.1 C
C 17.3
17.3 Cortex-M3

ARM Cortex-M3 RealView 3.0(RVDS)
www.arm.com RealView-ICE 1.5
ADS1.2 SDT Cortex-M3
KEIL(an ARM company) KEIL 8051
www.keil.com Realview MDK Cortrex-M3
ULINK ULINK2
CodeSourcery Cortex-M3 GNU
www.codesourcery.com www.codesourcery.com/gnu_toolchains/arm
GNU 4.0
Rowley Associates GNU C
www.rowley.co.uk www.rowley.co.uk/arm/index.htm
IAR Systems IAR Embedded Workbench for ARM and Cortex
www.iar.com C/C++ 4.40 IAR AVR
IAR JLINK
Lauterbach JTAG
www.lauterbach.com
17.4.2
OS RTOS OS
Cortex-M3 OS 17.4
244
Cortex-M3 17
17.4 Cortex-M3

FreeRTOS FreeRTOS
www.freertos.org
Express Logic ThreadX RTOS
www.expresslogic.com
Micrium uC/OS-II
www.micrium.com
Accelerated Technology Nucleus
www.acceleratedtechnology.com
Pumpkin Inc. Salvo RTOS
www.pumpkininc.com
CMX Systems CMX-RTX
www.cmx.com
KEIL ARTX-ARM
www.keil.com
Segger embOS
www.segger.com
IAR Systems IAR PowerPac for ARM
ww.iar.com
T-Engine uT-Kernel
www.t-engine.org
245
Cortex-M3 17
246
Cortex-M3 18
18
ARM7 Cortex-M3

C

18.1
CM3 ARM7TDMI
ARM7 CM3

C

18.2
CM3 ARM7
MPU
18.2.1
ARM7
4GB ARM
CM3 4GB
ROM RAM
ARM7 CM3
247
Cortex-M3 18
ARM7
SRAM CM3 NVIC
STM32 Flash/SRAM/ BootLoader

CM3 ARM7

ARM720T ARM9 WinCE
0xFFFF_0000CM3 WinCE
MMU
18.2.2 /
NVIC CM3
(directive)
C
CPSR CM3 CPSR PRIMASK
FAULTMASK
CM3
ARM FIQ
FIQ 4 R8-R11
FIQ push/popFIQ
CM3 FIQ FIQ
CM3 FIQ
FIQ
CM3 NVIC
ARM DAbt, IAbt, Undef 3
CM3 fault faults fault
faults faults fault fault
18.2.3 MPU
MPU CM3 ARM7TDMI
MPU ARM720T MMU
CM3 MPU MMU CM3
18.2.4
CM3
CM3 ARM7
248
Cortex-M3 18
18.2.5
ARM 7 CM3 18.1
8.1 ARM7TDMI CM3
ARM7 CM3
(supervisor) +MSP
SWI SVC
FIQ
IRQ
(IAbt) fault
(DAbt) fault
fault
+PSP
+PSP
CM3 ARM7 FIQ FIQ
ARM7 R8-R11 CM3 R0-R3,R12 FIQ
R0-R3,R12 R8-R11
NMI vs. FIQ

NMI FIQ
NMI FIQ

NMI ARM7 FIQ CPSR.F
CM3 NMI
NMI ARM7 FIQ
CM3 NMI SVC ARM7 FIQ SWI
ARM7 FIQ
IRQ CM3 NMI fault

18.3
ARM Thumb
18.3.1 Thumb
thumb
thumb CM3
ARM BLX
SWI SVC
CM3 push pop
249
Cortex-M3 18
18.3.2 ARM
ARM
ARM7 0 CM3
MSP

ARM7
SPLR SPSRCM3

CM3 ARM7 Thumb

ARM7 CPSR.I CM3
PRIMASK FAULTMASKCM3 FIQ F

CM3

ARM7
FIQ CM3
ISR ARM7 S PC
CM3 EXC_RETURN PC
CM3 MOVS SUBS

ARM7 IRQ CM3

FIQ ARM7 FIQ R8-R12 CM3 R0-R3R12
FIQ R8-R11 R8-R11
R0-R3
(SWI)SWI SVC
CM3 SVC ARM7
LR
SWP CM3 SWP
SWP

CPSR SPSR ARM7 CPSR CM3 xPSR SPSR
APSR
xPSR ARM7 SPSR CM3
SPSR
ARM7 Thumb-2
CM3 IF-THEN
IT
/
PC ARM7 PC PC +8
250
Cortex-M3 18
ARM7 PC PC
CM3 CM3 Thumb
PC 4
R13 R13 32 CM3 2 0
R13 2

18.4 C
C
C
RVDS C
RVDS 3.0
__irq ARM7 CM3
__irq RVDS 3.0 RVCT 3.0
__irq CM3__irq
18.5

CM3
CM3
KeilMDK/GCC
18.6
CM3
32 Thumb-2 16 thumb
Thumb-2
16 Thumb
CM3 64

Thumb-2 12 Thumb
Thumb-2
Thumb Thumb-2
251
Cortex-M3 18
BOOL
BOOL 1/32
IT IT

ARM/Thumb Thumb
ARM CM3
Thumb-2
overhead
252
Cortex-M3 19
19
GNU Cortex-M3

GNU

GNU C
19.1
GNU ARM ARM GNU
CM3 GNU CodeSourcery
(www.codesourcery.com) GNU C CM3 2008 3 31
GNU Cortex-M3 WinARM
GNU
GNU GNU AS ARM
the like ARM RealView GNU
19.2 GNU
GNU www.codesourcery.com/gnu_toolchains/arm/
EABI[]OS
WindowsLinux
EABI
19.2.1
ARM GNU
C 19.1
253
Cortex-M3 19
19.1 GNU
Symbian, Linux, EABI

EABI GCC
arm-xxxx-eabi-gcc CodeSourcery GNU ARM 19.1
19.1 winARM20080331 GNU

arm-none-eabi-as
arm-none-eabi-gcc
arm-none-eabi-ld
arm-none-eabi-objcopy
arm-none-eabi-objdump

19.3
GNU
19.3.1 1
10 GCC 10+9+8++1
========== example1.s ==========

/* */
.equ STACK_TOP, 0x20000800
.text
.global _start
.code 16
.syntax unified
/* .thumbfunc */
/ * .thumbfunc2006Q3-26CodeSourcery*/
_start:
254
Cortex-M3 19
.word STACK_TOP, start

.type start, function
/* */
start:
movs r0, #10
movs r1, #0
/* 10+9+8...+1 */
loop:
adds r1, r0
subs r0, #1
bne loop
/* Result is now in R1 */
deadloop:
b deadloop
.end
========== end of file ==========
.word MSP 0x2000_0800start
.text
.global _start
.code 16 thumb
.syntax unified
_start
start
.type start, function start
LSB thumb
.end
ARM GNU :/**/
.
thumb .code 16start.type
start, function LSB 1 Thumb
ARM fault
as
$> arm-none-eabi-as -mcpu=cortex-m3 -mthumb example1.s -o example1.o
example1.o-mcpu -mthumb
$> arm-none-eabi-ld -Ttext 0x0 -o example1.out example1.o

objcopy
$> arm-none-eabi-objcopy -Obinary example1.out example1.bin
(dump)objdump
$> arm-none-eabi-objdump -S example1.out > example1.list

example1.out: file format elf32-littlearm
Disassembly of section .text:
255
Cortex-M3 19
00000000 <_start>:
0: 0800 lsrs r0, r0, #32
2: 2000 movs r0, #0
4: 0009 lsls r1, r1, #0
...
00000008 <start>:
8: 200a movs r0, #10
a: 2100 movs r1, #0
0000000c <loop>:
c: 1809 adds r1, r1, r0
e: 3801 subs r0, #1
10: d1fc bne.n c <loop>
00000012 <deadloop>:
12: e7fe b.n 12 <deadloop>
19.3.2 2

example2a.s example2b.s
.global
========== example2a.s ==========
/* */
.global vectors_table
.global start
.global nmi_handler
.code 16
.syntax unified
vectors_table:
.word STACK_TOP, start, nmi_handler, 0x00000000
.end
========== end of file ==========
========== example2b.s ==========

/* */
.text
.global _start
.global start
.global nmi_handler
.code 16
.syntax unified
.type nmi_handler, function
_start:
/* */
256
Cortex-M3 19
start:
movs r0, #10
movs r1, #0
/* 10+9+8...+1 */
loop:
adds r1, r0
subs r0, #1
bne loop
/* R1 */
deadloop:
b deadloop
/* NMI */
nmi_handler:
bx lr
.end
========== end of file ==========

1. example2a.s
$> arm-none-eabi-as -mcpu=cortex-m3 -mthumb example2a.s -o example2a.o
2. example2b.s
$> arm-none-eabi-as -mcpu=cortex-m3 -mthumb example2b.s -o example2b.o
3. 2

$> arm-none-eabi-ld -Ttext 0x0 -o example2.out example2a.o example2b.o
4.
5.
make
19.3.3 3Hello World

hello world
UART 20 C UART
========== example3a.s ==========
/* */
.global vectors_table
.global _start
.code 16
.syntax unifi ed
vectors_table:
.word STACK_TOP, _start
.end
257
Cortex-M3 19
========== end of file ==========
========== example3b.s ==========

.text
.global _start
.code 16
.syntax unifi ed
.type _start, function
_start:
/* */
movs r0, #0
movs r1, #0
movs r2, #0
movs r3, #0
movs r4, #0
movs r5, #0
ldr r0, =hello
bl puts
movs r0, #0x4
bl putc
deadloop:
b deadloop
hello:
.ascii "Hello\n"
.byte 0
.align
puts:
/* UART */
/* r0 = */
/* */
push {r0, r1, lr} /* */
mov r1, r0 /* R1 */
/* R0 putc */
putsloop:
ldrb.w r0, [r1], #1 /* */
cbz r0, putsloopexit /* NULL */
bl putc
b putsloop
putsloopexit:
pop {r0, r1, pc} /* */
.equ UART0_DATA, 0x4000C000
.equ UART0_FLAG, 0x4000C018
putc:
/* UART */
258
Cortex-M3 19
/* R0 = */
push {r1, r2, r3, lr} /* */
ldr r1, =UART0_FLAG
putcwaitloop:
ldr r2, [r1] /* */
tst.w r2, #0x20 /* */
bne putcwaitloop /* */
ldr r1, =UART0_DATA /* */
str r0, [r1]
pop {r1, r2, r3, pc} /* */
.end
========== end of file ==========
.ascii .byte
.align .align

$> arm-none-eabi-as -mcpu_cortex-m3 -mthumb example3a.s -o example3a.o
$> arm-none-eabi-as -mcpu_cortex-m3 -mthumb example3b.s -o example3b.o
$> arm-none-eabi-ld -Ttext 0x0 -o example3.out example3a.o example3b.o
19.3.4 4 RAM
RW RAM RAM
========== example4.s ==========
.text
.global _start
.code 16
.syntax unified
_start:
.word STACK_TOP, start
start:
movs r0, #10
movs r1, #0
/* 10+9+1 */
loop:
adds r1, r0
subs r0, #1
bne loop
/* R1 */
ldr r0, =result
str r1, [r0]
259
Cortex-M3 19
deadloop:
b deadloop
/* */
.data
result:
.word 0
.end
========== end of fi le ==========
.data .word
4 Result result C

RAM -Tdata
$> arm-none-eabi-as -mcpu_cortex-m3 -mthumb example4.s -o example4.o

$> arm-none-eabi-ld -Ttext 0x0 -Tdata 0x20000000 -o example4.out
example4.o
$> arm-none-eabi-objcopy -Obinary R .data example4.out example4.bin
objcopy -R .data
19.3.5 5 C
GNU C
MSP C
C
========== example5.c ==========
#define STACK_TOP 0x20000800
//
void myputs(char *string1);
void myputc(char mychar);
int main(void);
void nmi_handler(void);
void hardfault_handler(void);
//
__attribute__ (( section(vectors) )) void (* const VectorArray[])(void) =
{
STACK_TOP,
main,
nmi_handler,
hardfault_handler
};
//
int main(void)
260
Cortex-M3 19
{
const char *helloworld[]="Hello world\n";
*NVIC_CCR = *NVIC_CCR | 0x200; /* NVIC STKALIGN */
myputs(*helloworld);
while(1);
return(0);
}
//
void myputs(char *string1)
{
char mychar;
int j;
j=0;
do
{
mychar = string1[j];
if (mychar!=0)
{
myputc(mychar);
j++;
}
} while (mychar != 0);
return;
}
void myputc(char mychar)
{
#define UART0_DATA ((volatile unsigned long *)(0x4000C000))
#define UART0_FLAG ((volatile unsigned long *)(0x4000C018))
// Wait until busy fl ag is clear
while ((*UART0_FLAG & 0x20) != 0);
// Output character to UART
*UART0_DATA = mychar;
return;
}
//
void nmi_handler(void)
{
return;
}
void hardfault_handler(void)
{
261
Cortex-M3 19
return;
}
========== end of file ==========
__attribute(( ))
vectors C vectors
vectors
simple.ld
========== simple.ld ==========
/* MEMORY */
/* */
/* */
/* */
MEMORY
{
/* ROM (r)(x) */
rom (rx) : ORIGIN = 0, LENGTH = 2M
/* RAM (r)(w)(x) */
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4M
}
/* SECTIONS : */
SECTIONS
{
. = 0x0; /* 0x00000000 */
.text : {
*(vectors) /* */
*(.text) /* */
*(.rodata) /* */
}
. = 0x20000000; /* 0x20000000 */
.data : {
*(.data) /* */
}
.bss : {
*(.bss) /* */
}
}
========== end of file ==========
simple.ld
$> arm-none-eabi-gcc -mcpu_cortex-m3 -mthumb example5.c -nostartfiles
-T simple.ld -o example5.o
simple.ld
$> arm-none-eabi-ld -T simple.ld -o example5.out example5.o

262
Cortex-M3 19

-nostartfiles
(crt)
GNU
CM3 ARM ARM7
ARM Thumb

bss
19.3.6 6 C C
C C
C GNU
CodeSourcery GNU ARM 2006q3-26
CodeSourcery armv7m-crt0.o
ARM 2006q3-27 bug
GNU
GNU
C 5 C armv7m-crt0
NMI fault _nmi_isr
_fault_isr 5 NMI Fault
//
void myputs(char *string1);
void myputc(char mychar);
int main(void);
void _nmi_isr(void);
void _fault_isr(void);
//
int main(void)
{
const char *helloworld[]="Hello world\n";
myputs(*helloworld);
while(1);
return(0);
}
//
void myputs(char *string1)
{
263
Cortex-M3 19
char mychar;
int j;
j=0;
do
{
mychar = string1[j];
if (mychar!=0)
{
myputc(mychar);
j++;
}
} while (mychar != 0);
return;
}
void myputc(char mychar)
{
// Wait until busy fl ag is clear
while ((*UART0_FLAG & 0x20) != 0);
// Output character to UART
*UART0_DATA = mychar;
return;
}
//
void _nmi_isr(void)
{
return;
}
void _fault_isr(void)
{
return;
}
CodeSourcery codesourcery/sourcery
g++/arm-none-eabi/lib lm3s8xx-rom.ld
LM3S8XX
Clib
Aside from the current directory, when the C program code is located, a library subdirectory called lib
is also created in the current directory
armvrm-crt0.olib-L lib
lib
264
Cortex-M3 19
C
$> arm-none-eabi-gcc mcpu=cortex-m3 -mthumb example6.c -L lib T
lm3s8xx-rom.ld -o example6.out
example6.out

19.4
CodeSourceryGNU ARM

msr control, r1
mrs r1, control
msr apsr, r1
mrs r0, psr
19.5
GNUGNU
.word
.equ DW_MSR_CONTROL_R0, 0x8814F380
...
MOV R0, #0x1
.word DW_MSR_CONTROL_R0 /* MSR CONTROL, R0 */
...
19.6 GNU C
GNUARM C
__asm (" inst1 op1, op2... \n"
" inst2 op1, op2... \n"
...
" inst op1, op2... \n"
: s /* */
: s /* */

void Sleep(void)
{
// Wait-For-Interrupt
__asm (
WFI\n
);
265
Cortex-M3 19
}
5
__asm ( "mov r0, %0\n"
"mov r3, #5\n"
"udiv r0, r0, r3\n"
"mov %1, r0\n"
: "=r" (DataOut) : "r" (DataIn) : "cc", "r3" );
CDataIn%0
CDataOut%12r3
ccclobbered
GCC-Inline-Assembly-HOWTO
266
Cortex-M3 20
20
KEIL RealView Microcontroller
Development KitRVMDK

uVision
UART Hello World

20.1
CM3 KEIL RealView
Microcontroller Development Kit RealView MDK RVMDKRVMDK
8051 KEIL RVMDK
uVision

ARM RealView
C/C++

RTX

Flash

RVMDK RVMDK
RVMDK CM3 CM3 uVison
CM3
RVMDK GNU
KEIL KEIL tool
http://www.realview.com.cn/
267
Cortex-M3 20
20.2 uVison
RVMDK Luminary Micro Stellaris
ST STM32
RVMDK v3.03
Luminary Micro LM3S811 RVMDK 3.20
Luminary Micro CM3 ST STM32 CM3
Atmel, TI, NXP CM3
RVMDK uVision
ARM New Project
CortexM3
268
Cortex-M3 20
LM3S811
RVMDK Yes
Startup.s
main C
hello.c
269
Cortex-M3 20
Source Group 1 Source Group 1
Target 1Source Group 1

hello.c 2
Misc Controls box entry
270
Cortex-M3 20
Reset_Handler Reset_Handler
Startup.s RVMDK 3.20
271
Cortex-M3 20
20.3 UART Hello World

CprintfC
UART
retargeting
Retargeting
Hello WorldLM3S811UART0Luminary
Micro LM3S8116MHzPLL50MHz
115,200PCUART
printfretargetfputc
fputcsendcharUART
#include "stdio.h"
#define CR 0x0D //
#define LF 0x0A //
void Uart0Init(void);
void SetClockFreq(void);
int sendchar(int ch);
// 6MHz
#define CLOCK50MHZ
// Register addresses
#define SYSCTRL_RCC ((volatile unsigned long *)(0x400FE060))
#define SYSCTRL_RIS ((volatile unsigned long *)(0x400FE050))
#define SYSCTRL_RCGC1 ((volatile unsigned long *)(0x400FE104))
#define GPIOPA_AFSEL ((volatile unsigned long *)(0x40004420))
#define UART0_IBRD ((volatile unsigned long *)(0x4000C024))
#define UART0_FBRD ((volatile unsigned long *)(0x4000C028))
#define UART0_LCRH ((volatile unsigned long *)(0x4000C02C))
#define UART0_CTRL ((volatile unsigned long *)(0x4000C030))
#define UART0_RIS ((volatile unsigned long *)(0x4000C03C))
int main (void)
272
Cortex-M3 20
{
SetClockFreq(); // (50MHz/6MHz)
Uart0Init(); // UART0
printf ("Hello world!\n");
while (1);
}
void SetClockFreq(void)
{
#ifdef CLOCK50MHZ
// BYPASS, USRSYSDIV SYSDIV
*SYSCTRL_RCC = (*SYSCTRL_RCC & 0xF83FFFFF) | 0x800 ;
// OSCSRC, PWRDN OEN
*SYSCTRL_RCC = (*SYSCTRL_RCC & 0xFFFFCFCF);
// SYSDIV, USRSYSDIV Crystal
*SYSCTRL_RCC = (*SYSCTRL_RCC & 0xF87FFC3F) | 0x01C002C0;
// PLLLRIS
while ((*SYSCTRL_RIS & 0x40)==0); // wait until PLLLRIS is set
// bypass
*SYSCTRL_RCC = (*SYSCTRL_RCC & 0xFFFFF7FF) ;
#else
// BYPASS, USRSYSDIV SYSDIV
#endif
return;
}
void Uart0Init(void)
{
*SYSCTRL_RCGC1 = *SYSCTRL_RCGC1 | 0x0003; // UART0 & UART1
// clock
*SYSCTRL_RCGC2 = *SYSCTRL_RCGC2 | 0x0001; // PORTA
*UART0_CTRL = 0; // UART
# ifdef CLOCK50MHZ
*UART0_IBRD = 27; // 50MHz
*UART0_FBRD = 9;
# else
*UART0_FBRD = 17;
# endif
*UART0_LCRH = 0x60; // 8 bit,
*UART0_CTRL = 0x301; // TX RX, UART
*GPIOPA_AFSEL = *GPIOPA_AFSEL | 0x3; // GPIOUART0
return;
}
// UART0printf
273
Cortex-M3 20
int sendchar (int ch)

{
if (ch == '\n')
{
while ((*UART0_FLAG & 0x8)); // UART
*UART0_DATA = CR; // CR
}
while ((*UART0_FLAG & 0x8)); // UART
return (*UART0_DATA = ch); //
}
//retargeting
int fputc(int ch, FILE *f)
{
return (sendchar(ch));
}
SetupClockFreq()50MHz
6MHz
UARTUart0Init()11520081
GPIOGPIOUART0
UARTGPIOSYSCTRL_RCGC1SYSCTRL_RCGC2
Retargetingfputc()
fputcfputc()
sendchar()sendchar()\n
CR
retargeting
20.4
Flash
1. flash
2.
274
Cortex-M3 20
3. flash
4.
20.5
uVision
JTAG
Debug

USB
275
Cortex-M3 20
IDE
Reset_Handler
main()
Insert/Remove Breakpoint
main()
276
Cortex-M3 20
main()SetClockFreq()25
277
Cortex-M3 20

PUSH r4,lr

20.6
uVison IDECM3
DebugSimulator:

NVIC
278
Cortex-M3 20
SVC
279
Cortex-M3 20

fault
UART
280
Cortex-M3 20
UART0x4000_C000-0x4000_DFFFRVMDK
RVMDK
RVMDKRVMDK
------------
uVision IDE

RVMDK
RVMDKARMRealView MDK

20.7
Startup.s
MSPNMIfault
Startup.s
ISRStartup.sstartup.s
startup.oISRIMPORTIMPORT
Cextern
IMPORT
281
Cortex-M3 20
20.8

SysTickUART0
PCUART
50MHzSysTick100Hz
SysTick50MHz(FCLK)SysTick
1TickCounter
UART
mani()
UART
stopwatch
stopwatch.c
#include "stdio.h"
#define CR 0x0D // Carriage return
#define LF 0x0A // Linefeed
void Uart0Init(void);
void SysTickInit(void);
void SetClockFreq(void);
void DisplayTime(void);
void PrintValue(int value);
int sendchar(int ch);
int getkey(void);
void Uart0Handler(void);
void SysTickHandler(void);
//
#define SYSCTRL_RCC ((volatile unsigned long *)(0x400FE060))
#define SYSCTRL_RIS ((volatile unsigned long *)(0x400FE050))
282
Cortex-M3 20

#define GPIOPA_AFSEL ((volatile unsigned long *)(0x40004420))
#define UART0_IBRD ((volatile unsigned long *)(0x4000C024))
#define UART0_FBRD ((volatile unsigned long *)(0x4000C028))
#define UART0_LCRH ((volatile unsigned long *)(0x4000C02C))
#define UART0_CTRL ((volatile unsigned long *)(0x4000C030))
#define UART0_IM ((volatile unsigned long *)(0x4000C038))
#define UART0_RIS ((volatile unsigned long *)(0x4000C03C))
#define UART0_ICR ((volatile unsigned long *)(0x4000C044))
#define NVIC_IRQ_EN0 ((volatile unsigned long *)(0xE000E100))
//
volatile int CurrState; //
volatile unsigned long TickCounter; //
volatile int KeyReceived; //
volatile int userinput ; //
#define IDLE_STATE 0 //
#define RUN_STATE 1
#define STOP_STATE 2
int main (void)
{
int CurrStateLocal; //
//
CurrState = 0;
KeyReceived = 0;
//
SetClockFreq(); //
Uart0Init();
SysTickInit();
printf ("Stop Watch\n");
while (1)
{
CurrStateLocal = CurrState; //
// SysTick ISR
switch (CurrStateLocal) {
case (IDLE_STATE):
printf ("\nPress any key to start\n");
break;
case (RUN_STATE):
printf ("\nPress any key to stop\n");
break;
case (STOP_STATE):
printf ("\nPress any key to clear\n");
283
Cortex-M3 20
break;
default:
CurrState = IDLE_STATE;
break;
} // end of switch
while (KeyReceived == 0)
{
if (CurrState==RUN_STATE)
{
DisplayTime();
}
}; //
if (CurrStateLocal==STOP_STATE)
{
TickCounter=0;
DisplayTime(); //
}
else if (CurrStateLocal==RUN_STATE)
{
DisplayTime(); //
}
if (KeyReceived!=0) KeyReceived=0;
}; // end of while loop
} // end of main
void SetClockFreq(void)
{
// Set BYPASS, clear USRSYSDIV and SYSDIV
// Clr OSCSRC, PWRDN and OEN
*SYSCTRL_RCC = (*SYSCTRL_RCC & 0xFFFFCFCF);
// SYSDIV, USRSYSDIV Crystal
*SYSCTRL_RCC = (*SYSCTRL_RCC & 0xF87FFC3F) | 0x01C002C0;
// PLLRIS
while ((*SYSCTRL_RIS & 0x40)==0); // PLLLRIS
// bypass
*SYSCTRL_RCC = (*SYSCTRL_RCC & 0xFFFFF7FF) ;
return;
}
// UART0
void Uart0Init(void)
{
*SYSCTRL_RCGC1 = *SYSCTRL_RCGC1 | 0x0003; // UART0 & UART1
*SYSCTRL_RCGC2 = *SYSCTRL_RCGC2 | 0x0001; // PORTA
284
Cortex-M3 20
*UART0_CTRL = 0; // UART
*UART0_FBRD = 9;
*UART0_LCRH = 0x60; // 8 bit,
*UART0_CTRL = 0x301; // TX RX, UART
*UART0_IM = 0x10; // UART
*GPIOPA_AFSEL = *GPIOPA_AFSEL | 0x3; // UART0GPIO
*NVIC_IRQ_EN0 = (0x1<<5); // NVICUART
return;
}
// SYSTICK
void SysTickInit(void)
{
#define NVIC_STCSR ((volatile unsigned long *)(0xE000E010))
#define NVIC_RELOAD ((volatile unsigned long *)(0xE000E014))
#define NVIC_CURRVAL ((volatile unsigned long *)(0xE000E018))
#define NVIC_CALVAL ((volatile unsigned long *)(0xE000E01C))
*NVIC_STCSR = 0; // SYSTICK
*NVIC_RELOAD = 499999; // 50MHz100Hz
*NVIC_CURRVAL = 0; //
*NVIC_STCSR = 0x7; // SYSTICK
return;
}
// SYSTICK
void SysTickHandler(void)
{
if (CurrState==RUN_STATE) {
TickCounter++;
}
return;
}
// UART0 RX
void Uart0Handler(void)
{
userinput = getkey();
//
KeyReceived++;
// UART
*UART0_ICR = 0x10;
//
switch (CurrState)
{
case (IDLE_STATE):
CurrState = RUN_STATE;
285
Cortex-M3 20
break;
case (RUN_STATE):
CurrState = STOP_STATE;
break;
case (STOP_STATE):
break;
default:
break;
} // end of switch
return;
}
//
void DisplayTime(void)
{
unsigned long TickCounterCopy;
unsigned long TmpValue;
sendchar(CR);
TickCounterCopy = TickCounter; //
// SysTick ISR
TmpValue = TickCounterCopy / 6000; //
PrintValue(TmpValue);
TickCounterCopy = TickCounterCopy - (TmpValue * 6000);
TmpValue = TickCounterCopy / 100; //
sendchar(':');
PrintValue(TmpValue);
TmpValue = TickCounterCopy - (TmpValue * 100);
sendchar(':');
PrintValue(TmpValue); // 1/100
sendchar(' ');
sendchar(' ');
return;
}
// 10
void PrintValue(int value)
{
printf ("%d", value);
return;
}
// UART0printf
int sendchar (int ch)
{
if (ch == '\n')
286
Cortex-M3 20
while ((*UART0_FLAG & 0x20)); // TXFIFO

*UART0_DATA = CR; // CR
}
while ((*UART0_FLAG & 0x20)); // TXFIFO
return (*UART0_DATA = ch); //
}
//
int getkey (void)
{
//
while (*UART0_FLAG & 0x10); // Rx FIFO
return (*UART0_DATA);
}
// retarget
int fputc(int ch, FILE *f)
{
return (sendchar(ch));
}
UARTUART
NVICSysTickNVICCM3
UARTSysTickSysTick
UART0_ICR
startup.sstartup.s
IMPORT
287
Cortex-M3 20
COM
COMbugRVMDK
PC
288
Cortex-M3 20
4
C
.s
movmovtpush/popC
MovMovTTest.h.c
void MovMovTTest(void);
ARM

Add3
add r0, r0, r1
add r0, r0, r2
bx lr
C
int Add3(int a, int b, int c); //a+b+c

4C

289
Cortex-M3 20
290
Cortex-M3 A
Cortex-M3
Cortex-M3C
U8unsigned char16
U16unsigned short16
S8signed char8
S16signed short16
charshort
CRn[Rm]Rn+Rm
32
C/
Rn[Rm]
*( (U32 *) (Rn+Rm) )Rn,Rm32

{S}SAPSR
1-1 16 Cortex-M3

Rd+= Rm+C ADC <Rd>, <Rm>
Rd= Rn+Imm3 ADD <Rd>, <Rn>, #<immed_3>
Rd+= Imm8 ADD <Rd>, #<immed_8>
Rd=Rn+Rm ADD <Rd>, <Rn>, <Rm>
Rd+=Rm ADD <Rd>, <Rm>
Rd=PC+Imm8*4 ADD <Rd>, PC, #<immed_8>*4
Rd=SP+Imm8*4 ADD <Rd>, SP, #<immed_8>*4
Rd=SP+Imm7*4 ADD <Rd>, SP, #<immed_7>*4 ADD SP, SP,

SP+=Imm7*4 #<immed_7>*4
Rd &= Rm AND <Rd>, <Rm>
Rd = Rm Imm5 ASR <Rd>, <Rm>, #<immed_5>
Rd = Rs ASR <Rd>, <Rs>
291
Cortex-M3 A

<contd> B<cond> <target address>
B<tartet address>
Rd &= ~Rs BIC <Rd>, <Rs>
BKPT <immed_8>
BL <Rm>
CBNZ <Rn>, <label>
CBZ <Rn>, <Rm>
Rm Rn CMN <Rn>, <Rm>

Rn 8 CMP <Rn>, #<immed_8>

Rn Rm CMP <Rn>, <Rm>
, CMP <Rn>, <Rm>

CPS <effect>, <iflags>
CPY <Rd>, <Rm>

Rd^=Rm EOR <Rd>, <Rm>
IT<cond>
IT<x> <cond>
IT<x><y> <cond>
IT<x><y><z> <cond>

LDMIA <Rn>!, <register>
5 LDR <Rd>, [<Rn>, #<immed_5*4>]

Rd= Rn[Imm5*4]
Rd= Rn[Rm] LDR <Rd>, [<Rn>, <Rm>]
Rd= PC[Imm8*4+4] LDR <Rd>, [PC, #<immed_8>*4]

Rd= SP[Imm8*4] LDR <Rd>, [SP, #<immed_8>*4]
Rd= (U8) Rn[Imm5] LDRB <Rd>, [<Rn>, #<immed_5>]
Rd= (U8) Rn[Rm] LDRB <Rd>, [<Rn>, <Rm>]
Rd= (U16) Rn[Imm5*2] LDRH <Rd>, [<Rn>, #<immed_5>*2]
Rd= (U16) Rn[Rm] LDRH <Rd>, [<Rn>, <Rm>]
Rn+Rm , LDRSB <Rd>, [<Rn>, <Rm>]

Rd
Rn+Rm , LDRSH <Rd>, [<Rn>, <Rm>]

Rd
Rd= Rm<<Imm5 LSL <Rd>, <Rm>, #<immed_5>

Rd<<= Rs LSL <Rd>, <Rs>
Rd= Rm>>Imm5 LSR <Rd>, <Rm>, #<immed_5>
Rd>>= Rs LSR <Rd>, <Rs>
Rd= (U32) Imm8 MOV <Rd>, #<immed_8>
292
Cortex-M3 A

Rd=Rn MOV <Rd>, <Rn>
Rd=Rm MOV MOV <Rd>, <Rm>

Rd*=Rm MUL <Rd>, <Rm>
Rd= ~Rm
MVN <Rd>, <Rm>
Rd= ~Rm + 1 NEG <Rd>, <Rm>
NOP <C>
Rd|= Rm ORR <Rd>, <Rm>
POP <>
PC POP <PC>
PUSH <registers>
LR PUSH <registers, LR>

Rd=Rn REV <Rd>, <Rn>
Rd=Rn REV16 <Rd>, <Rn>
Rn REVSH <Rd>, <Rn>

32 Rd
Rd = Rs ROR <Rd>, <Rs>

Rd-= Rm+C SBC <Rd>, <Rm>
SEV <c>
STMIA <Rn>!, <registers>

Rn Rn+4
Rn[Imm5*4]=Rd STR <Rd>, [<Rn>, #<immed_5>*4]
Rn[Rm]=Rd STR <Rd>, [<Rn>, <Rm>]
SP[Imm8*4]=Rd STR <Rd>, [SP, #<immed_8> * 4]
*( (U8*) (Rn+Imm5) ) = (U8) Rd STRB <Rd>, [<Rn>, #<immed_5>]
*( (U8*) (Rn+Rm) ) = (U8) Rd STRB <Rd>, [<Rn>, <Rm>]

*( (U16*) (Rn+Imm5*2) ) = (U16) Rd STRH <Rd>, [<Rn>, #<immed_5> * 2]
*( (U16*) (Rn+Rm) ) = (U16) Rd STRH <Rd>, [<Rn>, <Rm>]

Rd-= Imm8 SUB <Rd>, #<immed_8>
Rd= Rn-Rm SUB <Rd>, <Rn>, <Rm>
SP-= Imm7*4 SUB SP, #<immed_7> * 4
8 SVC <immed_8>
[7:0] SXTB <Rd>, <Rm>

32
[15:0] SXTH <Rd>, <Rm>

32
Rn & Rm TST <Rn>, <Rm>
[7:0] UXTB <Rd>, <Rm>

32
Rd= (U8) Rm
293
Cortex-M3 A

[15:0] UXTH <Rd>, <Rm>
32
Rd= (U16) Rm
WFE <c>
WFI <c>
1-2 32 Coxtex-M3 1-2 32 Coxtex-M3

Rd=Rn+Imm12+CS ADC{S}.W <Rd>, <Rn>,
S #<modify_constant(immed_12>
Rd= RnRmC ADC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Rd= Rn+Imm12 ADD{S}.W <Rd>,
<Rn>,#<modify_constant(immed_12)>
Rd=RdRm ADD{S}.W <Rd>, <Rm>{, <shift>}
Rd= Rn+Imm12 ADDW.W <Rd>, <Rn>, #<immed_12>
Rd= Rn & Imm12 AND{S}.W <Rd>, <Rn>,
#<modify_constant(immed_12>
Rd=RnRm AND{S}.W <Rd>, <Rn>, Rm>{, <shift>}
Rd = Rn>>RmS ASR{S}.W <Rd>, <Rn>, <Rm>
B{cond}.W <label>
BFC.W <Rd>, #<lsb>, #<width>
BFI.W <Rd>, <Rn>, #<lsb>, #<width>

Rd= Rn & ~Imm12 BIC{S}.W <Rd>, <Rn>,
#<modify_constant(immed_12)>
Rd&= Rn BIC{S}.W <Rd>, <Rn>, {, <shift>}
BL <label>
BL<c> <label>
B.W <label>
Rd=Rn CLZ.W <Rd>, <Rn>
Rn12 CMN.W <Rn>, #<modify_constant(immed_12)>
RnRm CMN.W <Rn>, <Rm>{, <shift>}

Rn12 CMP.W <Rn>, #<modify_constant(immed_12)>
RnRm CMP.W <Rn>, <Rm>{, <shift>}

Rm
DMB <c>
DSB <c>
Rd= Rn ^ Imm12 EOR{S}.W <Rd>, <Rn>,
Rd=RnRm EOR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Rm
barrier ISB <c>
4 LDM{IA|DB}.W <Rn>{!}, <registers>

4
Rxf= Rn[ofs12] LDR.W <Rxf>, [<Rn>, #<offset_12>]

PC= Rn[ofs12] LDR.W PC, [<Rn>, #<offset_12>]
294
Cortex-M3 A

LDR.W PC, #<+/-<offset_8>
Rxf= *Rn; LDR.W <Rxf>, [<Rn>], #+/<offset_8>
Rn+= ofs8;
Rn+= ofs8; LDR.W <Rxf>, [<Rn>, #<+/<offset_8>]!

Rxf= *Rn
PC= Rn[ofs8]; LDR.W PC, [<Rn>, #+/<offset_8>]!

Rn+= ofs8
Rxf=Rn[Rm] LDR.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]

0,1,2,3
PC=Rn[Rm] LDR.W PC, [<Rn>, <Rm>{, LSL #<shift>}]

0,1,2,3
Rxf= PC[ofs12] LDR.W <Rxf>, [PC, #+/<offset_12>]
PC= PC[ofs12] LDR.W PC, [PC, #+/<offset_12>]
Rxf=(U8) Rn[ofs12] LDRB.W <Rxf>, [<Rn>, #<offset_12>]
Rxf= (U8) *Rn; LDRB.W <Rxf>. [<Rn>], #+/-<offset_8>

Rn+= ofs8
Rxf= (U8) Rn[Rm]; LDRB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]

0,1,2,3
Rxf= Rn[ofs8]; LDRB.W <Rxf>, [<Rn>, #<+/<offset_8>]!

Rn+= ofs8
Rxf= PC[ofs12] LDRB.W <Rxf>, [PC, #+/<offset_12>]
Rn84 LDRD.W <Rxf>, <Rxf2>, [<Rn>, #+/<offset_8>

Rxf(32), Rxf2(32) * 4]{!}
Rn
RnRxf(32), Rxf2( LDRD.W <Rxf>, <Rxf2>, [<Rn>],
32)Rn+= ofs8*4 #+/<offset_8> * 4
Rxf= (U16) Rn[ofs12] LDRH.W <Rxf>, [<Rn>, #<offset_12>]
Rxf= (U16) Rn[ofs8]; LDRH.W <Rxf>, [<Rn>, #<+/<offset_8>]!

Rn+=ofs8;
Rxf= (U16) *Rn; LDRH.W <Rxf>. [<Rn>], #+/-<offset_8>

Rn+= ofs8;
Rxf= (U16) Rn[Rm]; LDRH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]

0,1,2,3
Rxf= (U16) PC[ofs12] LDRH.W <Rxf>, [PC, #+/<offset_12>]
295
Cortex-M3 A

Rn+ofs12 LDRSB.W <Rxf>, [<Rn>, #<offset_12>]
Rxf
RnRxf LDRSB.W <Rxf>. [<Rn>], #+/-<offset_8>

Rn+=ofs8
Rn+=ofs8Rn LDRSB.W <Rxf>, [<Rn>, #<+/<offset_8>]!

Rxf
Rm0,1,2,3 LDRSB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]

Rn+Rm
Rxf
PC+ofs12 LDRSB.W <Rxf>, [PC, #+/<offset_12>]
Rxf
Rn+ofs12 LDRSH.W <Rxf>, [<Rn>, #<offset_12>]

Rxf
RnRxf LDRSH.W <Rxf>. [<Rn>], #+/-<offset_8>

Rn+=ofs8
Rn+=ofs8Rn LDRSH.W <Rxf>, [<Rn>, #<+/<offset_8>]!

Rxf
Rm0,1,2,3 LDRSH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]

Rn+Rm
Rxf
PC+ofs12 LDRSH.W <Rxf>, [PC, #+/<offset_12>]
Rxf
Rd= Rn<<Rm LSL{S}.W <Rd>, <Rn>, <Rm>

Rd= Rn>>Rm LSR{S}.W <Rd>, <Rn>, <Rm>
Rd= Racc+Rn*Rm MLA.W <Rd>, <Rn>, <Rm>, <Racc>
Rd=Racc-Rn*Rm MLS.W <Rd>, <Rn>, <Rm>, <Racc>
Rd= Imm12 MOV{S}.W <Rd>,

RmRd=Rm MOV{S}.W <Rd>, <Rm>{, <shift>}
16Rd Rd MOVT.W <Rd>, #<immed_16>

16Rd MOVW.W <Rd>, #<immed_16>

Rd MRS<c> <Rd>, <psr>
Rn MSR<c> <psr>_<fields>,<Rn>
Rd= Rn*Rm MUL.W <Rd>, <Rn>, <Rm>
NOP.W
Rd= Rn | ~Imm12 ORN{S}.W <Rd>, <Rn>,
Rm ORN[S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Rd= Rn | ~Rm
Rd= Rn | Imm12 ORR{S}.W <Rd>, <Rn>,
#<modify_constant(immed_12)
296
Cortex-M3 A

Rm ORR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Rd= Rn | Rm
Rd=Rm RBIT.W <Rd>, <Rm>
Rd=Rm REV.W <Rd>, <Rm>
Rd=Rn REV16.W <Rd>, <Rn>
Rd=Rn REVSH.W <Rd>, <Rn>
Rd= RnRm ROR{S}.W <Rd>, <Rn>, <Rm>

Rd= Imm12-Rd RSB{S}.W <Rd>, <Rn>,
Rm RSB{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Rd= Rm-Rn
Rd= Imm12-Rn-C SBC{S}.W <Rd>, <Rn>,
Rm SBC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Rd=Rn-Rm-C
Rnlsbwidth SBFX.W <Rd>, <Rn>, #<lsb>, #<width>
Rd
, Rd= Rn/Rm SDIV<c> <Rd>,<Rn>,<Rm>
SEV<c>
64RdHi:RdLo+= Rn*Rm SMLAL.W <RdLo>, <RdHi>, <Rn>, <Rm>
64RdHi:RdLo= Rn*Rm SMULL.W <RdLo>, <RdHi>, <Rn>, <Rm>
RnRnImm SSAT <c> <Rd>, #<imm>, <Rn>{, <shift>}

Rd
Rn STM{IA|DB}.W <Rn>{!}, <registers>
Rn(IA)/
(DB)
Rn[ofs12]=Rxf STR.W <Rxf>, [<Rn>, #<offset_12>]
*Rn=Fxf; STR.W <Rxf>, [<Rn>], #+/<offset_8>
Rn+=ofs8
Rm STR.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Rn[Rm]=Rxf0,1,2,3
Rn[ofs8]=Rxf STR{T}.W <Rxf>, [<Rn>, #+/<offset_8>]{!}

Rn+=ofs8
*( (U8*) (Rn+ofs8) ) = (U8) Rxf STRB{T}.W <Rxf>, [<Rn>, #+/<offset_8>]{!}
Rn+=ofs8
*( (U8*) (Rn+ofs12) ) = (U8) Rxf STRB.W <Rxf>, [<Rn>, #<offset_12>]
*( (U8*) Rn ) = (U8) Rxf STRB.W <Rxf>, [<Rn>], #+/<offset_8>

Rn+=ofs8
Rm0,1,2,3 STRB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]

*( (U8*) (Rn+Rm) ) = (U8) Rxf
*(Rn+ofs8*4)=Rxf; STRD.W <Rxf>, <Rxf2>, [<Rn>, #+/<offset_8>

*(Rn+ofs8*4+4)=Rxf2 * 4]{!}
Rn+=ofs8
*Rn=Rxf; STRD.W <Rxf>, <Rxf2>, [<Rn>],
*(Rn 4)=Rxf2; #+/<offset_8> * 4
Rn+=ofs8*4
*( (U16*) (Rn+ofs12) ) = (U16) Rxf STRH.W <Rxf>, [<Rn>, #<offset_12>]
Rm0,1,2,3 STRH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]

*( (U16*) (Rn+Rm) ) = (U16) Rxf
297
Cortex-M3 A

*( (U16*) (Rn+ofs8) ) = (U16) Rxf STRH{T}.W <Rxf>, [<Rn>, #+/<offset_8>]{!}
Rn+=ofs8
*( (U16*) Rn ) = (U16) Rxf STRH.W <Rxf>, [<Rn>], #+/<offset_8>

Rn+=ofs8
Rd= Rn-Imm12 SUB{S}.W <Rd>, <Rn>,

Rm SUB{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Rd= Rn-Rm
Rd= Rn-Imm12 SUBW.W <Rd>, <Rn>, #<immed_12>
RmRm8 SXTB.W <Rd>, <Rm>{, <rotation>}

32Rd
RmRm16 SXTH.W <Rd>, <Rm>{, <rotation>}
32Rd
PC+= ( (U8)*(Rn+Rm) )*2 TBB [<Rn>, <Rm>]
PC+= ( (U16)*(Rn+Rm*2) )*2 TBH [<Rn>, <Rm>, LSL #1]
RnImm12 TEQ.W <Rn>, #<modify_constant(immed_12)>

Rm TEQ.W <Rn>, <Rm>{, <shift>}
RnRm
RnImm12 TST.W <Rn>, #<modify_constant(immed_12)>
Rm TST.W <Rn>, <Rm>{, <shift>}

RnRm
Rnlsbwidth UBFX.W <Rd>, <Rn>, #<lsb>, #<width>

Rd
Rd= Rn/Rm UDIV<c> <Rd>,<Rn>,<Rm>
64RdHi:RdLo+= Rn*Rm UMLAL.W <RdLo>, <RdHi>, <Rn>, <Rm>
64RdHi:RdLo= Rn*Rm UMULL.W <RdLo>, <RdHi>, <Rn>, <Rm>

RnRnImm USAT <c> <Rd>, #<imm>, <Rn>{, <shift>}
Rd

RmRm8 UXTB.W <Rd>, <Rm>{, <rotation>}
32Rd
RmRm16 UXTH.W <Rd>, <Rm>{, <rotation>}

32Rd
WFE.W
WFI.W
298
Cortex-M3 B-D
16 Thumb
B.1 ARM 16
v4T v5T v6 Cortex-M3(v7-M)

BKPT Y Y Y
BLX Y Y BLX <reg>
CBZ,CBNZ Y
CPS Y CPSIE <i/f>, CPSID <i/f>
CPY Y Y
NOP Y
IT Y
REV() Y Y
SEV Y
SETEND Y
SWI Y Y Y SVC
SXTB,SXTH Y Y
UXTB,UXTH Y Y
WFI,WFE Y
299
Cortex-M3 B-D
Cortex-M3
C.1

0 N/A N/A
1 -3
2 NMI -2 NMI

3 fault -1 fault
(escalation) fault
FAULTMASK fault
Fault

PRIMASK/BASEPRI
4 Mem faultMPU NVIC SHCSR.16
Manage E000_ED18 E000_ED24
fault fault
5 fault NVIC SHCSR.17
E000_ED19 Abort E000_ED24

6 NVIC SHCSR.18
Fault E000_ED1A E000_ED24
ARM
7-10 N/A N/A
11 SVCall SVC
E000_ED1F
12 NVIC DEMCR.16
E000_ED20 E000_EDFC
13 N/A N/A
14 PendSV
E000_ED22 pendable request
15 SysTick SysTick CTRLSTAT.1
E000_ED23 E000_E010
16- IRQ E000_E400 240 NVIC SETENA
255
300
Cortex-M3 B-D
C.2 SP

SP (N-0) -

(N-4) xPSR 2
(N-8) PC 1
(N-12) LR 8
(N-16) R12 7
(N-20) R3 6
(N-24) R2 5
(N-28) R1 4
SP (N-32) R0 3
SP
((OLD_SP-4) AND 0xFFFF_FFF8)
301
Cortex-M3 B-D
NVIC
D.1 ICTR 0xE000_E004

4:0 INTLINESUM R - 32
0=1 32
1=33 64
2=65 96

D.2 SysTick0xE000_E010

16 COUNTFLAG R 0 SysTick
0 1

2 CLKSOURCE R/W 0 0=(STCLK)
1=(FCLK)
1 TICKINT R/W 0 1=SysTick 0 SysTick
0= 0
0 ENABLE R/W 0 SysTick

23:0 RELOAD R/W 0

23:0 CURRENT R/Wc 0
SysTick
COUNTFLAG
D.5 SysTick0xE000_E01C

31 NOREF R - 1=STCLK
0=
30 SKEW R - 1= 10ms
0= 10ms
302
Cortex-M3 B-D
23:0 TENMS R/W 0 10ms

Cortex-M3

D.6 SETENA/CLRENA
SETENAs: xE000_E100 0xE000_E11C ; CLRENAs:0xE000E180 - 0xE000_E19C

SETENA0 R/W 0xE000_E100 0 0-31 32
[n]#n 16+n
SETENA1 R/W 0xE000_E104 0 32-63 32

SETENA7 R/W 0xE000_E11C 0 224-239 16
CLRENA0 R/W 0xE000_E180 0 0-31 32

[n]#n 16+n
CLRENA1 R/W 0xE000_E184 0 32-63 32

CLRENA7 R/W 0xE000_E19C 0 224-239 16
D.7 SETPEND/CLRPEND
SETPENDs:0xE000_E200 0xE000_E21C ; CLRPENDs:0xE000E280 - 0xE000_E29C
SETPEND0 R/W 0xE000_E200 0 0-31 32
[n]#n 16+n
SETPEND1 R/W 0xE000_E204 0 32-63 32
SETPEND7 R/W 0xE000_E21C 0 224-239 16

303
Cortex-M3 B-D
CLRPEND0 R/W 0xE000_E280 0 0-31 32
[n]#n 16+n
CLRPEND1 R/W 0xE000_E284 0 32-63 32
CLRPEND7 R/W 0xE000_E29C 0 224-239 16

D.8 ACTIVE 0xE000_E300_0xE000_E31C

ACTIVE0 RO 0xE000_E300 0 0-31 32
[n]#n 16+n
ACTIVE1 RO 0xE000_E304 0 32-63 32

ACTIVE7 RO 0xE000_E31C 0 224-239 16

D.9 0xE000_E400 0xE000_E4EF

PRI_0 R/W 0xE000_E400 08 #0
PRI_1 R/W 0xE000_E401 08 #1

PRI_239 R/W 0xE000_E4EF 08 #239
D.10 CPUID 0xE000_ED00

31:24 R 0x41 ARM=0x41
304
Cortex-M3 B-D
23:20 R 0x0/0x1/0x02
19:16 R 0xF
15:4 R 0xC23 Part
3:0 R 0x0/0x1
D.11 ICSR 0xE000_ED04

31 NMIPENDSET R/W 0 1 NMI NMI
NMI
28 PENDSVSET R/W 0 1 PendSV PendSV

27 PENDSVCLR W 0 1 PendSV
26 PENDSTSET R/W 0 1 SysTick PendSV

25 PENDSTCLR W 0 1 SysTick
23 ISRPREEMPT R 0 1

22 ISRPENDING R 0 1= NMI
21:12 VECTPENDING R 0 ISR

11 RETTOBASE R 0 (base level)
1

fault
0
9:0 VECTACTIVE R 0 ISR
ISRNMI
fault

16,
/
D.12 (VTOR) 0xE000_ED08

7-28 TBLOFF RW 0
29 TBLBASE R - Code 0 RAM 1
305
Cortex-M3 B-D
D.13 (AIRCR) 0xE000_ED0C

31:16 VECTKEY RW -
0x05FA
0xFA05
15 ENDIANESS R - 1(BE8)0

10:8 PRIGROUP R/W 0
2 SYSRESETREQ W -
1 VECTCLRACTIVE W -
OS
0 VECTRESET W - CM3

D.14 0xE000_ED10

4 SEVONPEND RW -
WFE
WFE
WFE
3 - - -
2 SLEEPDEEP R/W 0 SLEEPDEEP

1 SLEEPONEXIT R/W - SleepOnExit
0 - - -
D.15 0xE000_ED14

9 STKALIGN RW 0(r1 SP
) 0
1(r2
)
8 BFHFNMIGN RW 0 fault NMI
fault
7:5 - - -
4 DIV_0_TRP RW 0 fault
3 UNALIGN_TRP RW 0 fault
2 - - -
1 USERSETMPEND RW 0 1, STIR
0 NONBASETHRDENA RW 0 1,
306
Cortex-M3 B-D
EXC_RETURN

D.16 0xE000_ED18 0xE000_ED23

0xE000_ED1A PRI_6 fault
0xE000_ED1B - - - -
0xE000_ED1C - - - -
0xE000_ED1D - - - -
0xE000_ED1E - - - -
0xE000_ED1F PRI_11 SVC
0xE000_ED20 PRI_12
0xE000_ED21 - - - -
0xE000_ED22 PRI_14 PendSV
0xE000_ED23 PRI_15 SysTick
D.17 HandlerSHCSR 0xE000_ED24

18 USGFAULTENA R/W 0 fault
17 BUSFAULTENA R/W 0 fault
16 MEMFAULTENA R/W 0 fault
15 SVCALLPENDED R/W 0 SVC SVC

14 BUSFAULTPENDED R/W 0 fault
13 MEMFAULTPENDED R/W 0 fault
12 USGFAULTPENDED R/W 0 fault
11 SYSTICKACT R/W 0 SysTick
10 PENDSVACT R/W 0 PendSV
9 - - - -
8 MONITORACT R/W 0 Monitor
7 SVCALLACT R/W 0 SVC
6:4 - - - -
3 USGFAULTACT R/W 0 fault
2 - - - -
1 BUSFAULTACT R/W 0 fault
0 MEMFAULTACT R/W 0 fault
D.18 fault (MFSR) 0xE000_ED28
307
Cortex-M3 B-D

7 MMARVALID - 0 =1 MMAR
6:5 - - - -
4 MSTKERR R/Wc 0
3 MUNSTKERR R/Wc 0
2 - - - -
1 DACCVIOL R/Wc 0
0 IACCVIOL R/Wc 0
D.19 fault (BFSR) 0xE000_ED29

7 BFARVALID - 0 =1 BFAR
6:5 - - - -
4 STKERR R/Wc 0
3 UNSTKERR R/Wc 0
2 IMPRECISERR R/Wc 0 violation
1 PRECISERR R/Wc 0
0 IBUSERR R/Wc 0
D.20 fault (UFSR)0xE000_ED2A

9 DIVBYZERO R/Wc 0 DIV_0_TRP

8 UNALIGNED R/Wc 0 fault
7:4 - - - -
3 NOCP R/Wc 0
2 INVPC R/Wc 0 EXC_RETURN
PC
The return PC
PC

1 INVSTATE R/Wc 0 ARM
0 UNDEFINSTR R/Wc 0
D.21 fault 0xE000_ED2C
31 DEBUGEVT R/Wc 0 fault

308
Cortex-M3 B-D
30 FORCED R/Wc 0 fault fault fault

fault
29:2 - - - -
1 VECTBL R/Wc 0 fault
0 - - - -
D.22 fault (DFSR) 0xE000_ED30

4 EXTERNAL R/Wc 0 EDBGREQ
3 VCATCH R/Wc 0
2 DWTTRAP R/Wc 0 DWT
1 BKPT R/Wc 0 BKPT
0 HALTED R/Wc 0 NVIC HALT
D.23 (MMAR) 0xE000_ED34

31:0 MMAR R - fault
D.24 fault (BFAR) 0xE000_ED38

31:0 BFAR R - fault
D.25 fault (AFAR) 0xE000_ED3C

31:0 AFAR R -
D.26 MPU MPUTR 0xE00_ED90

23:16 IREGION R 0 MPU region ARMv7-M
MPU
15:8 DREGION R 0 MPU MPU 8,

0 SEPARATE R 0
D.27 MPU MPUCR 0xE00_ED94
309
Cortex-M3 B-D
2 PRIVDEFENA RW 0
region
1= region
0= region
region fault
1 HFNMIENA RW 0 1= NMI fault MPU
0= NMI fault MPU
0 ENABLE RW 0 MPU
D.28 MPU region MPURNR 0xE00_ED98

7:0 REGION RW - region 8
region[2:0]
D.29 MPU region MPURNR 0xE00_ED9C
31:N ADDR RW - Region N region

MPU region
SZENABLE ADDR

4 VALID RW - REGION
1=MPU regionREGION
0=MPU region
3:0 REGION RW - MPU region
310
Cortex-M3 B-D
D.30 MPU regionMPURASR0xE000_EDA0

31:29 3 -
28 1 XN 1=
2=
27 1 -
26:24 3 AP

0b000
0b001 RW OS
0b010 RW RO
0b011 RW RW
0b100 n/a n/a n/a
0b101 RO OS
0b110 RO RO
0b111 RO RO
23:22 2
21:19 3 TEX
18 1 S Sharable
1=
0=
17 1 C Cachable
1=
0=
16 1 B Buffable
1=
0=
15:8 8 SRD regionSRDregion
128region8region128
regionRegion
7:6 2 -
5:1 5 REGIONSIZE Region1<<(REGIONSIZE+1)32
0 1 SZENABLE 1=region 0=region
D.31 DHCSR 0xE00_EDF0

31:15 KEY W -
A05F
311
Cortex-M3 B-D
25 S_RESET_ST R -
24 S_RETIRE_ST R -
19 S_LOCKUP R - 1=
18 S_SLEEP R - 1=
17 S_HALT R - 1=
16 S_REGRDY R - 1=
15:6 - -
5 C_SNAPSTALL RW 0* stalled
4 - -
3 C_MASKINTS RW 0*
2 C_STEP RW 0* C_DEBUGEN=1
1 C_HALT RW 0* C_DEBUGEN=1
0 C_DEBUGEN RW 0*
D.32 DCRSR0xE00_EDF4

16 REGWnR W - 1=
0=
15:5 - - -
4:0 REGSEL W - 00000= R0
00001=R1

01111=R15
10000=xPSR
10001=MSP
10010=PSP
10100=
[31:24]: CONTROL
[23:16]: FAULTMASK
[15:8]: BASEPRI
[7:0]: PRIMASK
D.33 DCRDR0xE00_EDF8

31:0 DATA R/W -
DCRSR
D.34 DEMCR 0xE00_EDFC

24 TRCENA RW 0* DWT,ETM,ITM
312
Cortex-M3 B-D
TPIU
23:20
19 MON_REQ RW 0 1=

18 MON_STEP RW 0 MON_EN=1
17 MON_PEND RW 0
16 MON_EN RW 0
15:11
10 VC_HARDERR RW 0* fault
9 VC_INTERR RW 0* /
8 VC_BUSERR RW 0* fault
7 VC_STATERR RW 0* fault
6 VC_CHKERR RW 0* fault

5 VC_NOCPERR RW 0* fault
4 VC_MMERR RW 0* fault
3:1
0 VC_CORERESET RW 0*
*DEMCR NVIC
D.35 STIR 0xE000_EF00

8:0 INTID W - INTID
8 IRQ #8
D36 0xE000_E400 0xE000_E4EF

PERIPHID4 R 0xE000_EFD0 0x04 ID 4
PERIPHID5 R 0xE000_EFD4 0 ID 5
PERIPHID6 R 0xE000_EFD8 0 ID 6
PERIPHID7 R 0xE000_EFDC 0 ID 7
PERIPHID0 R 0xE000_EFE0 0 ID 0
PERIPHID1 R 0xE000_EFE4 0 ID 1
PERIPHID2 R 0xE000_EFE8 0x0B/0x1B ID 2
PERIPHID3 R 0xE000_EFEC 0 ID 3
PCELLID0 R 0xE000_EFF0 0x0D ID 0
PCELLID1 R 0xE000_EFF4 0xE0 ID 1
PCELLID2 R 0xE000_EFF8 0x05 ID 2
PCELLID3 R 0xE000_EFFC 0xB1 ID 3
313
Cortex-M3 B-D
314
Cortex-M3 E
Cortex-M3
E.1
CM3 faults
faults
CM3 faults
fault fault
E.1 CM3 fault

0xE000_ED28 MMSR MemManage fault
0xE000_ED29 BFSR fault
0xE000_ED2A UFSR fault
0xE000_ED2C HFSR fault
0xE000_ED30 DFSR fault
0xE000_ED3C AFSR fault

E.1 fulat
MMSR, BFSR UFSR
fault fault (CFSR)
PC
fault PC (SP-0x24) CM3 fault
fault MSP PSP
fault fault
MMAVALID/BFARVALID fault fault MMAR
fault BFAR MMAR BFAR
315
Cortex-M3 E
fault
E.2
E.2 CM3 fault

0xE000_ED34 MMAR MemManage fault
0xE000_ED38 BFAR fault
fault LR fault
fault EXC_RETURN fault LR
EXC_RETURN Fault LR
EXC_RETURN
E.2 Fault
fault
fault fault
fault
fault fault
dump fault
PendSV PendSV
fault
PendSV fault
E.2.1 fault
Fault fault
E.2.2 PC
PC
316
Cortex-M3 E
E.2 PC

TST LR, #0x4 ; EXC_RETURN.2=0?
ITTEE EQ ;
MRSEQ R0, MSP ; MSPR0
LDREQ R0,[R0,#24] ; MSPPC
MRSNE R0, PSP ; , PSPR0
LDRNE R0,[R0,#24] ; PSPPC
RVMDK
E.2.3 fault
MMARVALID BFARVALID 1
MMARVALID/BFAVRALID fault
BFAR/MMAR BFARVALID/MMARVALID
BFARVALID/MMARVALID
fault
1. BFARVALID/MMARVALID
2. VALID BFAR/MMAR
3. fault fault fault

4. fault BFARVALID/MMARVALID BFAR/MMAR
5. fault BFAR/MMAR
VALID BFAR/MMAR
BFAR/MMAR
fault
fault FSR fault fault
FSR fault fault fault
317
Cortex-M3 E
fault BFAR/MMAR
E.2.4
fault LR fault
LR R3-R0 R12
LR
SRAM fault
E.3 C fault
CM3 C C
C SP C fault
SP fault
MDK ARM __builtin_frame_address()
GNU
12 SVC C SVC
RealView MDK
fault
R0 C
// fault
//
// C
__asm void hard_fault_handler_asm(void)
{
IMPORT hard_fault_handler_c
TST LR, #4
ITE EQ
MRSEQ R0, MSP
MRSNE R0, PSP
B hard_fault_handler_c
}
C
fault
// C fault
//
void hard_fault_handler_c(unsigned int * hardfault_args)
{
unsigned int stacked_r0;
318
Cortex-M3 E

unsigned int stacked_lr;
unsigned int stacked_pc;
unsigned int stacked_psr;
stacked_r0 = ((unsigned long) hardfault_args[0]);


stacked_lr = ((unsigned long) hardfault_args[5]);
stacked_pc = ((unsigned long) hardfault_args[6]);
stacked_psr = ((unsigned long) hardfault_args[7]);
printf ("[Hard fault handler]\n");

printf ("R0 = %x\n", stacked_r0);
printf ("LR = %x\n", stacked_lr);
printf ("PC = %x\n", stacked_pc);
printf ("PSR = %x\n", stacked_psr);
printf ("BFAR = %x\n", (*((volatile unsigned long *)(0xE000ED38))));
printf ("CFSR = %x\n", (*((volatile unsigned long *)(0xE000ED28))));
printf ("HFSR = %x\n", (*((volatile unsigned long *)(0xE000ED2C))));
printf ("DFSR = %x\n", (*((volatile unsigned long *)(0xE000ED30))));
printf ("AFSR = %x\n", (*((volatile unsigned long *)(0xE000ED3C))));
exit(0); // terminate
return;
}
SP
C C
E.4 fault
E.3- E.7 faults
319
Cortex-M3 E
E.3 MemManage fault

MSTKERR
1
2 MPU region
MUNSTKERR

1.
2. MPU
DACCVIOL MPU
region
IACCVIOL 1. region
PC
2. regions
3. EXC_RETURN
4.
ARM
5. PC
E.4 fault

STKERR
1.
2.
3. PSP
UNSTKERR STKERR
SP
IMPRECISERR

LDM/STM fault
PRECISERR BFAR fault

IBUSERR MemManage fault IACCVIOL
E.5 fault

DIVBYZERO DIV_0_TRP fault
PC
UNALIGNED UNALIGN_TRP fault PC
320
Cortex-M3 E

NOCP fault PC
INVPC 1. EXC_RETURN
1) EXC_RETURN=0xFFFF_FFF1
2) EXC_RETURN=0xFFFF_FFF9 handler
2.
1)
VECTCLRACTIVE SHCSR
2)
3. IPSR INVPC fault PC
fault
ITM
4. ICI/IT LDM/STM
PC ICI
ICI PSR fault
INVSTATE 1. PC LSB=0 PC

2. LSB=0
3. PSR ARM
UNDEFINSTR 1. CM3
2.
3. ARM
4. GNU .ascii .align

E.6 fault

DEBUGEVF fault
1. /
2. fault MON_EN=0
C_DEBUGEN=0 BKPT
C BKPT
FORCED fault
1. SVC/ SVC/BKPT
SVC/BKPT
2. fault
3. fault
4. fault
VECTBL
1. fault
2.
E.7 fault
321
Cortex-M3 E

EXTERNAL EDBGREQ
VCATCH
DWTTRAP DWT
BKPT 1. BKPT
2. FPB
322

Cortex M3权威指南CnR2（电子书）

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Cortex M3权威指南CnR2（电子书）

Uploaded by

Copyright:

Available Formats

Cortex-M3

Cortex-M3Cortex-M3 Technical Reference Manual,

1 Cortex-M3 Technical Reference Manual (TRM) (Cortex-M3)

2 ARMv7-M Architecture Application Level Reference Manual(ARMv7-M)

3CoreSight Technology System Design GuideCoreSight

4 AMBA Specification (AMBA)

5 AAPCS Procedure Call Standard for the ARM Architecture(AAPCS ARM)

6 RVCT 3.0 Compiler and Library Guide(RVCT 3.0)

7 ARM Application Note 179: Cortex-M3 Embedded Software Development(ARM179

1.1 ARM Cortex-M3

1.1.1 Cortex-M3 Cortex-M3 MCU

1.1.2 ARM ARM

ARMv7-MThe ARMv7-M Architecture Application Level Reference Manual

1.4 Thumb-2 ISA

The Cortex-M3 Technical Reference Manual

The ARMv7-M Architecture Application Level Reference Manual2

CARM Application Note 179: Cortex-M3 Embedded Software Development

2.2.2 Banked R13:

(handler mode handler )

Vectored Interrupt Controller)

Cortex-M3 4GB 2.6

16-4-1=11 4+1 240 CM3 FIQ

3 (hard) fault -1 fault fault

7-10 N/A N/A

14 PendSV pendable request

255 IRQ #239 #239

CM3 240 CM3

SLEEPING SLEEPDEEP WFI

Cortex-M3 PUSH POP

PUSH {R0} ; *(--R13)=R0R13 long*

R13 SPboth MSP PSP

PC LSB 0LR LSB

0x1000: MOV R0, PC ; R0 = 0x1004

MSR <special_reg>, <gp_reg> ;

3.2.1 PSRs PSR

3.3 Cortex-M3 xPSR

3.2.2 PRIMASK, FAULTMASK BASEPRI

PRIMASK, FAULTMASK BASEPRI MRS/MSR ,

MRS R0, BASEPRI ; BASEPRI R0

3.3 Cortex-M3 CONTROL

CONTROL MRS MSR

NVIC NMI NMI

3.4 Cortex-M3 fault

POP {R2} ; R2 & SP

3.13 Cortex-M3 PUSH

3.14 Cortex-M3 POP

CONTROL[1]=1 MSP PSPhandler MSP

STR R1, [R0] ; *R0=R1 IRQ #0

DCI 0xBE00 ; (BKPT) 16

32 Thumb-2 Thumb-2 32 ARM

0x1000: LDR r0, [r1] ; 16

BLX #im BLX ARM Cortex-M3 Thumb

CM3 ARMv7-M ARMv7M Thumb2

CPS.W #mode CM3 PSR mode

hint CM3 NOP

STRB Rd, [Rn, #offset] Rd Rn+offset

CM3 LDM/STM Rd R13 SP

LDMIA SP!, {R0-R3, PC} PUSH {R0-R3, PC}

Rd(I ncrement )D ecrement Rd

STMIA.W R8!, {r0-R3} ; R8 0x8010

ldr r2, [r0, r3] ;

ldr r2, [r0], r3 ;

MRS APSR xPSR

MOV R0, #0x12

PUSH {R0} ; (--R13)=R0R13 long

AliasAddr 0x22000000+((A-0x20000000)8+n)4 =0x22000000+ (A-0x20000000)*32 +

AliasAddr 0x42000000+((A-0x40000000)8+n)4 =0x42000000+ (A-0x40000000)*32 +