DESIGN AND IMPLEMENTATION OF A RECONFIGURABLE 4G

RADIO RECEIVER ON FPGA

MR. SACHIN
M.Tech in Digital Electronics, Department of ECE, Don Bosco Institute of Technology,
Bangalore, Karnataka, India.
Sac1357patil@gmaill.com

MRS. LAKSHMIDEVI T.R

Assistant. Proffesor,Department of ECE,Don Bosco Institute of Technology, Bangalore,
Karnataka, India.
laxmikala.devi7@gmail.com

MR. VARUN DAS P.P

PG scholar, M.Tech in Digital Electronics, Department of ECE, Don Bosco Institute of
Technology, Bangalore, Karnataka, India.
varundaspp@gmail.com

MR. SANTOSH N S
Net Cracker, Bangalore, Karnataka, India
santhu.ns.in@gmail.com

ABSTRACT:Communication is a necessity in today life. This paper presents the implementation

of a reconfigurable 4G radio receiver on FPGA. In recent years the increase in demand for the
portable and wireless applications that help consumers to communicate from any place has
resulted in more compatible and flexible communication systems which can handle different
standards in different environments. The 4G systems which are currently available in the market
for some devices aim to integrate the present and future wireless technology on a single handset
having high data rate and more functions. Integration through software compromises with the
system speed; hence integration through hardware will be a better compliment by keeping the
power consumption under the limit. The architecture is designed in Modelsim SE 6.4 and
synthesized using Xilinx ISE simulator on FGPA.

INTRODUCTION

We expect future high-speed networks to span entire continents, even parts of the globe. In such
networks the applications running on the equipments consumes a lot of battery power leading to
the draining of the battery in lesser time [1]. Scientists are looking out for several ways to reduce
power in such equipments, either physically or at a circuit level [2], [3]. A lot of research has been
carried out in the past decade to reduce the power of such baseband devices [4] and this paper
discusses the same. Interpolation is an estimation of a value within two known values in a
sequence of values. It is an estimation of an unknown quantity between two known quantities
about missing data or information from the available information. Interpolation is useful where the
data surrounding the missing data is available and its trend, seasonality and longer term cycles are
known. Time series analysis and regression analysis are the two statistical techniques employing
the concept of interpolation.
Decimation is done in digital signal processing by in order to reduce the signal strength and
decimation is complement to interpolation process. Interpolation process in the system increases
the sampling rate of the signal. Decimation makes use of filtering to avoid aliasing, which occurs
during thedown samplingof a signal. Decimator is the system component which performs
decimation. Decimation reduces the sampling rate and the signal strength. Integer or rational
fraction greater than one is used as the decimation factor.The decimation factor is used to multiply
or divide with the signal. For example, if 16-bit disc audio (sampled at 42,100 Hz) signal will be
decimated to 21,050 Hz, the audio input signal is said to be decimated by a factor of 2. The bit rate
of the signal will also be reduced to half. Decimation of the signal by an integer factor of M, can
also be explained in 2-step as follows:
1. High-frequency signal components are reduced by using a lowpass digital filter.
2. Down sampling the input signal filtered by a factor M such that it keeps only the Mth
signal.
Down sampling alone causes high-frequency signal components to be misinterpreted by
subsequent users of the data, which is a form of distortion called aliasing. The first step, if
necessary, is to suppress aliasing to an acceptable level. When the filter is an IIR design, it relies
on feedback from output to input, prior to the down sampling step. With FIR filtering, it is an easy
matter to compute only every Mth output. The calculation performed by a decimating FIR filter for
the nth output sample is a dot product:
(1)
Y(n) =
h[.] sequence is the impulse response, and k is the impulse response length. Input sequence is
represented by x[].Simple way to obtain y[n+1] after computing y[n] is done by using the starting
index x[] by M array and the dot product is recomputed.

RELATED WORKS

As mentioned in the paper by Huang Y, Tang C, Duan hl et al.(2013), GPP based SDR platform
provides system engineers working on wireless communication system with a maximum
flexibility in architecture and versatility to design a wireless communication system. Nevertheless,
Time synchronization between the terminals and base station is difficult due to the lack of
hardware real-time timing control.

In this paper by Y.Ke (B) and G. Gielen Katholieke University of Leuven (2009), For different
modes in 4G radio, a fully reconfigurable analog-to-digital converter (ADC) is needed. Depending
on the communication mode, this analog to digital converter will switchits resolution and
bandwidth, but its specifications can also be relaxed with fine granularity within the given mode
inorder to save power. Due to their low power consumption and inherent trade-off between speed
and accuracy, DSMs areusually favored in multi-mode designs.

In this paper by Delia Rodriguez de LLera Ganzalez, Anu Rusu, Mohammed Ismail (2006),in
many instances, the system level design is still done by using the help of spreadsheets. This
method is error prone, this type of method is limited to different design possibilities, which can
explored within a given time. To automate the parts of this process, a number of EDA tools are
used.

In this paper by Veena, Cyril Prasanna Raj, M.N.Shanmukh swamy (2010),At both the transmitter
and the receiver in order to multiply input of a radio link, multiple antennas are put This system is

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known as Multiple input Multiple output (MIMO) system. The role of dynamic reconfiguration is
shown by MIMO-OFDM systems. Flexibility can be achieved by such systems with respect to
changing data transfer rates, increase in range and increase in diversity, while giving efficient
resource utilization.

In this paper by N.Khairudin, M.F.Md Idros, N.A.N Hassaan, A.H.A Razak, M.A Haron, S.A.M
Al-Alam Selangor(2011), The major issue with the high-tech application is its rising cost which
also includes the cost of the hardware, power consumption and battery life. The hardware
requirements for 3G wireless communication are the Root Raised Cosine (RRC) pulse shaping
filters. Implementation of the RRC filters on FPGA can yields greater clock rate with significant
hardware saving option. This paper has examined Root Raised Cosine pulse shaping filters for
processing the mobile baseband unit of the transmitter for WCDMA.

METHODOLOGY

Filter overview
Figure illustrates the summary of overall design flow of filter for this paper. First the equiripple
filter was designed and simulated in Matlab R2011b to achieve the required frequency response.
Filter coefficient and verilog coding is then developed from the design filter. The verilog coding
was simulated in Modelsim SE 6.3 for verification before being synthesized. All the result is then
being analysed.

Filter Design in Matlab 7.0

The filter was designed and analysed in MATLAB toolbox called filter design toolbox with a
finite number of bits for the wordlength. The FDA tool that can be found in filter design toolbox
was executed and the FDA tool window as shown in figure x will appear. The specifications used
to design this filter were sampling frequency, Fs = 15.36MHz, cut off frequency, Fs = 0.7MHz
with 65 tap coefficients and this specifications is accordance to the requirement.

Filter design and simulation in matlab 7.0

Generate filter coefficient

Generate verilog coding for filter

Verilog coding simulation in modelsim SE 6.3

Result analysis

Figure. 1 Fliter Design Flow

The filter coefficients were generated using the MATLAB FDA tool which was quantized into
fixed-point representation.

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Decimator overview
Figure illustrates the summary of overall design flow of decimator for this paper. The design of the
decimator was coded in verilog. The verilog coding was simulated in Modelsim SE 6.3 for
verification before being synthesized. All the result is then being analysed.

EXPERIMENTAL RESULTS

Simulation Result in Matlab R2011b

The filter implemented here is a 65 tap root raised cosine filter with the specifications as follows,
sampling frequency 15.36 MHz, cutoff frequency 3.84MHz, with the density factor of 20. The
frequency response of the filter is as shown below.

Figure. 2 Filter Design and analysis tool

Generate verilog code of Decimator

Verilog coding simulation in modelsim SE 6.3

Result analysis

Figure. 3 Decimator Design Flow

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 Figure. 4 Magnitude response of the filter

From the figure, the past-bandwidth is equal to 0.7MHz.

Simulation Result in Modelsim SE 6.3

The filter architecture that has been coded in verilog and is simulated in Modelsim SE 6.3 and the
result is shown in figure below. The clock period used in this verilog coding is 100ns. The output
of the filter designed in this paper is shown below.

Figure. 5 Simulation result of filter

The decimator architecture that has been coded in verilog and is simulated in Modelsim SE 6.3
and the result is shown in figure below. The clock period used in the verilog coding is 100ns. The
output of the decimator designed in this paper is shown below

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 Figure. 6 Simulation result of Decimator

CONCLUSIONS

A design and implementation of the Equiripple filter in the system was successfully achieved.
Results produced in Matlab R2011b and modelsim SE 6.3 shows that filter meet the specification
requirement and attenuation of -50dB. Similarly the decimator was designed and implemented
which meet the required specification.

FUTURE DEVELOPMENT

This project can be further improved for the low power design. It can also be further improved by
implementing the synthesized model to the Xilinx Virtex III pro FPGA. It will show actual I/O
signal for the filter and the results produced can be compared with the simulation result for
verification purpose.

REFERENCES

Rupanagudi, S.R.; Bhat, V.G.; Hemalatha, S.G.; Bhavana, N.; Archana, M.; Chandrika, B.V.;
Ashwini, R.; Torvi, K.G.; Darshan, S.R.; Abhilash, B.G.; Anil, K.S.; Vinayak, S.K.M (2014),
Design of a low power Digital Down Converter for 802.16m - 4G WiMAX on FPGA.
Huddar, S.R.; Rupanagudi, S.R.; Kalpana, M.; Mohan, S (2013), Novel high speed vedic
mathematics multiplier using compressors," Automation, Computing, Communication, Control
and Compressed Sensing.
Sushma R. Huddar, Sudhir Rao Rupanagudi, Venkatesh Janardhan, Surabhi Mohan, and S.
Sandya (2013), Area and Speed Efficient Arithmetic Logic Unit Design Using Ancient Vedic
Mathematics on FPGA," in Advances in Computing, Communication, and Control.
Rupanagudi, Sudhir Rao, et al, (2008), Reducing computational complexity of branch metric
calculations in a trellis decoder.
Huang Y, Tang C, Duan hl et al.(2013), efficient time synchronization approach for wireless
communication systems on GPP-based software defined radio platform.
Y.Ke (B) and G. Gielen Katholieke University of Leuven(2009), Multi-standard continuous- Time
sigma delta converters for 4G radios.
Delia Rodriguez de LLera Ganzalez, Anu Rusu, Mohammed Ismail (2006),Automated receiver
design and optimization for 4G wireless communication system.

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Veena, Cyril Prasanna Raj, M.N.Shanmukh swamy (2010), FPGA based Reconfigurable 200MHz
Transmitter and receiver front end for MIMO-OFDM.
N.Khairudin, M.F.Md Idros, N.A.N Hassaan, A.H.A Razak, M.A Haron, S.A.M Al-Alam
Selangor(2011),implementing root raised cosine (rrc) filter for wcdma using Xilinx.

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