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THE FAST DISCRETE PERIODIC RADON TRANSFORM FOR PRIME

SIZED IMAGES:ALGORITHM, ARCHITECTURE, AND FPGA


IMPLEMENTATION
SUNILKUMAR G K
PG Student,Dept.of ECE, Don Bosco Institute of Technology,Bangalore,Karnataka,India.

S. C. BIRADAR
Asst. Professor, Dept.of ECE, Don Bosco Institute of Technology, Bangalore,Karnataka,India.

ABSTRACT:In this paper introduces the Fast Discrete Periodic Radon Transform (FDPRT)
which tells the recent new algorithm that is associated architecture for computing Discrete
Periodic Radon Transforms. For square images of size p x p, p prime, the Discrete Periodic Radon
Transform requires p2(p-1) additions for calculating image projections along a minimal number of
prime directions. The proposed Fast discrete periodic radon transform architecture can caluculate
the DPRT in p+1+[log2(p)] clock cycles which represents a significant improvement over p2+p
+1 clock cycles and lesser the clock cycles that represents to the fastest, from all existing
methodologies.

INTRODUCTION

The Discrete Periodic Radon Transform is an essential component of a wide range of applications
in image processing. Applications of the DPRT include the classic application of reconstructing
objects from projections

A sequential implementation requires p2(p-1) additions that can be computationally prohibitive.


This project presents a new, parametrizable, parallel architecture that computes the additions very
efficiently, and can produce the results in p+1+[log2(p)] clock cycles. The architecture is
demonstrated using an FPGA implementation.

The current paper is by developing an architecture and associated algorithmof the DPRT that can
be used for computations of larger prime-sized images as it allows for trading off resources
andexecution time. The primary goal of the paper is to present a parametrizable approach that can
be implemented with limited hardware resources while allowing for the maximum possible
execution speed, as measured in the required number of clock cycles.

LITRATURE SURVEY

In this paper the author [1], The digital Radon transformation can be adapted to reconstruct back
images from analog projections data. This new technique is a variation of the conventional back-
projection method. It wants no prefiltering of the projection data, straightforward one dimentional
linear interpolation and some simple and sorting of projection samples.

In this paper the author [2], We describe approximate digital implementations of two new
mathematical transforms, namely, the ridgelet transform and the curvelet transform.
Ourimplementations offer exact reconstruction, stability against perturbations, ease of
implementation, and low computational complexity.

In this paper the author [3],In this paper, an efficient algorithm is proposed for blindimage
restoration based on the discrete periodic Radon transform(DPRT). With DPRT, the original two-
dimensional blind imagerestoration problem is converted into one-dimensional ones, whichgreatly
reduces the memory size and computational time required.Experimental results show that the
resulting approach is faster inalmost an order of magnitude as compared with the
traditionalapproach, while the quality of the restored image is similar.

METHODOLOGY

The basic idea behind the new approach is to use a shift register architecture to align the image
samples that need to be added for each projection. Then, along each shifted direction, an effective
adder-tree approach can be used to provide for an effective method for performing the additions.

Figure 1: Projection example for prime direction (1,0) for a 7 x 7 image.(a) Pixels are added along
each column using an adder tree. (b) Array of7 -operand adder tree for performing the additions.

The proposed FDPRT requires N+1+[log2(N)] clock cycles as compared to N2(N-1) reported
above and N2+N+1 clock cycles reported. The results are summarized above in terms of resources
and the number of cycles for various input image sizes (up to N=41 which takes 72% for a XC4V
FXlOO Virtex-4 FPGA). To compare resources, for image sizes of 7 x 7, 17 x 17 and 31 x 31,
above reports a usage of 336, 1,235 and 2,152 Virtex-II slices respectively, as compared to 834,
5,304 and 16,257 Virtex-4 slices for the FDPRT for the same sizes.

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Figure 2: Circular left-shift structure for aligning image samples for primedirection of (1, 1). All
shifts are performed in parallel in a single clockcycle. (a) Pixels sharing the same gray-scale value
need to be added butare not aligned along the columns. (b) Pixels are properly aligned alongeach
column following the required number of circular, left, shifts. (c) Arrayof circular shift registers.

Figure 3: The FDPRT hardware implementation. (a) FDPRT core and finite state machine (FSM).
(b) The FDPRT core showing the adder tree, the shiftregister, and fast transposition logic (the
rightmost input of every MUX allows for shifting and transposition in one clock cycle, step 6 and
7 of algorithm).(c) Detailed structure of the fast adder tree.

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RESULTS

Above is the outpt of D-flip flop in figure 3(b).

Above is the output of D-Register in Figure 3(b).

Above is the output of multiplexer in Figure 3(b).

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Above is the output of FSM in Figure 3(a).

Above is the output of figure 3(c)(i.eFast adder Tree)

CONCLUSION

The proposed FDPRT architecture can compute the DPRT in N+1+[log2(N)] clock cycles which
gives an significant improvement over N2+N+1 clock cycles so lesser the clock cycle gives fastest
reported implementation given in [8]. The speed comes at the expense of increased hardware
complexity that can still be implemented in a standard Virtex-4 device (up to 41 x 41). The
proposed architecture is also suitable for VLSI implementations. Currently, we are considering a
scalable implementation that will allow for a trade-off between performance and resources and
will also apply for images of sizes that are powers of two.

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