DATA ENCODING TECHNIQUES FOR REDUCING ENERGY

CONSUMPTION IN NETWORK-ON-CHIP
SHARATH KRISHNAMURTHY
P.G.Scholar,Dept. Of ECE, D.B.I.T, Bangalore, Karnataka, India
sharathkrishnamurthy91@gmail.com

RASHMI S.B
Asst. Professor, Dept.of ECE, Don Bosco Institute of Technology,
Bangalore,Karnataka,India

ABSTRACT: As technology shrinks, the power given by the links of a network-on-chip (NoC)
begins to equal with the power given by the other elements of the communication subsystem,
namely, the routers and the network interfaces. In this proposed paper we present a collection of
data encoding schemes for decreasing the power released by the links of a NoC. The proposed
schemes are general and transparent with respect to the NoC fabric (i.e., their application does not
require any sort of modification of the routers and link architecture). Experiments carried out
showcase the effectiveness of the proposed schemes, which allow reserving max of up to 50% of
power dissipation and 13% of energy consumption without any notable performance degradation
and with less than 15% area increase in the NI

INTRODUCTION

Moving from a silicon technology node to the other one concludes in rapid and more power
coherent gates but relaxed and more energy starving wires. However, more than 51% of the
complete dynamic power is given out in interlinks in current processors, and this is assumed to rise
to 65%80% over the next few years. Chip size will almost remain constant because the chip
function will continue to grow and RC delay also grows exponentially. These days, the on-chip
communication problems are as important as, and in few cases more important than, the
computation related issues. In fact, the communication subsystem growingly will impact the
orthodox design objectives of various parameters like price (i.e., silicon area), performance, power
dissipation, energy consumption, reliability, etc. As technology dwindles, huge part of the power
budget of a complex multi-core system-on-chip (SoC) is due to the communication subsystem.
The current paper focuses on methods aimed at decreasing the power dissipated by the network
links. The power given out by the network links is as important as that dissipated by routers and
network links[NI] and their benefaction is expected to be on the increasing trend as technology
scales.

PROPOSED ENCODING SCHEME

In this section, we put forward the encoding scheme whose objective is to decrease power given
out by interlinks by reducing the coupling transition activities on the interlinks of the
interconnection network. First, let us describe the power model that includes various components
of power dissipation of a link. The dynamic power given out by the interlinks are

P = [T01 (Cs + Cl ) + TcCc] V2 ddFck

where T01 is the number of 0 1 transitions in the bus in two consecutive transmissions, Tc is
the number of correlated switching between physically adjacent lines, Cs is the line to substrate
capacitance, Cl is the load capacitance, Cc is the coupling capacitance, Vdd is the supply voltage,
and Fck is the clock frequency. One can classify four types of coupling transitions. A Type I
transition happens when one line remains unchanged while the other changes from high to low or
low to high. In a Type II transition, one of the line switches from high to low and the other line
switches in the opposite manner. A Type III transition refers to the case wherein both lines switch
simultaneously .i.e both switch either from high to low or from low to high. Finally, in a Type IV
transition neither of the lines change.

Scheme I
In scheme I, our primary concern is on decreasing the total numbers of Type I transitions (by
changing them to Types III and IV transitions) and Type II transitions (by changing them to Type I
transition). The scheme equates the present data with the foregoing one to decide if odd inversion
or no inversion of the present data can lead to the link power diminution.

1) Power Model: If the flit is odd inverted prior to release, the dynamic power on the link is
P_ T _01+ _K1T _1+ K2T _2+ K3T _3+ K4T _4_Cc
where T _01, T _1, T _2, T _3, and T _4, are the self-transition activity, and the coupling
transition activity of Types I, II, III, and IV, respectively.

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2) Proposed Encoding Architecture: The proposed encoding architecture, which is based on the
odd invert condition defined by, is shown in Fig. 1. We consider a link width of w bits. If we do
not do encoding the flits will be grouped into w bits by the NI and are sent via the link. In our
method, one bit of the link is used for the inversion bit, which indicates if the flit traversing the
link has been inverted or not. More specifically, the NI packs the body flits in w 1 bits [Fig.
1(a)]. The encoding logic E, which is in the NI, is the most important part of the system. It is
responsible for deciding whether the inversion should take place and it also does the inversion if
needed. Fig. 1(a) shows the generic block diagram which is the same for all three encoding
schemes proposed in the paper and only the block E is different for the schemes. To decide, the
foregoing encoded flit is compared with the present flit being transmitted. This latter, whose w bits
are the total of w 1 payload bits and a 0 bit, constitute the primary input of the encoder, while
the foregoing encoded flit represents the second input of the encoder [Fig. 1(b)]. The w 1 bits of
the incoming (previous encoded) body flit are indicated by Xi (Yi ), i = 0, 1, . . . ,w 2. The wth bit
of the previously encoded body flit is indicated by inv which shows if it was inverted (inv = 1) or
left as it was (inv = 0). In the encoding logic, each Ty block takes the two adjacent bits of the input
flits (e.g., X1X2Y1Y2, X2X3Y2Y3, X3X4Y3Y4, etc.)

Scheme II
In the encoding scheme II, both odd (as discussed previously) as well as full inversion are used.
The full inversion operation converts Type II transitions to Type IV transitions. The scheme will
compare the present data with the foregoing one to decide whether the odd, full, or no inversion of
the current data will result in the link power reduction. The operating principles of this scheme II
encoder are almost near to those of the encoder implementing Scheme I. The scheme II encoding
architecture, works on the odd invert condition along with the full invert condition.

Scheme III
In scheme III, in addition to scheme II we add even inversion. The reason for this is that odd
inversion converts some of Type I (T 1 ) transitions to Type II transitions. As can be observed
from Table II, if the flit is even inverted, the transitions indicated as T 1 /T 1 in the table are
converted to Type IV/Type III transitions. Therefore, the even inversion may reduce the link
power dissipation as well. The scheme compares the current data with the previous one to decide
whether odd, even, full, or no inversion of the current data can give rise to the link power
reduction.

Scheme III
Operating principle is very much similar to that of Schemes I and II. The encoding architecture of
the proposed encoder of scheme III includes that of even invert condition , the full invert condition
and the odd invert condition.

CONCLUSION

The proposed data encoding schemes have been assessed by means of Xilinx. In the proposed
schemes, we have come up with a whole new set of new data encoding schemes which plays a
major role in decreasing power released by the links of an NoC. In fact, links play a major role in
dissipating a major fraction of the overall power dissipated by the communication system. Also,
their contribution is expected to grow in future technology nodes. The encoding schemes that we
have come up with does not require any modification neither in the routers nor in the links. An

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extensive evaluation has been carried out to assess the impact of the encoder and decoder logic in
the NI.

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