DEVARACONDA DINESH

D. No: 197-a, Srinilaya township, Email IDs: devaraconda.dinesh@gmail.com

Road no8, Badangpet, Hyderabad,
Telangana. Pin: 500058 Phone No: +91-7382547688

CAREER OBJECTIVE:

Seeking for a challenging job where I can utilize my skills to be a part of a progressive organization and
to upgrade my skills such that it will contribute effectively to the development of the organization.
EDUCATIONAL QUALIFICATION:
Qualification University/Institute Year of passing Percentage/CGPA

M. Tech (VLSI VIT University Chennai 2016 8.52 (CGPA)

Design)
B. Tech (EIE) CVR college of 2014 75.02
Engineering, JNTU
HYDERABAD
Higher Secondary Narayana Junior 2010 88
School (MPC) College, Board of
Intermediate
High School (CBSE) Defense Laboratory 2008 65.20
School

TECHNICAL SKILLS:
Programming languages : C .
Tools & Simulators : Cadence Virtuoso , nWave, ezWave, Cadence SOC Encounter,
Design Verification : Data Accuracy , Data Validation , ESPCV
CERTIFICATION:
CERTIFIED BY AMCAT.

AREAS OF INTREST:
Memory Design, Memory Characterization, Digital VLSI design.

EXPERIENCE:
Organization: ARM Embedded Technologies Private Limited Bangalore
Duration: May, 2016- Till Date.
Designation: Memory Design Engineer (Consultant).

Project 1: Design and analysis of memory compiler blocks .

Description: Aim of the project is to implement 32x4M2 memory block and analyzed the contol logic,
Column decoder , row decoder , and core array . Read and write assist circuits implementation and
analysis. EMA circuitry implementation and analysis.
Project2: SMIC28nm RA1HD.
Description: I have worked on ADM,WRM, read margin determining the sense amp offset related bit-cell
analysis for single port SRAM Design. Analysis of self timing path for synchronizing all the timing paths
inside the memory compiler block. .

Worked on ESPCV task . Debugging the issues in espcv if any changes to be made in design sign
side updating the strength multipliers for the corresponding mosfets in the design.
Analysing the maximum limit of the noise signal that the bit cell can withstand using N-Curve
methodology developed by IBM .
Worked on memory characterization , Data accuracy and Data validation.

ACHIEVEMENTS:
CERTIFICATE OF APPRECIATION for conducting technical event in CIENCIA 2K13.
Certificate of Merit Scholarship from DEFENSE ELECTRONICS RESEARCH
LABORATORY.

STRENGTHS:
Hard work
Listening to others views

CO-CURRICULAR ACTIVITIES:

Organized Reverse Engineering event in National Technical Fest CIENCIA 2K13.

Done PCB Design of Line Follower Circuit.

DECLARATION:

I hereby solemnly affirm that the details furnished above are true to the best of my knowledge and belief.

PLACE: Banglore .

DATE: Devaraconda Dinesh