MARTHANDAM COLLEGE OF ENGINEERING AND the appropriate subword boundaries this technique results

TECHNOLOGY in parallel processing of subwords. Since the same

INTERNAL EXAM I-2017 instruction is applied to all subwords within the word, This
Semester IV is a form of SIMD(Single Instruction Multiple Data)
ELECTRONICS & COMMUNICATION ENGINEERING processing.
CS6303 COMPUTER ARCHITECTURE
ANSWER KEY For example, ARM added more than 100
_________________________________________________ instructions in the NEON multimedia instruction
extension to support sub-word parallelism, which can be
Part A (10x2=20)
used either with ARMv7 or ARMv8.
Answer All Questions

1. Computer Architecture is the science of integrating the 7. The Classic CPU Performance Equation in terms of
functional components to achieve a level of functionality instruction count (the number of instructions executed by the
and performance. It includes the data formats, instruction program), CPI, and clock cycle time:
format, the instruction set and techniques for addressing
memory.
2.

8.

3. Amdahl's law states that the performance improvement to

be gained from using some faster mode of execution is
limited by the fraction of the time the faster mode can be
used.
4. Big-endian and little-endian are terms that describe the
order in which a sequence of bytes are stored in computer
memory. Little-endian is an order in which the "little end"
(least significant value in the sequence) is stored first. 9. A command that computer hardware understands and obeys
5. All computers are constructed using a clock that determines is called a Computer Instruction.
when events take place in the hardware. These discrete time 10. Response time is also called execution time. The total time
intervals are called clock cycles. The length of each clock required for the computer to complete a task, including disk
cycle is called Clock period. accesses, memory accesses, I/O activities, operating system
6. A subword is a lower precision unit of data contained overhead, CPU execution time, and so on is called response
within a word. In subword parallelism, multiple subwords time.
are packed into a word and then process whole words. With
 Part B (5 X 16 = 80) z i = xi yi ci-1 , which is equivalent to
11. a) i)
z i = pi gi ci-1
1.Design for Moores Law
2.Use Abstraction to Simplify Design
3.Make the Common Case Fast
4.Performance via Parallelism
5.Performance via Pipelining
6.Performance via Prediction
7.Hierarchy of Memories
8.Dependability via Redundancy
(8)

ii)
CPU time = (Instruction count * CPI) / Clock
rate
Time= Seconds/Program = Instructions/Program *
Clock cycles/ Instruction *
Seconds /Clock cycle (8)
ii)
a) Algorithm
b) Programming language
c) Compiler
d) Instruction set architecture (8)

b) i)
gi = xiyi pi = xi + yi
ci = gi + pi ci-1
ci-1 = gi-1 + pi-1 ci-2
ci = gi + pi gi-1 + pi pi-1ci-2

C0 = g0 + p0cin
C1 = g1 + p1g0 + p1p0cin
C2 = g2 + p2g1 + p2p1g0 + p2p1p0cin (8)
C3 = g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0cin
12. a) This yield,
CPU clock cycles1 (2 x1) + (1 x2) + (2x
3) = 2 + 2 + 6 = 10 cycles
CPU clock cycles2 (4 x1) + (1x 2) +
(1x 3) = 4 + 2 + 3 = 9 cycles
So code sequence 2 is faster, even though it
executes one extra instruction.

(6)

ii) Lets first find the number of clock cycles

required for the program on A:

(16)
(Or)

b) i) Sequence 1 executes 2 + 1 + 2 + 5
instructions.
Sequence 2 executes 4 + 1 + 1 = 6
instructions. To run the program in 6 seconds, B must
Therefore, sequence 1 executes fewer have twice the clock rate of A
instructions.
(5)
We can use the equation for CPU clock cycles
based on instruction count and CPI to find the
total number of clock cycles for each sequence:
iii)

ET = IC*CPI*CT
ETA = IC * 2*250 = 500IC
ETB = IC * 1.2 * 500 = 600IC
Since Instruction Count is same, clearly ET A <
ETB, so Computer A is faster than Computer B

Computer A is 0.83 times faster than computer B

(5)
13. a) Discuss about the various techniques to represent
instructions in a computer system. (16)

a) R-Format Instruction

b) I-Format Instruction

c) J-Format Instruction
(16)

14. a) Logical Operations (8)

Control Operations (8)
b) Addressing Modes are the ways of specifying an operand
or a memory address. Addressing Modes are the ways of b)
specifying an operand or a memory address. The MIPS The following are the steps involved in the addition of floating
addressing modes are the following point numbers
Immediate Addressing 1. Equalize the exponents. The operand with the smaller
Register Addressing exponent should be rewritten by increasing its exponent
Base Addressing and shifting the point leftwards.
PC-Relative Addressing 2. Add the mantissas or significands.
Pseudo-Direct Addressing 3. Normalize the result if necessary.
4. Round the number if needed.
 15. a)

Restoring Division:

Non- Restoring Division:

(16)

b) i)
Algorithm:
1. Pad the LSB with one zero.
2. If n is even dont pad the MSB ( n/2 PPs) and if
n is odd sign extend the MSB by 1 bit ( n+1/2
PPs).
3. Divide the multiplier into overlapping groups of
Example : 3-bits.
Adding the numbers 0.5ten and -0.4375ten in binary using the 4. Determine partial product scale factor from
algorithm modified booth 2 encoding table.
5. Compute the Multiplicand Multiples
6. Sum Partial Products
 Xi+1 Xi Xi-1 Action

0 0 0 0Y

0 0 1 1Y

0 1 0 1Y

0 1 1 2Y

1 0 0 -2 Y

1 0 1 -1 Y

1 1 0 -1 Y

1 1 1 0Y

(8)

(8) ii)