Trinary hybrid multilevel inverter used in STATCOM

with unbalanced voltages

Y. Liu and F.L. Luo

Abstract: The application of trinary hybrid multilevel inverter in synchronous static compensation
(STATCOM) with unbalanced voltages is investigated. Beneting from trinary hybrid topology of
the inverter, the cost of STATCOM is reduced because of not only fewer switching components
but also reduced cost of cooling systems and DC capacitors. The combination of vector control
based on synchronous frame and staircase modulation is used in the STATCOM system presented
to regulate reactive power or balance bus voltages under balanced or unbalanced conditions. To
achieve this control aim, a new method based on the comparison of reference amplitudes and
reference signals is presented. The performance of the proposed control strategy is conrmed by
simulation and experiment.

List of symbols Superscripts represent phases or serial numbers

a/b/c A-phase/B-phase/C-phase in ABC frame
Symbols with subscripts or superscripts abc ABC frame
Symbols a/b a axis/b axis in ab frame
CAP capacitor ab ab frame
HB H-bridge d+/q+ d+ axis/q+ axis in dq+ frame
i/i/I instantaneous value/vector of instantaneous dq+ dq+ frame
values/phasor of current d/q d axis/q axis in dq frame
M modulation index dq dq frame
S signal I, II serial number of H-bridges
SC switching component 1,2,3,4 serial number of switches or switching angles
SF switching function +/ positive sequence/negative sequence
SS switching signal * reference value
T transformation matrix
U unit voltage Other symbols
v/v/V instantaneous value/vector of instantaneous ABS function of absolute value
values/phasor of voltage Bb bipolar binary function
g instantaneous variable Bu unipolar binary function
FC function of comparing and keeping
Subscripts represent positions FSS function of switching signals
A arm of H-bridge MAX selecting the one with maximum value
B bus connected with STATCOM NL number of levels
C output of STATCOM TSA table of theoretical switching angles
D DC capacitor, diode WB width of band
G GTO dk kth nal switching angle
H output of H-bridge e regulation factor
I interface between STATCOM and bus fk kth theoretical switching angle
L load y phase angle in vector transformation
P output of power control module o radian frequency
S voltage source of distribution system j phase angle
U output of unbalanced voltage control 7v7 amplitude of v, which is a vector
module 7w71 amplitude of fundamental component of w,
which is a periodical variable
7w7n amplitude of nth order harmonic of w, which is
r IEE, 2005 a periodical variable
IEE Proceedings online no. 20045257
doi:10.1049/ip-epa:20045257
Paper rst received 9th December 2004 and in nal revised form 17th March
2005 1 Introduction
The authors are with the Center for Advanced Power Electronics, School of
Electrical and Electronics Engineering, Nanyang Technological University, Synchronous static compensation (STATCOM) is a exible
639798, Singapore AC transmission system (FACTS) device, which is
E-mail: eluo@ntu.edu.sg connected as a shunt to the network, for generating or

IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005 1203
absorbing reactive power. STATCOM can be utilised to source current IS load current IL
bus voltage
regulate voltage, control power factor and stabilise power
source Z VB
ow [1]. Many inherent benets of multilevel inverters have impedance S interface
led to their increased interest in STATCOM. In [2, 3], impedance I
Z
cascade multilevel inverters have been used in STATCOM. source
load
voltage STATCOM
Furthermore, the application of binary hybrid multilevel current impedance
inverters in STATCOM has also been investigated because VS IC ZL
the binary hybrid multilevel inverter can generate more STATCOM V
voltage C
voltage levels than the cascade multilevel inverter with the
same number of switches [46]. Recently, trinary hybrid
multilevel inverters have been presented and attracted more Fig. 2 Simplified model of distribution system with STATCOM
interest since it is said that they can generate the most
voltage levels among existing multilevel inverters [7, 8].
This paper investigates the application of trinary hybrid
multilevel inverter in STATCOM. In this topology, not Table 1: Parameters of compensator and distribution
only are fewer switches required, but also the cost of cooling system for simulations and experiments
systems and DC capacitors is decreased. Moreover, the
problem of regenerative power in trinary hybrid multilevel Simulations Experiments
inverters mentioned in [9] is avoided because the STAT-
Operating frequency 50 Hz 50 Hz
COM mainly generates or absorbs reactive power.
Voltage imbalance is a problem that STATCOM must Rating of source voltage 13.5 kV 196 V
deal with in the distribution system. Steady-state voltage (line-to-line RMS value)
imbalance can arise from unequal loading on each phase or Rating of reactive power 10 MVAr 2000 VAr
from unbalanced faults on the power system, which cause Rating of STATCOM current 428 A 6A
single-phase voltage sags. These sags are detrimental since (phase RMS value)
they cause heating in motors and affect sensitive single Interface impedance per phase oLI 3.64 O; oLI 3.64 O;
phase loads. The presented STATCOM can balance bus RI 0.3 O RI 0.3 O
voltages under unbalanced conditions. Source impedance per phase oLS 2.2 O; oLS 2.2 O;
The staircase PWM is widely used in STATCOM [10, 11] RS 0.3 O RS 0.3 O
since gate-turn-off thyristor (GTO) with lower switching Unit voltage of DC capacitors, UD 3.3 kV 48 V
frequency are employed as switches in such applications of
DC capacitor in the H-bridge with 2933 mF 3300 mF
high power and high voltage [1214]. Vector control based DC voltage UD
on synchronous frame transform has been used successfully
DC capacitor in the H-bridge with 1114 mF 1100 mF
in STATCOM to regulate reactive power [2, 15] and reduce
DC voltage 3UD
negative sequence component of the bus voltage [16]. In this
paper, vector control and staircase modulation are com-
bined to reach the control aims. The challenge here is that
the conventional method based on the comparison of
switching angles and phase angles [2, 10, 11] to generate the the bus B through the interface impedance ZI. ZS is the
switching signals cannot work well in such a control system. equivalent impedance of the source and ZL is the equivalent
A new method based on the comparison of reference impedance of the load. In the steady state and under
amplitudes and reference signals is proposed in this paper. balanced conditions, voltages and currents can be expressed
Furthermore, dead-zone control is used to improve as phasors. In Fig. 2, VS is the source voltage, VB is the bus
performance of the inverter. The performance of the voltage, VC is the generated voltage of the STATCOM, IC is
proposed control system is conrmed by simulation and the current generated by the STATCOM, IS is the source
experiment. current and IL is the load current. Parameters of the
compensator and the distribution system are shown in
2 System configuration Table 1. The STATCOM in the steady state will generate a
leading reactive current when the amplitude of VC is larger
2.1 Configuration of STATCOM system than that of VB, and vice versa, it will draw a lagging current
Figure 1 shows a one-line diagram of a distribution system from the source.
with STATCOM and Fig. 2 shows a simplied model of
Fig. 1. The STATCOM, which is based on a three-phase 2.2 Three-phase nine-level trinary hybrid
nine-level trinary hybrid multilevel inverter is connected to multilevel inverter
Figure 3 shows a three-phase Y-congured nine-level
trinary hybrid multilevel inverter used in the STATCOM.
transformer 2 transformer 3
The inverter has separate DC capacitors for each H-bridge
electrical wire electrical wire unit of each phase. To get maximum output voltage levels
B
load 2 of the inverter, the ratio of DC capacitor voltages is
interface arranged as 1:3, so the inverter can output nine voltage
impedance levels each phase. With two H-bridges per phase, however,
transformer 1 C
three-phase
a cascade multilevel inverter can output only ve voltage
nine-level levels each phase and a binary hybrid multilevel inverter can
trinary hybrid output only seven voltage levels each phase. The more
generator load 1 multilevel
inverter
output voltage levels a multilevel inverter has, the more
nearly a sinusoid waveform can be synthesised. Thereby,
more lower-order harmonics can be eliminated and total
Fig. 1 Distribution system with STATCOM harmonic distortion (THD) can be reduced greatly. Since
1204 IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005
 HBaI HBbI HBc I

vCb c
SC1 SC3 v aC SC1 SC3 SC1 SC3 vC

CAPaI + CAPb I + CAPc I +

UD aI
vH UD bI
vH UD cI
vH

SC2 SC4 SC2 SC4 SC2 SC4

HBaII HBbII HBc II

SC1 SC3 SC1 SC3 SC1 SC3

CAPaII + CAPbII + CAPc II +

3UD v aI
H
I
3UD bII
vH 3UD cII
vH

SC2 SC4 SC2 SC4 SC2 SC4

Fig. 3 Three-phase nine-level trinary hybrid multilevel inverter

the ratio of DC capacitor voltages of the inverter is trinary, STATCOM works at high voltages, so GTOs are selected
this kind of inverter can be called trinary hybrid multilevel as switching components that cannot switch at high
inverter. frequency. The staircase PWM, the most popular one
Three phases of the inverter are controlled separately and among optimal programmed PWM strategies, is used in the
the operating principle of each phase is identical. In the proposed STATCOM.
following, the A-phase of the inverter is analysed. HBak Figure 4 shows the A-phase waveforms of the inverter
represents the kth H-bridge in the A-phase leg of the (only waveforms with solid lines are considered). By
inverter, where superscript a means A-phase and k can be I applying the Fourier transform to vaC , the amplitude of
or II. nak ak
H and nD represent the output voltage and the DC any odd nth harmonic of vaC can be expressed as (3),
capacitor voltage of the HBak, respectively. A switching whereas the amplitudes of all even harmonics are zero:
function, SFak, is used to relate nak ak
H and nD as:
a
4UD X4

v
cosnfj  n 1; 3; 5; . . . 3
vak
H SF ak vak
D k I; II 1 C n
np j1
ak
The value of SF can be either 1,
1 or 0. For the value 1,
switching components SC1 and SC4 need to be turned on. The switching angles, f1, f2, f3 and f4, are chosen so as to
For the value
1, switches SC2 and SC3 need to be turned cancel predominant lower-frequency harmonics. For the
on. For the value 0, switches SC1 and SC3 need to be turned nine-level case in Fig. 4, the 5th, 7th and 11th harmonics
on or SC2 and SC4 need to be turned on. The A-phase can be eliminated with the appropriate choice of the
voltage of the inverter, vaC , is represented as: switching angles. One degree of freedom is used so that
the magnitude of the output waveform corresponds to the
X
II
modulation index of A-phase, Ma, which is expressed as:
vaC SF ak vak
D 2


kI
a
p
vaC
1
M 4
The unit voltage of DC capacitors is UD, i.e. vaI aII
D and vD are 16UD
a
UD and 3UD, respectively. So vC has nine levels in total.
a

Table 2 shows values of switching functions for different where
v
is the amplitude of the fundamental component
C 1
values of vaC . of vaC . Let the equations from (3) be as follows:
Two types of modulation for multilevel inverters have cosf1 cosf2 cosf3 cosf4 4M a
been presented in power applications: carrier-based PWM
strategies and optimal programmed PWM strategies [17]. cos5f1 cos5f2 cos5f3 cos5f4 0
With much lower switching frequency, the optimal cos7f1 cos7f2 cos7f3 cos7f4 0
programmed PWM strategies can eliminate the same cos11f1 cos11f2 cos11f3 cos11f4 0
number of lower-order harmonics as the carried-based
PWM strategies. In this distribution system, the proposed 5

Table 2: Values of switching functions for different values of vaC

vCa 4UD 3UD 2UD UD 0
UD
2UD
3UD
4UD

SFaI 1 0
1 1 0
1 1 0
1
aII
SF 1 1 1 0 0 0
1
1
1

IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005 1205
 4UD iCa
v Ba
vCa

t
0 1 3 4 2

3UD

2
2
t
vHall

/2
3
/2 2

2 +2
2 +2

UD
t
vHal
/2
3
/2 2

1 +1 3 +3 4 +4
3 +3

4 +4
1 +1

Fig. 4 Waveforms of output voltage of A-phase inverter, A-phase current and output voltages of H-bridges of A-phase inverter

Table 3: Table of theoretical switching angles for different FG1000BV-90DA) has a typical repetitive peak off-state
modulation indexes voltage of 4.5 kV and repetitive controlled on-state current
of 1 kA [18]. Normally, the GTO repetitive peak off-state
Modulation f1 (rad) f2 (rad) f3 (rad) f4 (rad) voltage and repetitive controlled on-state current are chosen
index (M a) to be 23 times of the system nominal ratings. In each
H-bridge module, GTOs are connected in series to make
0.56 0.59438 0.85477 1.0383 1.3207
up rated DC source voltage to satisfy the redundancy
.. .. .. .. .. requirement. The redundancy requirement is that if any
. . . . .
0.78 0.17641 0.39873 0.726 1.086
single GTO fails (such as short circuit) in one inverter arm,
the remaining functional GTOs can sustain continuous
0.79 0.17371 0.37637 0.6986 1.0709
operation until the next planned maintenance outage. The
0.8 0.17175 0.35575 0.6703 1.0545 number of GTOs required in trinary hybrid nine-level
.. .. .. .. .. inverters and common cascade nine-level inverters are given
. . . . .
in Table 4, where unit voltage of DC capacitors, UD, is
0.85 0.078667 0.35911 0.48161 0.95097 3.3 kV. The comparison shows that the trinary hybrid
multilevel inverter uses fewer GTOs since fewer redundant
switches are needed in the trinary hybrid topology.

2.4 Series connection of GTOs

Table 3 shows the ofine calculated switching angles, which One of the advantages of a multilevel inverter is to achieve
are stored in a lookup table. high voltage without having to connect switching devices in
series directly. But with the increase of power and voltage of
2.3 Counts of GTOs the applications, the series connection of switching devices is
GTOs are selected as switching components in the inevitable. The total DC-link voltages for each phase are
STATCOM. A readily available GTO (Mitsubishi GTO 13.2 kV in this paper and [19], 16 kV in [20] and 38.4 kV in

Table 4: Comparison of GTO counts

Trinary hybrid nine-level multilevel Cascade nine-level multilevel

inverter inverter

GTOs in series per valve in the H-bridge with DC voltage UD 3 (1 redundant) 3 (1 redundant)
GTOs in series per valve in the H-bridge with DC voltage 3UD 6 (1 redundant)
Total number of GTOs 108 144

1206 IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005
[21]. If the cascade multilevel inverters are used in these
systems and each valve contains only one GTO specied in
the paper, each phase of inverter will contain eight
H-bridges in this paper and [19], ten H-bridges in [20] and
23 H-bridges in [21]. Too many H-bridges result in very
complicated power circuits, too many control signals and a
bulky system. Therefore, in very high power and voltage
applications, the series connection of power semiconductors
is necessary.
In early systems, a large snubber was used to limit
the dv/dt of the switching component during the turnoff
period [22], and a variable inductor was placed between
each gate drive circuit and the corresponding switching
component in order to control the rising/falling time and to
adjust the transient voltage [23, 24]. These modications
increase the losses and reduce the dynamic performance,
so a system with fewer GTOs connected in series provides
better voltage sharing, and improves efciency and dynamic
performance [4]. Recently, however, technology that allows
the robust, reliable and cost-efcient series connection of
GTOs became industrially mature [19]. Especially, in [21],
with a digital control circuit for extremely accurate
adjustment of gate turn-off timing in units of 0.1 ms, the
up to 16 GTOs connected in series shared the voltage
uniformly in the turn-off period. This technology of
adjustment can be available even if the number of GTOs
is further increased for a higher-voltage converter in the
future. And with such technology, a system with more
GTOs connected in series has almost the same voltage
sharing, dynamic performance and efciency as a system
with fewer GTOs connected in series. Thanks to the precise
gate turn-off timing adjustment presented in [21], the trinary
inverter in which up to six GTOs connected in series is not
only feasible, but also has almost the same performance as
the cascade multilevel inverter in which three GTOs are
connected in series.
2.5 Device power loss and cost of cooling
systems
Figures 5 and 6 show waveforms of the currents owing
through the arms of HBaI and HBaII, respectively. iaij A i
I; II j 1 . . . 4 is the current owing through the jth arm
of the HBai. A positive value of iaij A means that the current
ows through GTOs, while a negative value of iaij A implies
that the current ows through antiparallel diodes. As
mentioned peviously, if the output voltage of an H-bridge is
zero, the switches SC1 and SC3 will be turned on or the
switches SC2 and SC4 will be turned on. For the purpose of
balancing the current stresses and power losses of switches,
both of these two switching states for the zero output
voltage of an H-bridge are used and each switching state is
1
used in an alternative cycle. In Fig. 5, if vaII
H is 0, the SC and
3 aII
SC of the HB are turned on when ot ranges from f2 to
f2+2p, but the SC2 and SC4 of the HBaII are turned on
when ot ranges from 0 to f2 or from f2+2p to 2p. In
1 3 aI
Fig. 6, if vaI
H is 0, the SC and SC of the HB are turned on
when ot ranges from f1 to f1+2p, but the SC2 and SC4 of
the HBaI are turned on when ot ranges from 0 to f1
or from f1+2p to 2p.
From Figs. 5 and 6, we note that the combination of
waveforms of the non-zero current that ows through an
arm during two periods is just the waveform of iaC in a
complete period. So the on-state power losses of a GTO,
PG,ON, and the on-state power losses of an antiparallel
diode, PD,ON, can be expressed as
Z
VG 3p=2 a
PG;ON i dot 6
2T p=2 C
Z 3p=2
VD
PD;ON iaC dot 7
2T p=2

a
iC
vHall
3UD
3
/2 2
t
2
/2
2 + 2
4

a ll1
iA

a ll2
iA

a ll3
iA

a ll4
iA

Fig. 5 Waveforms of currents flowing through arms of HBaII of inverter

IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005 1207
 1 2 3 4 iCa 1 + 2

v Hal
UD 3
/2
2
t

/2
4

i Aal1

i Aal2

i Aal3

i Aal4

Fig. 6 Waveforms of currents flowing through arms of HBaI of inverter

1.6 3.0
diT/dT = 300A/s
1.4
2.5
switching energy Eon , J/P

switching energy Eoff , J/P

1.2 200A/s

1.0 100A/s 2.0

VD = 2250V
0.8
VD = 2250V VDM = 3375V
IGM = 25A 1.5
0.6 diGQ/dt = 30A/s
diG/dt =10A/s VRG = 17V
0.4
CS = 0.7F 1.0 CS = 0.7F
0.2 RS = 5 LS = 0.3H
Tj = 125C Tj = 125C
0 0.5
200 400 600 800 1000 1200 200 400 600 800 1000
turn-on current, A turn-off current, A

Fig. 7 Turn-on and turn-off switching energy of GTO (Mitsubishi GTO FG1000BV-90DA)

where VG and VD are the voltage drops of a GTO and a (not including the redundant one) connected in series in
diode, respectively, if they are in the on-state. T is the period an arm of the HBaII, so the GTOs endure the off-state
of iaC . VG is 2.8 V approximately, according to the datasheet voltage, 3UD =5 (1980 V), after they are turned off. The
of the GTO, and VD is 1.3 V approximately. So, from (6), (7) turn-off switching energy of the GTO in the HBaII can
and Table 1, we nd that PG,ON is 269 W and PD,ON is be calculated as 1.6  1980/2250 1.4 J. From Fig. 5, we
125 W for the worst case. nd that the switching losses of the GTO in the HBaII are
As shown in Fig.
5,
the current that ows through a due to a switching-off process of the GTO in a period. So,
GTO in the
aHB


aII
is
iaC
1 sin f2 before the GTO is turned this switching losses can be calculated as PG;SW aII
1:4 
off, where
iC
1 is the amplitude of the A-phase STATCOM 50 70 W for the worst case. The switching losses of the
current. For the worst case, the current is 454 A. Figure 7 GTO in the HBaI are due to three switching-off processes
shows the datasheet of turn-on and turn-off switching and two switching-on processes in a period. By the same
energy of the GTO (Mitsubishi GTO FG1000BV-90DA) method, the switching losses of the GTO in the HBaI are
aI
when the DC off-state voltage is 2250 V. Based on Fig. 7, calculated as PG;SW 194 W for the worst case.
the turn-off switching energy is 1.6 J when the DC off-state If a nine-level cascade multilevel inverter is used in such a
voltage is 2250 V. As shown in Table 4, there are ve GTOs STATCOM system, the on-state losses and switching losses

1208 IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005
Table 5: Comparison of device power losses and cost of cooling systems

H-bridge Worst cases considered, redundant GTOs excluded Cost of cooling Total cost of
(DC voltage) system for a GTO cooling systems
and an antiparallel in three-phase
diode ($) inverter ($)
GTO on-state GTO switching Antiparallel diode
power losses losses (W) on-state power
(W) losses (W)

Trinary hybrid HB (UD) 269 194 125 588kcooling 54576kcooling

multilevel inverter HB (3UD) 269 70 125 464kcooling
Cascade multilevel HB (UD) 269 51 125 445kcooling 65644kcooling
inverter HB (UD) 269 62 125 456kcooling
HB (UD) 269 66 125 460kcooling
HB (UD) 269 69 125 463kcooling

of the GTOs for the worst cases can be calculated by the that
the
current generated by the STACOM is sinusoidal
same method above and the results are shown in Table 5. and
iaC
1 is the amplitude of the A-phase current. The A-
Suppose that the cost of cooling system is proportional to phase current of the STATCOM in Fig. 4 can be expressed
the power losses, that is, as:
Ccooling kcooling Ploss 8


ia
ia
sinot
p=2
C C 1 9
where Ccooling is the cost of cooling system, Ploss is power
losses and kcooling is the coefcient whose unit is $/W. As where o is the frequency in radians, assuming that the initial
shown in Table 5, the cost of the cooling system for a GTO voltages of A-phase DC capacitors are UD and 3UD,
and an antiparallel diode in the H-bridge with 3UD DC respectively. Table 6 shows capacitor voltages during rst
voltage in the trinary hybrid multilevel inverter is almost the half cycle in Fig. 4, where

a

a

same as that in the cascade multilevel inverter. Compara-
i

i

C 1 C 1
tively, the cost of the cooling system for a GTO and an m1 m2 10
antiparallel diode in the H-bridge with UD DC voltage in oCaI oCaII
the trinary hybrid multilevel inverter are a little higher since The e, DC voltage regulation factor, is selected as 5%,
the GTO switches at higher frequency. However, the total which means that the DC capacitor voltages uctuate
cost of cooling systems for the trinary hybrid multilevel within 0.951.05 times the normal value. To keep the DC
inverter is lower than that for the cascade multilevel inverter capacitor voltages within this range, the capacitances of DC
as shown in Table 5, since fewer GTOs are used in trinary capacitors are expressed as:
hybrid multilevel inverter.
a


i
MAXABSsinf
sinf ; ABSsinf
2sinf
C 1 1 2 1 2
2.6 Cost of DC capacitors aI sinf3 ; ABSsinf1
2sinf2 sinf3 sinf4
1
C
The trinary hybrid inverter not only needs fewer GTOs than 2oeUD
the cascade multilevel inverter, but also has lower cost of 11
DC capacitors. First, the required capacitances of DC
a

capacitors of the trinary hybrid multilevel inverter are
i
1
sinf
aII C 1 2
analysed. Figure 4 shows A-phase waveforms of the inverter C 12
(only waveforms with solid lines are considered). The 6oeUD
STATCOM supplies reactive power, so the output voltage where ABS is the function of absolute value, MAX is the
and output current of the inverter is orthogonal. Suppose function of selecting one with the maximum value. Based

Table 6: A-phase DC capacitor voltages during half cycle

Instant vDaI vDaII

0 UD 3UD
f1/(ot) UD 3UD
f2/(ot) UD
m1(sinf1
sinf2) 3UD
f3/(ot) UD
m1(sinf1
2sinf2 +sinf3) 3UD
m2(sinf2
sinf3)
f4/(ot) UD
m1(sinf1
2sinf2 +sinf3) 3UD
m2(sinf2
sinf4)
p/(2ot) UD
m1(sinf1
2sinf2 +sinf3 +sinf4
1) 3UD
m2(sinf2
1)
(p
f4)/(ot) UD
m1(sinf1
2sinf2 +sinf3) 3UD
m2(sinf2
sinf4)
(p
f3)/(ot) UD
m1(sinf1
2sinf2 +sinf3) 3UD
m2(sinf2
sinf3)
(p
f2)/(ot) UD
m1(sinf1
sinf2) 3UD
(p
f1)/(ot) UD 3UD
p/(ot) UD 3UD

IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005 1209
Table 7: Prices of capacitors with high voltage and high components of bus voltages and inverter output currents.
capacitance The function of the unbalanced voltage control module is to
eliminate the negative sequence components of the bus
Capacitors Series Prices (Europe $) voltages, so that the bus voltages can be balanced. The

reference output voltage of the inverter vabc
C  is the addition
A GMKPg 3.6 kV/1114 mF 1873
of the output of power control module vabcP  and the output
B GMKPg 2.6 kV/4400 mF 2565
of unbalanced voltage control module vabc U . Each phase of
C GMKPg 1.9 kV/4000 mF 1248
the inverter is controlled separately by the inverter control
D GMKPg 1 kV/9000 mF 943 module A, B or C. Inverter control modules not only
E GMKPg 0.9 kV/12000 mF 1598 control the output voltage waveform of the inverter, vabc C ,
but also are responsible for the balancing of each DC
capacitor voltage. In the following, we rst introduce vector
representation and transformation of instantaneous three-
on the consideration of the worst case from Table 3, the
phase quantities, and then specify these modules one by
required capacitances CaI and CaII are 2580 and 1050 mF.
one.
If a nine-level cascade multilevel inverter is used in such a
STATCOM system, the required capacitances are calcu- 3.1 Vector representation and transformation
lated by (13) for the comparison. From (13) and Table 3, of instantaneous three-phase quantities
for the worst cases, the required capacitances are 5380, A set of three instantaneous phase variables ga, gb and gc
3960, 3130 and 1060 mF: that sum to be zero can be uniquely represented in the ab-

a

ak

i
1
sinf
C 1 k
phase frame through the abc-ab transformation T abc!ab .
C 13 2 3
2oeUD 1 1
6 1


6 2 2 7
Table 7 shows the prices of high-voltage high-capacitance 6 p p 7
7
capacitors [25] and Table 8 shows the counts and cost of 26 3 37
T abc!ab  6 0
7 14
capacitors. Capacitors are connected to form an array of 36 2 2 7
capacitors to satisfy required capacitance and rating 6 7
4 1 1 1 5
voltage. The array has n rows in parallel and each row p p p
includes m capacitors connected in series. Moreover, an 2 2 2
additional row is used to satisfy the redundancy require- The ab ! abc transformation T ab!abc  is the inverse of
ment. Normally, the peak voltage and current rating of the T abc!ab :
capacitor array are chosen to be 23 times the system
3
nominal voltage. The comparison results show that the cost T ab!abc  T abc!ab 
1 T abc!ab T 15
of DC capacitors in a trinary hybrid inverter is less than 2
that in cascade multilevel inverters in which the current and Thus
voltage stresses of switches are balanced [10] or not 2 a3 2 a3
g g
balanced [2]. There are two reasons why the trinary hybrid 4 gb 5 T ab!abc cabc ; cabc T abc!ab 4 gb 5
inverter has lower cost of DC capacitors. First, it needs less 16
redundancy capacitors. Secondly, the capacitor CAPaI was 0 0
both charged and discharged in quarter cycles (0p/2, where
p/2p, p3p/2 or 3p/22p), as shown in Fig. 4, so the 2 3
required CaI is smaller. ga
cabc 4 gb 5 17
3 Control system of STATCOM gc
Furthermore, we can obtain dq+ or dq
co-ordinate
Figure 8 shows the control system of the STATCOM. The expressions by using the positive or negative sequence
power control module controls not only the reactive power synchronous reference frame transformations [Tab-dq+] or
but also the active power, which compensates the power [Tab-dq
], respectively:
losses of the inverter and interface impedance. The input
signals of the power control module are positive sequence cdq T ab!dq cab ; cab T dq!ab cdq 18

Table 8: Comparison of counts and costs of capacitors

H-bridge (DC Capacitance/rating Capacitor m series n+1 parallel Total price

voltage) per voltage of DC (euro)
phase capacitor

Trinary hybrid multilevel inverter HB (UD) 2.58 mF/3.3 kV B 3 2+1 305 253
HB (3UD) 1.05 mF/9.9 kV A 6 6+1
Cascade multilevel inverter (without HB (UD) 5.38 mF/3.3 kV B 3 4+1 333 816
balancing stresses) HB (UD) 3.96 mF/3.3 kV B 3 3+1
HB (UD) 3.13 mF/3.3 kV B 3 3+1
HB (UD) 1.06 mF/3.3 kV A 2 2+1
Cascade multilevel inverter (with Four HBs (UD) 5.38 mF/3.3 kV B 3 4+1 461 700
balancing stresses)

1210 IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005
 CAPaI CAPaII vDa II vDa I
a
iC
interface
impedance SS a a*
vC
multilevel inverter inverter control
(A phase) module A

CAPbI CAPbII vDb II vDb I b

iC

bus SS b b*
vC
multilevel inverter inverter control
(B phase) module B

c
CAPc I CAPc II vDc II vDc I iC

c*
multilevel inverter inverter control vC
SS c module C
(C phase)

UD v Pabc* abc*
vC
vBabc iCabc power control +
1/12
module
+

vUabc*
unbalanced voltage
control module

Fig. 8 Control system of STATCOM

cdq
T ab!dq
cab ; cab T dq
!ab cdq
19 voltage vector and the q+ axis is in quadrature with
where it, i.e.
!
      vbB
ab ga dq gd dq
gd
y arctan a 25
c b ; c q ; c q
20 vB
g g g
Under balanced steady-state conditions,
   abc 
cos y sin y dq jvB j
T ab!dq  ; vB 26

sin y cos y 21 0
T dq!ab  T ab!dq T where jvabc
B j is the amplitude of phase voltage of the bus.
Therefore, the reactive power and active power can be
  expressed as:
cos y
sin y
T ab!dq
 ; 3 3

sin y
cos y 22 P jvabc j i ; Q jvabc j i 27
dq
!ab ab!dq
T
2 B Cd 2 B Cq
T  T 
Z
RI
y ot y0 23 vBd+
d+
iC
where y0 is determined by the denition of the dq+ d+
vC + +
co-ordinate frame. 1/sLI

3.2 Power control module

LI
The power control module regulates the positive sequence
reactive power and active power injected into the bus.
Three-phase bus voltages vabc B and three-phase inverter
LI
output currents i abc
C can be transformed into vab ab
B and i C in
the ab phase frame by (16). The reactive power and active
iq+
power can be shown as v q+ + +
C
C 1/sLI
3 3
P vaB iaC vbB ibC ; Q vaB ibC
vbB iaC 24
2 2
vBq+
vab
B and i ab
can be transformed into
C and in the dq+ vdq
B i dq
C RI
frame by (18). The dq+ co-ordinate frame is dened where
the d+ axis is always coincident with the instantaneous Fig. 9 Plant of STATCOM system in s domain

IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005 1211
 +
UD +
d+
iC + + vCd+
PI PI

UD d+
iC
LI vPabc
abc
iC q+
iC T dq+  T  abc
T abc  T  dq+ LI
+
icq+ +
q+
vC
PI
+
v q+ +
vBabc B
T abc  T  dq+
v d+
B

Fig. 10 Power control module

d +
iC d+
iC
Fig. 10, respectively:
+ 1 d 
PI LI s + RI vd
C vC vq q
C vC 32

Figure 11 shows the equivalent control diagrams for id C
d+
equivalent control diagram for iC and iq
C , which is derived from Fig. 9, Fig. 10 and (32). The
controlled system is reduced to a rst-order transfer
q + q+
function [11].
iC + 1 iC Active power owing into STATCOM will regulate DC
PI LI s + RI capacitor voltages of the inverter. UD is the reference value

of unit voltage of DC capacitors. UD is the unit voltage of
q+ DC capacitors and can be calculated by
equivalent control diagram for iC
1 cI cII
q UD vaI vaII bI bII
D vD vD vD vD 33
Fig. 11 Equivalent control diagram for id
C and iC 12 D

The active current reference, id C , is generated from a PI
In Fig. 2, the resistance and inductance of interface controller, which controls UD. The reactive current

impedance are expressed as Rl and Ll. From Fig. 2 reference, iq
C , is given according to different compensation
di abc aims. For example, for a STATCOM to compensate for the
LI C RI i abc abc
C vC
vB
abc
28 reactive power of a load, it will be the load reactive current.
dt
Under balanced conditions, the dq+ component of the bus
From (16) and (28) 
voltages is shown in (26). The output of this module, vabc
P , is
di ab  
LI C RI i ab ab
C vC
vB
ab
29 obtained from vdC and vqC through T
dq!ab
and T ab!abc ,
dt as previously mentioned.
From (18), (25) and"(29) # " q #
d iC
d

iC 3.3 Unbalanced voltage control module
LI q
oLI Assuming that the sequence components are not coupled,
dt iC id Fig. 2 can be thought of as separately representing either the
C
" # " # positive or negative sequence. Considering the case of the
d
iC vC
vd
d
B negative sequence components and using the phasors, VC

RI q q 30
iC vC
vq B
represents the negative sequence component of compensa-
tor voltage generated by the STATCOM and VB
is the
Thus, under balanced conditions, the plant of the negative sequence component of bus voltage. Setting VC

STATCOM system can be expressed as (31) in the s equal to k times VB
, VB
can be expressed as
domain,
" as shown in Fig. 9: # " # ZI ZL
vd d q d
C
vB oLI iC
RI iC sLI id
C VB
VS
34
31 ZS ZI ZI ZL 1
kZS ZL
vq q d q
C
vB
oLI iC
RI iC sLI iq
C
A P controller in the synchronous reference dq frame is
A PI controller is used for both active and reactive current used to produce the amplitude of v
C from the amplitude of
control loop, as shown in Fig. 10. Under balanced v

B , as shown in Fig. 12. A large P can reduce the negative
conditions, the inverter can be regarded as a unit function, sequence component of the bus voltage greatly, which is

q d
i.e., vd
C and vC in Fig. 9 are equal to vC and vq
C and in derived from (34). The output of transform T ab!dq

B
vBabc vBd dq

T abc T  dq mean vB +
+
vBq P
+
vB =0
vC
dq
d
vC
vUabc*

T  abc T dq
C
q
vC

Fig. 12 Unbalanced voltage control module

1212 IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005
 all
vD

+ + TSA: table of theoretical switching angles
3UD mean PI
+ FC: function of comparing and keeping
a
iC 2
Bb()
a FSS: function of switching signals
vC

Bb() 0.81 : amplitude of the fundamental
1

UD + mean component of a periodical variable
PI part A
al Bu(): unipolar binary function
vD
Bb(): bipolar binary function
2
2 +
a sin() part B ABS(): absolute value
ABS(vC ) a 1 + 1
S
a S
Ma sin() 1
+
1
ABS() 1 TSA 3 3 : reciprocal
4 4 sin()
4 ABS(NLlast )
sin() +
+
1 1 + Bu()
Bu()
a + + Bu()
S + ABS(NL)
+ Bu() SS a
S
a
+
4UD 1
WB Bu() FC FSS
+ NL

+ Bu()
+
+
Bu()
Bu()

b()

Fig. 13 Inverter control module A

contains second-harmonic components with frequency versa. When vaII

H is shown as a real line in Fig. 4, the average
100 Hz in addition to DC components. A mean function charge into the capacitor CAPaII over each half cycle is zero.
that generates the average value of input during the last However, when vaII H is shifted by Dd2 by the dark dashed
0.01 s is used to eliminate the second-harmonic components. line, the charge over each half cycle can be expressed as
Thus, in the dq
frame, the regulated quantities appear as Z p
f2 Dd2
DC. When the STATCOM is used to balance the bus QaII 3UD jiaC j1 cos ydy
voltages, there is a problem that the inverter current may be f2 Dd2
over rating. Under unbalanced conditions, the output of the
P control in Fig. 12 is a signal corresponding to the voltage
6UD jiaC j1 cos f2 sin Dd2 36
drop across the STATCOM interface impedance. By where iaC is sinusoidal and jiaC j1 is the amplitude of iaC . QaII
limiting the value of this voltage drop, the inverter current is proportional to Dd2 when Dd2 is small. So QaII can be
is limited. written approximately as:
When the STATCOM balances the bus voltages, the
negative sequence power that the inverter sends can be QaII
6UD jiaC j1 cos f2 Dd2 37
expressed as: Therefore, the capacitor voltage vaIID can be controlled by
VC
VC

VB
RI slightly shifting the switching pattern. For high-power high-
P
35 voltage applications, the total power loss of the inverter is
R2I oLI 2
less than 1%, thus Dd2  0:1 rad [2]. The shifted switching
Since RI  oLI , the P
is quite small. This small deviation angles about HBaII during 0 to 2p are f2 Dd2 ,
of DC capacitor voltages that caused by the P
can be p
f2
Dd2 , p f2
Dd2 and 2p
f2
Dd2 .
balanced by ejecting or absorbing additional positive Suppose that
sequence power. d2 f2
Bb vaC iaC Dd2 38

3.4 Inverter control modules where Bb  is a bipolar binary function, which can be
Figure 13 shows the inverter control module A. The expressed as
8
operation and principle of inverter control modules B and C <1 t40
are the same as that of the inverter control module A. Bb t 0 t0 39
Inverter control module A can be divided as part A and :

1 to0
part B, as shown in Fig. 13.
The part A of Fig. 13 addresses the issue of balancing Therefore, the shifted switching angles about HBaII between
individual capacitor voltages vaI aII 0 and 2p are d2, pd2, p+d2 and 2pd2.
D and vD . Without addi-
tional control for balancing the individual capacitor The average charge current for CAPaII can be expressed
voltages, the capacitor voltages will become unequal under as:
unbalanced conditions or during a transient process. iaII aII
D 100Q 40
Additionally, each DC capacitor voltage may not be exactly
aII
balanced even under steady balanced conditions, since And the relationship between the current of CAP , iaII
D and
inverter devices are not ideal and have different tolerance the voltage of CAPaII, vaII
D , can be expressed as:
errors. Figure 4 shows the waveforms when the STATCOM
dvaII
supplies reactive power to the system. D
iaII
D C
aII
41
First, the second H-bridge of A-phase, HBaII, is analysed. dt
When the output voltage of HBaII, vaII H , has the same From (37), (40) and (41), the transfer function from Dd2 to
direction as iaC , the capacitor CAPaII is discharged and vice vaII
D in the s domain can be written as:

IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005 1213
 In the s domain, vaI
D can be expressed as
 
vaII
D k1
600UD jiaC j1 cos f2 k2 k3
k1 42 vaI
D Dd2 Dd 46
Dd2 s C aII s s
Once the switching angles of HBaII is decided, the where
switching angles of HBaI will be regulated for controlling 200UD jiaC j1 cos f2
the DC capacitor voltage of HBaI, vaI D . As shown in k2
Fig. 4, the switching angle of HBaII over the rst quarter C aI
cycle is f2 Dd2 , so the second switching angles of
200UD jiaC j1 cos f1 cos f3 cos f4 47
k3
HBaI over the rst quarter cycle must be f2 Dd2 , C aI
otherwise the inverter will generate voltage spikes. If the PI controllers are used to regulate the DC capacitor
switching angles of HBaI over the rst half cycle are f1 , voltages, as shown in Fig. 14. In the control loop, the
f2 Dd2 , f3 , f4 , p
f4 , p
f3 , p
f2 Dd2 and additional feedforward path (bold part) can enhance
p
f1 , the charge to CAPaI during the rst half cycle can dynamic response. The relationship between
k2 =k3 and
be expressed as modulation index is shown in Fig. 15. In general, the
0
QaI 4UD jiaC j1 cos f2 sin Dd2 43 inverter runs at a modulation index higher than 0.7. So

k2 =k3 is selected as 0.81 approximately.
aI
For balancing the CAP , other switching angles will shift Part B of Fig. 13 shows the main control scheme to
slightly, as shown in Fig. 4. Then the charge to the CAPaI generate desired switching signals from the reference
during a half cycle can be expressed as voltages of the inverter. In the paper and [2, 11], the
staircase PWM is used. In [2, 11], only the balanced
QaI
2UD jiaC j1
2 cos f2 sin Dd2 cos f1 sin Dd1 condition is considered and the control aim is just to
cos f3 sin Dd3 cos f4 sin Dd4 44 regulate the reactive power, so the amplitude of the inverter
voltage can be controlled by the control loop for reactive
To shift switching angles averagely, Dd1 , Dd3 and Dd4 are power and the phase angle of the inverter voltage can be
set equal to Dd. So (44) can be rewritten as controlled by the control loop for active power, respectively.
The above method cannot be applied in the STATCOM
QaI
2UD jiaC j1
2 cos f2 sin Dd2
control system presented in the paper since, in addition to
cos f1 cos f3 cos f4 sin Dd 45 regulation of reactive power, balance of bus voltages during
unbalanced conditions is involved in the control aims. To
achieve these aims, the reference voltages of the inverters,

vabc
C , are the addition of the resulting signals of the power

control module, vabc
P , and the resulting signals of the power

3UD 2 vDa ll control module, vabc
+
PI
k1 U , as shown in Fig. 8. Based on the
s reference voltages of the inverter, the switching signals are
produced to control the inverter.
k2 Under balanced conditions, the reference voltages of the
s inverter are quite close to pure sinusoidal waveforms since
k2
they only contain higher-order harmonic components

k3
whose amplitudes are very low. The 5th, 7th and 11th
order harmonics of the output voltage of the A-phase (B-
phase or C-phase) inverter are nearly eliminated by the
+ + staircase modulation, so these harmonic components of
UD +

 + k3 + vDal
PI the STATCOM currents and bus voltages are very small.
s
The output voltage of the A-phase (B-phase or C-phase)
inverter contains triple-order harmonic components. Under
balanced conditions, the amplitudes of triple-order harmo-
Fig. 14 Control scheme for individual DC capacitor voltages

Sa
: reference signal
1.2 Sa
1
WB
sin 4
reference amplitudes

1.0
sin 3
0.8
sin 2
0.6
k2 /k3

sin 1
0.4

0.2
4
ABS(NL)

0 3
2
0.2 1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
modulation index M
Fig. 16 Demonstration of comparison of reference amplitudes with
Fig. 15 Relationship between
k2/k3 and modulation index M reference signal in inverter control model A

1214 IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005
nic components of the output voltage of the A-phase of the inverter also contain high triple-order harmonic
inverter are the same as those of the B-phase inverter components, which passed from the STATCOM currents
and the C-phase inverter, so triple-order harmonic compo- and the bus voltages through the power control module.
nents of the STATCOM currents and bus voltages do So the reference voltages of the inverter are far from
not exist with the proper connection of the STATCOM pure sinusoidal waveforms. Without good sinusoidal
system. Amplitudes of other higher-order harmonic com- reference voltages of the inverter, the 5th, 7th and 11th
ponents of the STATCOM currents and bus voltages are order harmonic components of the output voltages
very low. As stated above, the reference voltages of the of the A-phase, B-phase and C-phase inverters cannot be
inverter are the addition of resulting signals of the power eliminated effectively by the staircase modulation. Thus,
control module and the unbalanced voltage control module the STATCOM currents and the bus voltages under
that are fed by the STATCOM currents and the bus unbalanced conditions contain higher 5th, 7th and
voltages, as shown in Fig. 8. As shown in Fig. 12, the 11th order harmonic components than those under
unbalanced voltage control module contains the mean balanced conditions. Therefore, the reference voltages
functions that eliminate the effect of harmonic components
of the STATCOM currents and the bus voltages. But the
power control module does not contain them to keep high
dynamic performance. So the reference voltages of the Table 9: Parameters of GTO (Mitsubishi GTO FG1000BV-
inverter contain higher-order harmonic components whose 90DA)
amplitudes are very low.
Under unbalanced conditions, the reference voltages of Forward voltage 2.3 V
the inverters are far from pure sinusoidal waveforms Turn-on resistance 0.002 O
since they contain lower-order harmonic components whose Turn-on inductance 10 mH
amplitudes are high. Under unbalanced conditions,
Current fall time 10 ms
the amplitudes of output voltages of A-phase inverter,
Current tail time 20 ms
B-phase inverter and C-phase inverter are not identical, so
the amplitudes of triple-harmonic components of Diode forward voltage 1.2 V
these output voltages are not identical. This causes the Diode turn-on resistance 0.0005 O
STATCOM currents and the bus voltages to contain high Snubber resistance 10 O
triple-order harmonic components, especially the third- Snubber capacitor 0.7 mF
order harmonic components. The reference voltages
W, VAr( 107)

1
Q* Q
0
P
1
a

1
V( 104)

1
b

1
V( 104)

1
c

500

0
A

500
d

1
V( 104)

1
0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24
e
time, s

Fig. 17 Simulation waveforms of STATCOM under balanced conditions

a P, Q and Q : active power, reactive power and reference value of reactive power
  
b vaC , vbC and vcC : reference voltages of inverter
a b c
c vC , vC and vC : the output voltage of A-phase, B-phase and C-phase inverter
d Phase currents of STATCOM
e Line-neutral voltages of bus

IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005 1215
 500.00 20000.00
400.00
10000.00
200.00 8000.00
6000.00
100.00 4000.00
80.00
60.00 2000.00
40.00
1000.00
20.00 800.00
600.00

,V
400.00
Ic a , A

10.00
8.00

b a
6.00
200.00

V
4.00
100.00
2.00 80.00
60.00
1.00 40.00
0.80
0.60
20.00
0.40
10.00
0.20 8.00
6.00
0.10 4.00
0.00 0.50 1.00 1.50 2.00 2.50 0.00 0.50 1.00 1.50 2.00 2.50
frequency, KHz frequency, KHz
a b

20 000.00

10 000.00
8000.00
6000.00
4000.00

2000.00

1000.00
800.00
600.00
Vref a , V

400.00

200.00

100.00
80.00
60.00
40.00

20.00

10.00
8.00
6.00
4.00
0.00 0.50 1.00 1.50 2.00 2.50
frequency, KHz
c

Fig. 18 Simulated frequency spectrums under balanced conditions

a Simulated frequency spectrum of A-phase current of STATCOM
b Simulated frequency spectrum of A-phase line-neutral voltage of bus
c Simulated frequency spectrum of reference voltage of A-phase inverter

of the inverter are far from pure sinusoidal waveforms
because of not only high triple-order harmonic components
but also 5th, 7th and 11th order harmonic components.
If mean functions or lters are added into the power control
module to eliminate the lower-order harmonic components
of the reference voltages of the inverter, the dynamic
performance of the reactive and active power control will be
worse. This is undesirable since the main purpose of the
STATCOM is to regulate reactive power quickly and the
STATCOM works under balanced conditions for most of
the time.
Therefore, a robust control method is needed in this
STATCOM system, which must satisfy the following two
items. First, under balanced conditions, reactive power can
be regulated rapidly and vaC does not contain 5th, 7th and
11th harmonics. Secondly, under unbalanced conditions,
the STATCOM can work steadily and the bus voltages can
be balanced. To achieve the above aims, a new control
method is proposed in this paper. By this method, vaC is
synthesised and satises the following two items. First,
under balanced conditions, the amplitude and phase angle
of fundamental component of vaC are the same as those of

1216 IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005
 1

V( 104)
0

1
a

V( 104)
0

3000
negative component of bus voltage (without comp.)
2000 negative component of bus voltage (with comp.)
V

1000

0
c

500

0
A

500

0.10 0.15 0.20 0.25 0.30 0.35 0.40

time, s
d

Fig. 19 Simulated waveform of STATCOM under unbalanced conditions

a Line-neutral voltages of bus without compensation
b Line-neutral voltages of bus with compensation
c Negative component of bus voltages with compensation and without compensation
d Phase currents of STATCOM with compensation

 
vaC . Moreover, vaC does not contain 5th, 7th and 11th
harmonics. Secondly, under unbalanced conditions, vaC can

follow the track of vaC .
The method by which vaC is synthesised is shown in part B

of Fig. 13. ABSvaC is the absolute value of vaC . The


reference signal S a equals to ABSvaC =4UD . jS a j1 is the
amplitude of the fundamental component of S a . From (4),
one can get modulation index M a that is just jS a j1 p=4.
From the table of switching angles (TSA) (Table 3), the
theoretical switching angles, f1 f4 , can be calculated. The
theoretical switching angles are shifted slightly to balance
individual capacitor voltages by the control loop shown in
part A of Fig. 13. Thus, the nal switching angles are d1 d4 .
The following is the key part of the new
method. The conventional method used in [2, 10, 11] is
to compare the phase angle ot with switching angles to
determine the switching states. The new method is to
compare the reference signal S a =jS a j1 with a series of
reference amplitudes (sin d1sin d4), as shown in Fig. 16.

First, the case in which vaC is a perfect sinusoidal
waveform is considered. In the rst quarter cycle, S a is a
perfect sinusoidal waveform and can be expressed as
S a jS a j1 sinot
In the rst quarter cycle,
Sa
4 sin di , ot4di i 1; 2; 3; 4
jS a j1

Equation (49) shows, as vaC is a perfect sinusoid, the new
method has the same function as the conventional method
by which the lower-order harmonics can be eliminated. In
practice, under balanced conditions, vaC is quite close to a
sinusoidal waveform. So, under balanced conditions, the
new method can also eliminate lower-order harmonics just
like the conventional method.

Secondly, under unbalanced conditions, vaC is far from a
sinusoidal waveform because of lower-order harmonic
components. With the new method as shown in Fig. 16,
one can obtain a vaC whose waveform is quite similar to that

of vaC . Moreover, the new method is more robust than the
method in which the switching angles are compared with
ot, which is obtained by a phase lock loop (PLL). Under
unbalanced condition and during transient process, the
increasing rate of the value of ot obtained by PLL is not
very stable, so a small deviation of this rate will result in a
large deviation of the comparison result. Therefore, the new
method based on the comparison of amplitudes is more
robust than the conventional method based on the
comparison of angles under unbalanced conditions and
during transient processes.
Thus, with the new method, the two aims mentioned
previously are achieved. Moreover, the dead zone control is
used to avoid high-frequency switching of switches in a
short interval. In Fig. 16, WB is the width of the dead zone.
48 The control system of the dead zone is shown in Fig. 13.
The values of S a =jS a j1 WB and S a =jS a j1
WB are
compared with sin d1 to sin d4, respectively. The comparison
results are the inputs of Bu , which is a unipolar binary
49
function dened as

1 t0
Bu t 50
0 to0

IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005 1217
 300.00 20 000.00
200.00
10 000.00
8000.00
100.00
80.00 6000.00
60.00 4000.00
40.00
2000.00
20.00
1000.00
10.00 800.00
8.00 600.00

,V
,A
6.00

b a
c a

400.00
4.00

V
I

200.00
2.00

1.00 100.00
0.80 80.00
0.60 60.00
0.40 40.00

0.20 20.00

0.10 10.00
a b

10 000.00 700.00
600.00
8000.00
6000.00 400.00

4000.00 200.00

2000.00 100.00
80.00
60.00
40.00
1000.00
800.00
20.00
600.00
Vref a, V

,A

400.00 10.00
8.00
c b

6.00
I

200.00
4.00

2.00
100.00
80.00 1.00
60.00 0.80
0.60
40.00
0.40

20.00 0.20

10.00 0.10
0.00 0.50 1.00 1.50 2.00 2.50 0.00 0.50 1.00 1.50 2.00 2.50
frequency, kHz frequency, kHz
c d

Fig. 20 Simulated frequency spectra under unbalanced conditions

a Simulated frequency spectrum of A-phase current of STATCOM
b Simulated frequency spectrum of A-phase line-neutral voltage of bus
c Simulated frequency spectrum of reference voltage of A-phase inverter
d Simulated frequency spectrum of B-phase current of STATCOM
e Simulated frequency spectrum of B-phase line-neutral voltage of bus
f Simulated frequency spectrum of reference voltage of B-phase inverter
g Simulated frequency spectrum of C-phase current of STATCOM
h Simulated frequency spectrum of C-phase line-neutral voltage of bus
i Simulated frequency spectrum of reference voltage of C-phase inverter

The addition results of Bu  are compared in the function 4 Simulation results

of comparing and keeping, FC, as shown in Fig. 7. Suppose
that NL is the expected level number of vaC and ABS(NL) is
the absolute value of NL. If the two addition results are
different, the FC outputs the ABS(NLlast) (the last values of
ABS(NL)). If the two addition results are identical, the FC
outputs this addition result. NL is obtained from ABS(NL)

and the polar of vac . Finally, based on Table 2 and
denition of the switching function, the switching signals for
the A-phase inverter can be obtained from NL. From
Fig. 16, one can see that the waveform of ABS(NL) will
slightly shift right because of the dead zone, which will
result in additional charge or discharge of DC capacitors.
But, with the control loop shown in part A of Fig. 13, the
DC capacitor voltages can be balanced.
1218
The performance of the STATCOM system presented
above has been veried under balanced and unbalanced
conditions by simulation. The simulation investigations
were performed with MATLAB Simulink. The parameters
of the distribution system and STATCOM are shown in
Table 1. In Table 1, the capacitance of the DC capacitors
used in the simulation is calculated based on Tables 7 and 8
(redundancy capacitors are not considered). The parameters
of the GTOs are shown in Table 9.
Figure 17 shows simulated waveforms under balanced
conditions. The step changes of the reference signal of the
reactive power, Q , is from 0 to 7 MVAr at 0.12 s and from
7 to
7 MVAr at 0.18 s. It is seen that the reactive power Q
IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005
 20 000.00 20 000.00

10 000.00 10 000.00
8000.00 8000.00
6000.00 6000.00
4000.00 4000.00

2000.00 2000.00

1000.00 1000.00
800.00 800.00

Vref b , V
Vb b , V
600.00 600.00
400.00 400.00

200.00 200.00

100.00 100.00
80.00 80.00
60.00 60.00
40.00 40.00

20.00 20.00

10.00 10.00
e f

600.00 20 000.00
400.00
10 000.00
200.00 8000.00
6000.00
100.00 4000.00
80.00
60.00
40.00 2000.00

20.00 1000.00
800.00
600.00
Vb c , V
Ic c , A

10.00
8.00 400.00
6.00
4.00
200.00
2.00
100.00
1.00 80.00
0.80 60.00
0.60
40.00
0.40

0.20 20.00

0.10 10.00
0.00 0.50 1.00 1.50 2.00 2.50 0.00 0.50 1.00 1.50 2.00 2.50
frequency, kHz frequency, kHz
g h

20 000.00

10 000.00
8000.00
6000.00
4000.00

2000.00

1000.00
800.00
Vref c , V

600.00
400.00

200.00

100.00
80.00
60.00
40.00

20.00

10.00
0.00 0.50 1.00 1.50 2.00 2.50
frequency, kHz
i

Fig. 20 continued

p
rapidly tracks the step-changing reference while the active 2 2p4UD , the response speed of this system is only
power maintains zero. Complete decoupled control is constrained by a practical DC voltage. Figure 18 shows
achieved. Because the maximum RMS value of the output simulated frequency spectra of the A-phase STATCOM
voltage of one phase of the inverter is bounded at current, the A-phase line-neutral voltage of the bus and the

IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005 1219
 m m m m
1 1.00V 2 5.00V 0.00s 10.0 s / 1 STOP 1 500 v 2 500 v 0.00s 20.0 s / 1 STOP

1 1

2 2

a
a
m m m
1 1.00V 2 5.00V 0.00s 10.0 s / 1 STOP 1 500 v 0.00s 20.0 s / 1 STOP

b b

1 1.00V 2 5.00V m
0.00s 10.0 s / 1 STOP Fig. 22 Experimental waveforms of STATCOM under unbalanced
conditions without compensation
From 0 to 40 ms and from 120 to 200 ms, the source voltages are
1 balanced; from 40 to 120 ms, source voltages are unbalanced
a CH1: AB line-to-line voltage of bus (200 V/div.); CH2: BC line-to-line
voltage of bus (200V/div.)
b CH1: CA line-to-line voltage of bus (200 V/div.)

c control loops shown in part A of Fig. 13, in which P and I
Fig. 21 Experimental waveforms of STATCOM under balanced
conditions
From 0 to 20 ms, reference value of reactive power that STATCOM
sends is zero; from 20 to 60 ms, reference value is 850 Var; from 60 to
100 ms, reference value is 850 Var
a CH1: output voltage of A-phase inverter (200 V/div.); CH2: A-phase
current of STATCOM (1 A/div.)
b CH1: output voltage of B-phase inverter (200 V/div.); CH2: B-phase
current of STATCOM (1 A/div.)
c CH1: output voltage of C-phase inverter (200 V/div.); CH2: C-phase
current of STATCOM (1 A/div.)
reference voltage of the A-phase inverter when Q is

7 MVAr. In these spectra, the triple-order harmonic
components are nearly zero and the 5th, 7th and 11th order
harmonic components are low. The reference voltages of
the inverter still contain 13th and higher-order harmonics,
which may result in additional switching of the switches.
Two methods are used to avoid the additional switching.
Firstly, smaller P in the PI controller as shown in Fig. 10

will reduce the amplitude of harmonics of vabc
C . P and I are
adjusted to 9 and 500, respectively, so that the inverter has
enough dynamic response and the amplitudes of the

harmonics of vabc C are limited to an appropriate range.
Furthermore, the dead zone control as shown in part B of
Fig. 13 eliminates the effect of the harmonics. The width of
the dead zone, WB, is selected as 0.008. From Fig. 17, one
1220
can see that voltage levels of the inverter are identical, which
means that the DC capacitor voltages are balanced by the
are selected as 0.001 and 0.01, respectively.
Figure 19 shows simulated waveforms of the STATCOM
during unbalanced conditions. Before 0.2 s and after 0.4 s,
the source voltage is balanced. From 0.2 to 0.3 s , the source
voltages are unbalanced with 0.25 p.u. negative sequence
voltage components added. Figures 19a and b show the
bus voltages without compensation and with compensation.
With compensation, the bus voltage is balanced. By limiting
the value of the P controller in Fig. 6, the current sent by
the STATCOM is limited within the rating values, as shown
in Fig. 19d. When the compensator is active, the negative
sequence component of the bus voltage is reduced. The
amount of compensation is subject to the limitation of
the inverter current. In the unbalanced voltage control
module as shown in Fig. 6, P is selected as 10 and the limits
of the P controller are from
7000 to 7000. Figure 20
shows simulated frequency spectra of the STATCOM
currents, the bus voltages and the reference voltages
of the inverter during the unbalanced conditions
with compensation. The inverter is well controlled to
compensate for the bus voltages in spite of high lower-
order harmonic components in the reference voltages of
the inverter, which proves that the new method as shown in
part B of Fig. 13 is effective. The dominant lower-order
harmonic components in the STATCOM currents are
the third-order harmonics, whose amplitudes are lower
than 15% of the rating value of the STATCOM currents.
In the worst case, the voltage ripple of a DC capacitor
caused by the third-order harmonic component of
IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005
 m m
1 500 v 2 5.00 V 0.00s 20.0 s /
a value from 850 to
850 VAr. The results show excellent
m m
1 500 v 2 5.00 V 0.00s 20.0 s /
b
m m
1 500 v 2 5.00 V 0.00s 20.0 s /
c by which the switching signals are generated from the
Fig. 23 Experimental waveforms of STATCOM under unbalanced
conditions with compensation
From 0 to 40 ms and from 120 to 200 ms, source voltages are balanced;
from 40 to 120 ms, source voltages are unbalanced
a CH1: AB line-to-line voltage of bus (200 V/div.); CH2: A-phase
current of STATCOM (1 A/div.)
b CH1: BC line-to-line voltage of bus (200 V/div.); CH2: B-phase
current of STATCOM (1 A/div.)
c CH1: CA line-to-line voltage of bus (200 V/div.); CH2: C-phase
current of STATCOM (1 A/div.)
the STATCOM current is less than 0.5% of the normal
voltage of a DC capacitor. The effect of other
harmonic components on the voltage ripple of a DC
capacitor is much lower than that of the third-order
harmonic. And the durations of unbalanced conditions are
generally short. So the effect of harmonic components of
the STATCOM currents on the voltage ripples of DC
capacitors is small and transitory. The determination of
DC capacitance can still be based on the assumption of a
sinusoidal current from the STATCOM.
5 Experimental results
To verify the performance of the proposed compensator
experimentally, a hardware prototype has been built in the
IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005
laboratory using the scaled system parameters as given in
1 STOP
Table 1. For the experimental system, a programmed AC
source is used to represent the voltage source of the system.
1 The STATCOM consists of a three-phase nine-level
MOSFET inverter, which is controlled using a
TMS320F240 controlled card, and three inductances.
Figure 21 shows the output voltages of the A-phase, B-
phase and C-phase inverters and the phase currents. From 0
2 to 20 ms, the reference value of reactive power that the
STATCOM sends is set as zero. At 20 ms, there is a step
change of the reference value of reactive power from 0 to
850 VAr. At 60 ms, there is a step change of the reference
dynamic response to the step changes.
1 STOP Figure 22 shows the line-to-line bus voltages without
compensating unbalanced voltages. Figure 23 shows the line-
1
to-line bus voltages and phase currents of the STATCOM
with compensation of unbalanced voltages. From 0 to 40 ms
and from 120 to 200 ms, the source voltages are balanced.
From 40 to 120 ms, the source voltages are unbalanced
with 0.25 p.u. negative sequence voltage components added.
With compensation, the bus voltages are balanced partially.
2
The extent of compensation is constrained by the current of
the STATCOM, which is limited within the normal value, as
shown in Fig. 23.
6 Conclusions
1 STOP
The application of a trinary hybrid multilevel inverter in a
1
STATCOM with unbalanced voltages, which is cost-
effective because of reduced cost of switching components,
cooling systems and DC capacitors, has been investigated.
The staircase modulation permits the inverter to be run at
lower frequency. Vector control based on synchronous
frame transform leads to high dynamic performance of the
2
STATCOM. Moreover, the bus voltages are rebalanced
during unbalanced conditions and the compensation
current is limited within normal values. The new method
reference inverter voltages is based on the comparison of
amplitudes instead of angles. By this method, the output
voltage of the inverter does not contain lower-order
harmonics under stable balanced conditions and the
inverter can keep high dynamic performance under
unbalanced conditions or transient processes.
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