FAN7392 - High-Current, High - and Low-Side, Gate-Drive IC

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FAN7392 High-Current, High- and Low-Side, Gate-Drive IC
July 2012
FAN7392
High-Current, High- and Low-Side, Gate-Drive IC
Features Description
Floating Channel for Bootstrap Operation to +600V The FAN7392 is a monolithic high- and low-side gate
3A/3A Sourcing/Sinking Current Driving Capability drive IC, that can drive high-speed MOSFETs and IGBTs
Common-Mode dv/dt Noise Canceling Circuit
that operate up to +600V. It has a buffered output stage
with all NMOS transistors designed for high pulse current
3.3V Logic Compatible
driving capability and minimum cross-conduction. Fairch-
Separate Logic Supply (VDD) Range from 3.3V to 20V ilds high-voltage process and common-mode noise can-
Under-Voltage Lockout for VCC and VBS celing techniques provide stable operation of the high-
Cycle-by-Cycle Edge-Triggered Shutdown Logic side driver under high dv/dt noise circumstances. An
Matched Propagation Delay for Both Channels advanced level-shift circuit offers high-side gate driver
operation up to VS=-9.8V (typical) for VBS=15V. Logic
Outputs In-phase with Input Signals
inputs are compatible with standard CMOS or LSTTL
Available in 14-DIP and 16-SOP (Wide) Packages
output, down to 3.3V logic. The UVLO circuit prevents
malfunction when VCC and VBS are lower than the speci-
fied threshold voltage. The high-current and low-output
Applications voltage drop feature makes this device suitable for half-
High-Speed Power MOSFET and IGBT Gate Driver and full-bridge inverters, like switching-mode power sup-
ply and high-power DC-DC converter applications.
Server Power Supply
Uninterrupted Power Supply (UPS)
Telecom System Power Supply 14-PDIP 16-SOP
Distributed Power Supply
Motor Drive Inverter
Ordering Information
Operating
Part Number Package Packing Method
Temperature Range
FAN7392N 14-PDIP Tube
FAN7392M -40C to +125C Tube
16-SOP
FAN7392MX Tape and Reel
2009 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN7392 Rev. 1.0.4
Typical Application Diagrams
Up to 600V
Q1
15V
R1
8 NC HO 7
9 VDD VB 6
CBOOT
HIN 10 HIN VS 5 Load
DBOOT
Controller SD 11 SD NC 4
RBOOT
LIN 12 LIN VCC 3 15V
C1
13 VSS COM 2 Q2
R2
14 NC LO 1
Figure 1. Typical Application Circuit (Referenced 14-DIP)
Up to 600V
Q1
R1
9 NC HO 8
15V
10 NC VB 7
CBOOT
11 VDD VS 6 Load
HIN 12 HIN NC 5 DBOOT
Controller SD 13 SD NC 4
RBOOT
LIN 14 LIN VCC 3 15V
C1
15 VSS COM 2 Q2
R2
16 NC LO 1
Figure 2. Typical Application Circuit (Referenced 16-SOP)

FAN7392 Rev. 1.0.4 2
Internal Block Diagram
6 VB
UVLO
DRIVER
VDD 9
GENERATOR
7 HO
R
PULSE
NOISE R
CANCELLER S Q
HIN 10
SCHMITT 5 VS
TRIGGER INPUT HS(ON/OFF)
LIN 12 UVLO 3 VCC
DRIVER
CYCLE-By-CYCLE
LS(ON/OFF) VSS/COM
SD 11 EDGE TRIGGERED
LEVEL
DELAY 1 LO
SHUTDOWN
SHIFT
VSS 13 2 COM
Pin 4, 8, and 14 are no connection
Figure 3. Functional Block Diagram (Referenced 14-Pin)
7 VB
UVLO DRIVER
VDD 11
GENERATOR
8 HO
R
PULSE
NOISE R
CANCELLER S Q
HIN 12
SCHMITT 6 VS
TRIGGER INPUT HS(ON/OFF)
LIN 14 UVLO 3 VCC

DRIVER
CYCLE-By-CYCLE
LS(ON/OFF) VSS/COM
SD 13 EDGE TRIGGERED
LEVEL
DELAY 1 LO
SHUTDOWN
SHIFT
VSS 15 2 COM
Pin 4, 5, 9,10 and 16 are no connection
Figure 4. Functional Block Diagram (Referenced 16-SOP)

FAN7392 Rev. 1.0.4 3
Pin Configuration
LO 1 16 NC
COM 2 15 VSS
LO 1 14 NC
FAN7392M
VCC 3 14 LIN
COM 2 13 VSS
FAN7392
NC 4 13 SD
VCC 3 12 LIN
NC 5 12 HIN
NC 4 11 SD
VS 6 11 VDD
VS 5 10 HIN
VB 7 10 NC
VB 6 9 VDD
HO 8 9 NC
HO 7 8 NC
(a) 14-DIP (b) 16-SOP (Wide Body)
Figure 5. Pin Configurations (Top View)
Pin Definitions
14-Pin 16-Pin Name Description
1 1 LO Low-Side Driver Output
2 2 COM Low-Side Return
3 3 VCC Low-Side Supply Voltage
5 6 VS High-Voltage Floating Supply Return
6 7 VB High-Side Floating Supply
7 8 HO High-Side Driver Output
9 11 VDD Logic Supply Voltage
10 12 HIN Logic Input for High-Side Gate Driver Output
11 13 SD Logic Input for Shutdown Function
12 14 LIN Logic Input for Low-Side Gate Driver Output
13 15 VSS Logic Ground
4,8,14 4, 5, 9, 10, 16 NC No Connect

FAN7392 Rev. 1.0.4 4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25C unless otherwise specified.
Symbol Characteristics Min. Max. Unit

VB High-Side Floating Supply Voltage -0.3 625.0 V
VS High-Side Floating Offset Voltage VB-25.0 VB+0.3 V
VHO High-Side Floating Output Voltage VS-0.3 VB+0.3 V
VCC Low-Side Supply Voltage -0.3 25.0 V
VLO Low-Side Floating Output Voltage -0.3 VCC+0.3 V
VDD Logic Supply Voltage -0.3 VSS+25.0 V
VSS Logic Supply Offset Voltage VCC-25.0 VCC+0.3 V
VIN Logic Input Voltage (HIN, LIN and SD) VSS-0.3 VDD+0.3 V
dVS/dt Allowable Offset Voltage Slew Rate 50 V/ns
14-PDIP 1.6
PD Power Dissipation(1, 2, 3) W
16-SOP 1.3
14-PDIP 75
JA Thermal Resistance C/W
16-SOP 95
TJ Maximum Junction Temperature +150 C
TSTG Storage Temperature -55 +150 C
Notes:
1. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).
2. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions, natural convection; and
JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages.
3. Do not exceed power dissipation (PD) under any circumstances.
Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Min. Max. Unit

VB High-Side Floating Supply Voltage VS+10 VS+20 V
VS High-Side Floating Supply Offset Voltage 6-VCC 600 V
VHO High-Side Output Voltage VS VB V
VCC Low-Side Supply Voltage 10 20 V
VLO Low-Side Output Voltage 0 VCC V
VDD Logic Supply Voltage VSS+3 VSS+20 V
VSS Logic Supply Offset Voltage -5 5 V
VIN Logic Input Voltage VSS VDD V
TA Operating Ambient Temperature -40 +125 C

FAN7392 Rev. 1.0.4 5
Electrical Characteristics
VBIAS(VCC, VBS, VDD)=15.0V, VSS=COM=0V and TA=25C, unless otherwise specified. The VIH, VIL, and IIN
parameters are referenced to VSS and are applicable to the respective input leads: HIN, LIN, and SD. The VO and IO
parameters are referenced to VS and COM and are applicable to the respective output leads: HO and LO.
Symbol Characteristics Test Condition Min. Typ. Max. Unit

Low-Side Power Supply Section
IQCC Quiescent VCC Supply Current VIN=0V or VDD 40 80 A
IQDD Quiescent VDD Supply Current VIN=0V or VDD 10 A
IPCC Operating VCC Supply Current fIN=20kHz, rms, VIN=15VPP 430 A
IPDD Operating VDD Supply Current fIN=20kHz, rms, VIN=15VPP 300 A
ISD Shutdown Supply Current SD=VDD 120 A
VCC Supply Under-Voltage
VCCUV+ VIN=0V, VCC=Sweep 7.7 8.8 9.9 V
Positive-Going Threshold Voltage
VCC Supply Under-Voltage
VCCUV- VIN=0V, VCC=Sweep 7.3 8.4 9.5 V
Negative-Going Threshold Voltage
VCC Supply Under-Voltage Lockout
VCCUVH VIN=0V, VCC=Sweep 0.4 V
Hysteresis Voltage
Bootstrapped Supply Section
IQBS Quiescent VBS Supply Current VIN=0V or VDD 60 130 A
IPBS Operating VBS Supply Current fIN=20kHz, rms value 500 A
VBS Supply Under-Voltage
VBSUV+ VIN=0V, VBS=Sweep 7.7 8.8 9.9 V
Positive-Going Threshold Voltage
VBS Supply Under-Voltage
VBSUV- VIN=0V, VBS=Sweep 7.3 8.4 9.5 V
Negative-Going Threshold Voltage
VBS Supply Under-Voltage Lockout
VBSUVH VIN=0V, VBS=Sweep 0.4 V
Hysteresis Voltage
ILK Offset Supply Leakage Current VB=VS=600V 50 A
Input Locic Section (HIN, LIN, and SD)
VDD=3V 2.4 V
VIH Logic 1 Input Threshold Voltage
VDD=15V 9.5 V
VDD=3V 0.8 V
VIL Logic 0 Input Threshold Voltage
VDD=15V 4.5 V
IIN+ Logic Input High Bias Current VIN=VDD 20 40 A
IIN- Logic Input Low Bias Current VIN=0V 3 A
RIN Logic Input Pull-Down Resistance 375 750 K
Gate Driver Output Section
VOH High-Level Output Voltage (VBIAS - VO) No Load (IO=0A) 1.5 V
VOL Low-Level Output Voltage No Load (IO=0A) 200 mV
IO+ Output High, Short-Circuit Pulsed Current(4) VO=0V, PW 10s 2.5 3.0 A
IO- Output Low, Short-Circuit Pulsed Current(4) VO=15V, PW 10s 2.5 3.0 A
VSS/COM VSS-COM/COM-VSS Voltage Endurability -5.0 5.0 V
Allowable Negative VS Pin Voltage for HIN
- VS -9.8 -7.0 V
Signal Propagation to HO

FAN7392 Rev. 1.0.4 6
Dynamic Electrical Characteristics
VBIAS(VCC, VBS, VDD)=15.0V, VSS=COM=0V, CLOAD=1000pF, TA=25C, unless otherwise specified.
Symbol Parameter Conditions Min. Typ. Max. Unit

ton Turn-On Propagation Delay Time VS=0V 130 180 ns
toff Turn-Off Propagation Delay Time VS=0V 150 200 ns
tsd Shutdown propagation Delay Time(4) 130 180 ns
tr Turn-On Rise Time 25 50 ns
tf Turn-Off Fall Time 20 45 ns
MT Delay Matching, HO & LO Turn-On/Off 35 ns
Note:
4. These parameters guaranteed by design.

FAN7392 Rev. 1.0.4 7
Typical Characteristics
180 200
160 180
tOFF [ns]
140 160
tON [ns]
120 140
100 120
80 100
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Temperature [C] Temperature [C]
Figure 6. Turn-On Propagation Delay Figure 7. Turn-Off Propagation Delay

vs. Temperature vs. Temperature
50 50
40 40
tR [ns]
tF [ns]
30 30
20 20
10 10
0 0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 8. Turn-On Rise Time Figure 9. Turn-Off Fall Time

30
30
MTON [ns]
MTOFF [ns]
20
20
10
10
0
0
-40 -20 0 20 40 60 80 100 120
-40 -20 0 20 40 60 80 100 120
Temperature [C]
Temperature [C]
Figure 10. Turn-On Delay Matching vs. Temperature Figure 11. Turn-Off Delay Matching vs. Temperature

FAN7392 Rev. 1.0.4 8
Typical Characteristics (Continued)
180 40
160
30
IIN+ [A]
tSD [ns]
140
20
120
100 10
80 0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 12. Shutdown Propagation Delay Figure 13. Logic Input High Bias Current
80
120
70
60 100
IQBS [A]
50
IQCC [A]
80
40
60
30
40
20
10 20
0 0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 14. Quiescent VCC Supply Current Figure 15. Quiescent VBS Supply Current
1000 1000
800 800
IPBS [A]
600 600
IPCC [A]
400 400
200 200
0 0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 16. Operating VCC Supply Current Figure 17. Operating VBS Supply Current

FAN7392 Rev. 1.0.4 9
9.5
9.5
9.0
VCCUV+ [V]
VCCUV- [V]
9.0
8.5
8.5
8.0
8.0
7.5
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120

Figure 18. VCC UVLO+ vs. Temperature Figure 19. VCC UVLO- vs. Temperature
9.5
9.5
9.0
VBSUV+ [V]
VBSUV- [V]
9.0
8.5
8.5
8.0
8.0
7.5
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120

Figure 20. VBS UVLO+ vs. Temperature Figure 21. VBS UVLO- vs. Temperature
1.5 20
15
10
1.0
VOL [mV]
VOH [V]
0.5 -5
-10
-15
0.0 -20
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 22. High-Level Output Voltage Figure 23. Low-Level Output Voltage

FAN7392 Rev. 1.0.4 10
11 10
VDD = 15V VDD = 15V
9
10
8
VIL [V]
VIH [V]
9 7
8 6
5
7
4
6 3
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 24. Logic High Input Voltage Figure 25. Logic Low Input Voltage
-7 12
Logic Threshold Voltage [V]
-8 10
8
VS [V]
-9
6
-10
4
VIH
-11
2 VIL
-12 0
-40 -20 0 20 40 60 80 100 120 0 2 4 6 8 10 12 14 16 18 20
Temperature [C] VDD Logic Supply Voltage [V]
Figure 26. Allowable Negative VS Voltage Figure 27. Input Logic (HIN & LIN) Threshold Voltage
vs. Temperature vs. VDD Supply Voltage
.
-4 VCC=VBS
-6 COM=0V
-8
TA=25C
VS [V]
-10
-12
-14
-16
10 11 12 13 14 15 16 17 18 19 20
Supply Voltage [V]
Figure 28. Allowable Negative Vs Voltage for HIN

Signal Propagation to High Side vs. Supply Voltage

FAN7392 Rev. 1.0.4 11
Switching Time Definitions
15V
8 NC HO 7 HO
9 VDD VB 6
1nF 10F 100nF 15V

HIN 10 HIN VS 5
(0 to 600V)
10F
SD 11 SD NC 4
15V
LIN 12 LIN VCC 3

10F 100nF
13 VSS COM 2
14 NC LO 1 LO
1nF
Figure 29. Switching Time Test Circuit (Referenced 14-DIP)
HIN
LIN
SD
HO
LO
Shutdown Skip
Figure 30. Input/Output Timing Diagram
HIN 50% 50%

LIN
tON tR tOFF tF
90% 90%
HO
LO 10% 10%
Figure 31. Switching Time Waveform Definitions

FAN7392 Rev. 1.0.4 12
Switching Time Definitions (Continued)
50%
SD
tSD
90%
HO
LO
Figure 32. Shutdown Waveform Definition
HIN 50% 50%

LIN
LO HO MT
10% 10%
90% 90%
LO HO
MT
Figure 33. Delay Matching Waveform Definitions

FAN7392 Rev. 1.0.4 13
Application Information
Negative VS Transient
The bootstrap circuit has the advantage of being simple Figure 36 and Figure 37 show the commutation of the
and low cost, but has some limitations. The biggest diffi- load current between high-side switch, Q1, and low-side
culty with this circuit is the negative voltage present at freewheelling diode, D3, in same inverter leg. The para-
the emitter of the high-side switching device when high- sitic inductances in the inverter circuit from the die wire
side switch is turned-off in half-bridge application. bonding to the PCB tracks are jumped together in LC and
LE for each IGBT. When the high-side switch, Q1, and
If the high-side switch, Q1, turns-off while the load cur-
low-side switch, Q4, are turned on, the VS1 node is
rent is flowing to an inductive load, a current commuta-
below DC+ voltage by the voltage drops associated with
tion occurs from high-side switch, Q1, to the diode, D2,
the power switch and the parasitic inductances of the cir-
in parallel with the low-side switch of the same inverter
cuit due to load current is flows from Q1 and Q4, as
leg. Then the negative voltage present at the emitter of
shown in Figure 36. When the high-side switch, Q1, is
the high-side switching device, just before the freewheel-
turned off and Q4, remained turned on, the load current
ing diode, D2, starts clamping, causes load current to
to flows the low-side freewheeling diode, D3, due to the
suddenly flow to the low-side freewheeling diode, D2, as
inductive load connected to VS1 as shown in Figure 37.
shown in Figure 34.
The current flows from ground (which is connected to the
DC+ Bus COM pin of the gate driver) to the load and the negative
voltage present at the emitter of the high-side switching
Q1
device.
D1
iLOAD In this case, the COM pin of the gate driver is at a higher
ifreewheeling potential than the VS pin due to the voltage drops associ-
ated with freewheeling diode, D3, and parasitic ele-
VS Load ments, LC3 and LE3.
DC+ Bus
Q2
D2 LC1 VLC1 LC2
Q1 Q2
D1 D2
iLOAD
ifreewheeling
LE1 VLE1 LE2
Figure 34. Half-Bridge Application Circuits VS1 Load VS2
This negative voltage can be trouble for the gate drivers LC3 VLC4 LC4
output stage, there is the possibility to develop an over- Q3 Q4
voltage condition of the bootstrap capacitor, input signal D3 D4
missing and latch-up problems because it directly affects

the source VS pin of the gate driver, as shown in Figure LE3 VLE4 LE4
35. This undershoot voltage is called negative VS tran-

sient.
Figure 36. Q1 and Q4 Turn-On
Q1 DC+ Bus
GND
LC1 LC2
Q1 Q2
D1 D2
iLOAD
ifreewheeling
LE1 LE2
VS
VS1 Load VS2
GND LC3 VLC3 VLC4 LC4
Q3 Q4
Freewheeling
D3 D4
LE3 VLE3 VLE4 LE4
Figure 35. VS Waveforms During Q1 Turn-Off
Figure 37. Q1 Turn-Off and D3 Conducting

FAN7392 Rev. 1.0.4 14
Placement of Components
The FAN7392 has a negative VS transient performance The recommended placement and selection of compo-
curve, as shown in Figure 38. nent as follows:
Place a bypass capacitor between the VDD and VSS
pins. A ceramic 1F capacitor is suitable for most
-100
applications. This component should be placed as
-90 close as possible to the pins to reduce parasitic ele-
ments.
-80
The bypass capacitor from VCC to COM supports both
-70 the low-side driver and bootstrap capacitor recharge.
A value at least ten times higher than the bootstrap
-60
capacitor is recommended.
-50 The bootstrap resistor, RBOOT, must be considered in
VS [V]
sizing the bootstrap resistance and the current devel-

-40
oped during initial bootstrap charge. If the resistor is
-30 needed in series with the bootstrap diode, verify that
VB does not fall below COM (ground). Recommended
-20
use is typically 5 ~ 10 that increase the VBS time
-10 constant. If the votage drop of of bootstrap resistor
and diode is too high or the circuit topology does not
0
0 100 200 300 400 500 600 700 800 900 1000
allow a sufficient charging time, a fast recovery or
ultra-fast recovery diode can be used.
Pulse Width [ns]
The bootstrap capacitor, CBOOT, uses a low-ESR
Figure 38. Negative VS Transient Chracteristic capacitor, such as ceramic capacitor.
Even though the FAN7392 has been shown able to han- It is stongly recommended that the placement of compo-
dle these negative VS tranient conditions, it is strongly nents is as follows:
recommended that the circuit designer limit the negative
Place components tied to the floating voltage pins (VB
VS transient as much as possible by careful PCB layout
to minimized the value of parasitic elements and compo- and VS) near the respective high-voltage portions of
nent use. The amplitude of negative VS voltage is pro- the device and the FAN7392. NC (not connected) pins
portional to the parasitic inductances and the turn-off in this package maximize the distance between the
speed, di/dt, of the switching device. high-voltage and low-voltage pins (see Figure 5).
Place and route for bypass capacitors and gate resis-
General Guidelines tors as close as possible to gate drive IC.
Locate the bootstrap diode, DBOOT, as close as possi-
Printed Circuit Board Layout ble to bootstrap capacitor, CBOOT.
The relayout recommended for minimized parasitic ele- The bootstrap diode must use a lower forward voltage
ments is as follows: drop and minimal switching time as soon as possible
Direct tracks between switches with no loops or devia-
for fast recovery or ultra-fast diode.
tion.
Avoid interconnect links. These can add significant
inductance.
Reduce the effect of lead-inductance by lowering
package height above the PCB.
Consider co-locating both power switches to reduce
track length.
To minimize noise coupling, the ground plane should
not be placed under or near the high-voltage floating
side.
To reduce the EM coupling and improve the power
switch turn-on/off performance, the gate drive loops
must be reduced as much as possible.

FAN7392 Rev. 1.0.4 15
Physical Dimensions
.
19.69
18.67
14 8
7.11
6.10
1 7
(1.21)
1.78 8.26
4X 1.14 7.62
0.28
4.95 0.20
2.92 5.33 MAX
3.81 0.38 MIN

2.92
0.56
0.36 10.92 MAX
2.54
0.25 C
NOTES: UNLESS OTHERWISE SPECIFIED

THIS PACKAGE CONFORMS TO
A) JEDEC MS-001 VARIATION AA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS ARE EXCLUSIVE OF BURRS,
C) MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV8
Figure 39. 14-Lead Dual In-Line Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchilds worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductors online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.

FAN7392 Rev. 1.0.4 16
Physical Dimensions (Continued)
.
10.300.20 A 9.44
8.890
16 9
B
7.500.10
10.325 9.2 10.95
1 8
PIN ONE 0.51 1.27 0.55 TYP
INDICATOR 0.35 1.75 TYP
1.27 TYP
0.25 M C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
2.65 MAX
0.33
C 0.20
0.10 C
0.200.10 SEATING PLANE
0.75
0.25 X 45 NOTES: UNLESS OTHERWISE SPECIFIED
(R0.10) A) THIS PACKAGE CONFORMS TO JEDEC

MS-013, ISSUE E, DATED SEPT 2005.
GAGE PLANE B) ALL DIMENSIONS ARE IN MILLIMETERS.
(R0.10) C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
0.25 pdip8_dim.pdf
8 D) LANDPATTERN STANDARD: SOIC127P1030X265-16L
0 E) DRAWING FILENAME: MKT-16Brev2
0.40~1.27 SEATING PLANE

(1.40)
DETAIL A
SCALE: 2:1
M16BREV2
Figure 40. 16-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchilds worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductors online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.

FAN7392 Rev. 1.0.4 17

FAN7392 Rev. 1.0.4 18
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FAN7392M FAN7392MX

FAN7392 - High-Current, High - and Low-Side, Gate-Drive IC

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LIN 12 LIN VCC 3 15V

Figure 1. Typical Application Circuit (Referenced 14-DIP)

HIN 12 HIN NC 5 DBOOT

LIN 14 LIN VCC 3 15V

Figure 2. Typical Application Circuit (Referenced 16-SOP)

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LIN 12 UVLO 3 VCC

Pin 4, 8, and 14 are no connection

Figure 3. Functional Block Diagram (Referenced 14-Pin)

LIN 14 UVLO 3 VCC

Pin 4, 5, 9,10 and 16 are no connection

Figure 4. Functional Block Diagram (Referenced 16-SOP)

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(a) 14-DIP (b) 16-SOP (Wide Body)

Figure 5. Pin Configurations (Top View)

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Symbol Characteristics Min. Max. Unit

Recommended Operating Conditions

Symbol Parameter Min. Max. Unit

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Symbol Characteristics Test Condition Min. Typ. Max. Unit

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Symbol Parameter Conditions Min. Typ. Max. Unit

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Figure 6. Turn-On Propagation Delay Figure 7. Turn-Off Propagation Delay

Figure 8. Turn-On Rise Time Figure 9. Turn-Off Fall Time

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-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120

-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120

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Figure 28. Allowable Negative Vs Voltage for HIN

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1nF 10F 100nF 15V

LIN 12 LIN VCC 3

Figure 29. Switching Time Test Circuit (Referenced 14-DIP)

Figure 30. Input/Output Timing Diagram

HIN 50% 50%

Figure 31. Switching Time Waveform Definitions

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Figure 32. Shutdown Waveform Definition

HIN 50% 50%

Figure 33. Delay Matching Waveform Definitions

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missing and latch-up problems because it directly affects

35. This undershoot voltage is called negative VS tran-

GND LC3 VLC3 VLC4 LC4

LE3 VLE3 VLE4 LE4

Figure 35. VS Waveforms During Q1 Turn-Off

Figure 37. Q1 Turn-Off and D3 Conducting

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sizing the bootstrap resistance and the current devel-

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3.81 0.38 MIN

NOTES: UNLESS OTHERWISE SPECIFIED

Figure 39. 14-Lead Dual In-Line Package (DIP)

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(R0.10) A) THIS PACKAGE CONFORMS TO JEDEC

0.40~1.27 SEATING PLANE

Figure 40. 16-Lead Small Outline Package (SOP)