1 MOSFET

1. What type(s) of gate-to-source voltage(s) can depletion

MOSFET (D-MOSFET) operate with?
(a) Zero (b) positive
(c) Negative (d) any of the above

2. Midpoint bias for a D-MOSFET is ID = ________, obtained

by setting VGS = 0.
(a)IDSS / 2 (b) IDSS / 3.4
(c)IDSS (d) zero

3. Which of the following devices has the highest input

resistance?
(a) Diode (b) JFET
(c)MOSFET (d) Bipolar junction transistor

4. Which of the following FETs has the lowest input

impedance?
(a)JFET (b) MOSFET depletion-type
(c)MOSFET enhancement-type (d) none of the above

5. Which of the following transistor(s) has (have) depletion and

enhancement types?
(a)BJT (b) JFET
(c)MOSFET (d) None of the above

6. Which of the following applies to a safe MOSFET handling?

(a) Always pick up the transistor by the casing.
(b) Power should always be off when network changes are
made.
(c) Always touch ground before handling the device.
(d) All of the above

7. It is the insulating layer of ________ in the MOSFET

construction that accounts for the very desirable high input
impedance of the device.
(a) SiO (b) GaAs (c) SiO2 (d) HCl

8. How many terminals can a MOSFET have?

(a) 2 (b) 3 (c) 4 (d) 3 or 4

9. Which of the following applies to MOSFETs?

(a) No direct electrical connection between the gate terminal
and the channel
(b) Desirable high input impedance
(c) Uses metal for the gate, drain, and source connections
(d) All of the above
10. Which of the following is (are) the advantage(s) of VMOS
over MOSFETs?
(a) Reduced channel resistance
(b) Higher current and power ratings
(c) Faster switching time
(d) All of the above

11. Identify the p-channel D-MOSFET

(a) a (b) b (c )c (d) d

(a) (b) (c) (d)

12. Identify the n-channel D-MOSFET.

(a)a (b)b (c)c (d)d

(a) (b) (c) (d)

13. Identify the p-channel E-MOSFET.

(a) a (b)b (c)c (d)d

(a) (b) (c) (d)

14. Identify the n-channel E-MOSFET.

(a)a (b)b (c)c (d)d

(a) (b) (c) (d)

15. Refer to the given figure. ID = 6 mA. Calculate the value of
VDS.

(a) 13.2 V (b) 10 V (c) 6.8 V (d) 0 V

+ 20 V

2.2 K

5 M

16. referring to the following transfer curve, determine the level

of VGS when the drain current is 20 mA. I (mA) D
17
(a)1.66 V 16
15
14
(b)1.66 V 13
12
(c)0.66 V 11
10
(d)0.66 V 9
8
7
6
5
4
3
2
1

-4 -3 -2 -1 0 +1 VGS
VP

17. At room temperature, a possible value for the mobility of

electrons in the inversion layer of a silicon n-channel
MOSFET is (EC-GATE 2010)

(a) 450cm2/Vs (b) 1350 cm2/V-s

(c) 1800cm2/V-s (d) 3600cm2/V-s
18. Match List I (Symbols) with List II (Devices) and select the
correct answer: (EE-IES-2000)

List I List II

A. G 1. Depletion mode MOSFET

B. G 2. P-channel JFET

C. G 3. N-channel JFET

D. G 4. Enhancement mode MOSFET

A B C D
(a) 2 1 4 3
(b) 4 3 2 1
(c) 2 3 4 1
(d) 4 1 2 3

19. The drain current of a MOSFET in saturation is given ID = K

(VGS VT)2 where K is a constant. The magnitude of the
Transconductance gm is (EC-GATE 2008)
K VGS VT
2

(a) (b) 2K(VGS VT)

VDS
K VGS VT
2
Id
(c) (d)
VGS VDS VGS
21. For an n-channel MOSFET and its transfer curve shown in
figure, the threshold voltage is (EC-GATE 2005)
ID
VD = 5V
Transfer D
Characteristics
VG = 3V

VGS
G
S
1V
VS = 1V
(a) 1V and the device is in active region.
(b) 1V and the device is in saturation region
(c) 1V and the device is in saturation region.
(d) 1V and the devices is in active region.

22. Consider the following two statements about the internal

conditions in an n-channel MOSFET operative in the active
region. (EC-GATE-2009)

S1: The inversion charge decreases from source to drain

S2: The channel potential increases from source to drain

Which of the following is correct?

(a) only S1 is true
(b) Both S1 and S2 are false
(c) Both S1 and S2 are true, but S2 is not reason for S1
(d) Both S1 and S2 are true, and S2 is a reason for S1
24. A MOS capacitor made using p-type subtract is in the
accumulation mode. The dominant charge in the channel is
due to the presence of (EC-GATE 2005)
(a) Holes (b) Electrons
(c) Positively charged ions (d) negatively charged ions

25. A FET operates on (JTO -2001)

(a) Majority carries only (b) Minority carries only
(c) Positively charged ions only (d) none

26. MOSFET can operate in (JTO -2001)

(a) Depletion mode (b) Enhancement mode
(c) Depletion-only mode (d) both a & b

27. Consider the following statements S1 and S2.

(EC-GATE 2004)
S1 : The threshold voltage (VT) of a MOS capacitor
decreases with increase in gate Oxide thickness.
S2 : The threshold voltage (VT) of a MOS capacitor decreases
with increases in substrate doping concentration.

Which one of the following is correct?

(a) S1 is FALSE and S2 is TRUE
(b) Both S1 and S2 are TRUE
(c) Both S1 and S2 are FALSE
(d) S1 is TRUE and S2 is FALSE

28. The output VI characteristics of an enhancement type

MOSFET has (ISRO SET-2009)
(a) Only an ohmic region
(b) Only a saturation region
(c) An ohmic at low voltage value followed by a saturation
region at higher voltages
(d) An ohmic region at large voltage values preceded by a
saturation region at lower voltages

29. The drain of an n-channel MOSFET is shorted to the gate so

that VGS = VDS. The threshold voltage (VT) of MOSFET is
1V. If the drain current ID is 1 mA for VGS = 2V then for
VGS = 3V ID is (EC-GATE 2004

(a) 2 mA (b) 3 mA (c) 9 mA (d) 4 mA

30. For an n channel enhancement type MOSFET if the source

is connected at a higher potential than that of the bulk (i.e.
VSB > 0), the threshold voltage VT of the MOSFET will
(EC-GATE 2003)
(a) remain unchanged (b) decrease
(c) change polarity (d) increase
31. Which of the following devices is used at the first stage of an
electronic voltmeter? (EC-IES-2009)

(a) BJT (b) SCR (c) MOSFET (d) UJT

32. A power MOSFET is a (ISRO SET-2009)

(a) Current controlled device
(b) Frequency controlled device
(c) Voltage controlled device
(d) None of the above

33. MOSFET can be used as a (EC-GATE 2001)

(a) current controlled capacitor
(b) voltage controlled capacitor
(c) current controlled inductor
(d) voltage controlled inductor

34. The effective channel length of a MOSFET in saturation

decreases with increase in (EC-GATE 2001)

(a) Gate voltage (b) drain voltage

(c) Source voltage (d) body voltage

35. The threshold voltage of an n-channel MOSFET can be

increased by (EC-GATE1994)
(a) Increasing the channel dopant concentration.
(b) Reducing the channel dopant concentration
(c) Reducing the gate-oxide thickness
(d) Reducing the channel length.

36. When the gate to source voltage (VGS) of a MOSFET

with threshold voltage of 400 mV, working in saturation is
900 mV, the drain current is observed to be 1 mA, Neglecting
the channel width modulation effect and assuming that the
MOSFET is operating at saturation. The drain current for an
applied VGS of 1400 m V is (EC-GATE 2003)

(a) 0.5 mA (b) 2.0 mA (c) 3.5 mA (d) 4.0 mA

38. The source of a silicon (ni = 1010 per cm3) n channel MOS
transistor has an area of 1 sq m and a depth of 1 m. If the
dopant density in the source is 1019/cm3, the number of holes
in the source region with the above volume is approximately
(EC-GATE 2012)
7
(a) 10 (b) 100 (c) 10 (d) 0

41. MOSFET can be used as a (ISRO SET-2010)

(a) Current controlled capacitor
(b) Voltage controlled capacitor
(c) Current controlled inductor
(d) Voltage controlled inductors

45. The MOSFET switch in its onstate may be considered

equivalent to: (EC-GATE-1999)
(a) Resistor (b) inductor
(c) Capacitor (d) battery

47. The p-type substrate in a conventional pn-junction isolated

integrated circuit should be connected to (EC-GATE-1996)
(a) No where, i.e. left floating
(b) A dc ground potential
(c) The most positive potential available in the circuit
(d) The most negative potential available in the circuit

49. In a MOSFET, the transfer characteristics can be used to

determine which of the following device parameters?
(EC-IES-2008)
(a) Threshold voltage and output resistance
(b) Trans-conductance and output resistance
(c) Threshold voltage and trans-conductance
(d) Trans-conductance and channel length modulation
parameter

50. Thermal run way is not possible in FET because as the

temperature of FET increases (ISRO SET-2010)

(a) The mobility decreases

(b) The transconductance increases
(c) The drain current increases
(d) None of the above

51. In n-channel enhancement MOSFET, at a fixed drain voltage

(EC-IES-2008)
(a) The drain current is maximum at zero gate voltage and it
decreases with applied negative gate voltage
(b) The drain current has a finite value at zero gate voltage
and it increases or decreases with the applied voltage of
proper polarity
 (c) The drain current is zero at zero gate voltage and it
increases with the positive applied gate voltage
(d) The drain current is zero for negative bias voltage to gate
and it increases as negative gate bias is decreased in
magnitude.

53. The threshold voltage of an n-channel enhancement mode

MOSFET is 0.5V. When the device is biased at a gate
voltage of 3V. pinch off would occur at a drain voltage of
(EC-IES-1998)
(a) 1.5V (b) 2.5V (c) 3.5V (d) 4.5V

54. Consider the following statements:

The threshold voltage of a MOSFET can be lowered by
1. Using a thinner gate oxide
2. Reducing the substrate concentration
3. Increasing the substrate concentration
(a) 3 alone is correct (b) 1 and 2 are correct
(c) 1 and 3 are correct (d) 2 alone is correct

56. In modern electronic multi meter a FET or MOSFET is

preferred over BJT because (EE-IES-2005)

(a) Its input resistance is low

(b) Its input resistance is high
(c) Its input resistance is high and does not vary with the
change of range
(d) It is cheaper

57. A source follower using an FET usually has a voltage gain

which is (ISRO SET-2010)

(a) greater than +100

(b) slightly less unity but positive
(c) exactly unity negative
(d) about -10

59. In an MOS transistor, the gate source input impedance is

(EC-IES-2001)
1. lower than the input impedance of a BJT
2. higher than the input impedance of a BJT
3. lower than the input impedance of a JFET
4. higher than the input impedance of a JFET
(a) 1 alone (b) 2 and 3 (c) 4 alone (d) 2 and 4
 62. A MOSFET device has both n- type source and drain and the
drain current flows only when gate to source voltage exceeds
+2.0V. Which of the following conclusion can be drawn
about the device? (EC-IES-2005)
1. The device is an n-channel MOSFET
2. It is enhancement type MOSFET
3. It has threshold voltage of +2V
4. The channel conductance is determined by the hole
mobility
Select the correct answer using the code given below:
(a) 1 and 3 (b) 1, 2 and 3
(c) 2 and 4 (d) 1, 2, 3 and 4

64. As the drain voltage is increased for a junction FET in the

pinch off region then the drain current (JTO -2001)
(a) become zero (b) abruptly decreases
(c) abruptly increases (d) remains constant

66. Consider the following devices: (EC-IES-1999)

1. BJT in CB mode
2. BJT in CE mode
3. JFET
4. MOSFET
The correct sequence of these devices in increasing order of
their input impedance is
(a) 1, 2, 3, 4 (b) 2, 1, 3, 4
(c) 2, 1, 4, 3 (d) 1, 3, 2, 4

Common data for questions 67 & 68

In the three dimensional view of a silicon n-channel MOS
transistor shown below, = 20 nm. The transistor is of width 1
m. The depletion width formed at every p-n junction is 10 nm.
The relative permitivities of Si and SiO2, respectively, are 11.7 and
3.9, and 0 = 8.9 10-12 F/m. (EC-GATE 2012)
1 m

1 m
D 1 nm

0.2 m 0.2 m
D S

0.2 m 0.2 m
P substrate

B
67. The source-body junction capacitance is approximately
(a) 2 fF (b) 7 fF (c) 2 pF (d) 7 pF

68. The gate-source overlap capacitance is approximately

(a) 0.7 fF (b) 0.7 pF (c) 0.35 fF (d) 0.24 pF

69. The parameter of the transistor in fig. are VTN = 1.2V,

Kn = 0.5mA/V2 and = 0. The voltage VDS is
(EC-IES-2003) +5V

50A
(a) 1.69V (b) 1.52V
(c) 1.84V (d) 0

70. The parameter of the transistor in fig. are VTN = 0.6V and Kn
= 0.2mA/V2. The voltage VS is
+9V
(a) 1.72V
(b) 1.72V 24k

(c) 7.28V
(d) 7.28V
0.25mA

9V
71. In the circuit of fig. the transistor parameters are VTN = 1.7V
and Kn = 0.4mA/V2. If ID = 0.8mA and VD = 1V, then
value of resistor RS and RD are respectively
+5V
(a) 2.36K, 5K
RD
(b) 5K, 2.36 K

(c) 6.43 K, 8.4K

50k
(d) 8.4K, 6.43K RS

5V
72. The parameters for the transistor in circuit of fig. are
VTN = 2V and Kn = 0.2mA/V2. The power dissipated in the
transistor is +10V

(a) 5.84mW
(b) 2.34mW
(c) 0.26mW 10k
(d) 58.4mW

Statement for Linked answer Questions 73 & 74

Consider the circuit shown in fig.

The both transistor have parameter as follows +5V
VTN = 0.8V, K1n = 30 A/V2
M1

V0
M2

73. If the width-to length rations of M1 and M2 are

W W
= 40. The output V0 is
L 1 L 2
(a) 2.5V (b) 2.5V (c) 5V (d) 0V

W W
74. If the ratio is = 40 and = 15, then V0 is
L 1 L 2
(a) 2.91V (b) 2.09V (c) 3.41V (d) 1.59V

75. In the circuit of fig. the transistor parameters are

VTN =1V and K= 36A/V2. If ID = 0.5mA, V1 = 5V and V2
= 2V then the width to-length ratio required in each transistor
is
+10V

W W W

L 1 L 2 L 3 M1
(a) 1.75 6.94 27.8
V1
(b) 4.93 10.56 50.43
M2
(c) 35.5 22.4 8.53
(d) 56.4 38.21 12.56 V2
M3
76. The transistors in the circuit of fig. have parameter VTN =
0.8V, K1n = 40A/V2 and = 0. The width to-length ratio
W
of M2 is = 1. If V0 = 0.10V when Vi = 5V, then
L 2
W +5V
for M1 is
L 1
M2
(a) 47.5
V0
(b) 40.5
Vi M1
(c) 28.4
(d) 20.3

77. For the circuit in fig. the transistor parameter are VTN = 0.8V
and K1n = 30A/V2. If output voltage is V0 = 0.1V, when
input voltage is Vi = 4.2V, the required transistor width to
length ratio is
+5V
(a) 1.568
10K
(b) 0.986 V0
(c) 48 Vi
(d) 1.843

78. In the circuit shown below. For the MOS transistors,

n Cox 100 A / V 2 and the threshold voltage VT = 1V. The
voltage Vx at the source of the upper transistor is
6V
(EC-GATE 2011)
(a) 1V

(b) 2V 5V
W/L = 4

(c) 3V Vx

(d) 3.67V
W/L = 1
 Common data for questions 79 & 80

The figure shows the high-frequency capacitance-voltage (C-V)

characteristics of a Metal /Si O2/silicon (MOS) capacitor having an
area of 1 10-4 cm2. Assume that the permittivities 0 r of
silicon and Si O2 are 1 10-12 F/cm and 3.5 10-13 F/cm
respectively C
7pF

1pF
V
0
79. The gate oxide thickness in the MOS capacitor is:
(EC-GATE 2007)
(a) 50nm (b) 143nm (c) 350nm (d) 1m

80. The maximum depletion layer width in silicon is

(EC-GATE 2007)
(a) 0.143m (b) 0.857m (c) 1m (d) 1.143m

81. Both transistors T1 and T2 in figure have a threshold voltage

of 1Volt. The device parameters K1 and K2 of T1 and T2 are,
respectively, 36A/V2 and 9A/V2. The output voltage V0 is
(EC-GATE 2005) 5v

(a) 1V
(b) 2V T1
(c) 3V
(d) 4V
V0

T2
82. The given figure shows a composite transistor consisting of a
MOSFET and a bipolar transistor in cascode
(EC-IES-1991)
The MOSFET ha a trans-conductance gm of 2mA/V and the
bipolar transistor has ( hfe) of 99. The overall
Transconductance of the composite transistor is
VCC
(a) 198 mA/V

(b) 19.8 mA/V

(c) 1.98 mA/V C is very large

(d) 0.198 mA/V

83. In the MOSFET amplifier shown in figure below, the

transistor has = 50 rd = 10K, Cgs = 5pF, Cgd = 1pF and
Cds = 2pF. Draw a small signal equivalent circuit for the
amplifier for mid band frequencies and calculate its mid band
voltage gain. (EC-GATE 1994)
VDD

RD = 20K
rgre = 100K
50F
+ RL = 20K
VS
RS = 1K
_

87. Group I lists four different semiconductor devices. Match

each device in Group I with its characteristic property in
Group II. (EC-GATE-2007)
Group I Group II
P. BJT 1. Population inversion
Q. MOS capacitor 2. Pinch off voltage
R. LASER diode 3. Early effect
S. JFET 4. Flat-band voltage
Codes:
P Q R S P Q R S
(a) 3 1 4 2 (b) 1 4 3 2
(c) 3 4 1 2 (d) 3 2 1 4
88. The variation of drain current with gate-to source voltage
(ID-VGS characteristic) of a MOSFET is shown in. The
MOSFET is (EE-GATE-2003)
(a) an n-channel depletion mode device ID
(b) an n-channel enhancement mode device
(c) a p-channel depletion mode device
(d) a p-channel enhancement mode device
0 VGS
90. The MOSFET switch in its on-state may be considered
equivalent to: (EE-GATE-1998)
(a) resistor (b) inductor
(c) capacitor (d) battery

91. For the n-channel enhancement MOSFET shown in figure,

the threshold voltage Vth = 2V. The drain current I D of the
MOSFET is 4 mA when the drain resistance is 1K . If the
value of R D is increased to 4k , the drain current I D will
become 10V (EE-GATE-2003)
(a) 2.8 mA ID RD
(b) 2.0 mA
(c) 1.4 mA
(d) 1.0 mA

Fig.

93. The transistor in the circuit of fig. has parameters IDSS = 8mA
and VP = 4V. The value of VDSQ is
+20V
(a) 2.7V
(b) 2.85V 140K 2.7K

(c) 1.30V
(d) 1.30V 60K 2K

94. In the circuit of fig., the parameters are gm = 1mA/V,

r0 = 50K. The gain Av = v0/vd is VDD

(a) 8.01
60K 10K
(b) 8.01
(c) 14.16
(d) 14.16 Vs 300K
 Common Data Questions 95 & 96

+10V
For the circuit shown in fig.
transistor parameters are 10K
VTN = 2V, Kn = 0.5mA/V2 and V0
= 0. The transistor is in
saturation. Vi

VGG

95. If IDQ is to be 0.4mA, the value of VGSQ is

(a) 5.14V (b) 4.36V (c) 2.89V (d) 1.83V

96. The values of gm and r0 are

(a) 0.89mS, (b) 0.89 mS, 0
(c) 1.48mS, 0 (d) 1.48mS,

97. The small signal voltage gain Av is

(a) 14.3 (b) 14.3 (c) 8.9 (d) 8.9

Common Data Questions 98 & 99

Consider the source-follower circuit in fig.

The values of parameter are gm= = 2mS and r0 = 100K.
+5V

R0
Vi V0
500K I
VGG 4K

5V

98. The voltage gain Av is

(a) 0.89 (b) 0.89 (c) 2.79 (d) 2.79

99. The output resistance R0 is

(a) 100 K (b) 0.498K
(c) 1.33K (d) None of these
103. Consider the following statements regarding an FET:
(EC-IES2010)
1. Its operation depends upon the flow of majority carriers
only
2. It has a high input resistance
3. It is suitable for high frequency
4. Its operation depends upon the flow of both majority and
minority carriers.
Which of the above statements are correct?
(a) 1, 2, 3 and 4 (b) 1 and 2 only
(c) 2 and 3 only (d) 3 and 4 only

107. Which of the following devices is used in the

microprocessors? (EC-IES 2009)
(a) JFET (b) BJT
(c) MOSFET (d) CMOS

109. Consider the following statement: (EC-IES 1997)

The threshold voltage of a MOSFET can be lowered by
(a) Using a thinner gate oxide.
(b) Reducing the substrate concentration.
(c) Increasing the substrate concentration.

Of these statements
(a) 3 alone is correct (b) 1 and 2 are correct
(c) 1 and 3 are correct (d) 2 alone is correct
110. An N-channel enhancement mode MOSFET with threshold
voltage of 1V is biased at VGS = 2V and VDS = 2V. If the
drain voltage is doubled to 4V, the drain-to-source current
will (JTO -2001)
(a) double (b) more than double
(c) increase only slightly (d) become half

111. To double the drain current of an N-channel enhancement

mode MOSFET biased saturation. (JTO -2001)

(a) Channel length should be doubled

(b) Channel width should be halved
(c) Channel length should be halved
(d) Oxide thickness should be doubled.

112. Which one of the following gain equations is correct from a

MOSFET common-source amplifier? (gm is mutual
conductance, and RD is load resistance at the drain)
(EC-IES 2007)
(a) AV g m / R D (b) A V g m R D
(c) A V g m /(1 R D ) (d) A V R D / g m
113. Consider the following statements related to a CMOS
(Complementary metal oxide semiconductor) inverter:
(EC-IES2006)
1. It combines an n-channel and a p-channel MOS transistor.
2. For binary 1 input, both transistors are OFF.
3. For binary 0 input, both transistors are ON.
4. Whatever is the state of input, one transistor is ON while
the other is OFF.
Which of the statements given above are correct?

(a) 1,2,3 and 4 (b) 1 and 4

(c) 1,2 and 3 (d) 3 and 4

114. A MOSFET devices has both n -type source and drain, and
the drain current flows only when gate to source voltage
exceeds +2.0V. Which of the following conclusions can be
drawn about the device? (EC-IES 2005)
1. The device is an n-channel MOSFET
2. It is enhancement type MOSFET
3. It has threshold voltage of value +2.0V
4. The channel conductance is determined by hole mobility

Select the correct answer using the code given below:

(a) 1 and 3 (b) 1,2 and 3

(c) 2 and 4 (d) 1,2,3 and 4

115. In the circuit given above, both VDD

transistors have the same VT. What is
the approximate value of the highest
possible output voltage Vout, if V can
range from 0 to VDD? (Assume
0 < VT < VDD) (EC-IES 2005)

(a) VDD - VT Vout

(b) VDD Vin

(c) VT
(d) 0

116. The threshold voltage of an n-channel enhancement mode

MOSFET is 0.5 V. When the device is biased at a gate
voltage of 3V.Pinch-off would occur at a drain voltage of
(EC-IES 1998)
(a) 1.5V (b) 2.5V (c)3.5V (d) 4.5V
117. Match List-I (State of operation of an N-MOSFET) with List-
II (Required condition) and select the correct answer using
the codes given below the lists: (EC-IES 2002)
List-I List-II
A. OFF 1. Vgs Vth , and Vds Vgs Vth
B. Linear region 2. Vgs Vth , and Vds Vgs Vth
C. Non-linear region 3. Vgs Vth
D. Saturation region 4. Vgs Vth
Codes:
A B C D
(a) 2 3 1 4
(b) 4 1 3 2
(c) 2 1 3 2
(d) 4 3 1 2

118. The FET shown above is a (EE-IES2010)

(a) Common drain OUTPUT

D

(b) Common gate

(c) Common source S

INPUT
(d) Common source follower

119. The MOSFETS M1 and M2 are connected in parallel to carry

a total current of 20 A. The drain to source voltage of M1 is
2.5 V and that of M2 is 3V. What are the drain currents of M1
and M2 when the current sharing series resistances are each
of 0.5? (EE-IES2009)

(a) 10.5 A and 9.5 A (b) 9.5 A and 10.5 A

(c) 10.5 A and 10.5 A (d) 9.5 A and 9.5 A

121. A power MOSFET is a (DRDO SET-2008)

(a) Voltage controlled device

(b) Current controlled device
(c) Frequency controlled
(d) None of the above
123. In modern electronic multi meter a FET or MOSFET is
preferred over BJT because (EE-IES2005)

(a) Its input resistance is low

(b) Its input resistance is high
(c) Its input resistance is high and does not vary with the
change of range
(d) It is cheaper

124. In a MOSFET, the pinch-off voltage refers to (JTO -2009)

(a) drain-to-source voltage at which drain-to-source current

is constant
(b) gate-to-source voltage at which gate-to-source current is
constant
(c) drain-to-source voltage at which gate-to-source current is
zero
(d) gate-to-source voltage at which drain-to-source current is
zero

126. Which of the following describe(s) the difference(s) between

JFETs and depletion- Type MOSFETs?

(a) VGS can be positive or negative for the depletion-type.

(b) ID can exceed IDSS for the depletion-type.
(c) The depletion-type can operate in the enhancement mode.
(d) All of the above

127. Which of the following is (are) true of a self-bias

configuration compared to a fixed-Bias configuration?

(a) One of the dc supplies is eliminated.

(b) A resistor RS is added.
(c) VGS is a function of the output current ID.
(d) All of the above

128. MOSFET digital switching is used to produce which digital

gates?

(a) inverters (b) NOR gates

(c) NAND gates (d) all of the above
130. Two identical NMOS transistors M1 and M2 are connected
as shown below. Vbias is chosen so that both transistors are in
saturation. The equivalent gm of the pair is defined to be
I out
at constant Vout. The equivalent gm of the pair is Iout
V Vout
(EC-GATE-2008)
V M2
(a) The sum of individual gms of the transistors bios
(b) The product of individual gms of the transistors
(c) Nearly equal to the gm of M1 V1 M1
(d) Nearly equal to gm/g0 of M2.

131. In the MOSFET amplifier of Fig., the signal outputs V1 and

V2 obey the relationship (EC-GATE-1998)

V2 RD
(a) V1 =
2 +
V V1
(b) V1 = - 2
2
+
(c) V1 = 2V2 Vi RD V2
2
(d) V1 = 2V2

133. For what value of R2 is VGSQ equal to 1 V?

18V
(a) 10 M

(b) 100 M 1.8K

110M
(c) 110 M V0

V0 IDSS=6mA
(d) 220 M Vp=3V

R2
750
RS
134. For what value of RS can the depletion-type MOSFETs
operate in enhancement mode? 20V

(a)2.4 K
6.2K
(b)5 K
V0

(c) 6.2 K IDSS = 8mA

V0 Vp = 8V
(d) None of the above
1M RS

135. For the circuit shown in the following figure, transistors M1

and M2 are identical NMOS transistors. Assume the M2 is in
saturation and the output is unloaded.
The current Ix is related to Ibias as (EC-GATE 2008)

(a) Ix = Ibias + Is
VDD
(b) Ix = Ibias

(c) Ix = Ibias Is
Ibias
RE
VD
V Vout
(d) I x I bias VDD out Ix
RE M1 M2
IS