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Anecdotes
Intels 8086
Stanley Mazor
Intel advertised its new CPU chip for PC and laptop com-
puters in 1993 as the Intel Pentium processor. This chip
was the fifth generation (586) evolved from the original
8086 chip, developed in 1976. The results of this 30-year
lineage (e.g. 186, 286, 386, 486) have allowed Intel to
dominate microcomputers ever since.12
In 1976, I had just returned from being Intel
Europes first applications engineer and was doing mar-
ket development for the consumer and game market-
place. Having worked on three earlier microcomputer
chips, I consulted with, but was not part of the 8086
CPU design organization. I recall being in one architec-
ture meeting where I suggested removing a single non-
essential instruction. This was unusual, as most
contributors add to an instruction set. In fact, instruc-
tion sets become unwieldy because of this design-by-
committee effect. Mostly, I just observed from else-
where in the company. Still, my recollections of the
events surrounding the 8086 CPU chip development re-
veal that the project was not originally planned, but
rather was a crash, catch-up project that strove to fill
a gap in the Intel product line caused by problems
with the 8800 and 8085 chip designs.
Intel 8800 CPU
Chip manufacturers offer new products as users
needs expand and semiconductor processing improves.
Generally, there are two categories of new products:
minor enhancements that extend the life of a product
(mid-life kickers), and major product enhancements
that offer dramatic increase in capabilities. Marketing
names (numbers) new products accordingly. For exam-
ple, Intels first 8-bit CPU chip was called the 8008.38
Two years later, the 8080 chip was introduced, shifting
the last 8 in 8008 one position to the left reflected a
major (10x) speed improvement over the earlier
8008.910 A year later, a slightly improved CPU was des-
ignated 8085. In 1976, the code name for Intels in-
tended major new 8-bit CPU chip (8800) would
follow this shifted-8 tradition, with another expected
large chip performance gain.11
It is the computer architects job to choose the partic-
ular improvements for the new product. Justin Rattner
was the 8800 CPUs chief architect, under project man-
ager Bill Lattin, and he had no personal ties to the ear-
lier Intel chips. On the contrary, he only witnessed their
shortcomings. The 8800 was not designed for any spe-
cific application, as was the 4004 for the Busicom calcu-
lator and the 8008 for Datapoints terminal, so Rattner
had the luxury of taking a fresh look at microcomputer
architecture.
Rattner told me that if an architect chooses some
finite number of visible resources (e.g. eight or
IEEE Annals of the History of Computing Published by the IEEE Computer Society
Editor: Dave Walden
16 registers) that the programmer would always hit
the limit and be unhappy. He said there should either
be a seemingly infinite number of resources or none
visible at all. He reckoned that although registers
offer a speedup (compared to using main memory)
they should be invisible to the programmer. Hence,
the 8800 CPU was a radical departure from the existing
microcomputers and most large-scale computers of
the day that provided programmer visible registers,
such as
MOV R1, R2 [move data to R1 from R2]
Cleverly, Rattner felt that microcomputer CPUs
should be able to be ganged together to run multiple
programs in parallel, and his team included multiprog-
ramming within the CPUs microcode. Because custom-
ers could easily implement multiple processors to
enhance performance and tackle heavier program
loads, the 8800 architecture team wasnt worried
about an individual CPUs performance. In hindsight,
this was a mental trap. Normally, CPU architecture
starts with a speed objective, and one would have
expected the 8800 to be 5x to 10x faster than the
8080. However, with multiple CPUs planned, speed
wasnt emphasized in the 8800 specification because
the designers attitude was dont worry about it.
Another breakthrough on the 8800 CPU was repre-
sentations for multiple data types including floating-
point numbers and variable-length instructions. Every
instruction could vary in size, in stark contrast to earlier
machine instruction formats that rigorously obeyed
memory word boundaries. Instructions were defined
in terms of the number of bits occupied, and byte boun-
daries were not a constraint. Hardware shifters within
the 8800 CPU would locate instructions within mem-
ory words.
The 8800 CPU architecture started with a blank slate,
was unbounded, and had no compatibility constraints
with earlier processors. Most designers would consider
this an ideal environment for defining a new product.
However, in my experience, constraints that define
the scope and boundaries, and appear to be limiting,
often lead to success.
Some of us on the periphery of the 8800 design wor-
ried that the architectural features were top heavy and
ahead of the market. In particular, had I been working
on the project after having worked on a high-level lan-
guage computer at Fairchild,1213 I might have been
suspicious of firming software into microcode, but I
was observing from a distance.
In 1981, five years and hundreds of millions of dol-
lars later, Intel announced the 8800 as the IAPX432.
1058-6180/10/$26.00  2010 IEEE
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Anecdotes
Table 1. Intel CPU chip metrics.
Density Gate delay
Chip Year Transistors factor (ns)
8008 1972 2,000 1 30
8080 1974 4,500 0.9 15
8085 1976 6,500 0.7 5 speed for early Intel CPU chips. Moving
8086 1978 29,000 0.3 3 from 8008s PMOS process to the 8080s
Today (more than 25 years later), with more
than one billion transistors on a chip, there
might be a better match between the 8800 ar-
chitecture and modern semiconductor pro-
cesses,14 but lets get back to 1975.
Intel 8085 and competition
In 1975, a year after the 8080 CPU chip in-
troduction, Intel engineers were working on
two different projects: the 8800 and the
8085, a mid-life kicker for the 8080. The
8085 chip enhanced the 8080 by adding 12
new instructions, several integrated resources,
and a simpler hardware interface.15 However,
while Intel was struggling with its new chip
designs, competition wasnt standing still.
After successfully launching Intels 4004,
8008, and 8080, Federico Faggin founded a
competing company, Zilog, and brought the
8080s chip designer Shima Masatoshi from
Intel to join them. Their resultant Z-80 CPU
chip was a great improvement over Intels
8080. Zilog experienced considerable success,
especially in the nascent personal and hobby
computer marketplace. Many designers
found the 8085 inferior to the Z-80, and
Intel was losing design wins to the Motor- memory than the 8080s 64 Kbytes. Custom-
ola 6800 and the MOS Technology 6502.
Intel also faced competition from TIs 16-bit
CPU (TMS 9900). Intel argued that the micro-
computer customer, unlike the minicomputer
customer, didnt need 16-bits. (Actually for
signal processing 14-bits would be a nice
choice, but that was not a dominant applica-
tion in the late 1970s.) Clearly, Intel needed a
breakthrough processor such as the 8800, but
the project was languishing with a constant
time to completionalways a year away
and the 8085 wouldnt be competitive.
By mid-1976, the manager of Intels
Microcomputer division, Bill Davidow, saw
a poor prognosis for the 8085 even before it
was completed and promises of the 8800
that werent materializing. Accordingly, he
put together a crash program to develop an
improved follow-on CPU chip to the 8080
and 8085. To save Intels market share, this
new chip would be compatible with the
76 IEEE Annals of the History of Computing
earlier generation; the designation 8086
emphasized this point.16 By taking advantage
of the latest NMOS semiconductor process, it
was believed that the 8086 would provide
more features and higher performance.17
Table 1 shows chip density and circuit
NMOS halved the on-chip circuit gate delay
(30 to 15 ns) and more than doubled the
transistor count (2,000 to 4.500). In just six
years, transistor count went up 15x and cir-
cuit speed improved 10x. More transistors
allow for more hardware that also improves
instruction execution performance. Each
generation of semiconductor process offered
at least two dimensions of improvement:
higher performance and higher density
(Moores law).1819
8086 development
By 1976, Intel had a respectable software
group that had developed an operating sys-
tem, ISIS, for Intels Intellec development
system and some experience in compiler
development. Drawing from this broader
spectrum, Davidow assembled a new design
team: Steve Morse and Bruce Ravenel from
software and architecture and Bill Pohlman,
James McKevitt and John Bayliss as chip
designers, with J.C. Cornet supervising. In
May 1976, Steve Morse began specifying the
instruction set for the 8086 CPU chip (see
Figure 1). He had a speed objective, an aes-
thetic objective (more complete instruction
set for both 8- and 16-bit data), and more
ers always wanted larger memory systems.
CPU compatibility
Computer users are concerned about pre-
serving their investment in software and
engineering and are reluctant to change com-
puters. On the other hand, they often need
the speed improvements offered by a new
CPU. High-level language programming
avoids ties to a particular CPUs instruction
codes, but microcomputers are often pro-
grammed using assembler language. Accord-
ingly, a CPU chip designer is burdened with
compatibility constraints from earlier and in-
ferior products when designing a new CPU.
There are several levels of CPU compatibility
for both the designer and user to consider:
 Upward versus downward. Will old software
run on a new CPU? Will software written
for a new CPU run on an old CPU?
[3B2] man2010010075.3d 6/2/010 16:21
Figure 1. Intel 8086 die photo. (Courtesy of Intel)
 Instruction machine code. Is the new CPU
object code identical to the old CPUs?
Will an old object program run on the
new CPU?
 Symbolic code. Is the symbolic assembler
programming language the same? Can
old symbolic programs be reassembled
for the new CPU?
 Translation 1:1 or not 1:1. Can an old sym-
bolic source program be converted to a
new format? For each old instruction, are
one or more instructions required?
Morse decided that 8086 CPUs instruc-
tions would be multibyte in length, just as
in the 8080 and 8085, but soon gave up on
machine code compatibility. With no such
compatibility, customer ROM chips would
need to be scrapped, but he reckoned this
Page 77
would be an acceptable trade-off. Maintain-
ing object program size was not an objective
either. These key decisions gave Morse some
freedom in selecting the new instruction set.
On the other hand, he would design the
8086 instruction set so that in most cases
there would be a single instruction mapping
1 to 1 from the older 8080. In a few cases, it
might be necessary to generate more than
one 8086 instruction to perform what the
8080 did in a single instruction. He recog-
nized that a software conversion tool could
convert 8080 source programs to an equiva-
lent 8086 source program. After assembling,
the new programs object code would proba-
bly occupy more memory but would function
the same as the old 8080 program.
Another constraint for the new 8086 CPU
resulted from the 12 new instructions
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Anecdotes
implemented in the yet to be announced
8085. Although 8085 users would benefit
from these new instructions, they would bur-
den the 8086 instruction set. Davidow made
a surprising and important decision: leave all
12 instructions on the already designed 8085
CPU chip, but document and announce only
two of them! A CPU chip is a monolithic sil-
icon structure that doesnt easily allow add-
ing or removing logical functions whereas
a CPUs paper reference manual is easily
modified.
16 versus 8 bits
The older 8080 provided a few 16-bit oper-
ations, including load, add, and shift. In con-
cert, these would let the programmer
reasonably code multiply and divide opera-
tions. A clear enhancement for the 8086
was to provide a complete set of 16-bit oper-
ations as well as multiply and divide hard-
ware. All the older chips 8-bit data
capabilities were also maintained. However,
if the 8086 had only a 16-bit data bus inter-
face to memory, it would have lost the com-
patibility with the earlier 8-bit processor and
the versatility to perform single byte opera-
tions. Worse than this, Intel sales and mar-
keting had made many disparaging remarks
about 16-bit CPUs, and Intel would have to
eat its words, all 16-bits of them. So the
mandate was for a CPU to have single byte
memory addressing but operating on 2-byte
datum as well. The 8086 was given a 16-bit
data bus to memory, and earlier 8-bit bus
memory systems wouldnt work with it.
Fortuitously, the 8086 CPU chip design
evolved into two separate products: the
8088 was instruction compatible with the
8086 but featured a one-byte-wide data bus
and could thus be easily placed into existing
8-bit computer systems, saving customers
from having to redesign their hardware
platform and memory system. The 8088
executed the same code but was just a little
slower than the 8086, which featured a 16-
bit-wide data bus. Hence, Intel could adver-
tise the 8086 family as both 8- and 16-bit
processors. The eventual IBM PC used
Intels 8086 CPU chip, and IBMs Display
Writer word processor used the 8088 CPU
chip.
Memory size
The 8008 could address only 16 Kbytes of
memory, and the 8080 could address up to
64 Kbytes. Most applications of their day fit
within these parameters, but computer users
78 IEEE Annals of the History of Computing
Although Intel had
originally intended the
8800 to be its third-
generation CPU, the
8086 played that role by
default in 1978.
needs for memory have historically always
increased. Memory addressing needed to be
expanded in the new 8086 CPU, and Intels
primary business was DRAM memory
chipsIntel wanted to sell more, bigger
memories.2021 Regrettably, 16-bit addresses
dont provide an easy way to address more
than 64 Kbytes. (For larger 24- or 32-bit com-
puters, their larger word sizes provide larger
addresses and consequently enable a lot
more memory).
The IBM 360 designers in 1960 were also
concerned with memory addressing.22 That
machines instructions used three compo-
nents to generate a memory address:
 12-bit displacement in the instruction,
 a base register to hold a 16-bit address for
the start of a data region, and
 an index register to select a unique datum.
These three values were added together to
generate a memory address. The benefit is
that instructions were smaller, holding only
12-bits of address. In a typical program, a sub-
routine call uses a branch and link register
(BALR) instruction to load a base register
with the subroutines data region address.
Improving on this idea, RCAs CPU shifted
the index register value to the left depending
on the data type being referenced. This saved
the programmer from having to correct an
index value for the referenced data type.
These two mainframe CPUs provided two im-
portant ideas: using registers to augment a
memory address and shifting a register prior
to adding its value. However, because any
one of the 16 general-purpose registers
could be chosen in both these systems,
4 bits of the instruction were used to desig-
nate an index or base register.
Morse extended these two ideas in his
8086 CPU design. He partitioned memory
[3B2] man2010010075.3d 6/2/010 16:21 Page 79
into regions for code, data, and stack and
used specialized 16-bit segment registers:
code segment (CS), data segment (DS), and
stack segment (SS). Segment register selection
was implicit, saving instruction coding bits.
These registers were chosen automatically;
the instruction pointer (IP) register (program
counter) was always in the CS, the stack
pointer was always within the SS, and data
references were to the DS. To enable data
transfer between two different segments,
one extra segment (ES) register was provided,
which was chosen with an explicit instruc-
tion prefix byte when needed.
Extending RCAs idea, Morse called for
shifting a 16-bit segment register value 4 bits
to the left before adding the address displace-
ment, forming a 20-bit address. Therefore,
although the 8086 was a 16-bit CPU, every
address was 20 bits wide and memory could
total 1 Mbyte. Typically, an 8086 program-
mer organized memory with numerous seg-
ments, less than 64 Kbytes each. The long
subroutine call instruction loaded both the
IP and the CS register to set the context for
a subroutine similar to the IBM 360s use of
the BALR instruction.
8086 legacy
Although Intel had originally intended the
8800 to be its third-generation CPU, the 8086
played that role by default in 1978. Con-
strained to be compatible with the 8080 fam-
ily, it influenced its precursor (the 8085) and
dropped a few 8080 features. Although it
was decreed to not have floating-point arith-
metic, an honor reserved for the 8800,
the 8086 was soon joined by the 8087
floating-point coprocessor. Over the follow-
ing generationsthe 286, 386, 486, and
Pentiumenhancements provided memory
protection, dynamic memory management,
and 32-bit data.
Even though it was a crash, stop-gap pro-
gram, the 8086 CPU provided a solid base for
successive and remarkable generations of
CPU chips at Intel (see Figure 1). Its talented
computer chip architects were versatile and
creative in response to the challenge of
building a new, but compatible computer
chip.
References
1. S. Mazor, The History of the Microcomputer,
Readings in Computer Architecture, M. Hill,
N. Jouppi, and G. Sohi, eds., Morgan Kaufman,
2000, p. 16.
2. R. Noyce and M. Hoff, A History of Microproc-
essor Development at Intel, IEEE Micro, vol. 1,
no.1, 1981, pp. 8-21.
3. S. Mazor, Micro to Mainframe, IEEE Annals of
the History of Computing, vol. 27, no. 2, 2005,
pp. 82-84.
4. MCS-4 Micro Computer Set, Data Sheet
#7144, Intel, 1971.
5. M. E. Hoff, S. Mazor, and F. Faggin, Memory
System for a Multichip Digital Computer,
US Patent #3,821,715, Intel Corp., June 1974.
6. S. Mazor, 8-Bits of Irony, IEEE Annals of the His-
tory of Computing, vol. 28, no. 2, 2006, pp. 73-76.
7. MCS 8 User Manual, Intel, 1972.
8. G. Bylinsky, Here Comes the Second Com-
puter Revolution, Fortune, Nov. 1975.
9. S. Mazor, Intel 8080 CPU Chip Development,
IEEE Annals of the History of Computing, vol. 29.
no. 2, 2007, pp. 70-73.
10. F. Faggin, M. Shima, and S. Mazor, Single Chip
CPU, US Patent # 4,010,499, Intel Corp., 1977.
11. T. Jackson, Inside Intel, Dutton Publishing, 1997.
12. S. Mazor, Fairchild Symbol Computer, IEEE
Annals of the History of Computing, vol. 30,
no. 1, 2008, pp. 92-95.
13. M. Wilkes, The Genesis of Microprogram-
ming, IEEE Annals of the History of Computing,
vol. 8, no. 2, 1986, pp. 115-126.
14. S. Mazor and S. Wharton, Compact Code:
iAPX 432 Addressing Techniques, Computer
Design, May 1982, pp. 249-253.
15. 8085 User Manual, Intel, 1977.
16. S. Morse et al., Intel Microprocessors 8008 to
8086, Computer, Oct 1980, pp. 42-60.
17. F.G. Heath, Large Scale Integration in Electron-
ics, Scientific American, Feb. 1970, p. 22.
18. G.E. Moore, Cramming More Components
onto Integrated Circuits, Electronics, vol. 38,
no. 8, 19, 1965, pp. 114-117.
19. The Technical Impact of Moores Law, IEEE
SSCS Newsletter, vol. 20, no. 3, 2006.
20. G. Blynsky, Little Chips Invade the Memory Mar-
ket, Fortune Magazine, Apr. 1971, pp.100-104.
21. L. Berlin, The Man Behind the Microchip, Oxford
Press, 2005.
22. B.O. Evans, System/360: A Retrospective
View, IEEE Annals of the History of Computing,
vol. 8, no 2, 1986, pp. 155-179.
Readers may contact Stanley Mazor at stanmazor@
sbcglobal.net.
Contact department editor David Walden at annals-
anecdotes@computer.org.
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