Professional Documents
Culture Documents
1 a
1/0 fault activation
1 b
f
0 fault propagation
0 c
FA => a=1, b=1, c=1 => G1= D', G3=0; FP => through G5 or G6.
Decision: through G5 => G2=1 => d=0, a=0. => inconsistency => backtracking!!
Decision: through G6 => G4=1 => e=0. => done!!
The resulting test is 111x0.
D-frontier: The set of all gates whose output value is currently x but have one or more
fault signals on their inputs. Ex: Initially, the D-frontier of this example is
{G5, G6}.
Combinational & Sequential Test Generation.10
Ex: Decisions When Line Justification
a k
b q q=1
c l l=1 k=1
d
m F r=1
n r s o=1
m=1
o n=1
S
e p
f The corresponding decision tree
h
FA => h=D'; FP => e=1, f=1 (=> o=0); FP => q=1, r=1.
To justify q=1 => l=1 or k=1.
Decision: l=1 => c=1, d=1 => m=0, n=0 => r=0. => inconsistency => backtracking!!
Decision: k=1 => a=1, b=1.
To justify r=1 => m=0 or n=0 (=> c=1 or d=1). => done!!
J-frontier: The set of all gates whose output value is known but is not implied by its
input values. Ex: Initially, the J-frontier of the example is {q=1, r=1}.
Before After
0 x 0 0
x x
1 x 1 1
1 1
1 0 J-frontier={ ...,a } 1 0
x 0 a J-frontier={ ... }
a
D' x D-frontier={ ...,a } D' 0
D a D a D-frontier={ ... }
Before After
x 1 1 1
x 1
x 0 0 0
1 1
x 0 x
x x 0
a J-frontier={ ... } a J-frontier={ ...,a }
1 1
x 1
x 1
A D 1
A D
1 0
B F B F
E E
C C
(2) F=1 implies B=1. (3) F=0 implies B=0 when A=1.
(Static learning) (Dynamic learning)
(2), (3) are based on contraposition law: (A=>B) <=> (!B => !A).
h
d'
1
d
i
j
e'
n
e
0 a g k
1 b
c
1 D
f' l
f
m
{k,m,n}
n k Two times of backtracking!!
F {m,n}
n m
F S
{i,k,m}
i
{k,m,n} No backtracking!!
n
S
The main difference between the D-algorithm and 9-V algorithm is:
Whenever there are k possible paths for fault propagation , the D-
algorithm may eventually try all the 2k -1 combinations of paths.
However, since the 9-V algorithm tries only one path at a time without
precluding simultaneous fault propagation on the other k-1 paths, it will
enumerate at most k ways of fault propagation.
Combinational & Sequential Test Generation.21
PODEM (Path-Oriented Decision Making)
D x F 0A C D 1 F
xA C
=>
xB x x xB 1 x
E x E x
The first time of backtracing
D 1 F 0A C D 1 F
0A C
=>
xB 1 x 1B 1 1
E x E 0
h
d'
0 1
1d
i
D'
j
e'
0 n
e 1 1
0 a g 0 k
1 b
c 1
1 D x-path (to PO) check fail
f' l
=> backtracking!!
f
m
Objective
CY1=0.25
1A G1 1/0
B G5
CY1=0.656 G7
C G2
G4 G6
G3 0
1A 1 CY1=0.25 1/0
G1 G5
1B
CY1=0.656 G7
C G2
G4 G6
0
G3 0
1A 1 CY1=0.25 1/0=D
G1 G5
1B
0 CY1=0.656 G7 D
0C G2
G4 G6
0
0 0
G3
No backtracking!!
1A G1 1/0
B G5
G7
C G2
G4 G6
G3
0
1A 1 1/0
G1 G5
1B
G7
C G2
G4 G6
0
G3
0
1A 1 1/0=D
G1 A
1B G5 0 1
0 G7 D F B
0C G2 0 1
G4 G6 F C
0 0 0
G3 S
0
g 0->D'
0 a
x b
c h m
l p
d
e i
f
j
n
k
No backtracking !!
Combinational & Sequential Test Generation.34
ECAT Circuit: D-Algorithm
START
Conflict!!
Combinational
Logic
y1 Y1
y2 Y2
FF
FF
PI PO PI PO PI PO
Y1
y2 Y2
FF2
y1
FF1
I
1
O
y1 Y1
y2 0 Y2
D* D* D*
Time-frame 0
I I
1
1 D*
O O
D*
D* Time-frame D* D*
0 0 Time-frame 1
I I
I
1
0 1 D*
O O
O
D* D* D*
Time-frame -1 0 0 D* Time-frame 0 Time-frame 1
FF
a 1/0
a ..... 0/1
0/x
0/1 0/1
b 0/0
b 1/x 1/x
0/x 1/x
0/x
Conflict
a D
a ..... D* 1 0 D*
b 0 1
0 1
b 1 D* 0
0
0
Start
Starting
No
Phase 1 vectors given
Yes Generate
initialization
Generate fault list vectors
Fault simulate with given or
initialization vectors
Adequate
Yes Stop
coverage
Phase 2
No
Generate vectors to
cover undetected faults
in concurrent mode
Adequate
Yes Stop
coverage
No
Phase 3 Generate vectors to cover
undetected faults using
dynamic C/O cost functions
Stop
Simulation-Based Approaches
Advantages:
Timing is considered.
Asynchronous circuits can be handled.
Can be easily implemented by modifying a fault simulator.
Disadvantages:
Can not identify undetectable faults.
Hard-to-activate faults may not be detected.
1 x
! Timing can not be considered by time-frame expansion.
- Generated tests may cause races and hazards.
- Asynchronous circuits can not be handled.
Initialization is avoided.
Assumption is valid for pure controllers
that usually have a reset mechanism
(reset PI, resetable flip-flops, ...).
[1] G. R. Putzolu and T. P. Roth, "A Heuristic Algorithm for the Testing of
Asynchronous Circuits", IEEE Trans. Computers, pp. 639-647, June 1971.
[2] P. Muth, "A Nine-Valued Circuit Model for Test Generation", IEEE Trans.
Computers, pp. 630-636, June 1976.
[3] V. D. Agrawal, K. T. Cheng, and P. Agrawal, "A Directed Search Method for Test
Generation Using a Concurrent Simulator", IEEE Trans. CAD, pp. 131-138, Feb.
1989.
[4] K. T. Cheng and V. D. Agrawal, "Unified Methods for VLSI Simulation and Test
Generation", Chapter 7, Kluwer Academic Publishers, 1989.
[5] H-K. T. Ma, et al, "Test Generation for Sequential Circuits", IEEE Trans. CAD, pp.
1081-1093, Oct. 1988.