VLSI Design for Test/Power

Spring 2017
Project 4: Chip Testing

Lab Final Reports due on 11:59pm, 4/30/2017

1. For your project from Introduction to VLSI Design, develop the test vectors
you will be using to test the chip. At the time you were asked to design a
system into which data is shifted into the circuit through shift registers (scan
chain) and results are shifted out. You can use strings of alternating zeros and
ones to test the shift registers themselves in the scan chain. It remains to test
the combinational logic portion of the chip ensuring a high degree of fault
coverage. Use the following approach to generate test vectors for this purpose.

Define a combinational logic blob to be a collection of combinational logic

gates in your chip such that the blob is fed by either primary input pins or by
the outputs of registers and the blob feeds either primary outputs or scan
registers. Your circuit can be divided into a number of combinational logic
blobs which can be tested provided the test data for each blob can be loaded
into its input registers and its output registers are observable at the primary
outputs. Identify all the combinational logic blobs in your circuit. Code each
of these blobs (i.e., net-lists) in a form suitable to be input to the test compiler
(Synopsys) test generation system. Generate test vectors for each blob
ensuring maximum fault coverage.

Then, write a comprehensive test procedure for the chip using the test vectors
you have generated and any additional vectors that may be necessary to test
the non-scannable sequential logic in the chip. Give the estimated fault
coverage for the entire chip using your test procedure.

If it is very difficult to generate net-lists by Test Compiler, you are allowed to

use functional testing. By functional testing, you test functions, instead of
structural defects such as single stuck-at faults. For example, if your circuit is
a multiplier, you must test multiplication of numbers with different signs.
Further, you have to test important corner conditions for functional testing.
For example, for functional testing of a multiplier, you have to test multiplied
by 0 (or by 1), test overflow......

2. Test the IC chip assigned to you using the test patterns generated discussed
above, using the test stations (logic analyzer) in the lab.

Your lab kit will contain a bread-board and most of the connectors and
grabbers necessary. However, it is important that you take a look at the kit to
make sure that you have everything you need to mount the chip on a stable
fixture and connect it to the the tester. Do this as soon as possible. Pay specific
attention to power and clocking needs. Contact the Teaching Assistant if
necessary. Here is the TA contact information: Sangeetha Shenoi by e-mail:
Sangeetha Chandra (shenoisa) <shenoisa@mail.uc.edu>

You must test all the chips (3) given to you. TA Sangeetha will announce a
schedule to demonstrate how to use the logic analyzer and schedules (24 hrs)
for you to really test your chips using the logic analyzer.

The following paragraph is ONLY for your reference. This is to show you
how to write a detailed report. To save your time, it is waved this year.

Your detailed lab report must contain the testing methodology (strategy) you
have adopted, the test-vector generation strategy, number of type of faults
covered (if ATPG is used), expected and actual responses from the chip,
maximal clock speed, and the eventual diagnosis. Try to be as complete as
possible in testing full functionality and in isolating the fault locations if any.
The detailed lab report must also include screen shots for test response
waveforms and pictures of your circuit set-up and wire connection (taken
using your cell phone). If you take your VLSI design report (from Intro to
VLSI Design Course), you must submit an electronic version of the final
report in that course. Note that grading is NOT based on whether your chips
are working, instead, it depends on how complete your test is. You also have to
submit a short test report that will be discussed below. Please zip all three
files together and submit the zip file to Blackboard.

After you finish your chip testing, make an appoinement with the TA to give a
demo. Please save your test patterns to a storage (i.e., flash disk) to avoid
wasting time. Note that you should give demo before you pass the test kit to
the next group. There are time slots that you can choose from to give TA
Sangeetha a demon: 4:30-5:00pm (the day you receive the kits) or 10:00-
10:30am (the day you return the kits). The first time slot is preferred. Please
use e-mail to communicate this message to her.
 3. You must send a Short Test Report (eventually to MOSIS) that has the
subject line: TEST REPORT FOR <name of your chip> and exactly the
following content:

4. REQUEST : REPORT
5. ID : <ID of your chip>
6. P-PASSWORD :
7. FAB-ID : <FAB ID of your chip>
8. P-NAME : <Name of your chip>
9. REPORT :
10.
11. <Description of the chip's function and its design.>
12.
13. <Overall testing procedure described briefly.>
14.
15. <Use of test generartion system and any other software for test generation>
16.
17. <Testing of sequential logic parts>
18.
19. <Testing of combinational logic parts>
20.
21. <Any other testing done>
22.
23 <The maximum frequecy that the chip can work, e.g., 50MHz>
24.
25. <Test equipment used and how it was used>
26.
27. <Result of testing, coverage achieved, whether passed/failed, and
other comments>

Again, the short test report must be submitted to Blackboard. Without the file
submitted, no grade for this lab will be assigned.
Following is a sample test report:
REQUEST : REPORT
ID : 38255
P-PASSWORD :
FAB-ID : N2CJCD01
P-NAME : AJHEEB
REPORT :

AJHEEB is a permutation network chip that produces a permutation of the

given input based on the Control Word applied to it. It consists of mainly two
logic parts; a sequential part and a combinational part....

Testing of the chip is conducted in three phases; testing the sequential part,
testing the cimbinational part, and testing the integrated chip as a whole.

Test vectors are obtained manually for the sequential part, while the Test
Compiler tool by Synopsys are used to generate test vectors for the
combinational part. The same test vectors are used to test the whole chip
beside other test vectors generated manually.

The sequential logic part testing is performed as follows :

1. This logic part actually is a series of D-ffs connected in a shift register

fashion.
2. Apply a constant input pattern to the input pins (assuming that the
combinational part is fault-free).
3. Use the serial input to shift a '1-0' sequence through the shift register.
4. At each clock, observe the output if it matches the expected output.

The control word here has a "walking" '1-0' through the shift register, and if
there is a flip-flop that is faulty, then the output will not change from the
previous one, then we can determine the faulty flip flop.

Applying the previous procedure gave no errors in the shift register.

The number of test vectors used to achieve that is 56 test vectors.

The combinational logic part testing is performed as follows :

1. Load the control word in the shift register.

2. Apply the input test vector to the input pins.
3. Observe and compare the output with the expected one.
4. Repeat the above procedure for all the test vectors.
 The test vectors used in this part were generated using Test Compiler of
Synopsys. The number of vectors that used is 24 vectors, and these vectors
give 100 % fault coverage. Applying the previous procedure gave no faults in
the circuit.

Testing the whole chip is performed as follows :

A. 1. Load a random control word in the shift register.

2. Apply input test vector that has only one bit '1' to the input pins.
3. Observe and compare the output with the expected one.
4. Repeat (1-3) for different locations of the '1'.
5. Repeat (1-4) for different control words.
6. Repeat (1-5) for input vectors that have two '1's.
7. Repeat (1-5) for input vectors that have three '1's.
8. Repeat the steps used to test the combinational logic part.

B. 1. Load specific control word that to bring the circuit in the test mode
2. Apply input vector at the input pins.
3. Observe the output if it shows the expected internal points.
4. Repeat (1-3) several times for different input vectors.

Applying the previous procedure ensured that the chip is fault-free. And the
second part of the test showed that the MUX circuits, that used to multiplex
some of the output pins with some internal points, function correctly. About 60
test vectors were used.

All of the chips have been tested using HP 16500A Logic Analysis
Systems......

We have tested five chips of AJHEEB and both have been shown to function
correctly.

HP logic Analyzer Demons by TA Sangeetha

Time: TBA
Place: Rhodes 804