1000w Inverter PURE SINE WAVE Schematic Diagram

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PWM Amplifiers * Under development
40
PRODUCT
SELECTOR SA03
SA13
Output Current (Amps)

30
MATRICES
PWM AMPLIFIERS, SA04
POWER AMPLIFIERS SA01 SA14
20
Product See Page
SA01 50
SA60* SA06
SA09* SA02 SA16
SA02 58 10
SA03 68
SA04 76 SA07 SA50
0 SA51
SA06 80
0 100 200 300 400 500
SA07 88
Total Supply Voltage (Volts)
SA13 98
SA13, SA14, SA16 = Half bridge
SA14 106
SA16 110
SA50 118
SA51 124 High Voltage Amplifiers * Under development
PA01/73 130 250
PA45/PA46 1.5 Amps
PA02 136 5 Amps PB50 PB58
2 Amps PA85/PA15*
PA03 144 200 PA90*
Output Current (mA)
PA04 148
PA05 158 PA08 PA08V
150
PA07 162
PA08 168 PA41/PA42/PA44 PA88 PA89
PA09 174 100
PA83
PA10 180
PA12 185 50
PA81 PA84
PA19 191 PA82
PA21/25/26 195
0
PA41/42 209 0 100 200 300 400 500 1200
PA44 219 Total Supply Voltage (Volts)
PA45 225
PA46 231
PA51 237
High Current Amplifiers * Under development
35
PA61 243
PA05 PA03
PA81/82J 249 30
PA83 253
PA84 259
25
PA85 265 PA04
20 PA13*
PA88 271
PA12A
PA89 277 15
PB50 281 PA51 PA61/PA12
10 PA93 (400V)*
PB58 287 PA10
PA02 PA01 PA73 PA07 PA45/PA46
5 PA92 (400V)*
For the complete PWM Amplifier, PA21/25 PA26 PA19 PB50
0 PA09 PB58 (300V)
High Current Amplifier, High Voltage 0 50 100 150 200
Amplifier and High Speed selector Total Supply Voltage (Volts)
guides, please refer to pages 43 - 45.
APEX MICROTECHNOLOGY CORPORATION 5980 NORTH SHANNON ROAD TUCSON, ARIZONA 85741 USA APPLICATIONS HOTLINE: 1 (800) 546-2739
3
Discrete Off-The-Shelf
Design Power Amplifier
HIGH Research Components for Prototype
Purchase Components A
Build Prototype
Project Costs
Debug Prototype
Test Prototype in Circuit
Place Production Buy Request Apex Data Book
Elapsed Time: As long as 1 year Talk with Apex Applications Engineers
Select Apex Part
Sample Apex Part
Test Apex Part in Circuit
Place Production Buy
LOW
Elapsed Time: As little as 2 weeks
LOW HIGH
Productivity
DISCRETE OR OFF-THE-SHELF? FREE APPLICATIONS ENGINEERING

Designing a power amplifier or dc/dc converter into a circuit ENHANCES PRODUCT RELIABILITY
can be approached one of two ways: discretely or off-the-shelf. The Apex reputation for high quality, high reliability products
The former requires using a myriad of components, combined is due in large part to the positive results Apex Applications
with multiple hours of design time, procurement and production. Engineers generate for Apex customers. By working closely
The latter involves an Apex manufactured hybrid or monolithic with customers from the very start of their circuit design, Apex
component that the user selects based on their circuit require- Applications Engineers can guarantee a reliable outcome when
ments. the project reaches production.
Apex Microtechnology is in the business of designing and Starting with product selection assistance, Apex Applications
manufacturing power amplifiers and dc/dc converters to help Engineers work closely with customers through circuit design,
engineers work smarter and faster. Apex offers more than 75 schematic review and prototype evaluation. Apex Applications
models of power amplifiers and hybrid dc/dc converters for use Engineers also visit customers on site to assist with critical
in thousands of commercial, industrial and military applications issues such as circuit debugging.
worldwide.
The benefits of using an off-the-shelf power amplifier or dc/dc LIFETIME WARRANTY ON HERMETIC PRODUCTS
converter solution from Apex can be summarized as follows:
All hermetically packaged products manufactured by APEX
* Higher Reliability MICROTECHNOLOGY are warranted to be free of manufactur-
able defects when operated within the
* Reduced Size and Weight
published specified operating condi-
Requirements
tions for the life of the equipment in
* Reduced Design Time which the APEX component is origi-
* Reduced Procurement nally installed and purchased from
Time and Costs APEX or an authorized distributor. The
warranty applies only to the original
customer, or the first system buyer of
the original equipment from an APEX
customer. For non-hermetic packages,
the warranty period is for one year
from the date of invoice/shipment.
Leading edge design

tools foster Apexs
product development
APEX MICROTECHNOLOGY CORPORATION TELEPHONE (520) 690-8600 FAX (520) 888-3329 ORDERS (520) 690-8601 EMAIL prodlit@apexmicrotech.com
4
TYPICAL APPLICATIONS
Power amplifiers are typically used in applications involving
drivers, positioning or deflection. Apex products can be found in
robotics, optical disk drives, heating and cooling controls, ATE,
piezo drives and scanning tunneling microscopes. The creative
possibilities for new applications are infinite.
The circuit schematics below are for several typical power
amplifier applications.
R 20R 20R
20R
V IN
3 7 +175 +175
EA +VS 2.2K 2.2K
+VIN IN OUT
1 10pF
A A1 10pF A2
7.5V 6
5 EA OUT PA41 R CL R CL PA41 Rn
REF PWM Tach
180 180
100 Cn
2
+IN B 100
9 PIEZO
SHDN/ OUT 330pF 330pF
SA01 FILTER I SENSE GND
10 8 4 175 175
MOTOR
RFILTER
RLIMIT
CFILTER
+15V
+150V
OBJECT RCL
TOOL VIN OP
AMP
POSITION PB58
CC
FEEDBACK
+VS
RBAL 15V 150V
+ RG
RD IO = 2A
+5V +S
SHUT DOWN S PA03 CF
0/10V CF'
DAC VS
R1 MOTOR YOKE
DESIRED
POSITION C1
RF
R2
VOUT RS
100V/s
+VS
(12V or RF
10K 28V)
2K 10K +VS
10K
+VS
(12V or 1/2 PA26 10K
28V) R IN
1
5V A B PIEZO DRIVE
Reference R CL
1/2 PA26 1 PA87 V OUT
1
VIN .1F .1F
COMPUTER
10K 2K 10K FOCUS
COMMAND
VOLTAGE
Rd SOLENOID PIEZO
V S
Cf
5
APEX CAN WORK IN YOUR APPLICATION
Time to use some creativity of your own. The chart that able to provide you with free product selection assistance,
follows will help guide your thought patterns regarding the circuit design and schematic review. Call toll free 1-800-546-
possibilities of using an Apex power amplifier in your applica- APEX (1-800-546-2739).
tion. Remember, Apex Applications Engineers are also avail-
Typical Power Amplifier Applications A

Industry End Product Circuit Type Power Amplifier
Selection
Industrial Controls Engraving Machine Spindle Elevation Control High Power/PWM
and Machinery (linear motor)
Process Control System Proportional Valve Driver High Power/PWM
Emergency Alarms Audio High Power
Robotics Position Control(motor drive) High Power/PWM
Wire Pull Tester Precision Torque(motor drive) High Power/PWM
Ink Jet Printers Electrostatic Deflection High Voltage
Computers and Optical Scanning System Galvanometer Drive High Power/PWM

Office Equipment Infrared Scanning System Speed Control Motor High Power/PWM
Disk Drive Head Positioning (linear motor) High Power
Communications Telecom Test Equipment Ring Generator High Voltage

Equipment Phone Line Driver High Voltage
Line Fault Detection High Voltage
Broadcast Radio Transmitter Tuning Control(motor drive) High Power
Aerospace Guidance Systems Gyro Motor Control High Power/PWM

Ring Laser Gyro High Voltage
Heads-Up Displays Magnetic Deflection High Power
Engine Controls Proportional Valve High Power/PWM
Noise Vibration Cancellation Actuator Drive High Power
High Voltage
Fin Actuator and Control Surfaces Motor Drive High Power/PWM
Weapon Systems Transmitters, Seekers Motor Drive High Power/PWM

Fin Actuator and Control Surfaces Motor Drive High Power/PWM
Gun Mount Control Motor Drive High Power/PWM
Test and Automatic Test Equipment (ATE) Pin Driver High Power
Measurement Programmable Power Supplies High Voltage
Equipment Waveform Generator Output Amplifier High Power/
High Voltage/
High Speed
Materials Testing Torque Motor High Power/PWM
Shake Table High Power/PWM
Actuator High Power/PWM
Optical Interferometer Piezo Drive High Voltage

Moving, Segmented Mirrors Piezo Drive High Voltage
Scanning Tunneling Microscope Piezo Drive High Voltage
Surface Analysis Piezo Drive High Voltage
Atomic Force Microscope Piezo Drive High Voltage
Laser, Beam Deflection Galvanometer Drive High Power
Medical Surgical, Medical Instruments Pumps High Power/PWM

Electro Surgery High Voltage Driver High Voltage
Hearing Test Equipment Audio Amplifier High Power
6
LIFE SUPPORT POLICY
As a general policy, Apex Microtechnology Corp. does not recommend the end use of any of its standard, commercial or military
products in life support applications where the failure or malfunction of the Apex product can be reasonably expected to cause failure
of the life support device or significantly affect the devices safety or effectiveness. Apex will only sell its products for use in such
applications under written agreement.
Examples of life support devices are neonatal oxygen analyzers, nerve stimulators (for any use), autotransfusion devices, blood
pumps, defibrillators, arrhythmia detectors and alarms, pacemakers, hemodialysis systems, peritoneal dialysis systems, ventila-
tors of all types, and infusion pumps, as well as other devices designated as critical by the FDA. The above are representative
examples only and are not intended to be conclusive or exclusive of any other life-supporting devices.
Apex has made every effort to insure the accuracy of this handbook to factory specifications as of March 1, 1998; however, no
responsibility is assumed for possible omission or inaccuracies.
Apex Microtechnology Corp. reserves the right to make changes without further notice to any specifications or products herein to
improve reliability, function or design. Changes and additions made after the publication of this handbook will be reflected in updated
product data sheets or other literature as soon as possible. If more detailed information on any product is desired, contact Apex
directly or any Apex authorized representative.
Apex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it
convey any license under its patent rights, nor the rights of others.
The following is a trademark of APEX MICROTECHNOLOGY CORP.
TM
M I C R O T E C H N O L O G Y
Certain Apex products are manufactured under the following U.S. patents:
4833423, 07108745, 4871965, 5519357, 5142243.
Copyright 1998 by Apex Microtechnology Corporation. All rights reserved. Printed in U.S.A.
7
A
To Our Valued Customer,
In 1991, we began a change in our

culture. Today, our team members
are more involved in their jobs and
are actively making improvements
that result in better quality prod-
ucts and outstanding customer
service. We share our financial
progress with our team members
and through the use of Open Book
Management, our team members
are helping us to be more success-
ful. As a team, we have created a
vision for Apex, To provide world
leadership in innovation, product
quality, and customer service.
To help us achieve our vision, we

solicit your input. Your feedback has been and will continue to be
appreciated. Please call me on my direct line or send me an e-mail.
I look forward to hearing from you.
Lisa Putt
President
(520) 690-8619
e-mail: lputt@apexmicrotech.com
8
NOTES:
9
Tab Index
A A
General
General Info,
Info, Tab
Tab Index,
Index, Table
Table of
of Contents,
Contents, Quality/Screening
Quality/Screening
B B
DC/DC
DC/DC Converters
Converters
C C
PWM
PWM Amplifiers,
Amplifiers Power Operational Amplifiers
D D
Application
Application Notes
Notes
E E
Packages,
Packages, Accessories,
Accessories, Product
Product Marking
Marking
F F
Customer
Customer Service,
Service, Corporate
Corporate Directory,
Directory, Sales
Sales Representatives,
Representatives,
Subject
Subject Index,
Index, Customer
Customer Support
Support Request
Request Card
Card
10
Contents
A SECTION A General Info, Tab Index, Table of Contents, Quality
Simplify Your Circuit Design .......................................................................................................................... 3

Life Support, Liability, Trademarks, Patents ................................................................................................. 7
A Message To Our Customers ...................................................................................................................... 8
Tab Index ...................................................................................................................................................... 10
Table of Contents ........................................................................................................................................ 11
A Quality Message To Our Customers ....................................................................................................... 15
Grade Comparison: Industrial and Military Product .................................................................................... 16
SMD Grade Availability ............................................................................................................................... 17
M and /883 Screening Program ................................................................................................................ 18
Parameter Definitions and Test Methods .................................................................................................... 22
Reactance Chart ......................................................................................................................................... 24
B SECTION B DC/DC Converters
DC/DC Features ....................................................................................................................................... 27

DC/DC Converter Competitive Comparisons ........................................................................................... 28
DB2800S Series ....................................................................................................................................... 30
DHC2800S Series .................................................................................................................................. 36
C SECTION C General Operating Considerations, PWM Amplifiers,

Power Operational Amplifiers, Power Boosters
Product Selector Guides .......................................................................................................................... 43
Second Sources ....................................................................................................................................... 46
Frequency/Saturation Tables ................................................................................................................... 48
PWM AMPLIFIERS
SA01 ......................................................................................................................................................... 50
EK01, Evaluation Kit for SA01 Pin-out ................................................................................................... 54
SA02 .................................................................................................... NEW ......................................... 58
EK02, Evaluation Kit for SA02 Pin-out ................................................ NEW ......................................... 64
SA03 .................................................................................................... NEW ......................................... 68
EK03, Evaluation Kit for SA03/SA04 Pin-out ...................................... NEW ......................................... 72
SA04 .................................................................................................... NEW ......................................... 76
SA06 .................................................................................................... NEW ......................................... 80
SA07 .................................................................................................... NEW ......................................... 88
SA13 .................................................................................................... NEW ......................................... 98
EK10, Evaluation Kit for SA13/SA14 Pin-out ...................................... NEW ......................................... 102
SA14 .................................................................................................... NEW ......................................... 106
SA16 .................................................................................................... NEW ......................................... 110
SA50 ....................................................................................................................................................... 118
EK-SA50, Evaluation Kit for SA50 Pin-out ............................................................................................. 122
SA50M .................................................................................................................................................... 123
SA51 ....................................................................................................................................................... 124
SA51M .................................................................................................................................................... 128
EK-SA51, Evaluation Kit for SA51 Pin-out ............................................................................................. 129
11
POWER OPERATIONAL AMPLIFIERS
PA01, PA73 ............................................................................................................................................ 130 A
PA73M .................................................................................................................................................... 134
PA02, PA02A ......................................................................................................................................... 136
PA02M .................................................................................................................................................... 140
PA02 Design Ideas .............................................................................................................................. 141
PA03, PA03A ....................................................................................................................................... 144
PA04, PA04A ....................................................................................................................................... 148
EK04, Evaluation Kit for PA04 and PA05 Pin-out ................................................................................ 152
PA05, PA05A ....................................................................................................................................... 158
PA07, PA07A ....................................................................................................................................... 162
PA07M .................................................................................................................................................. 166
PA08, PA08A ....................................................................................................................................... 168
PA08M .................................................................................................................................................. 172
PA08V .................................................................................................................................................. 173
PA09, PA09A ....................................................................................................................................... 174
PA09M .................................................................................................................................................. 178
PA10, PA10A ....................................................................................................................................... 180
PA10M .................................................................................................................................................. 184
PA12, PA12A ....................................................................................................................................... 185
PA12M .................................................................................................................................................. 189
PA12H .................................................................................................................................................. 190
PA19, PA19A ....................................................................................................................................... 191
PA21/PA25/PA26 ................................................................................................................................. 195
PA21M .................................................................................................................................................. 200
PA21/PA25/PA26 Design Ideas ........................................................................................................... 201
EK26, Evaluation Kit for PA26 Pin-out ................................................................................................. 202
EK21, Evaluation Kit for PA21 Pin-out ................................................................................................. 204
PA25DIE ............................................................................................................................................... 207
PA41/PA41A/PA42/PA42A .................................................................................................................. 209
PA41M .................................................................................................................................................. 213
PA41DIE ............................................................................................................................................... 214
PA41/42 Design Ideas ......................................................................................................................... 215
EK42, Evaluation Kit for SIP10 (PA42, PA87) Pin-out ......................................................................... 217
PA44 .................................................................................................... NEW ....................................... 219
EK13, Evaluation Kit for PA44 Pin-out ................................................ NEW ....................................... 223
PA45 ..................................................................................................................................................... 225
PA45DIE ............................................................................................................................................... 229
PA46 .................................................................................................... NEW ....................................... 231
EK12, Evaluation Kit for PA46 Pin-out ................................................ NEW ....................................... 235
PA51, PA51A ....................................................................................................................................... 237
PA51M .................................................................................................................................................. 241
PA61, PA61A ....................................................................................................................................... 243
PA61M .................................................................................................................................................. 247
PA81J/82J ............................................................................................................................................ 249
PA83, PA83A ....................................................................................................................................... 253
PA83M .................................................................................................................................................. 257
PA84, PA84A, PA84S .......................................................................................................................... 259
PA84M .................................................................................................................................................. 263
PA85, PA85A ....................................................................................................................................... 265
PA85M .................................................................................................................................................. 269
PA88, PA88A ....................................................................................................................................... 271
PA88M .................................................................................................................................................. 275
PA89, PA89A ....................................................................................................................................... 277
POWER BOOSTERS
PB50 ..................................................................................................................................................... 281
EK50, Power Booster Evaluation Kit .................................................................................................... 285
PB58, PB58A ....................................................................................................................................... 287
12
Contents
NOTE: For a complete listing of all /883 products and Standardized Military Drawing numbers (SMD), see page 18.
D SECTION D Application Notes
Applications Engineer Message .................................................................................................................... 292

Application Notes Cross-Reference .............................................................................................................. 293
Application Note 1, General Operating Considerations ................................................................................ 294
Application Note 2, Optoelectronic Position Control ................................................................................... 303
Application Note 3, Bridge Circuit Drives .................................................................................................... 305
Application Note 5, Precision Magnetic Deflection ..................................................................................... 308
Application Note 6, Applying the Super Power PA03 ................................................................................. 312
Application Note 7, Programmable Power Supplies ................................................................................... 317
Application Note 8, Optimizing Output Power ............................................................................................. 319
Application Note 9, Foldover Current Limiting ............................................................................................. 323
Application Note 10, Power Amp Output Impedance .................................................................................. 326
Application Note 11, Thermal Techniques .................................................................................................. 327
Application Note 13, Voltage to Current Conversion .................................................................................. 329
Application Note 14, Power Booster Applications ....................................................................................... 332
Application Note 16, SOA Advantages of MOSFETs ................................................................................. 334
Application Note 17, Wideband, Low Distortion Techniques ...................................................................... 336
Application Note 19, Stability for Power Amplifiers ..................................................................................... 339
Application Note 20, Bridge Mode Operation of Power Amplifiers .............................................................. 359
Application Note 21, Single Supply Operation of Power Amplifiers ............................................................ 363
Application Note 22, SOA and Load Lines .................................................................................................. 368
Application Note 24, Brush Type DC Motor Drive ....................................................................................... 372
Application Note 25, Driving Capacitive Loads ........................................................................................... 374
Application Note 26, Parallel Connection .................................................................................................. 393
Application Note 28, Proper Analog Wiring of Power Amplifiers ............................................................... 396
Application Note 30, PWM Basics ............................................................................................................. 398
Application Note 31, Basic Op Amp Theory and Practice ......................................................................... 403
Application Note 32, Low Pass Filtering .................................................. NEW ....................................... 405
E SECTION E Packages and Accessories, Product Marking
Packages Outline Dimensions ...................................................................................................................... 411

Accessories ................................................................................................................................................. 419
Product Marking .......................................................................................................................................... 435
Subject Index, Customer Support Request Card

F SECTION F Customer Service, Corporate Directory, Sales Representatives
Ordering Information, Product Warranty, Terms & Conditions ....................................................................... 442

Corporate Telephone Directory, Hours of Operation ..................................................................................... 444
Sales Representatives ................................................................................................................................... 445
Street Map Guide to Apex .............................................................................................................................. 446
Subject Index ................................................................................................................................................. 447
13
A
QUALITY
A Quality Message To Our Customers ................................................................ 15

Grade Comparison: Industrial and Military Product ............................................. 16
SMD Grade Availability ........................................................................................ 17
M and /883 Screening Program ......................................................................... 18
Parameter Definitions and Test Methods ............................................................. 22
Reactance Chart .................................................................................................. 24
14
SIGMA PLUS
TOTAL QUALITY MANAGEMENT
Seven Years of Sigma Plus; Quality Through
Knowledge and Understanding...
Dear Valued Customer:
Seven years of Sigma Plus have lead to consistent increases in quality and
performance for Apex and our customers. Sigma Plus, our Total Quality
Management program, continues to produce measurable quality improve-
ments, a culture based on teamwork, and increased value for our customers.
In alignment with Sigma Plus, we have instituted training and development in

the fundamentals of our business, further supporting Apex teams with the
tools they need to perform at high productivity and quality levels. With a firm
foundation of Sigma Plus quality tools that solve the how of continuous
improvement, team members are now learning the why with Open Book
Management. As a result, Apex teams are gaining greater understanding of
their personal impact on organizational systems and how they can directly improve organizational perfor-
mance. By giving team members a stake in the outcome, they gain personal satisfaction and ownership of the
products and services they provide to you, our customers.
We will continue to improve our systems and processes to exceed our customers expectations. Feedback
systems that identify internal and external customers needs and expectations keep us focused on customer
value. Teams have increased their job skills and have become functionally cross-trained to quickly adapt to
changes that anticipate customer needs. Our quality goal is to be #1 with our customers.
Automation and quality integration are two methods we are using to streamline manufacturing processes while
building quality directly into our products. Implementing automated processing in manufacturing will lead to
increased capacity to meet customer demand to ensure timely product delivery. Integrating quality processes
into manufacturing systems has enabled team members to make just-in-time improvements. Our automation
and quality initiatives are designed to provide greater product quality and value to our customers.
Our entire Apex Team is committed to Sigma Plus. This commitment provides the momentum necessary to
continually improve the quality of products and services we provide for our customers. If you have any
questions on our Quality Systems, please feel free to call or e-mail me.
John Jarvise
Quality Team Leader
jjarvise@apexmicrotech.com
15
INDUSTRIAL AND MILITARY PRODUCT
GRADE COMPARISON
M I C R O T E C H N O L O G Y HTTP://WWW.APEXMICROTECH.COM (800) 546-APEX (800) 546-2739
A
Apex offers two different levels of quality screening: INDUSTRIAL AND MILITARY GRADE. Both
grades are produced on the same production line and assembled in the same Class 100,000 clean
room. This approach ensures a high quality level for our INDUSTRIAL products, as well as our
MILITARY products.
Our INDUSTRIAL products are 100% static and dynamic tested, performed at +25C. Our
MILITARY products are 100% tested over their respective full temperature range for both static and
dynamic parameters.
INDUSTRIAL MILITARY
OPERATION GRADE GRADE/883 and
NON-COMPLIANT
Clean room processing ............................................ YES .......................................... YES

Clean room testing ................................................... YES .......................................... YES
Solder Integrity tested .............................................. YES .......................................... YES
Wire bond integrity tested ........................................ YES .......................................... YES
All processing under
document control YES YES
High power die inspection ......................................... NO ........................................... YES
Processed on military line ........................................ YES .......................................... YES
Certified operators ..................................................... NO ........................................... YES
Maximum Number Of
Rework Cycles Specified:
Solder .................................................................. YES .......................................... YES
Epoxy ................................................................... NO ........................................... YES
Wirebond .............................................................. NO ........................................... YES
Pre-cap visual ...................................................... SAMPLE ..................................... 100%
Pre-seal vacuum bake ............................................. 1 hr. .......................................... 2 hrs.
Welded in controlled ATM. ....................................... YES .......................................... YES
Each unit checked for hermeticity ............................. NO ........................................... YES
Temp. cycle:
65C to +150C @ 10 cycles NO YES
Constant acceleration 10000G Y1 ............................ NO ........................................... YES
Burn-in: 160 hrs. @ TC = 125C ................................ NO ........................................... YES
Dynamic testing ...................................................... +25C .......................... 55C, +25C, +125C
External visual ........................................................... NO ........................................... YES
Pin finish ............................................................. Ni or solder .................................... Solder
16
MARCH 1, 1998
SMD GRADE AVAILABILITY

M STOCKED
BASE MODEL INDUSTRIAL NON-COMPLIANT MILITARY /883 SMD # 2
DHC2803 .......................... S .......................................... S .................................. N1 ................................................ N

DHC2805 .......................... S .......................................... S .................................. N1 ................................................ N
DB2803 ............................. S .......................................... S .................................. N1 ................................................ N
DB2805 ............................. S .......................................... S .................................. N1 ........................... N
DB2812 ............................. S .......................................... S .................................. N1 ........................... N
DB2815 ............................. S .......................................... S .................................. N1 ........................... N
PA01 ................................. S .......................................... N .................................. N ............................ N
PA02 ................................. S .......................................... N .................................. C .............. 5962-9067901HXA
PA03 ................................. S .......................................... N .................................. N ............................ N
PA04 ................................. S .......................................... N .................................. N ............................ N
PA05 ................................. S .......................................... N .................................. N ............................ N
PA07 ................................. S .......................................... N .................................. C .............. 5962-9063801HXA
PA08 ................................. S .......................................... N .................................. C .............. 5962-9072301HXA
PA09 ................................. S .......................................... N .................................. C .............. 5962-9170001HXA
PA10 ................................. S .......................................... N .................................. C .............. 5962-9082801HXA
PA12 ................................. S .......................................... N .................................. C .............. 5962-9065901HXA
PA19 ................................. S .......................................... N .................................. N ............................ N
PA21 ................................. S .......................................... S ................................... C .............. 5962-9215201HXA
PA25 ................................. S .......................................... N .................................. N ............................ N
PA41 ................................. S .......................................... S ................................... N ............................ N
PA51 ................................. S .......................................... N .................................. C ............... 5962-8762002YA
PA61 ................................. S .......................................... N .................................. S ............................ N
PA73 ................................. S .......................................... N .................................. S ............................ N
PA81 ................................. S .......................................... N .................................. N ............................ N
PA82 ................................. S .......................................... N .................................. N ............................ N
PA83 ................................. S .......................................... N .................................. C .............. 5962-9162101HXA
PA84 ................................. S .......................................... N .................................. C .............. 5962-9073601HXA
PA85 ................................. S .......................................... S ................................... N ............................ N
PA88 ................................. S .......................................... S ................................... N ............................ N
PA89 ................................. S .......................................... N .................................. N ............................ N
PB50 ................................. S .......................................... N .................................. N ............................ N
PB58 ................................. S .......................................... N .................................. N ............................ N
S = stocked
C = custom order basis, SMD part # is recommended
N = not available
1
Under development
2
The suffix on the Stocked SMD numbers listed below ends in an A indicating solder dipped pin.
NOTE: For a complete, up-to-date listing of all /883 products and Standardized Military Drawing (SMD) num-
bers, refer to the current Apex Pricing & Ordering data sheet.
17
M and /883 SCREENING PROGRAM
DESCRIPTION 1.4 PERFORMANCE SPECIFICATIONS A

These Apex Microtechnology power hybrids have been screened The performance specifications for a particular M or /883
to MIL-PRF-38534, Class H and manufactured in a DESC Certified hybrid circuit are contained in the following documents:
Facility using the baseline documents listed herein. They provide a 1. Industrial Grade Data Sheet (i.e. PA02/PA02A).
high reliability product option and satisfy the requirements for This contains Typical Characteristics and Performance Graphs.
components used in airborne and ground-based military applica- 2. M Data Sheet (i.e. PA02M).
tions. Compliance with these requirements is signified by the /883 This is the Table 4 Group A Inspection which defines the
suffix in the model number. Non-compliant version is identified parameters and limits that the product must meet when tested
using M only in the model number. over the full military case temperature range of -55C to +125C.
Complete description of an APEX M or /883 product In the event of conflicting requirements, the order of precedence
consists of the following: will be: purchase order, customers SCD, the APEX M data sheet,
1. Industrial Grade Data Sheet (i.e. PA02/PA02A). and other reference documents.
This contains Typical Characteristics and Performance Graphs.
2. M Data Sheet (i.e. PA02M). 2.0 GENERAL REQUIREMENTS
This is the Table 4 Group A Inspection which defines the The individual requirements are specified herein and in accor-
parameters and limits that the product must meet when tested dance with the applicable APEX M data sheet. The static and
over the full military case temperature range of 55C to +125C. dynamic electrical performance requirements for the hybrid circuit
3. APEX /883 Screening Program Data Sheet (i.e. this docu- and test conditions are as specified in the applicable APEX M data
ment). sheet.
This defines the manufacturing processes and screening steps
for an M or /883 product. (Refer to Figure 1 for order of flow.) 2.1 PROCESS CONDITIONING,
4. Package and Accessories Information Data Sheet TESTING, RELIABILITY, and QUALITY
This contains the package outline dimensions (i.e. 8-pin TO-3).
All applications data and performance optimization suggestions ASSURANCE SCREENING
given for the Industrial model apply to Military versions of a given Process conditioning, screening and testing are as specified in
product family as well. Package outlines are identical except that Section 4.0. Figure 1 illustrates the process flow for M or /883
Military grade pins are gold plated to meet the solderability require- products processed to MIL-PRF-38534, Class H.
ments of MIL-STD-883, Method 2003.
2.1.1 PRODUCT or PROCESS CHANGE
QML-38534 FACILITY APPROVAL STATUS APEX will not implement any major change, as listed in MIL-PRF-
APEX is a DESC certified and qualified QML-38534 facility. 38534, to the design, materials, construction, configuration, or
APEX received certification November 8, 1989 and a QML listing as manufacturing process which may affect the performance, quality,
of May 31, 1990. reliability, or interchangeability of the circuit without full or partial re-
qualification. M product is a HI-REL non-compliant product.
CONSTRUCTION
These power hybrids have been built and assembled using the 2.2 QUALITY CONFORMANCE
chip and wire process. A metallized ceramic (beryllia) substrate is The M or /883 hybrid circuits furnished under this specification
used with thick film resistors and gold conductors. Power transistors are products which have been produced and tested in conformance
are attached to silver conductors at the same time that the substrate with all the provisions of this specification.
is attached to the header, using high temperature solder and reflow
techniques. Small signal die are attached using MIL-STD-883 2.3 MARKING
method 5011 conductive epoxy. Chip capacitors are attached with 2.3.1 MARKING EACH DEVICE
conductive epoxy. Die to substrate and pin to substrate wire bonds
use 1, 5 or 10 mil diameter aluminum wire. The package is The following marking is placed on each hybrid circuit:
hermetically sealed using high-speed, one-shot resistance welding a) Index point (see 2.3.4)
in a dry nitrogen atmosphere. b) Part number (see 2.3.5)
c) CAGE code number (see 2.3.6)
1.0 APPLICABLE DOCUMENTS d) Lot identification code (see 2.3.7)
e) Manufacturers identification (see 2.3.8)
1.1 SPECIFICATIONS f) Country of origin (see 2.3.9)
MIL-M-55565 Microcircuits, Packaging of g) BeO warning (if applicable, see 2.3.10)
MIL-PRF-38534 General Specification for Hybrid Microcircuits h) ESD identifier
These units are Class 1 as defined in MIL-PRF-38534; therefore,
1.2 STANDARDS the ESD identifier is incorporated in the mark.
MIL-STD-883 Test Methods and Procedures for
Microelectronics 2.3.2 MARKING ON INITIAL CONTAINER
Marking on initial anti-static packaging for delivery includes:
1.3 BASELINE DOCUMENTS a) Manufacturers identification
APEX maintains on file the procedures, process specifications b) Customer name
and process qualification reports that are in general the documents c) Customers P.O. number
which have established the baseline for APEX in satisfying the d) Quantity packaged
requirements of certification in accordance with Appendix D of MIL- e) Lot code
PRF-38534. f) Customers SCD number
g) Date packaged
h) Packaging operators initials
18
2.3.3 MARKING PERMANENCE 3.7 HERMITICITY
Marking is permanent in nature to MIL-STD-883, Method 2015. Hermiticity tests are performed per the following:
2.3.4 INDEX POINT 3.7.1 FINE LEAK TESTING
The index point, denoting location of Pin 1, is indicated as shown Fine leak testing is performed to MIL-STD-883, Method 1014,
on the appropriate Package Outline. Condition A, at 1X10-6 cc/sec standard leak rate.
2.3.5 PART NUMBER 3.7.2 GROSS LEAK TESTING
The part number is the APEX generic part number and DESC Gross leak testing is performed to MIL-STD-883, Method 1014,
SMD part number, when applicable. Condition C, at 60 PSIG pre-pressurization.
2.3.6 CAGE CODE NUMBER 3.8 EXTERNAL VISUAL INSPECTION
The CAGE code number for APEX is 60024 as designated by the All M and /883 hybrid circuits receive external visual to MIL-
Federal government. STD-883, Method 2009.
2.3.7 LOT IDENTIFICATION CODE 4.0 QUALITY ASSURANCE PROVISION*
The lot identification code is a 9-digit alphanumeric code. The first
two letters indicate the assembly operator responsible for 4.1 QUALITY CONFORMANCE INSPECTION
manufacture of the lot. These initials are followed by a three digit lot Quality Conformance Inspection (QCI) is to MIL-PRF-38534,
code, a two digit year-of-seal code, and a two digit week-of-seal Option 1, in-line qualification method. Lots failing to meet quality
code. conformance inspection for a given product assurance level are
rejected.
2.3.8 MANUFACTURERS IDENTIFICATION
The manufacturers identification is signified by the name, logo, 4.1.1 GROUP A ELECTRICAL TESTING
or trademark of APEX MICROTECHNOLOGY incorporated in the Group A electrical testing is performed using in-line verification in
mark. accordance with Option 1 of MIL-PRF-38534. Electrical param-
eters and test limits are as shown in the M data sheet.
2.3.9 COUNTRY OF ORIGIN
The country of origin is signified by USA incorporated in the mark. 4.1.2 GROUP B INSPECTION
Group B inspection is satisfied by performing in-line inspection
2.3.10 BeO WARNING sampling, to MIL-PRF-38534, Option 1.
Since these hybrid circuits contain beryllium oxide substrates, the
BeO identifier is marked on the package as an alert to the user, that 4.1.3 GROUP C INSPECTION
if the package seal is broken, not to crush, machine, or subject the Group C inspection is performed on the first lot submitted for
substrate to temperatures in excess of 850C to avoid generating inspection and as required to evaluate or qualify changes in
toxic fumes. manufacturing processes per MIL-PRF-38534, Option 1.
3.0 CONDITIONS AND METHODS OF TEST 4.1.4 GROUP D INSPECTION
Conditions and methods of test are to MIL-PRF-38534 and as Group D testing in accordance with MIL-PRF-38534, Option 1, is
specified herein. This section establishes the stress screening tests accomplished during package evaluation at incoming inspection
and quality conformance inspection tests for this program. The and is not repeated.
purpose of these tests is to assure the quality and reliability of the
product to a particular process level commensurate with the products 5.0 DATA AND REPORTS*
intended application. All tests are performed on a 100% basis
except where indicated. 5.1 CERTIFICATE of COMPLIANCE
3.1 HIGH POWER DIE INSPECTION All /883 hybrid circuits are accompanied by a Certificate of
Compliance.
High power die inspection is performed to MIL-STD-750 Method
2072 and 2073, and MIL-STD-883 Method 2010. 5.2 QUALITY CONFORMANCE REPORTS
3.2 INTERNAL VISUAL INSPECTION (PRECAP) MIL-PRF-38534, Option 1, Group A lot data is kept on file with the
production records. In-line Groups B, C and D (reference 4.1.4)
Internal visual inspection is performed to MIL-STD-883, Method
generic data is also on file.
2017 and 2032.
3.3 TEMPERATURE CYCLING 5.3 TRACEABILITY
Traceability is in accordance with MIL-PRF-38534. Each hybrid
Temperature cycling is performed to MIL-STD-883, Method
circuit is traceable to the production lot. Re-worked or repaired
1010, Condition C, using 10 cycles from 65C to +150C.
circuits maintain traceability.
3.4 BURN-IN 6.0 PACKAGING
Burn-in is performed to MIL-STD-883, Method 1015, Condition D
Packing and packaging are to MIL-M-55565.
for 160 hours at a case temperature of 125C.
3.5 CONSTANT ACCELERATION 7.0 CUSTOM MARKING
Production quantities of M and /883 devices may be dual or
Constant acceleration is performed to MIL-STD-883, Method
solely marked with an applicable SCD number.
2001, Condition B, at 10,000 Gs, in the Y1 axis only.
3.6 FINAL ELECTRICAL TEST
Final electrical tests are performed to MIL-PRF-38534*. Both
static and dynamic parameters from Group A, Subgroups 1-6, are
100% tested to the M data sheet limits at 55C, 25C and +125C.
The PDA (Percent Defective Allowable) shall be 10% maximum and
shall only apply to static (DC) measurements at 25C.
* Applies to compliant (/883) product only.
19
FIGURE 1: APEX COMPLIANT /883 & NON-COMPLIANT M GRADE PRODUCT SCREENING FLOW
Header and cap: Package evaluation to MIL-PRF-38534*

Raw Substrate: Inspected in accordance with APEX specification QUAL 52, visual based
on MIL-STD-883, Method 2032
Small signal die: Component evaluation to MIL-PRF-38534* A
Large signal die: Component evaluation to MIL-PRF-38534*
Chip components: Component evaluation to MIL-PRF-38534*
(diodes, capacitors, etc.)
Wire: Inspected in accordance with APEX specification WIRE01
Epoxy: Inspected to MIL-STD-883, Method 5011
Thick film paste: Inspected in accordance with APEX specification PASTEI
Solder: Inspected in accordance with APEX specification PASTEI
Substrate fabrication
High power die inspection
to MIL-STD-883,
Method 2010, MIL-STD-750, 100% substrate manufacturing inspection per
Method 2072 and 2073 APEX specification PROC290; based on
MIL-STD-883, Method 2032
Sample nondestruct wire-pull

Substrate and power die attach
in reflow furnace
OPTIONAL FUNCTIONAL TEST

25C static and dynamic parameters tested per
APEX industrial data sheet with
widened min/max limits
Small signal die attach using
conductive epoxy;
oven-cured at 155C
OPTIONAL LASER TRIM
and 100% inspection to
MIL-STD-883, Method 2032
Sample destruct wire-pull
PRECAP TEST
25C static and dynamic parameters tested per
APEX industrial data sheet
Ultrasonic aluminum wire bond
(10, 5 & 1 MIL Wire)
and assembly inspection
A
* Applies to compliant (/883) product only.

20
FIGURE 1: APEX COMPLIANT /883 & NON-COMPLIANT M GRADE PRODUCT SCREENING FLOW
FINAL ELECTRICAL TEST

APEX M data sheet;
both static and dynamic parameters at
Tc = 55C, +25C and +125C
A PDA = 10% for static DC
parameters @ 25C only
PRECAP VISUAL INSPECTION FINE LEAK TEST

100% manufacturing inspection to To MIL-STD-883,
MIL-STD-883, Method 2017and 2032 Method 1014, Cond. A
1X10-6 cc/sec standard leak rate
QI SAMPLE PRECAP INSPECTION GROSS LEAK TEST

To MIL-STD-883, Method 2017 and 2032 To MIL-STD-883,
and APEX specification QUAL 50 Method 1014, Cond. C
60 PSIG pre-pressurization
VACUUM BAKEOUT MARKING

2 hour bake at 150C To MIL-PRF-38534
PACKAGE SEAL EXTERNAL VISUAL

One shot resistance welding in a 100% manufacturing inspection to
dry nitrogen atmosphere MIL-STD-883, Method 2009
Moisture content will not exceed 5,000PPM
QI FINAL GATE
MIL-STD-883 Method 2009
TEMPERATURE CYCLING and APEX specification PROC99
To MIL-STD-883,
Method 1010, Cond. C M PRODUCT
65C to +150C for 10 cycles ?
/883 PRODUCT
LOT QUALIFICATION
BURN-IN TEST Quality conformance inspection (QCI)
To MIL-STD-883, is done to MIL-PRF-38534, Option 1,
Method 1015, Cond. D in-line inspection method and is performed
160 hours at 125C case temperature throughout the lot processing
APEX
CONSTANT ACCELERATION
MILITARY GRADE DEVICES; /883
To MIL-STD-883,
Method 2001, Cond. B
5,000 Gs in the Y1 axis only
PACKAGING FOR SHIPMENT
Packing and packaging for shipment are
done per MIL-M-55565
APEX MICROTECHNOLOGY
This data CORPORATION
sheet has been carefully checked to
and is believed 5980 NORTH
be reliable, SHANNON
however, ROAD isTUCSON,
no responsibility assumed forARIZONA 85741 or omissions.
possible inaccuracies USA APPLICATIONS HOTLINE:
All specifications are 1 (800)
subject to change 546-2739
without notice.
/883U REV. F FEBRUARY 1998 1998 Apex Microtechnology Corp.
21
PARAMETER DEFINITIONS & TEST METHODS

ABSOLUTE MAXIMUM RATINGS COMMON MODE REJECTION: CMR

A
Absolute maximum ratings are stress levels which may be applied Common mode rejection is the ability of the amplifier to reject two
to the amplifier one at a time. The amplifier will not suffer permanent equal input signals as they vary from the midpoint of the two supply
damage. However, proper operation is not implied. Simultaneous voltages (ground in the case of dual symmetric supplies).
application of two or more of these maximum stress levels may induce
permanent damage to the amplifier. INPUT BIAS CURRENT: IB
IB is the net current flowing into or out of the amplifier input pins at
DIFFERENTIAL INPUT VOLTAGE a zero signal condition. This current results from base currents of
Differential input voltage is the voltage difference between the two bipolar input transistors (sometimes reduced by cancellation net-
input pins. It will be near zero in any linear (nonsaturated) operating works) or gate leakage of FET input transistors. Measurement tech-
mode. Non-zero voltages arise with very fast rising input waveform, niques require insertion of very large impedances in series with the
shorted outputs, overdriven inputs, and other abnormal conditions. inputs and converting the resulting output voltage change to a bias
current in accordance with Ohms Law.
RTI (REFERRED TO THE INPUT)
All input errors will be seen at the output of the amplifier at an 100R
amplitude equal to the input error term times the noninverting gain of
the circuit. Errors are seen from the noninverting input pin, i.e., voltage RIN
R
offset will appear at a gain of two at the output in an inverting gain of
one circuit.
EO
LOOP GAIN RIN+
Loop gain is the difference between open loop gain and the gain of
the external circuit. This excess gain over the required signal amplifi-
cation is the key feature of all operational amplifiers that provide a
IB = [ EO /101] /RIN
proportional increase in accuracy.
TYPICAL SUPPLY VOLTAGE FIGURE 2. INPUT BIAS CURRENT

Typical supply voltage is a value which APEX has determined to be
the optimum voltage to specify. This value is influenced by both INPUT OFFSET CURRENT: IOS
customer input and competitor specifications. IOS is the difference between the two bias currents. The offset
current rating is generally smaller than the bias current rating which
COMMON MODE IMPEDANCE: ZIN implies that matching impedances for the two amplifier inputs will result
ZIN is the effective impedance from either input to common (ground). in smaller error than either bias current alone would produce.
Because most op amps do not have ground pins, the specification is
often referred to the midpoint of the two power pin voltages as in the INPUT OFFSET VOLTAGE: VOS
case of single supplies. Measuring the effect of a known source VOS is the voltage required at the input of an amplifier to produce zero
impedance driving a buffer configuration will yield common mode input output. Most often, this parameter is measured in the opposite man-
impedance. Low frequency inputs are used to characterize resistive ner, namely, the output voltage resulting from a zero input. With a given
elements and higher frequencies enable measuring capacitive ele- gain configuration, the output voltage is divided by the noninverting
ments of the input impedance. This value is generally very high and gain of the circuit to determine the voltage at the input (referred to the
can be neglected; therefore, it is usually part of the design character- input or RTI).
ization data rather than a 100% tested parameter.
100R
COMMON MODE VOLTAGE: CMV
CMV is the average (common component) of two input voltages with +VS
respect to the midpoint of the two power supply voltages (ground in the R
case of dual symmetric supplies). Because most op amps do not have
ground pins, the parameter is often specified as a minimum voltage EO
difference between the CMV and either supply rail. When operating
on a single supply, the CMV specifications of most APEX amplifiers do
not allow input pin voltages to reach zero or the supply voltage. In any VS VOS = EO /101
nonsaturated operating mode, both input voltages will be essentially
equal.
FIGURE 3. INPUT OFFSET VOLTAGE
100R
INPUT VOLTAGE NOISE: VN
+40 [+10] VN is the noise component of voltage offset. The noise is measured
R at the output with a true RMS meter and referred to the input. Low pass
and bandpass filters may be used to limit meter response. At any given
EO 3dB bandwidth, the RMS value is divided by the square root of that
bandwidth to obtain the spectral noise density.
SUPPLY INPUT CURRENT NOISE: IN
10 [40] MIDPOINT = +15 [15]
CMV = 15V IN is the noise component of bias current. It is an RTI specification
CMR = 30V / [EO /101] similar to current offset. The use of the filters and the calculation of
FIGURE 1. SUPPLY MIDPOINT, COMMON MODE VOLTAGE, spectral noise density is similar to the procedures used for voltage
COMMON MODE REJECTION noise.
22
POWER SUPPLY REJECTION: PSR
VERT
PSR is the ability of the amplifier to reject the effect of changes in
R R
total supply voltage on voltage offset. Dual supplies are varied simul-
taneously to test this parameter. Supply values will include the
100R
minimum and maximum operating specifications. Changing from dual
15V supplies to dual 20V supplies is a 10V change of total supply +VS
voltage. A resulting 1mV offset change would indicate a PSR of 100V/ R TRIG
V or 80dB. When PSR is plotted versus frequency, one supply at a time
has the AC waveform impressed upon it.
VIN
OUTPUT VOLTAGE SWING: VO TIME
VO is the minimum voltage swing capability of the amplifier and is VS
usually specified at multiple current ratings. The amplifier is driven in
excess of the specified output and then checked for minimum output TRIG
with the appropriate load.
FIGURE 6. SETTLING TIME
100R
+VS
R
OPEN LOOP GAIN: AOL
AOL is the actual gain from the inverting input pin to output, with the
noninverting input grounded. If plotted versus frequency, it is called a
VOUT
bode plot.
VIN RL
VS 100R
FIGURE 4. OUTPUT VOLTAGE SWING +VS

R
CURRENT LIMIT: ICL VOUT

With the amplifier overdriven, a small resistor is used to detect the
point of current limiting. Resistance values and power supply voltages
are selected to insure that a nonlimiting amplifier will be detected VS
without excessive internal power dissipation. VIN
AOL = VOUT / VIN
100R AOL [dB] = 20 Log [VOUT /VIN]
+VS FIGURE 7. OPEN LOOP GAIN
R
VOUT
OPEN LOOP PHASE RESPONSE
Open loop phase response is the actual phase from the noninverting
VIN input pin to output. While ideally between 0 and 90, it may be higher.
RL
It is usually plotted versus frequency. Measurement techniques are
VS similar to those used for open loop gain.
ICL = VOUT /RL PHASE MARGIN

FIGURE 5. CURRENT LIMIT
Phase margin is 180 less the open loop phase at frequency where
the open loop gain of the amplifier is unity.
SLEW RATE: SR
SR is the maximum rate of change of the output voltage. An inverting QUIESCENT CURRENT: IQ
gain circuit is usually used with an input signal at least 10 times faster Quiescent current is the current drawn from each supply rail with
than the amplifier rating. Measurement points are between 10 and zero output voltage and load current. Insignificant differences between
90% of total output swing. Overdriving the amplifier is permissible the two supply rail currents may exist due to input bias currents.
though at times may result in overload recovery problems.
FULL POWER RESPONSE

Full power response is the highest frequency at which the amplifier
can drive a sine wave without visible distortion (3-5%) on an oscillo-
scope. Supply voltage is set to the typical rating. Power response
curves relate the reduced output as a function of frequency but
independent of gain.
GAIN BANDWIDTH PRODUCT

Gain Bandwidth Product is the product of gain times frequency at a
specified frequency. This is always measured at or below the unity gain
frequency of the amplifier.
SETTLING TIME
Settling time is the time required for the amplifier to settle within a
specified error of final value. Slewing time is included. This parameter
is usually measured using the inverting gain of one circuit, a false
summing junction, and a very fast rising input waveform triggering an
oscilloscope.
23
REACTANCE CHART
24
NOTES:
25
DC/DC
CONVERTERS
B
Apex DC/DC Converter Features .......................................................................... 27

DC/DC Converter Competitive Comparisons ......................................................... 28
DB2800S Series .................................................................................................... 30
DHC2800S Series ................................................................................................ 36
26
HIGH RELIABILITY DC/DC CONVERTERS
FEATURES
HIGH RELIABILITY BUILT IN. 1

APEXS LIFETIME WARRANTY 2
We know our customers really put our converters to the test. Thats 1 3
why Apexs DHC2800 and DB2800 Series DC/DC Converters utilize 3
all ceramic capacitors and surface mount magnetics to provide hybrid
reliability across the full military temperature range and to 5000 g of
acceleration. The built-in ruggedness of Apex DC/DC Converters
allows Apex to offer the only lifetime product warranty in the industry.
4
All Apex DC/DC Converter products are sold in single unit quantities
to assist your circuit design evaluation. Our Evaluation Orders pro-
1
gram even allows you to purchase up to three DC/DC Converter units
and should they not meet your design needs, and they have not been 3 B
damaged or soldered, you can return them to Apex within 30 days of
the invoice date to receive a full credit.
2
1 Surface Mount Magnetics 5

2 100% Ceramic Capacitors
3 Reflow Soldered Components DHC2800 Series
4 Welded Package
Hermetically Sealed
5 Low Thermal Resistance,
Ceramic On Solid Steel 1
1 2
1
2 3
3 5
3
PRODUCT DESIGN HIGHLIGHTS

Commercial grade parts designed for military ruggedness
Withstands 5000g acceleration DB2800 Series
100% ceramic capacitors offer higher reliability
DHC Series: Input meets MIL-STD-704A/D requirements (80V transient play through)
DB Series: Input meets MIL-STD-704D requirements (80V transient survival)
55C to +125C full power operation
Fault Tolerant
Full short circuit protection
Fully isolated
Output voltage adjustment standard
Remote shutdown provides on/off capabilities
27
DC/DC CONVERTERS ELECTRICAL/MECHANICAL
COMPETITIVE COMPARISONS
Advanced
Interpoint Analog
FEATURE
DHC2800 MSA2800 ASA2800

Series Series Series
No Temperature Derating
Between 55C and 125C STD STD Extra
B
100% Temperature Tested
STD Extra Extra
DURABILITY
55C to 125C
Rugged Military Design

Internal components mounted to withstand military STD Extra Extra
applications up to 5000 G of acceleration
Welded Case STD STD STD

No flux left inside package from soldered lid
All Ceramic Capacitors STD N/A STD

Provide stable and reliable performance over both
time and temperature
Wave Solderable STD N/A STD

Converter can be easily wave soldered
Wide Continuous Input Voltage Range STD N/A N/A

1150 volt operation at full output current
UTILITY
Output Voltage Adjust Standard +/10% N/A N/A

Allows custom output voltage
3V Output Availability STD N/A N/A
Power Output Capabilities Up to 6W Up to 5W Up to 5W
28
DC/DC CONVERTERS ELECTRICAL/MECHANICAL
COMPETITIVE COMPARISONS
Advanced
M I C R O T E C H N O L O G Y Interpoint Analog
FEATURE DB2800 MHE2800 AHE2800
Series Series Series
COTS
No Temperature Derating
STD N/A Extra
Between 55C and 125C
100% Temperature Tested

55C to 125C
STD Extra Extra
DURABILITY
Rugged Military Design

STD N/A Extra
Internal components mounted to withstand military appli-
cations up to 5000 G of acceleration
Welded Case STD N/A STD

No flux left inside package from soldered lid
All Ceramic Capacitors

Provide stable and reliable performance over both time STD N/A STD
and temperature
Wave Solderable
STD N/A STD
Converter can be easily wave soldered
Wide Continuous Input Voltage Range STD N/A N/A

1640 volt operation at full output current
Remote Sense
UTILITY
STD N/A N/A

Reduces DC output voltage errors
Synchronizable
Allows multiple converters to run at the same switching STD N/A Extra
frequencies
Output Voltage Adjust Standard

Allows custom output voltage +/10% +6%/0% +5%/0%
3V Output Availability STD N/A N/A
29
DB2800S 20W SERIES DC/DC CONVERTERS
DB2803S DB2805S DB2812S DB2815S

HI-REL DESIGN
SURFACE MOUNT MAGNETICS DB280
5S
WELDED HERMETIC PACKAGE

LOW INTERNAL TEMPERATURE GRADIENTS USA
TE9493 BeO
11
ALL CERAMIC CAPACITORS
WITHSTANDS 5000G
OTHER FEATURESSINGLE OUTPUT

NO DERATING 55 C to +125 C
OUTPUT VOLTAGE ADJUSTMENT STANDARD
REMOTE SHUTDOWN
DESCRIPTION
The DB2800S series of DC/DC converters provides the EXTERNAL CONNECTIONS
ruggedness, reliability and features required to meet the
advanced design challenges of todays hi-rel market. This has
been accomplished using a new package pioneered by Apex
having very low thermal gradients, excellent hermeticity and + INPUT INPUT
high voltage isolation. The use of advanced substrate and 1 12
reflow soldering techniques during construction results in a SHUTDOWN + TIMING 2
2 11
rugged, cost-effective pin solderable package. CLOCK 3 10 TIMING 1
The DB2800S hybrid converter series utilizes all ceramic TOP
ADJUST/COMP* 4 VIEW 9
capacitors and surface mount magnetics to provide reliable CASE
5 8
operation at all operating temperatures while surviving very
OUTPUT 7 SENSE
high G forces. 6
DB2800S series standard features include kelvin sense, + OUTPUT + SENSE
indefinite short circuit protection, remote shutdown, output
fault monitoring, turn on voltage point adjustment, switching
* Optional N/C on DB2800S /F
frequency synchronization of up to 3 units using no external
components and pi-network input filtering. An output voltage
adjustment/load compensation pin is also standard, however BLOCK DIAGRAM
a DB2800S series converter may be ordered without this
feature (/F option)
Fault tolerant design protects these converters from most 1 6
external circuit faults. The output and output adjust pins will
withstand +35V while the shutdown and all synchronization
pins will withstand +50V protecting the converters from a
12 5
variety of system or board faults, i.e. solder bridges, etc.
Unique load fault protection circuitry allows this converter to
pull up loads having difficult static load line characteristics and
allows short term load excursions significantly beyond ratings
in most applications.
The DB2800 series is a current mode push-pull topology 7
PWM ERROR AMPLIFIER
converter which operates at a switching frequency of 500kHZ. CURRENT MODE REFERENCE AND 4
Internal filtering of both input and output eliminates the need for CONTROLLER ISOLATION
8
external capacitors in many applications. 2
The 12-pin MO-127 High Profile Power Dip package (see 3
Package Outlines) allows connection to a heatsink and is 10
hermetically sealed and isolated from the internal circuits.
11
Please see the package outlines dimension section for dimen-
sions and recommended mounting torque. The use of com-
pressible isolation washers may void the warranty.
30
ABSOLUTE MAXIMUM RATINGS
DB2800S SERIES SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS INPUT VOLTAGE RANGE (Pin 12 to 1, 2, 3, 10 or 11) 0 - 50 Vdc

INPUT TRANSIENT (Pin 12 to 1) 80 V @ 50 ms
OUTPUT WITHSTAND (Pin 5 and 8 to 7, 6 or 4) 35 Vdc
OUTPUT CURRENT (Continuous) 5.5 Adc DB2803S
4 Adc DB2805S
1.9 Adc DB2812S
1.5 Adc DB2815S
TEMPERATURE, Storage 65oC, 150oC
TEMPERATURE, Pin Soldering 10s 300oC
SPECIFICATIONS DB2803S B
PARAMETER TEST CONDITIONS1 MIN TYP MAX UNITS
STEADY STATE CHARACTERISTICS
INPUT VOLTAGE RANGE 16 28 40 Vdc

OUTPUT VOLTAGE VIN; min max Vdc @ IMIN 3.2 3.3 3.4 Vdc
OUTPUT CURRENT VIN; min max Vdc 500 5500 mAdc
EFFICIENCY 66 %
OUTPUT RIPPLE VOLTAGE Bandwidth 10 kHz 1MHz 20 50 mVrms
INPUT RIPPLE CURRENT Bandwidth 10 kHz 1MHz 20 50 mArms
OUTPUT POWER2 1.6 18.0 W
LINE REGULATION3 VIN; min max3 2 20 mVdc
LOAD REGULATION3 IOUT; min max3 1 15 mVdc
TEMPERATURE COEFFICIENT .01 %/C

TEMPERATURE RANGE, case2 55 125 C
QUIESCENT CURRENT IOUT = 0 A 35 40 mAdc
INHIBITED VPIN5 ; < 8 Vdc .09 1.25 2.5 mAdc
ISOLATION CHARACTERISTICS
(INPUT/OUTPUT/CASE)
LEAKAGE RESISTANCE (VTEST = 500Vdc) 100 M

LEAKAGE CAPACITANCE (f = 10kHz) 50 pF
DYNAMIC CHARACTERISTICS
LINE STEP RESPONSE VIN; TR, TF = 10s

VOLTAGE CHANGE VIN; 16 40 Vdc 300 mV
RECOVERY TIME (95%) 30 s
WITH 100F OUTPUT CAP
VOLTAGE CHANGE VIN; 16 40 Vdc 100 mV
LOAD STEP RESPONSE IOUT; TR, TF = 10s
VOLTAGE CHANGE IOUT; 50% max Adc 1400 mV
WITH 100F OUTPUT CAP
VOLTAGE CHANGE IOUT; 50% max Adc 300 mV
START-UP OVERSHOOT VIN ; 0 40 Vdc 0 mV
SHUTDOWN DELAY VPIN5 ; > 10 Vdc < 8 Vdc 220 500 s
SHUTDOWN RECOVERY4 VPIN5 ; < 8 Vdc > 10 Vdc 30 60 mS
NOTES: 1. Unless otherwise stated: TC = 25, VIN = 28V, IOUT = IMAX AMPS
2. Derate power linearly to zero from 125C to 135C.
3. Regulation measured between pin 8 and pin 7.
4. Recovery spec assumes that converter has been OFF for at least 500ms.
CAUTION
CAUTION: The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush, machine, or
subject to temperatures in excess of 850C to avoid generating toxic fumes.
31
SPECIFICATIONS DB2800S SERIES
DB2805S DB2812S DB2815S

MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
16 28 40 16 28 40 16 28 40 Vdc
5.00 5.05 5.1 12.00 12.05 12.1 15.0 15.1 15.2 Vdc
400 4000 190 1900 150 1500 mAdc
70 72 73 %
20 50 25 50 25 50 mVrms
20 30 20 30 20 30 mArms
2 20 2.3 23 2.2 22 W
5 50 5 50 10 50 mVdc
2 25 5 50 20 50 mVdc
.01 .01 .01 %/C

55 125 55 125 55 125 C
35 40 35 40 35 40 mAdc
.09 1.25 2.5 .09 1.25 2.5 .9 1.25 2.5 mAdc
100 100 100 M

50 80 85 pF
400 300 300 mV

30 40 40 s
200 150 150 mV

250 250 250 s
1400 800 800 mV

40 60 60 s
500 280 280 mV

150 400 400 s
0 0 0 mV
220 500 220 500 220 500 s
30 60 30 60 30 60 ms
PACKAGE THERMAL SPECIFICATIONS MIN TYP MAX UNITS
RESISTANCE, case to air 12 C/W

TEMPERATURE RISE, junction to case 10 15 C
32
TYPICAL PERFORMANCE
DB2803S GRAPHS
EFFICIENCY CONTOURS EFFICIENCY CONTOURS EFFICIENCY CONTOURS

40 40 40
40% 30% 40% TEMP = 125C
50% 40% 50%
TEMP = 25C
INPUT VOLTAGE, VIN (V)

56% 50% 60%
35 35 TEMP = 35 64%
60% 54%
64% 58% 55C 66%
66% 60%
30 30 62%
30
67% 67%
64%
68% 65%
25 25 66% 25 68%
69% 69%
20
70%
20 20 B
66% 67% 70% 64%
16 16 16
.55 1.1 2.2 3.3 4.4 5.5 .55 1.1 2.2 3.3 4.4 5.5 .55 1.1 2.2 3.3 4.4 5.5
OUTPUT CURRENT, IOUT (A) OUTPUT CURRENT, IOUT (A) OUTPUT CURRENT, IOUT (A)
LOW LINE DROP OUT LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE 100F
20
OUTPUT RESPONSE, X (UNITS/DIV)

CURRENT RATING
OUTPUT DC
TEMP = 25C
18 VOUT VOUT
1V
1V
16
14 5.5A 5.5A
12 2.75A 2.75A
2A
2A
IOUT IOUT
NO OUTPUT BUS CAPCITANCE INCLUDES 100F ON OUTPUT BUS

10
0.0 2.0 4.0 6.0
OUTPUT CURRENT, IOUT (A) TIME, t (100sec/DIV) TIME, t (200sec/DIV)
LOAD TRANSIENT RESPONSE 1000F LINE TRANSIENT RESPONSE

LOAD = 5.5A
100mV
VOUT VOUT
1V
40V
5.5A
16V
10V
2.75A VIN
2A
IOUT
INCLUDES 1000F ON OUTPUT BUS INCLUDES 100F ON OUTPUT BUS
TIME, t (500sec/DIV) TIME, t (200sec/DIV)
TURN ON THRESHOLD TURN ON RESPONSE AUDIO REJECTION

28 0
VIN = 28VDC
TURN ON VOLTAGE, ETO (V)
AUDIO REJECTION, AV (dB)
IOUT = 5.5 Amps

RESPONSE, X (UNITS/DIV)
3.3V
20
24
VOUT
LOAD = 5.5A 40
2V
20
0V 28V 60
16
VIN 80
10 V
INCLUDES 100F ON
0V OUTPUT BUS
12 100
10K 20K 30K 40K 60K 90K 100 200 400 1K 2K 10K 20K 100K
SET POINT RESISTOR, RSP () TIME, t (5msec/DIV) FREQUENCY, f (Hz)
33
TYPICAL PERFORMANCE
GRAPHS DB2805S

40 40 40
30% 40% 30%
40% 50% 50% TEMP =

50% 55% 125C
35 35 TEMP = 35 60%
60% TEMP = 25C 60%
55C 64%
63% 64%
67%
66% 66% 30 69%
30 30
68% 68% 70%
70% 69%
71% 70% 71%
25 25 25
72%
72%
20 20 71% 20
73%
73% 67%
16 15 16
.4 .8 1.6 2.4 3.2 4 .8 1.6 2.4 3.2 4 .4 .8 1.6 2.4 3.2 4
20

CURRENT RATING
OUTPUT DC
TEMP = 25C
VOUT VOUT
18
1V
1V
16
4A 4A
14
2A 2A
1A
1A
12 IOUT IOUT

10
0.0 1.0 2.0 3.0 4.0 5.0
LOAD TRANSIENT RESPONSE 1000F LINE TRANSIENT RESPONSE

LOAD 4A
100mV
VOUT VOUT
1V
4A 40V
2A
1A
16V
10V
IOUT VIN
TIME, t (500sec/DIV) TIME, t (200sec/DIV)

28 0
VIN = 28VDC
AUDIO REJECTION, AV (dB)
5.1V IOUT = 4 Amps

20
24
VOUT
LOAD 4A 40
0V
2V
20
28V 60
16
0V VIN 80
10 V
INCLUDES 100F ON OUTPUT BUS

12 100
10K 20K 30K 40K50K 70K 90K 100 200 400 1K 2K 10K 20K 100K
34
APPLICATION
INFORMATION DB2800S SERIES
OUTPUT ADJUST / COMP MULTIPLE CONVERTER SYNCHRONIZATION

The output voltage of the DB2800S may be adjusted from Synchronized operation of up to three DB2800S series
90% to 110% of nominal value by the use of a 50k potentiom- converters may be accomplished without external compo-
eter as shown. Adjustment beyond this range is possible nents. One unit selected to be the master is connected
however certain characteristics of the converter such as but normally with pin 10 grounded. The clock output pin 3 will
not limited to input voltage range, efficiency, ripple and tem- provide the sync signal for up to two slave units. The slave units
perature performance will change. Characterization by the have pin 10 not connected and receive the clock signal into pin
user is recommended in such applications. 11. The clock signal lines may be shielded to prevent radiation.
A separate 50 ohm coax to each slave unit is recommended in
order to preserve signal integrity. Shield ends should be
connected to pin 12 of the nearest converter. B
4 7 8 DB2800S converters may also be synchronized to an exter-
nal 500 khz (+/- 5%) frequency source driving pin 11 of the
50K converters. Pin 10 is not connected. The converters synchro-
nize to the positive edge of the frequency source allowing a
variety of wave forms (pulse, square, spike) to be used. Pin 11
is internally capacitively coupled allowing unipolar or bipolar
Adjust/comp (pin 4) may be driven by external circuitry frequency sources to be used. The source should have a
referenced to pin 8 (-output sense) if desired. Grounding pin 4 waveform rise time of 20 ns or less and be capable of driving
causes output voltage to increase (25% typically) while driving at least 4 volts peak into each 50 ohm pin 11 input (50 volts
pin 4 above 1.3 V causes output voltage to decrease. Pin 4 may peak max).
be driven through 10K or more if connection of the comp An externally synchronized unit may be used to synchronize
function is also required. other (slave) units. The slave units may be used in turn to
The comp function of pin 4 allows transient response and synchronize other slave units from their pin 3 outputs. Each
phase margin to be tailored to suit a specific application. This generation of slave units has a delay (100-200ns typical)
feature may be utilized by connecting a small (1-500 nf) from the unit that it is synchronizing to.
capacitor between pins 4 and 6 or 7. This is generally recom-
mended when very large low esr load capacitances are used. TYPICAL APPLICATION
SHUTDOWN PLUS
Pin 2 is used for remote shutdown, output fault detection, 4
1 6 +V
and/or setting the input voltage point at which the converter will
turn on as shown in the typical application diagram. No VIN 7
connection to pin 2 is necessary for normal operation of the CONTROL
10 DB2800S 50K
converter. Pin 2 is referenced to pin 12 (-input). VTRIM SYSTEM
Shutdown may be implemented by simply connecting pin 2 11
8
to an open collector logic output or switch rated at 2.5 mA, 25
12 5 V
Vdc or higher. 2
Input voltage turn on point is programmed with a single +5V
SET UV R SP
resistor from pin 2 to 12. An input turn on/off hysteresis LOCKOUT
(typically 3.5% of Vin) will be observed. This should be consid- 200K 5K
ered when making or verifying set point adjustment. The value OPERATION
NORMAL
of the setpoint resistor may be determined by the following: J174 (TTL)
SHUTDOWN
3 OPTO
R = 210 10 (10% accuracy at 25C)
ETO 9.5
The above diagram shows the remote sense feature which
Set point temperature coefficient is typically +400ppm/C. reduces Vo errors due to the resistance of the conductors
Output fault monitoring is accomplished by observing pin 2 feeding the load. This diagram also shows the connections for
with a high impedance monitoring circuit. Pin 2 voltage drops non-synchronized operation (TIMING 1 and 2) as well as
from over 10 V to below 1 V when a load fault causes the output voltage trim, remote shutdown, fault monitoring, and
converters fault protection circuitry to activate. It will remain input voltage turn on point adjustment.
low for at least 100 mS and return high. If the load fault is still
present pin 2 will return low and the cycle will repeat. If there
is no input setpoint programming resistor already in place a
resistor > 400 k from pin 2 to 12 will provide pin 2 pull down.
This data sheet has been carefully CORPORATION TELEPHONE
checked and is believed to be reliable,(520) 690-8600
however, FAXis(520)
no responsibility assumed888-3329
for possibleinaccuracies
ORDERS (520) 690-8601
or omissions. EMAILare
All specifications prodlit@apexmicrotech.com
subject to change without notice.
DB2800SU REV. J AUGUST 1998 1998 Apex Microtechnology Corp.
35
DHC2800S SERIES 5W/6W DC/DC CONVERTERS
DHC2803S DHC2805S
HI-REL DESIGN
WAVE SOLDERABLE PACKAGE
ALL CERAMIC CAPACITORS
SURFACE MOUNT MAGNETICS
WITHSTANDS 5000G
FEATURESSINGLE OUTPUT
NO DERATING 55 C to +125 C
WIDE SUPPLY RANGE 12V to 50V Package Dimensions
1" W x 1" L x .35" H
HIGH ISOLATION 500V
HIGH POWER DENSITY 17W/IN3
OUTPUT VOLTAGE ADJUSTMENT STANDARD TYPICAL APPLICATION WITH OPTIONS
REMOTE SHUTDOWN
OPERATES TO 11VIN AT 5W 10nF
8 3 1 +V
DESCRIPTION
50K
The DHC2800S series of DC/DC converters provides the DHC2800S 2 V
ruggedness, reliability, and features required to meet the VTRIM
Control
advanced design challenges of todays hi-rel market. This is 5 7 6 System
accomplished while retaining a power density of 17 W/in3 and RSP
425 mW/gram of power/package performance. The use of SET UV
LOCKOUT +5V
advanced substrate and reflow soldering techniques during 200K VIN
construction results in a rugged, cost-effective, and completely SHUTDOWN 5K
OPERATION
solderable package. OPTO NORMAL
J174 (TTL)
DHC2800S hybrid converter series utilizes all ceramic ca-
pacitors and surface mount magnetics to provide reliable
operation at all operating temperatures while surviving very
high G forces. BLOCK DIAGRAM
DHC2800S standard features include output fault monitor-
ing and/or turn on voltage point programming via the shutdown
6 1
pin. All three functions may be implemented simultaneously
with a minimum of external components. An output voltage
adjustment / load compensation pin is also standard however
DHC2800S may be ordered without this feature (/F option). 2
Fault tolerant design protects these converters from most PWM
5 FEED FORWARD
external circuit faults. The output and output adjust pins will CONTROLLER
withstand +35 V while the shutdown pin will withstand +50 V
protecting the converters from a variety of system or board
faults i.e. solder bridges etc. Unique load fault protection 7
ERROR AMPLIFIER
circuitry allows this converter to pull up loads having difficult REFERENCE AND
static load line characteristics and allows short term load ISOLATION
excursions significantly beyond ratings in most applications.
3
A resonant reset transformer isolated forward converter
topology operating at a switching frequency of 400 kHZ allows
operation over a wide input voltage range. Internal filtering of
EXTERNAL CONNECTIONS
both input and output eliminates the need for external capaci-
+ OUTPUT 1 8 CASE
tors in many applications.
The 8-pin DIP package (see Package Outlines) is hermeti- OUTPUT 2
cally sealed and isolated from the internal circuits. Heat sinking TOP
ADJUST/COMP* 3 VIEW 7 INPUT
is recommended for full power operation at elevated ambient
temperatures. NO CONNECTION 4
SHUTDOWN PLUS 5 6 + INPUT
* Optional N/C on DHC2800S/F
36
DHC2803S/DHC2805S SPECIFICATIONS
DHC2803S DHC2805S
ABSOLUTE MAXIMUM RATINGS INPUT VOLTAGE RANGE (Pin 7 to 6 or 5) 0 50Vdc 0-50Vdc
INPUT TRANSIENT (Pin 7 to 6) 80V @ 50ms 80V @ 50ms
OUTPUT WITHSTAND (Pin 2 to 1 or 3) 35Vdc 35Vdc
OUTPUT CURRENT (Continuous) 2Adc5 1.2Adc
TEMPERATURE, Storage 65C, 150C 65C, 150C
TEMPERATURE, Pin Soldering 10s 300C 300C
DHC2803S DHC2805S
SPECIFICATIONS
PARAMETER TEST CONDITIONS1 MIN TYP MAX MIN TYP MAX UNITS
STEADY STATE
CHARACTERISTICS
INPUT VOLTAGE RANGE 12 28 50 12 28 50 Vdc
OUTPUT VOLTAGE VIN; min max Vdc @ IMIN 3.2 3.3 3.4 5.00 5.05 5.1 Vdc
OUTPUT CURRENT VIN; min max Vdc 180 1520 120 1200 mAdc
VIN; 13 max Vdc 18205 mAdc
EFFICIENCY 61 66 64 69 %
OUTPUT RIPPLE VOLTAGE Bandwidth 10kHz 1MHz 38 80 30 80 mVrms
INPUT RIPPLE CURRENT Bandwidth 10kHz 1MHz 30 100 30 100 mArms
OUTPUT POWER2 .5 5.06 .6 6.0 W

LINE REGULATION VIN; min max3 6 15 6 15 mVdc
LOAD REGULATION IOUT; min max3 10 25 10 25 mVdc
TEMPERATURE COEFFICIENT .006 .006 %/C

TEMPERATURE RANGE, case2 55 125 55 125 C
QUIESCENT CURRENT IOUT = 0A 38 45 38 45 mAdc
INHIBITED Vpin5; < 8Vdc .09 1.25 2.5 .09 1.25 2.5 mAdc
ISOLATION CHARACTERISTICS
(input/output/case)
LEAKAGE RESISTANCE VTEST = 500Vdc 100 100 M
LEAKAGE CAPACITANCE f = 10kHz 55 60 pF
LINE STEP RESPONSE VIN; TR, TF = 10s
VOLTAGE CHANGE VIN; 16 40 Vdc 350 300 mV
RECOVERY TIME (95%) 30 30 s
LOAD STEP RESPONSE IOUT; TR, TF = 10s

VOLTAGE CHANGE IOUT; 50% max Adc 700 700 mV
RECOVERY TIME (95%) 30 40 s
START-UP OVERSHOOT VIN; 0-50 Vdc 0 400 0 400 mV
SHUTDOWN DELAY VPIN5; > 10Vdc <8Vdc 220 500 220 500 s
SHUTDOWN RECOVERY TIME4 VPIN5; < 8Vdc > 10Vdc 60 60 ms
NOTES: 1. Unless otherwise stated: TC = 25C, VIN = 28V, IOUT = IOUT MAX.
2. Derate power linearly to zero from 125C to 135C.
3. Regulation measured between pin 1 and pin 2 1/6" from case.
4. Recovery spec assumes that converter has been OFF for at least 500ms.
5. DHC2803S IOUT MAX = 2.0ADC when voltage is adjusted to 3.0Vdc, VIN = 13-50Vdc, AND CLOAD 100F.
6. DHC2803S POUT MAX = 6W when VIN = 13-50Vdc
CAUTION
CAUTION: The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush, machine, or
PACKAGE THERMAL SPECIFICATIONS MIN TYP MAX UNITS
RESISTANCE, case to air 30 C/W

TEMPERATURE RISE, junction to case 10 15 C
37
TYPICAL PERFORMANCE
GRAPHS DHC2803S

50 50 50
30% 30% 30% TEMP =
40% TEMP = 25C TEMP = 55C
125C

40% 40%
50% 50%
40 40 40
55% 55%
50%
60% 60%
55%
63% 62%
30 30 60% 30
65%
63%
67% 64%
65%
66%
20 68% 20 20
67% 65%
69% 68% 66%
70% 67%
11 11 68% 11
.18 .36 .72 1.08 1.44 1.8 .18 .36 .72 1.08 1.44 1.8 .18 .36 .72 1.08 1.44 1.8
16

CURRENT RATING
OUTPUT DC
VOUT VOUT
1V
1V
14
1.8A 1.8A
12
500mA
500mA
.9A .9A
IOUT IOUT

10
0.0 0.5 1.0 1.5 2.0
LOAD TRANSIENT RESPONSE 1000F LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE

100mV
50mV
VOUT VOUT VOUT

1V
40V 80V
1.8A
500mA
.9A
16V
10V
IOUT VIN
VIN 11V
20V
TIME, t (500sec/DIV) TIME, t (200sec/DIV) TIME, t (200sec/DIV)

28 0
LOAD 1.8A VIN = 28V
AUDIO REJECTION, A V (dB)
IOUT = 2.0A
3.3V 20
24
VOUT 40
20
0V 28V 60
1V
16
80
INCLUDES 100F ON
10 V
12 0V VIN OUTPUT BUS

100
10K 20K 30K 40K 60K 90K 100 200 400 1K 2K 4K 10K 20K 40K 100K
38
TYPICAL PERFORMANCE
DHC2805S GRAPHS

50 50 50
30% 30% 30%
40% TEMP = 25C TEMP = 55C TEMP =

40% 40%
50% 125C
40 40 40 50%
55% 55%
50%
60% 60%
55%
63%
30 65% 30 60% 30
68% 63% 66%
70% 66%
20 71% 20 68% 20 68%
72% 69% 69%

70%
70%
11 11 11
.12 .24 .48 .78 .96 1.2 .12 .24 .48 .78 .96 1.2 .12 .24 .48 .78 .96 1.2
16

TEMP = 25C
CURRENT RATING
OUTPUT DC
VOUT VOUT
1V
1V
14
12 1.2A 1.2A
500mA
500mA
IOUT 600mA IOUT 600mA

10
0.0 0.4 0.8 1.2 1.6
LOAD TRANSIENT RESPONSE 1000F LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
LOAD = 1.2A INCLUDES 100F ON OUTPUT BUS

VOUT
100mV
50mV
VOUT
1V
VOUT
40V 80V LOAD = 1.2A
1.2A
16V
10V
600mA
500mA
IOUT VIN
VIN 11V
20V
TIME, t (500sec/DIV) TIME, t (200sec/DIV) TIME, t (200sec/DIV)

28 0
LOAD = 1.2A VIN = 28V
AUDIO REJECTION, A V (dB)
5.0V IOUT = 1.2A

20
24
VOUT
40
0V
28V
2V
20
60
16
0V VIN 80
10 V

12 100
10K 20K 30K 40K 60K 90K 100 200 400 1K 2K 10K 20K 100K
39
APPLICATION
INFORMATION DHC2803S/DHC2805S
OUTPUT ADJUST / COMP LOAD FAULT RESPONSE

The output voltage of the DHC2800S may be adjusted from The Apex families of dc-dc converters share load fault
90% to 110% of nominal value by the use of a 50k potentiom- philosophies. Load fault conditions include short-circuit and
eter as shown. Adjustment beyond this range is possible severe overload conditions. The DHC2800 converter series
however certain characteristics of the converter such as but responds to load faults by turning off all power conversion
not limited to input voltage range, efficiency, ripple and tem- circuits for 250 mS and then attempting to restart for 10 mS
perature performance will change. Characterization by the (typical). The net "on" duty factor during a fault is very low
user is recommended in such applications. resulting in low converter dissipation and immunity from
overheating at 125C. Current beyond rated can flow into the
load at startup time. This allows the converter to bring up
capacitive and other difficult load types more reliably than
3 1 2 competing converters.
50K
10nF Vo
O
Adjust/comp (pin 3) may be driven by external circuitry
referenced to pin 2 (-output) if desired. Grounding pin 3 causes
voltage to increase (25% typically) while driving pin 3 above
1.3 V causes output voltage to decrease. Pin 3 may be driven
through 10K or more if connection of the comp function is
also required. Io
The comp function of pin 3 allows capacitive loads as large O
as 1000 F to be accommodated on the DHC2805S without
loss of stability. This feature may be utilized by connecting a 10
nF capacitor between pins 3 and 1. This is generally recom-
mended when low esr load capacitances of 100 F or greater NORMAL LOAD FAULT NORMAL
are used.
TIME
SHUTDOWN PLUS
Pin 5 is used for remote shutdown, output fault detection,
and/or setting the input voltage point at which the converter will
turn on as shown in the typical application diagram. No
connection to pin 5 is necessary for normal operation of the
converter. Pin 5 is referenced to the input (pin 7).
Shutdown may be implemented by simply connecting pin
5 to an open collector logic output or switch rated at 2.5 mA, 25
Vdc or higher.
Input voltage turn on point is programmed with a single
resistor from pin 5 to 7. An input turn on/off hysteresis (typically
3.5% of Vin) will be observed. This should be considered when
making or verifying set point adjustment. The value of the
setpoint resistor may be determined by the following:
3
R = 210 10 (10% accuracy at 25C)
ETO 9.5
Set point temperature coefficient is typically +400ppm/C.
Output fault monitoring is accomplished by observing pin 5
with a high impedance monitoring circuit. Pin 5 voltage drops
from over 10 V to below 1 V when a load fault causes the
converters fault protection circuitry to activate. It will remain
low for at least 100 ms and return high. If the load fault is still
present pin 5 will return low and the cycle will repeat. A resistor
> 400 k from pin 5 to 7 provides pull down for pin 5 if there is
no input setpoint programming resistor already in place.
sheet has been carefully checked 5980
and is believed NORTH
to be reliable, SHANNON
no responsibility assumed forARIZONA 85741 or USA
possible inaccuracies APPLICATIONS
omissions. HOTLINE:
All specifications are subject to 1 (800)
change 546-2739
without notice.
DHC2800SU REV. F SEPTEMBER 1998 1998 Apex Microtechnology Corp.
40
NOTES:
41
POWER
AMPLIFIERS
Product Selector Guide ................................................................... 43 PA09, PA09A .............................................................................. 174
Second Sources .............................................................................. 46 PA09M ........................................................................................ 178
Frequency/Saturation Tables .......................................................... 48 PA10, PA10A .............................................................................. 180
PA10M ........................................................................................ 184
PWM AMPLIFIERS PA12, PA12A .............................................................................. 185
SA01 ............................................................................................... 50 PA12M ........................................................................................ 189
EK01 ............................................................................................. 54 PA12H ......................................................................................... 190
SA02 ............................................................................................. 58 PA19, PA19A .............................................................................. 191
EK02 Evaluation Kit for SA02 Pin-out ........................................... 64 PA21, PA21A, PA25, PA25A, PA26 ........................................... 195
SA03 ............................................................................................. 68 PA21M ........................................................................................ 200
EK03, Evaluation Kit for SA03/SA04 Pin-out ................................ 72 PA21, 25, 26 Design Ideas ......................................................... 201
SA04 ............................................................................................. 76 EK26, Evaluation Kit for PA26 Pin-out ........................................
EK21, Evaluation Kit for PA21 Pin-out ........................................
202
204
C
SA06 ............................................................................................. 80
PA25 DIE .................................................................................... 207
EK05, Evaluation Kit for SA06 Pin-out .......................................... 84 PA41, PA41A, PA42, PA42A ...................................................... 209
SA07 ............................................................................................. 88 PA41M ........................................................................................ 213
EK07, Evaluation Kit for SA07 Pin-out .......................................... 94 PA41DIE ..................................................................................... 214
SA13 ............................................................................................. 98 PA41/42 Design Ideas ................................................................ 215
EK10, Evaluation Kit for SA13/SA14 Pin-out ................................ 102 EK42, Evaluation Kit for SIP10 Pin-out ....................................... 217
SA14 ............................................................................................. 106 PA44 ........................................................................................... 219
SA16 ............................................................................................. 110 EK13, Evaluation Kit for PA44 Pin-out ........................................ 223
EK08, Evaluation Kit for SA16 Pin-out .......................................... 114 PA45 ........................................................................................... 225
SA50 ............................................................................................. 118 PA45DIE ..................................................................................... 229
EK-SA50 ....................................................................................... 122 PA46 ........................................................................................... 231
SA50M .......................................................................................... 123 EK12, Evaluation Kit for PA46 Pin-out ........................................ 235
SA51 ............................................................................................. 124 PA51, PA51A .............................................................................. 237
SA51M .......................................................................................... 128 PA51M ........................................................................................ 241
EK-SA51 ....................................................................................... 129 PA61, PA61A .............................................................................. 243
PA61M ........................................................................................ 247
POWER OPERATIONAL AMPLIFIERS PA81J/82J ................................................................................... 249
PA01, PA73 .................................................................................. 130 PA83, PA83A .............................................................................. 253
PA73M .......................................................................................... 134 PA83M ........................................................................................ 257
PA02, PA02A ................................................................................ 136 PA84, PA84A, PA84S ................................................................. 259
PA02M .......................................................................................... 140 PA84M ........................................................................................ 263
PA85, PA85A .............................................................................. 265
PA02 Design Ideas ..................................................................... 141 PA85M ........................................................................................ 269
PA03, PA03A .............................................................................. 144
PA88, PA88A .............................................................................. 271
PA04, PA04A .............................................................................. 148
PA88M ........................................................................................ 275
EK04, Evaluation Kit for PA04 Pin-out ........................................ 152
PA05, PA05A .............................................................................. 158 PA89, PA89A .............................................................................. 277
PA07, PA07A .............................................................................. 162
PA07M ........................................................................................ 166 POWER BOOSTERS
PA08, PA08A .............................................................................. 168 PB50 ........................................................................................... 281
PA08M ........................................................................................ 172 EK50, Power Booster Evaluation Kit ........................................... 285
PA08V ......................................................................................... 173 PB58, PB58A .............................................................................. 287
NOTE:For a complete listing of all /883 products and Standardized Military Drawing numbers (SMD)
refer to the most current APEX Order Information and Price List.
42
HIGH VOLTAGE/HIGH SPEED
PRODUCT SELECTOR GUIDE

HIGH VOLTAGE
Model Supply IOUT mA Saturation Internal Slew VOS VOS Bias Iq

Gain BW Current Thermal Temp Packaging
Range Cont. (min) @IOCont. Power Rate Initial vs Temp Current Product Limit Shutdown Range Type
Volts Pk (Typ) (VS-VO) Watts V/s mV V/C nA mA MHz C
Min/Max Volts, Max Max Typ Max Max Max Max Typ (Amps) Min/Max
PA89 75/600 75/100 30 40 16 2 30 .05 6 10 Ext Adj No 25/85 MO-127
PA89A * * * * * .5 10 .01 * * * * * *
PA85 15/225 200/350 10 40 1000 2 30 .05 25 100 Ext Adj No 25/85 TO-3
PA85A * * * * * .5 10 .01 * * * * * *
PA85M * * * * * 4 30 .05 * * * * 55/125 *
PA88 15/225 100/200 10 15 30 2 30 .05 2 2.1 Ext Adj No 25/85 TO-3
PA88A * * * * * .5 10 .01 * * * * * *
PA41 50/175 60/120 14 12 40 60 130 .05 2 1.6 Ext Adj No 25/85 TO-3
PA41A * * 12 * * 30 65 * 1.8 * * * * *
PA41M * * * * 5 60 130 * 2 * * * 55/125 *
PA42 50/175 60/120 14 9 40 60 130 2 2 1.6 Ext Adj No 25/85 SIP10
PA42A * * 12 * * 30 * * 1.8 * * * * *
PA44 50/175 60/120 14 12 40 60 130 .2 2 1.6 Ext Adj No -25/85 PSOP1
PA08 15/150 150 15 17.5 30 2 30 .05 8.5 5 Ext Adj No 25/85 TO-3
PA08A * * * * * .5 10 .01 * * * * * *
PA08M/883 * * * * * 2 30 .05 * * * * 55/125 *
PB58 15/150 1500 11 83 100 1750 7000 18 2.5 Ext Adj No 25/85 TO-3
PB58A * 2000 12 * * 1000 * * * * * * *
PA83 15/150 75 10 17.5 30 3 25 .05 8.5 5 (.1) Yes 25/85 TO-3
PA83A * * * * * 1 10 .01 * * * * * *
PA83M/883 * * * * * 3 25 .05 * * * * 55/125 *
PA84 15/150 40 7 17.5 180 3 25 .05 7.5 75 (.05) Yes 25/85 TO-3
PA84A * * * * * 1 10 .01 * * * * * *
PA84M/883 * * * * * 3 25 .05 * * * * 55/125 *
PA82J 70/150 15 5 11.5 20 3 25 .05 8.5 5 (.025) Yes 0/70 TO-3
PB50 30/100 2000 11 35 100 1750 7000 25 2.5 Ext Adj No 25/85 TO-3
PA81J 32/75 30 5 11.5 20 3 25 .05 8.5 5 (.05) Yes 0/70 TO-3
PA45 15/75 5000 10 85 27 10 50 .1 50 4.5 Ext Adj No 25/85 TO-3
PA46 15/75 5000 10 75 27 10 50 .1 5/50 4.5 Ext Aju No -25/85 POWER SIP 10
Specifications apply for TC = 25C, unless otherwise stated. *Specification is same as above.
HIGH SPEED
Model Slew Output Supply Saturation Internal VOS VOS Bias Iq Gain BW Current Thermal Temp Packaging
Rate Current Range @IOMax Power Initial vs Temp Current Product Limit Shutdown Range Type
V/s (Cont.) Volts (VS-VO) Watts mV V/C nA mA MHz C
Typ Amps., Min Min/Max Volts, Max Max Max Max Max Max Typ (Amps) Min/Max
PA85 1000 .2 15/225 10 40 2 30 .05 25 100 Ext Adj No 25/85 TO-3

PA85A * * * * * .5 10 .01 * * * * * *
PA85M * * * * * 2 30 .05 * * * * 55/125 *
PA19 900 4 15/40 5 78 3 30 .2 120 100 Ext Adj Yes 25/85 TO-3
PA19A * * * * * .5 10 .05 * * * * * *
PA09 400 2 12/40 8 78 3 30 .1 85 150 (4.5) Yes 25/85 TO-3
PA09A * * * * * .5 10 .02 * * * * * *
PA09M/883 * 3 * 10 * 3 30 .1 * * * * 55/125 *
43
HIGH CURRENT

HIGH CURRENT
Model Internal Output Supply Saturation Slew VOS VOS vs Bias Iq Gain BW Current Thermal Temp Packaging
Power Current Range @IOMax Rate Initial Temp Current Product Limit Shutdown Range Type
Watts (Cont.) Volts (VS-VO) V/s mV V/C nA mA MHz C
Max Amps., Min Min/Max Volts, Max Typ Max Max Max Max Typ (Amps) Min/Max
PA03 500 30 15/75 7 8 2 30 .05 300 1 Thermal Yes 25/85 MO-127
PA03A * * * * * .5 10 .01 * * * * * *
PA04 200 20 15/100 6.8/10(1) 50 10 50 .05 90 2 Ext Adj No 25/85 MO-127
PA04A * * * * * 5 30 .02 * * * * *
PA05 250 30 15/50 5.8/11.2(1) 100 10 50 .05 120 3 Ext Adj Yes -25/85 MO-127
PA05A * * * * * 5 30 .02 * * * * * *
PA12 125 10 10/45 6 4 6 65 30 50 4 Ext Adj No 25/85 TO-3
PA12A * 15 10/50 7 * 3 40 20 * * * * 55/125 *
PA12M/883 * 10 10/45 6 * 6 65 30 * * * * * *
PA61(2) 97 10 10/45 7 2.8 6 65 30 10 1 Ext Adj No 25/85 TO-3
PA61A(2) * * * 6 * 3 40 20 * * * * * *
PA61M/883(2) * * * 7 * 6 65 30 * * * * 55/125 *
PA51(2) 97 10 10/36 8 2.6 10 65 40 10 1 Ext Adj No 25/85 TO-3
PA51A(2) * * 10/40 * * 5 40 20 * * * * 55/125 *
PA51M/883(2) * * * * * 10 65 40 * * * * * *
PA45
PA46
85
75
5
5
15/75
15/75
10
10
27
27
10
10
50
50
.10
.10
50
5/50
4.5
4.5
Ext Adj
Ext Adj
No
No
25/85
-25/85
TO-3
POWER SIP 10
C
PA07 67 5 12/50 5 5 2 30 .05 30 1.3 Ext Adj Yes 25/85 TO-3
PA07A * * * * * .5 10 .01 * * * * * *
PA07M/883 * * * * * 2 30 .05 * * * * 55/125 *
PA10 67 5 10/45 8 3 6 65 30 30 4 Ext Adj No 25/85 TO-3
PA10A * * 10/50 6 * 3 40 20 * * * * 55/125 *
PA10M/883 * * 10/45 8 * 6 65 30 * * * * * *
PA73(2) 67 5 10/30 8 2.6 10 65 40 5 1 Ext Adj No 25/85 TO-3
PA73M/883(2) * * * * * * * * * * * * 55/125 *
PA01 67 5 10/28 10 2.6 12 65 50 50 1 * * 25/85 TO-3
PA02 48 5 7/19 4 20 10 50 .2 40 4.5 Ext Adj No 25/85 TO-3
PA02A * * * * * 3 25 .1 * * * * 55/125 *
PA02M/883 * * * * * 10 50 .2 * * * * * *
PA21 36 2.5 2.5/20 3.0 1.2 10 15 typ 1000 90 .6 (3) No 25/85 TO-3
PA21A * 3.0 * 4.0 * 4 10 typ 250 * * (4) * * *
PA21M * 2 * * * 10 15 typ 1000 75 * (3) * 55/125 *
PA25 36 2.5 2.5/20 3.0 1.2 10 15 typ 1000 90 .6 (3) No 25/85 TO-3
PA25A * 3.0 * 4.0 * 4 10 typ 250 * * (4) * * *
PA26 36 2.5 2.5/20 1.2 10 15 typ 1000 90 .6 (3) No 25/85 SIP12
PB50 35 2 30/100 11 100 1750 7000 25 2.5 Ext Adj No 25/85 TO-3
PB58 83 1.5 15/150 11 100 1750 7000 18 2.5 Ext Adj No 25/85 TO-3
PB58A * 2.0 * 12 * 1000 * * * * * * *
(1) 1st number with Boost Voltage = VS + 5V; 2nd number without Boost Voltage (2) Class C outputoptimized for low costnot recommended above 1KHz
44
PWM AMPLIFIERS

PWM AMPLIFIERS
Model Output Power Efficiency Internal Supply Switching Bridge Current Thermal Temp Packaging
Current Delivery % Power Range Frequency Type Limit Shutdown Range C Type
(Cont.) (Cont.) Watts Volts KHz Min/Max
Amps., Min Watts Max Min/Max Typ
SA01 20 2000 97 185 16/100 42 Full Ext Adj Yes 25/+85 PD10/60S
SA02 10 800 94 160 16/80 250 Full Ext Adj Yes 25/+85 DIP7
SA03 30 3000 97 300 16/100 22.5 Full Ext Adj Yes 25/+85 MO-127
SA07 5 200 94 80 5/40 500 Full Ext Adj Yes -25/+85 DIP6
SA13 30 3000 97 150 16/100 22.5 Half Ext Adj Yes 25/+85 MO-127
SA50 5 400 97 120 /80 45 Full No No 25/+85 TO-3
SA51 5 400 97 120 /80 Full No No 25/+85 TO-3
45
EQUIVALENT/SECOND SOURCES
SECOND SOURCES FOR APEX POWER AMPLIFIERS
PA01 (page 130) OPA511AM (P/D) Burr-Brown Higher cost; slightly improved Vos and Vsat.
PA02 (page 136) LH0101 (F/E) National PC layout can be designed to accept either; output=case; may require
external swing enhancement network; some loss of speed and
linearity.
PA10 (page 180) OPA511AM (P/D) Burr-Brown No foldover current limit; supplies to 30V only.
OPA512 (P/D) Burr-Brown 10A output; higher cost.
PA12 (page 185) OPA512 (P/F) Burr-Brown
PA25 (page 195) OPA2541 (P/D) Burr-Brown Higher Vsat, higher cost, more distortion, higher supply voltages,
wider bandwidth.
OPA2544 (P/D) Burr-Brown Lower IQ, higher VSAT, higher VS, wider bandwidth
PA51 (page 237) OPA501 (P/F) Burr-Brown
PA73 (page 130) 3573 (P/F) Burr-Brown
PA81J (page 249) 3581J (P/F) Burr-Brown
PA82J (page 249) 3582J (P/F) Burr-Brown
PA83 (page 253) 3583 (P/D) Burr-Brown Supplies down to +/-50V only.
PA84 (page 259) 3584 (P/D) Burr-Brown Slightly slower; supplies down to 70V only.
Products not listed have no known second source.
APEX ALTERNATIVES FOR EXISTING DESIGNS

ALLEGRO (SPRAGUE) C
ULN3755W PA26 (page 195) (P/F)
BURR-BROWN
OPA501 PA51 (page 237) (P/F) Slightly improved thermal performance for all grades.
PA61 (page 243) (P/D) Supplies to 45V; lower Vsat, Lower Vos.
OPA511AM PA01 (page 130) (P/D) Lower cost; slightly higher Vos and Vsat.
PA10 (page 180) (P/D) Supplies to 45V; lower Vos; faster; slightly higher cost.
OPA502BM PA12 (page 185) (P/D) Bipolar, slew rate = 4V/s, VS = 50V.
OPA502SM PA12A (page 185) (P/D) Bipolar, slew rate = 4V/s, IOUT = 15A, VS = 50V.
OPA512BM PA12 (page 185) (P/F)
OPA512SM PA12A (page 185) (P/F)
OPA541 Apex alternatives provide: independent setting of current limits; lower distortion, except
on class C units; PC layout could accommodate alternates easily except for PA02. Two
grades of OPA541 are FET input amplifiers with 1 and 10 mV of input offset. Both have
max DC thermal resistance of 1.9 C/W.
PA02 (page 136) (F/E) Lower Vsat; higher speed; Vos = 3 and 10mV; thermal resistance is 2.6 C/W.
PA10 (page 180) (P/D) Bipolar; Vos = 3 and 6 mV, thermal resistance is 2.6 C/W.
PA45 (page 225) (P/D) MOSFET input and output, VOS = 10mV; thermal resistance is 1.5C/W; supplies to 75V,
external compensation (slew rate to 27V/s).
PA61 (page 243) (P/D) Bipolar; Vos = 3 and 6 mV; thermal resistance is 1.8 C/W; class C output stage.
PA51 (page 237) (P/D) Bipolar; Vos = 5 and 10 mV; thermal resistance is 1.8 C/W; class C output stage.
PA12 (page 185) (P/D) Bipolar; Vos = 3 and 6 mV; thermal resistance is 1.4 C/W; fully tested to 10A or 15A.
PA07 (page 162) (P/D) FET Vos = 0.5 and 2 mV; thermal resistance is 2.6 C/W; supplies to 50V; includes
thermal shutdown.
OPA2541 PA25 (page 195) (P/D) Supplies to 20V only; lower Vsat; lower cost; lower distortion.
OPA2544 PA25 (page 195) (P/D) Higher IQ, Lower VSAT, lower VS, lower bandwidth.
3571, 72 PC layout could accommodate Apex alternates easily.
PA07 (page 162) (P/D) Higher voltage, power dissipation, frequency response.
PA01 (page 130) (P/D) Supplies to 28V; bipolar input; very low cost.
PA10 (page 180) (P/D) High performance bipolar input; supplies to 50V; much lower cost than 3572.
PA12 (page 185) (P/D) Output currents to 15A; supplies to 50V; high performance bipolar input.
PA61 (page 243) (P/D) Output currents up to 10A; bipolar input; class C output; lower cost than 3572.
3573 PA73 (page 130) (P/F)
3580-83 PA83 (page 253) (P/F) Extends the best specs of each model through the entire voltage range.
3581J PA81J (page 249) (P/F) Recommend PA41 for any new design of 3580-3583 series.
3582J PA82J (page 249) (P/F)
3583AM PA83 (page 253) (P/F)
3583AMQ PA83Q (Consult Factory) (P/F)
3583J PA83 (page 253) (P/F)
3584JM PA84 (page 259) (P/D) Slightly faster, improved phase margin, higher current; APEX
temperature range is -25 to +85C.
46
EQUIVALENT/SECOND SOURCES
INTERSIL, HARRIS
8510, 15 PA01 (page 130) (F/E) All Apex current models offer more power and several offer accuracy improvements.
8520, 30 PA07 (page 162) (F/E) The models listed here are 5A, 67W devices. All are 8 pin TO-3 packages.
NATIONAL
LH0101 PA02 (page 136) (P/D) PA02 swing enhancement network is internal; PC layout can often accept either part;
isolated case; better speed and linearity; 19V supplies max.
LM12 PA02 (page 136) (F/E) Often has efficiency advantages on applications up tp 19V due to low Vsat at 5A or less.
PA07 (page 162) (F/E) Lower Vos; adjustable Vos balance; supplies to 50V; output currents to 5A.
PA10 (page 180) (F/E) Lower Vos; supplies to 45V and 50V; 5A output current.
PA61 (page 243) (F/E) Lower Vos; supplies to 45V; 10A output current; low Iq; class C operation.
PA12 (page 185) (F/E) Lower thermal resistance; lower Vos; supplies to 45V or 50V; 10A or 15A output
currents.
LM675 PA26 (page 195) (F/E) PA26 is a dual, unity gain stable.
SGS-THOMPSON
L165 PA26 (page 195) (F/E) PA26 is a dual, unity gain stable.
TELEDYNE
1460 PA09 (page 174) (P/D) Faster and considerably more powerful.
1461 PA09 (page 174) (F/E) Slower but more powerful.
1468 PA12 (page 185) (P/D) PC layout could accommodate both parts; PA12 offers foldover current limit.
1480 PA83 (page 253) (P/F)
PA84 (page 259) (P/D) Faster; external compensation; lower output current; PC layout could accommodate
either part.
NOTES: (P/F) = Pin for pin compatibleform, fit and functional replacement
(P/D) = Pin for pin compatiblemajor performance differences noted
(F/E) = Functional equivalentnot pin for pin compatiblemajor differences noted
47
POWER AMPLIFIERS/PWM AMPLIFIERS
FREQUENCY/SATURATION TABLES
OUTPUT SATURATION VOLTAGE FREQUENCY (kHz) VS PEAK-TO-PEAK

VS OUTPUT CURRENT OUTPUT VOLTAGE (TYP)
RANKED BY OUTPUT CURRENT RANKED BY SUPPLY VOLTAGE RANGE
IO .05 .12 .5 2.5 5 7.5 10 15 20 30 VO(p-p) 20 25 30 45 60 90 120 180 280 430 1000
SA13 .01 .02 .1 .4 .7 1.1 1.4 2.1 2.8 4.2 PA89 30 23 17 10 6 2.7
SA03 .01 .03 .1 .7 1.4 2.1 2.8 4.2 5.6 8.4 PA85 3000 3000 3000 3000 2500 1600 1250 830 530 350
SA01 .05 .2 .5 1.0 2.0 2.3 5.0 7.0 9.2 14 PA87 200 200 200 200 180 110 85 60 40 24
PA05+Vb 2.3 2.3 2.4 2.6 2.9 3.2 3.5 4.1 4.6 5.8 PA88 70 60 55 40 28 21 15 11 7 4
PA03 4.0 4.0 4.1 4.3 4.5 4.8 5.0 5.5 6.0 7.0 SA06 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2
PA05 6.0 6.0 6.1 6.4 6.9 7.3 7.8 8.8 9.5 11.3 SA16 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2
SA14 .01 .02 .1 .5 1.0 1.4 1.9 2.9 3.9 PA41 350 300 250 150 110 70 55 35 25
SA04 .02 .05 .2 1.0 1.9 2.9 3.9 5.8 7.7
PA42/43 350 300 250 150 110 70 55 35 25
SA01 .02 .05 .2 1.1 2.2 3.3 4.4 6.6 8.8
PA04+Vb 3.8 3.8 3.9 4.2 4.6 4.9 5.3 6.1 6.8 PA84 500 500 500 500 500 380 330 220 130
PA04 5.9 5.9 6.0 6.4 6.9 7.3 7.8 8.8 9.7 PB58 300 300 300 300 300 300 260 160 102
PA12A 5.0 5.0 5.0 5.2 5.3 5.5 5.7 6.0 PA08 630 500 420 280 210 140 105 70 45
SA02 .04 .09 .4 1.8 3.7 5.5 7.4 PA83 700 560 460 310 230 150 110 80 50
SA16 .04 .10 .4 2.1 4.2 6.3 8.4 PA82 500 400 330 220 160 110 80 55 36
SA06 .08 .20 .8 4.2 8.3 12.5 16.6 PB50 300 300 300 300 300 300 260 160
PA12 5.0 5.0 5.1 5.3 5.5 5.8 6.0 PA04 900 720 600 400 300 200 150 100
PA61A 5.0 5.0 5.1 5.3 5.5 5.8 6.0 PA81 500 400 330 220 160 110 80 55
PA61 5.0 5.0 5.1 5.5 6.0 6.5 7.0 SA04 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2
PA51 6.0
SA50 .04
6.0
.11
6.1
.4
6.5
2.2
7.0
4.4
7.5 8.0

SA14 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 C
PA03 135 108 90 60 45 30 22
SA51 .04 .11 .4 2.2 4.4 PA45 400 380 260 190 130 80 65
PA02 1.4 1.5 1.7 2.7 4.0 PA05 1800 1440 1200 800 600 400
PA07 5.0 5.0 5.0 5.0 5.0
PA07 60 48 40 27 20 13
PA10A 5.0 5.0 5.1 5.5 6.0
PA73 5.0 5.1 5.3 6.5 8.0 PA12 60 48 40 27 20 13
PA10 5.0 5.1 5.3 6.5 8.0 PA10 88 70 60 40 30 20
PA01 5.1 5.1 5.5 7.5 10.0 PA61 40 33 30 24 18 13
PA45 5.5 5.6 6.0 7.8 10.0 SA03 2.2 2.2 2.2 2.2 2.2 2.2
PA19 1.2 1.3 1.7 3.6 6.0 SA13 2.2 2.2 2.2 2.2 2.2 2.2
PA21/25/26.7 .8 1.2 3.1 SA02 25 25 25 25 25
PA09 6.9 7.0 7.2 SA01 4.5 4.5 4.5 4.5 4.5
PB50 7.9 8.0 8.6 SA50 4.5 4.5 4.5 4.5 4.5
PB58 7.9 8.0 8.9 PA195000 5000 5000 5000 5000
PA85 8.3 9.1 PA09 2600 2600 2200 1500 1100
PA85 8.3 9.1 PA51 55 45 37 25 18
PA87 6.0 10.2 PA73 50 42 35 23
PA08 7.4 12.7 PA01 50 42 35 23
PA88 9.5 13.0 PA02 300 240 200
PA41/42 12.3 14.0
PA21/25 33 20 17
PA89 25.4
PA83 8.0 PA26 33 20 17
PA84 7.7 Av = 10V/V
48
NOTES:
49
PULSE WIDTH MODULATION AMPLIFIER
SA01
FEATURES
SINGLE SUPPLY OPERATION
SA01
WIDE SUPPLY RANGE 16-100V
20A CONTINUOUS OUTPUT
PROGRAMMABLE CURRENT LIMIT USA
TE9493 BeO
11
SHUTDOWN CONTROL
HERMETIC PACKAGE
2 IN2 FOOTPRINT
APPLICATIONS
BRUSH TYPE MOTOR CONTROL
PELTIER CONTROL
REACTIVE LOADS
MAGNETIC COILS (MRI)
ACTIVE MAGNETIC BEARING TYPICAL APPLICATION
VIBRATION CANCELLING
DESCRIPTION
The SA01 amplifier is a pulse width modulation amplifier that
EA
3 7
C
can supply 2KW to the load. The full bridge output amplifier can +VS
+VIN IN OUT
be operated from a single power supply over a wide range of 1
voltages. An error amplifier is included which can provide gain A
for the velocity control loop in brush type motor control appli- 7.5V 6
5 EA OUT
cations. Current limit is programmable by a single resistor. A C1 REF PWM M T
shutdown input turns off all four drivers of the H bridge output. .1F
2
A precision reference output is provided for use in offsetting +IN B
9
the error amplifier. The error amplifier can then be scaled for SHDN/ OUT
standard input signals. The amplifier is protected from shorts
to supply or ground. The H bridge output MOSFETs are 10 8 4
protected from thermal overloads by directly sensing the RFILTER
temperature of the die. The 10-pin hermetic power package RLIMIT
occupies only 2 square inches of board space. SHUT CFILTER
DOWN
Motor Driver With Tach Feedback
BLOCK DIAGRAM
7 +VS
7.5V REF OUT
5 SUP/
REF OUTPUT
DRIVERS EXTERNAL CONNECTIONS
9 B OUT
3 PWM 6 A OUT CFILTER
EA OUT
CURRENT
LIMIT
AND ISENSE
SHUTDOWN 8
IN 1
CONTROL 10 SHDN/
IN 1 10
ERROR SHDN/ R FILTER
FILTER
+IN 2
AMP FILTER
+IN 2 9
B OUT +
GND 4 EA OUT 3 TOP 8
VIEW I SENSE
AS EA OUT (3) GOES MORE POSITIVE, HIGH STATE OF A OUT (6)
GND 4 7 +VS
INCREASES AND HIGH STATE OF B OUT (9) DECREASES. REF
5 6
.1F A OUT
C1 R LIMIT
R LIMIT = .2
ILIMIT
50
SA01 SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS SUPPLY VOLTAGE, +VS 100V

OUTPUT CURRENT, peak 30A
POWER DISSIPATION, internal 185W1
TEMPERATURE, pin solder - 10s 300C
TEMPERATURE, junction2 150C
TEMPERATURE, storage 65 to +150C
OPERATING TEMPERATURE RANGE, case 55 to +125C
SHUTDOWN VOLTAGE 10V
REFERENCE LOAD CURRENT 10mA
ERROR AMP INPUT 0 to +12V
SPECIFICATIONS
ERROR AMP
OFFSET VOLTAGE 10 mV
BIAS CURRENT 5 A
OFFSET CURRENT 1 A
COMMON MODE VOLTAGE RANGE4 +2 +8 V
COMMON MODE REJECTION, DC4 75 dB
SLEW RATE 15 V/S
OPEN LOOP GAIN4 75 dB
GAIN BANDWIDTH PRODUCT 2 MHz
OUTPUT
TOTAL RON .25
EFFICIENCY, 10A OUTPUT VS = 100V 97 %
SWITCHING FREQUENCY 35.3 42 48.7 KHz
CURRENT, continuous4 20 A
CURRENT, peak4 30 A
REFERENCE
VOLTAGE IREF = 5mA 7.46 7.50 7.54 V
VOLTAGE VS. TEMP4 Full temperature range 50 PPM/C
OUTPUT CURRENT 5 mA
LOAD REGULATION4 20 50 PPM/mA
LINE REGULATION 1 PPM/V
POWER SUPPLY
VOLTAGE Full temperature range 16 50 100 V
CURRENT IOUT = 0, IREF = 0 76 90 mA
CURRENT, shutdown IREF = 0 25 mA
SHUTDOWN
TRIP POINT .18 .22 V
INPUT CURRENT 100 nA
THERMAL2
RESISTANCE, junction to case Full temp range, for each transistor 1.0 C/W
RESISTANCE, junction to air Full temperature range 12 C/W
TEMPERATURE RANGE, case Meets full range specifications 25 +85 C
NOTES: 1. Each of the two active output transistors can dissipate 125W, however the N-channel will be about 1/3 of the total dissipated
power. Internal connection resistance is .05.
2. Unless otherwise noted: TC = 25C.
3. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to
achieve high MTTF. For guidance, refer to the heatsink data sheet.
4. Guaranteed but not tested.
The SA01 is constructed from MOSFET transistors. ESD handling procedures must be observed.
CAUTION
The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush, machine, or
51
TYPICAL PERFORMANCE
GRAPHS SA01
NORMALIZED SWITCHING FREQUENCY, (%)

POWER DERATING NORMALIZED CLOCK DRIFT VOLTAGE DROP
INTERNAL POWER DISSIPATION, P (W)
125
101 9
8 CASE TEMP. 60C
100 CASE TEMP. 85C
VOLTAGE DROP, (V)

7
100 6 CASE TEMP. 110C
75
5
4
50
99 3
25 2
CASE TEMP. 35C
EACH OUTPUT TRANSISTOR 1
0 98 0
0 25 50 75 100 125 55 15 25 85 125 0 2 4 6 8 10 12 14 16 18 20
CASE TEMPERATURE, T C (C) CASE TEMPERATURE, TC (C) OUTPUT CURRENT, (A)
MAXIMUM CONTINUOUS OUTPUT ERROR AMP SMALL SIGNAL GAIN ERROR AMP SMALL SIGNAL PHASE
OPEN LOOP GAIN RESPONSE, A (dB)
25 120 0
OPEN LOOP PHASE, ()

OUTPUT CURRENT , (A)
20
45
80
15
90 C
40
10
135
5
0
TJ = 150C 180
0
25 45 65 85 105 125 1 10 100 1K 10K 100K 1M 10M 1 10 100 1K 10K 100K 1M 10M
CASE TEMPERATURE, TC (C) FREQUENCY, F (Hz) FREQUENCY, F (Hz)
FLYBACK DIODES FET ON RESISTANCE BRIDGED OUTPUT SWING

VOLTAGE DROP, VS [AOUTBOUT] (V)
SOURCE TO DRAIN DIODE VOLTAGE
4 .3
10.0 125C
25C L
N NE .25 6.00
HA VS NEL
ON RESISTANCE, ()
3 P-C O+ 85C
TT HAN 2.00
U P-C
A /B O .2 25C
1.00
2 .15 0.40
L
ANNE
N-CH
NEL .1 0.10
1 N-CHAN
0.06
TO I SENSE
A/B OUT .05
0.02 JUNCTION TEMPERATURE
0 0
0 5 10 15 20 50 70 90 110 130 150 0.1 0.4 1.0 2.0 6.010.0 40.0
FLYBACK CURRENT, I SD, (A) CASE TEMPERATURE, T J (C) BRIDGE DRIVE CURRENT, IOUT (A)
QUIESCENT CURRENT DRIFT NORMALIZED REFERENCE DRIFT DUTY CYCLE

NORMALIZED REFERENCE, VREF, (X)
1.0004
QUIESCENT CURRENT, IQ (mA)
VS = 100V
80 80
1.0002
VS = 80V
PERCENT HIGH
VS = 60V
70 1.0000
40
BO
VS = 40V
UT
UT
O
A
0.9998
60
VS = 20V
0.9996 0
55 15 25 85 125 50 25 0 25 50 75 100 125 2 4 6 8
CASE TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C) CONTROL, EA OUT (V)
52
OPERATING
SA01 CONSIDERATIONS
GENERAL PROTECTION CIRCUITS

Helpful information about power supplies, heatsinking and There are two conditions which will latch all the output
mounting can be found in the General Operating Consider- transistors off. The first of these conditions is activation of the
ations section of the Apex data book. For information on the high side current limit. Specifically, current in pin 7 (+VS) is
package outline, heatsinks, and mounting hardware see the monitored. The DC trip level is about 35A and response time
Package Outlines and Accessories section of the data book. about 5us. As actual currents increase the response time
Also see Application Note 30 on PWM Basics. decreases. The external fault generally associated with this
condition is shorting one of the outputs to ground. However, a
CURRENT LIMIT load fault can also activate this high side current limit if the
current rise time is less than the response time of the filter
The current limit function sets a peak limit on current flow in discussed under Current Limit. The second of these condi-
pin 8 (Isense). This limits load current and also limits current in tions is activation of any of the four output transistor over-
the event of a short of either output to +Vs. This circuit can trip temperature sensors at about 165C. Ambient temperature, air
anytime during the conduction period and will hold the output flow, amplifier mounting problems and all the previously men-
transistors off for the remainder of that conduction period. tioned high current faults contribute to junction temperature.
For proper operation the current limit sense resistor must be When either of these protection circuits are activated, the root
connected as shown in the external connection diagram. It is fault must be corrected and power cycled to restore normal
recommended that the resistor be a non-inductive type. Load operation.
current flows in pin 8. No current flows in pin 10 (Shutdown/
filter) so no error will be introduced by the length of the DEAD TIME
connection to pin 10. However, the voltage at pin 10 is com- There is a dead time between the on and off of each output.
pared to GND (pin 4) and an error could be introduced if the The dead time removes the possibility of a momentary conduc-
grounded end of RLIMIT is not directly tied to pin 4. Good circuit tion path through the upper and lower transistors of each half
board layout practice would be to connect RLIMIT directly be- bridge output during the switching interval. During the dead
tween pins 8 and 4. time all output transistors are off. Noise or flyback may be
Switching noise spikes will invariably be found at pin 8. The observed at the outputs during this time due to the high
amplitude and duration will be load dependent. The noise impedance of the outputs in the off state. This will vary with the
spikes could trip the current limit threshold which is only 200 nature of the load.
mV. RFILTER and CFILTER should be adjusted so as to reduce the
switching noise well below 200 mV to prevent false current
REF OUT 5
limiting. The sum of the DC level plus the noise peak will .1F
determine the current limiting value. Suggested starting values
are CFILTER = .01F, RFILTER = 5k.
R2 R1
The required value of RLIMIT may be calculated by: C1 R3
C2 R4
RLIMIT = .2 V / ILIMIT TO TACH
where RLIMIT is the required resistor value, and ILIMIT is the IN
R5
maximum desired current. SIGNAL 1
R6 3
+IN
SHUTDOWN 2 E/A OUT
The shutdown circuitry makes use of the internal current R7
limiting circuitry. The two functions may be externally combined
as shown below in Figure 1. RLIMIT will normally be a very low FIGURE 2.
value resistor and can be considered zero for this application.
RSD and RFILTER form a voltage divider for the shutdown signal.
After a suitable noise filter is designed for the current limit adjust ERROR AMPLIFIER
the value of RSD to give 317 mV of shutdown signal at pin 10 The internal error amplifier is an operational amplifier. For
when the shutdown signal is high. This means pin 10 will reach highest loop accuracy it is best to configure the op amp as an
the 200 mV trip point in about one time constant with low output integrator (See Figure 2). Feedback can be adjusted with
current and less time as output current increases. The voltage appropriate poles and zeroes to properly compensate the
at pin 10 is referenced velocity loop for optimum stability.
RSD to pin 4 (GND). CFILTER The op amp is operated from a single supply voltage gener-
SHUTDOWN SHDN/FILTER will filter both the cur- ated internally. The non-inverting input of the op amp does not
SIGNAL 10 rent limit noise spikes have a common mode range which includes ground. R2 and R7
and the shutdown sig- are used with the reference voltage provided at pin 5 to bias the
CFILTER nal. Shutdown and cur- non-inverting input to +5 volts, which is approximately half of
R FILTER rent limit operate on the voltage supplied internally to the op amp. Similarly, R1 and
each cycle of the inter- the parallel combination of R5 R6 are selected to bias the
8
nal switching rate. As inverting input also at +5 volts. Resistors R1 R2 must be
I SENSE
RLIMIT long as the shutdown matched. Likewise the parallel combination of R5 R6 must be
signal is high the output matched with R7. The source impedances of the tach and the
will be disabled. signal source may affect the matching and should be consid-
FIGURE 1. ered in the design.
omissions. HOTLINE:
change 546-2739
without notice.
SA01U REV. D JANUARY 1998 1998 Apex Microtechnology Corp.
53
EVALUATION KIT FOR SA01 PIN-OUT
EK01
INTRODUCTION ASSEMBLY
This easy-to-use kit provides a platform for the evaluation of 1. From the non-silk screen side, insert and solder cage jacks. Be
PWM amplifiers using the SA01 pin-out configuration. It can be used sure each one is fully seated.
to analyze a multitude of standard or proprietary circuit configura- 2. From the non-silk screen side, push spacer grommets into PC
tions, and is flexible enough to do most standard amplifier test board until fully seated. Grommets will snug when screws are
configurations. The board is designed for surface mounting all inserted for heatsink mounting.
components except the switching amplifier. 3. Apply TW10 thermal washer or a thin, even coat of thermal
The schematic is shown in Figure 2. Note that all of the compo- grease to the bottom of the SA01. If grease is from a tube make
nents shown on the schematic will probably not be used for any sure there is no sign separation of solids and liquids. If from a jar,
single circuit. Some components will simply be omitted, while others stir it prior to application.
require installation of a jumper to complete the signal path. 4. Use #14 sleeving to insulate and align at least 2 opposite pins of
Only components unique to the EK01 are provided in this kit. the amplifier.
Hardware similar to that shown in figure 1 must be obtained locally. 5. Mount amplifier to heatsink using #6 screws and nuts. Do not
The PC board and the foot print of the heatsink measure 3" by 5". over torque.
6. Install components as needed. External connections may be
PARTS LIST soldered directly or standard banana jacks may be soldered to
these pads.
Part # Description Quantity 7. Insert amplifier pins into cage jacks and fasten board to heatsink.
HS16 Heatsink 1
MS04 PC mount Cage Jacks 1 Bag/12 each
EK01PC PC Board 1
60SPG00001 Spacer Grommets 4
TW10 Thermal Washer 1 Box/10 each
C
BEFORE YOU GET STARTED
* All Apex amplifiers should be handled using proper ESD precautions.
* Always use the heatsink included in this kit with thermal grease.
* Torque the part to the specified 8 to 10 in-lbs (.9 to 1.13 N*M)
* Always use adequate power supply bypassing.
* Do not change connections while the circuit is powered.
* Initially set all power supplies to the minimum operating levels allowed in the device data sheet.
* Check for oscillations.
Cage Jack
PC Board (Silkscreen side) Solder as required
Spacer Grommet
6-32 x 1/2 Lg. Screw
TW10 thermal washer or

thermal grease as required
Heatsink
#8 or #10 Screw (1/2" - 3/4" LG) Switching Amplifier
Hex Nut 6-32 THD 1/4"
FIGURE 1.
54
EVALUATION KIT
EK01 FOR SA01 PIN-OUT
FIGURE 2. PCB SCHEMATIC.

TACH/
FEEDBACK
R7
C3 C4 R2
R12 R16
R11
C10
+VS
R6 C6 C1 C7
SIG C5
R5 3 7
EA +VS
IN OUT
IN 1
D4
A
D6 R14 7.5V 6 AOUT
R1 5 EA OUT
11V
REF PWM
D1
REF D3
2 B
OUT +IN 9 BOUT
SHDN/ OUT
C9
D7 C12 SA01 FILTER I SENSE GND
11V 10 8 4 D2
R4 R17 R3 GND
GND
R8 R9
R10
SHDN
C8 SIG
+IN
C13 C2
D5
C11 11V
R13 R15
TYPICAL COMPONENT FUNCTIONS

R1 Provides -IN bias from the Reference voltage.
R2 Sets DC scaling for external feedback such as tachometers, position sensors or current sensors.
R3 With R4 sets DC operating point of +IN, with R13 and R15 sets gain of voltage feedback circuit.
R4 With R3 sets DC operating point of +IN.
R5 Input scaling of the control signal.
R6 With C6 sets the corner frequency of the integrator.
R7 With C3 & C4 forms a low pass filter for the external feedback loop. Often used with tachometers.
R8 With C2 forms a low pass filter for the current limit circuit.
R9 Current sense. Often is a piece of resistance wire.
R10 With R8 divides shutdown signal voltage feeding SHDN/FILTER pin.
R11 With C5 sets corner frequency for external feedback loop.
R12, 13, 15, 16 Provides voltage feedback for a voltage controlled output.
R14 Helps set gain or scale input voltage levels.
R17 With C12 provides low pass filtering of +IN signal.
C1 Power supply bypass.
C2 With R8 form a low pass filter for the current limit circuit, also filters the SHDN signal.
C3, 4 With R7 forms a low pass filter for the external feed back loop. Often used with tachometers.
C5 With R11 sets corner frequency for external feedback loop.
C6 With R6 sets the corner frequency of the integrator.
C7 Power supply bypass, must have very low ESR in MHz range.
C8 Filters reference or feedback voltage at +IN.
C9 Bypass for the reference voltage.
C10, 11 With R15 and R16 provides low pass filtering of voltage feedback.
C12 With R17 provides low pass filtering of +IN signal.
C13 Provides AC coupling of +IN signal.
D1 D4 Optional flyback diodes.
D5 D7 Input protection zener diodes.
55
EVALUATION KIT
FOR SA01 PIN-OUT EK01
FIGURE 3. PCB FRONT.
OPEN LOOP OPERATION

R6 C6
+VS
3 7 C1 C7
EA +VS
IN OUT
1
A
7.5V 6 AOUT
5 EA OUT
REF PWM
REF 2
OUT +IN B
9 BOUT
C9 SHDN/ OUT
R17 C12
10 8 4
GND
IN R8 R9
+2.5/+7.5
R10
VIN Duty Cycle @ AOUT SHDN
SIG
2.5V 0% C2
5V 50%
7.5V 100%
VIN 5
(A B) = V I R
2.5 * S O * DSON
56
COMMON
EK01 CONFIGURATIONS
VOLTAGE CONTROL R12 R16

RF C10
+VS
SIG R6 C6
3 7 C1 C7
R5
EA +VS
IN OUT
1
A
7.5V 6 AOUT
R1 5 EA OUT
RO REF PWM
REF 2
OUT +IN B
9 BOUT
R17 SHDN/ OUT
C9
10 8 4
R3 GND
R4
RF RO R8 R9
(A B) = VIN * RI
RI R10
SHDN
C8 SIG
RF C2
R13 C11 R15
POSITION CONTROL
TACH/
FEEDBACK
R7
R2
R11 +VS
SIG
R6 C6 C1 C7
R5 C5 3 7
EA +VS
IN OUT
1 +REF
A AOUT
7.5V 6
R1 5 EA OUT
REF PWM M
REF 2
OUT +IN B
9
SHDN/ OUT BOUT
C9 R17 REF
10 8 4
R3 GND
R4
R8 R9
R10
SHDN
C8 SIG
+IN
C2
SPEED CONTROL
TACH/
FEEDBACK
R7
C3 C4 R2
R11
+VS
R6 C6
SIG C5 C1 C7
R5 3 7
EA +VS
IN OUT
1
A AOUT
7.5V 6
R1 5 EA OUT
REF PWM M T
REF 2
OUT +IN B
9
SHDN/ OUT BOUT
C9 R17
10 8 4
R3 GND
R4
R8 R9
R10
SHDN
C8 SIG
+IN
C2
omissions. HOTLINE:
change 546-2739
without notice.
EK01U REV. C JANUARY 1998 1998 Apex Microtechnology Corp.
57
SA02
FEATURES SA02
250kHz SWITCHING
7
Q 9 8 1e O
MB 3 0 9U S A B
600 24
FULL BRIDGE OUTPUT 16-80V (160V P-P)
10A OUTPUT
FAULT PROTECTION
SHUTDOWN CONTROL
SYNCHRONIZABLE CLOCK
HERMETIC PACKAGE
APPLICATIONS EXTERNAL CONNECTIONS
AIRCRAFT AUDIO AMPLIFIER
BRUSH TYPE MOTOR CONTROL INT 1 18 ILIM/SHDN
VIBRATION CANCELLING AMPLIFIER + INT 2 17 NC
INT OUT 3 16 ISENSE B *R LIMIT
DESCRIPTION *
RAMP/PWM 4 15 B OUT
The SA02 amplifier is an 80 volt, 250kHz PWM amplifier. TOP
The full bridge output circuit provides 10 amps of continuous * +PWM 5 14 Vs
VIEW *
drive current for applications as diverse as aircraft audio and GND 6 13 A OUT
brush type motors. Clock output and input pins can be used for *R LIMIT
synchronization with other amplifiers or an externally gener- CLK IN 7 12 ISENSE A
ated clock. A separate integrator amplifier is also accessible *
CLK OUT 8 11 NC
and the integration may be varied for the application. Direct
access to the pwm input is provided for connection to digital NC 9 10 Vcc
motion control circuits. Protection circuits guard against ther- *
mal overloads as well as shorts to supply or ground. The Case tied to pin 6. Bypassing of supplies is required.
current limit is programmable with one or two external resistors Package is Apex DIP7. See Outline Dimensions/Packages
depending on the application. A shutdown input disables all in Apex data book.
output bridge drivers. The 18 pin DIP7 steel package is
If +PWM > RAMP/PWM then A OUT > B OUT
hermetically sealed. and ISENSE B > ISENSE A.
BLOCK DIAGRAM AND * See text.
TYPICAL APPLICATION +VS
CONNECTIONS 14
Vcc
AIRCRAFT THERMAL,
SHORT 10
AUDIO CIRCUIT
PROTECT. NC
+PWM B REG.
100 100 R 17
5 I
100K D
1000pF A OUT
G 5V
1000pF RAMP/PWM E 13
100
4
D B OUT
R
18K I 15
LOAD
V 5V
100pF
CLK OUT E
R
8 ILIM/SHDN R FILTER R SHDN
18
C FILTER 1K
OSC CLK/2
I SENSE B
CLK IN 16
7 I SENSE A
12
GND R LIMIT
NC 9
6
NC 11
INT OUT
3
+ INT
2.5V 2
INT
1
2.5V
SIGNAL
58
SA02 SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS SUPPLY VOLTAGE, Vcc to GND 15V

SUPPLY VOLTAGE, +VS to GND 80V
PWM 0 TO Vcc
CLK IN, INT VIN, ILIM/SHDN VIN 0 to +6V
SPECIFICATIONS
INTEGRATOR, CLOCK3
OFFSET VOLTAGE 2 mV
BIAS CURRENT 150 nA
OFFSET CURRENT 30 nA
COMMON MODE VOLTAGE RANGE 0 +3 V
COMMON MODE REJECTION, DC 80 dB
SLEW RATE 15 V/S
OPEN LOOP GAIN RL = 10K 94 dB
GAIN BANDWIDTH PRODUCT 4.5 MHz
CLOCK OUT RL 10K 500 kHz
CLOCK OUT, high level 4.7 5.3 V
CLOCK OUT, low level 0 .2 V
CLOCK IN, low level 0 .3 V
CLOCK IN, high level 2 5.6 V
OUTPUT
EFFICIENCY, 10A output VS = 80V 94 %
SWITCHING FREQUENCY 250 kHz
CURRENT, continuous 10 A
CURRENT, peak3 15 A
RDS(ON)3 .42
POWER SUPPLY
VOLTAGE, VCC Full temperature range 10 12 15 V
VOLTAGE, VS Full temperature range 16 80 V
CURRENT, VCC VCC = 12V 36 50 mA
CURRENT, VS Switching, No Load, VS = 60V 70 90 mA
INPUTS3
ILIM/SHDN, trip point 90 110 mV
PWM COMMON MODE VOLTAGE 1 Vcc 1.5 V
THERMAL4
RESISTANCE, junction to case Full temperature range 1.6 C/W
TEMPERATURE RANGE, case Meets full range specifications 25 85 C
NOTES: 1. 80W in each of the two active output transistors on at any one time.
3. Min max values guaranteed but not tested.
4. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation
to achieve high MTTF. For guidance, refer to the heatsink data sheet.
CAUTION
59
TYPICAL PERFORMANCE
GRAPHS SA02
POWER DERATING CLOCK LOADING CLOCK FREQUENCY OVER TEMP
INTERNAL POWER DISSIPATION, (W)
80 100 102.0
NORMALIZED FREQUENCY, (%)

101.5
99.5
60 101.0
99.0 100.5
40 100
98.5 99.5
20
98.0 99.0
EACH ACTIVE
OUTPUT TRANSISTOR F NOMINAL = 500kHz 98.5
0 97.5 98.0
0 25 50 75 100 125 100 1K 10K 100K 50 25 0 25 50 75 100 125
CASE TEMPERATURE, (C) CLOCK LOAD RESISTANCE, () CASE TEMPERATURE, (C)
REVERSE DIODE INTEGRATOR GAIN INTEGRATOR PHASE

10 100 0
8
FLYBACK CURRENT, Isd (A)
6
OPEN LOOP GAIN, A (dB)
OPEN LOOP PHASE, ()

5 80
4 45
3
60
2
40 90
1
8
20
6
5 135
4 0
3
20 180
0.6 0.8 1.0 1.2 1.4 1.6 1.8 100 1K 10K 100K 1M 10M 10 100 1K 10K 100K 1M 10M
SOURCE TO DRAIN DIODE VOLTAGE FREQUENCY, F (Hz) FREQUENCY, F (Hz)
NORMALIZED Vcc QUIESCENT CURRENT, (%)
CONTINUOUS OUTPUT DUTY CYCLE VS ANALOG INPUT Vcc QUIESCENT CURRENT

10 100 100
B OUTPUT
90
8 80
CONTINUOUS AMPS
DUTY CYCLE, (%)
80
6 60 70
60
4 40
50
2 20
40
A OUTPUT
0 0 30
25 50 75 100 125 150 1 2 3 4 0 50 100 150 200 250
CASE TEMPERATURE, (C) ANALOG INPUT, (V) SWITCHING FREQUENCY, F (kHz)
Vcc QUIESCENT CURRENT Vs QUIESCENT VS VOLTAGE Vs QUIESCENT VS FREQUENCY

NORMALIZED Vs QUIESCENT CURRENT, (%)
125 180 100

Vcc = 12V 90
F = 250kHz 160
125C 80
100 140 85C 70
NORMAL OPERATION 120 25C 60
75 100 55C 50
80 40
30
50 60
20
40 10
SHUTDOWN OPERATION
25 20 0
50 25 0 25 50 75 100 125 10 20 30 40 50 60 70 80 0 50 100 150 200 250
CASE TEMPERATURE, TC (C) Vs, (V) SWITCHING FREQUENCY, F (kHz)
60
OPERATING
SA02 CONSIDERATIONS
TOTAL VOLTAGE DROP NOISE FILTERING

6
CASE Switching noise can enter the SA02 through the INT OUT to
70C
TOTAL VOLTAGE DROP, (V)
5 TEMPERATURE +PWM connection. A wise precaution is to low pass filter this

connection. Adjust the pass band of the filter to 10 times the
4
125C bandwidth required by the application. Keep the resistor value
100C to 100 ohms or less since this resistor becomes part of the
85C hysteresis circuit on the pwm comparator.
3
2 PCB LAYOUT
25C The designer needs to appreciate that the SA02 combines
1 25C in one circuit both high speed high power switching and low
55C level analog signals. Certain layout rules of thumb must be
0 considered when a circuit board layout is designed using the
0 2 4 6 8 10 SA02:
OUTPUT, I (A)
1. Bypassing of the power supplies is critical. Capacitors must
be connected directly to the power supply pins with very
GENERAL short lead lengths (well under 1 inch). Ceramic chip capaci-
Helpful information about power supplies, heatsinking and tors are best.
mounting can be found in the General Operating Consider-
ations section of the Apex data book. For information on the 2. Make all ground connections with a star pattern at pin 6.
package outline, heatsinks, and mounting hardware see the 3. Beware of capacitive coupling between output connections
Package Outlines and Accessories section of the data book.
and signal inputs through the parasitic capacitance be-
Also see Application Note 30 on PWM Basics.
tween layers in multilayer PCB designs.
4. Do not run small signal traces between the pins of the output
CLOCK CIRCUIT AND RAMP GENERATOR section (pins 11-17).
The clock frequency is internally set to a frequency of
5. Do not allow high currents to flow into the ground plane.
approximately 500 kHZ. The CLK OUT pin will normally be tied
to the CLK IN pin. The clock is divided by two and applied to an 6. Separate switching and analog grounds and connect the
RC network which produces a ramp signal at the RAMP pin. An two only at pin 6 as part of the star pattern.
external clock signal can be applied to the CLK IN pin for
synchronization purposes. If a clock frequency lower than INTEGRATOR
500kHZ is chosen an external capacitor must be tied to the
The integrator provides the inverted signal for negative
RAMP pin. This capacitor, which parallels an internal capaci-
feedback and also the open loop gain for the overall application
tor, must be selected so that the ramp oscillates 2.5 volts p-p
circuit accuracy. Recommended value of CINT is 10 pF for
with the lower peak 1.25 volts above ground.
stability. However, poles and zeroes can be added to the circuit
for overall loop stability as required.
BYPASSING
Adequate bypassing of the power supplies is required for CURRENT LIMIT
proper operation. Failure to do so can cause erratic and low
There are two load current sensing pins, I SENSE A and I
efficiency operation as well as excessive ringing at the outputs.
SENSE B. The two pins can be shorted in the voltage mode
The Vs supply should be bypassed with at least a 1F ceramic
connection but both must be used in the current mode connec-
capacitor in parallel with another low ESR capacitor of at least
tion (see figures A and B). It is recommended that RLIMIT
10F per amp of output current. Capacitor types rated for
resistors be non-inductive. Load current flows in the I SENSE
switching applications are the only types that should be consid-
pins. To avoid errors due to lead lengths connect the I LIMIT/
ered. The bypass capacitors must be physically connected
SHDN pin directly to the RLIMIT resistors (through the filter
directly to the power supply pins. Even one inch of lead length
network and shutdown divider resistor) and connect the RLIMIT
will cause excessive ringing at the outputs. This is due to the
resistors directly to the GND pin.
very fast switching times and the inductance of the lead
connection. The bypassing requirements of the Vcc supply are
less stringent, but still necessary. A .1F to .47F ceramic
capacitor connected directly to the Vcc pin will suffice.
61
OPERATING
CONSIDERATIONS SA02
I SENSE A SHUTDOWN
The shutdown circuitry makes use of the internal current
R LIMIT limiting circuitry. The two functions may be externally com-
I SENSE B
bined in voltage and current modes as shown below in Figures
1K
A and B. The RLIMIT resistors will normally be very low values
SHUTDOWN
I LIMIT/SHDN R
FILTER SIGNAL and can be considered zero for this application. In Figure A,
RSHDN and 1K form a voltage divider for the shutdown signal.
R SHDN
C FILTER After a suitable noise filter is designed for the current limit,
adjust the value of RSHDN to give a minimum 110 mV of
shutdown signal at the I LIMIT/SHDN pin when the shutdown
FIGURE A. CURRENT LIMIT WITH
SHUTDOWN VOLTAGE MODE. signal is high. Note that CFILTER will filter both the current limit
noise spikes and the shutdown signal. Shutdown and current
I SENSE A limit operate on each cycle of the internal switching rate. As
1K long as the shutdown signal is high the output will be disabled.
R LIMIT PROTECTION CIRCUITS

I SENSE B Circuits monitor the temperature and load on each of the
1K
bridge output transistors. On each cycle should any fault
R LIMIT
condition be detected all output transistors in the bridge are
shut off. Faults protected against are: shorts across the out-
puts, shorts to ground, and over temperature conditions.
I LIMIT/SHDN R SHUTDOWN
FILTER SIGNAL Should any of these faults be detected, the output transistors
will be latched off. The fault must be removed and VCC power
R SHDN
C FILTER recycled to restart the SA02. In addition there is a built in dead
time during which all the output transistors are off. The dead
FIGURE B. CURRENT LIMIT WITH time removes the possibility of a momentary conduction path
SHUTDOWN CURRENT MODE. through the upper and lower transistors of each half bridge
during the switching interval. Noise or flyback may be ob-
Switching noise spikes will invariably be found at the I served at the outputs during this time due to the high imped-
SENSE pins. The noise spikes could trip the current limit ance of the outputs in the off state. This will vary with the nature
threshold which is only 100 mV. RFILTER and CFILTER should be of the load.
adjusted so as to reduce the switching noise well below 100
mV to prevent false current limiting. The sum of the DC level
plus the noise peak will determine the current limiting value. As
in most switching circuits it may be difficult to determine the
true noise amplitude without careful attention to grounding of
the oscilloscope probe. Use the shortest possible ground lead
for the probe and connect exactly at the GND terminal of the
amplifier. Suggested starting values are CFILTER = .001uF,
RFILTER = 5k .
The required value of RLIMIT in voltage mode may be calcu-
lated by:
RLIMIT = .1 V / ILIMIT
where RLIMIT is the required resistor value, and ILIMIT is the
maximum desired current. In current mode the required value
of each RLIMIT is 2 times this value since the sense voltage is
divided down by 2 (see Figure B). If RSHDN is used it will further
divide down the sense voltage. The shutdown divider network
will also have an effect on the filtering circuit.
however, ROAD is TUCSON,
no responsibility assumed forARIZONA 85741 or
possible inaccuracies omissions.
USA APPLICATIONS HOTLINE:
without notice.
SA02U REV. E DECEMBER 1998 1998 Apex Microtechnology Corp.
62
NOTES:
63
EK02
components except the switching amplifier. 3. Apply TW02 thermal washer to the bottom of the SA02.
The schematic is shown in Figure 2. Note that all of the compo- 4. Use #14 sleeving to insulate and align at least 2 opposite pins of
nents shown on the schematic will probably not be used for any the amplifier.
single circuit. Some components will simply be omitted, while others 5. Mount amplifier to heatsink using #6 screws and nuts. Torque the
require installation of a jumper to complete the signal path. part to the specified 8 to 10 in-lbs (.9 to 1.13 N*M). Do not over
Only components unique to the EK02 are provided in this kit. torque.
Hardware similar to that shown in figure 1 must be obtained locally. 6. Install components as needed. External connections may be
soldered directly or standard banana jacks may be soldered to
PARTS LIST these pads.
7. Insert amplifier pins into cage jacks and fasten board to heatsink.
Part # Description Quantity
HS19 Heatsink 1
MS02 PC mount Cage Jacks 3 Bags/8 each
EVAL08 PC Board 1
TW02
OX7R105KWN
Thermal Washer
1F Capacitor
1 Box/10 each
6
C
1825B105K201N/Novacap
HK03 Clamp 1 Bag/2 each

* Always use the heatsink included in this kit with TW02 washer.
Cage Jack
Spacer Grommet
TW02 thermal washer
Heatsink

FIGURE 1. HK03 CLAMP
64
EVALUATION KIT
A block diagram of the SA02

is shown in Figure 2 along with
pcb connections of all the com-
monly used external compo-
nents. Your application circuit
will not use all of the compo-
nents. Add those components
required by your circuit. You
may have to jumper some com-
* ponents to make the desired
electrical connections. J2 is an
optional way to connect the clock
circuit. Power supply bypass-
ing is particularly important and
that is why high quality ceramic
chip capacitors are supplied with
the kit. In addition you may
need to add a 10-50 uF or larger
capacitor on the +Vs pin. This
additional capacitor needs to be
rated for switching operation.
Note that the signal ground and
power ground are separated and
tie together only at the ground
pin (6). A breadboarding area is
supplied which can accomodate
1 or 2 IC amplifiers and associ-
ated components. The large
terminal pads can be used to
solder wire connections or
bannana jacks.
*
*
* Input protection, 5V zener diode.
65
EVALUATION KIT
FIGURE 3. FUNCTIONAL TEST CIRCUIT
The schematic of Figure 3 can be

used to verify the functionality of your
amplifier and help you gain a familiarity
with proper operation. At either A Out
or B Out, with respect to ground, you
should observe a square wave approxi-
mately 30 V in amplitude with a fixed
frequency and duty cycle that varies
from approximately 0 to 100% at a rate
of 1 Hz. The current limit is set to 2
amps.
66
EK02
FIGURE 4. PCB COMPONENT SIDE
omissions. HOTLINE:
change 546-2739
without notice.
67
SA03
FEATURES
WIDE SUPPLY RANGE16-100V SA03
30A CONTINUOUS TO 60 C CASE
3 PROTECTION CIRCUITS USA
ANALOG OR DIGITAL INPUTS TE9493
11
BeO
SYNCHRONIZED OR EXTERNAL OSCILLATOR

FLEXIBLE FREQUENCY CONTROL
APPLICATIONS
MOTORS TO 4HP
REACTIVE LOADS
LOW FREQUENCY SONAR
LARGE PIEZO ELEMENTS
OFF-LINE DRIVERS
C-D WELD CONTROLLER
DESCRIPTION ISENSE A
The SA03 is a pulse width amplifier that can supply 3000W CLK IN 1 12
A OUT
to the load. An internal 45kHz oscillator requires no external CLK OUT 2 11
components. The clock input stage divides the oscillator +PWM 10
* VCC
3
frequency by two, which provides the basic switching of 22.5 TOP
4 VIEW 9 *
kHz. External oscillators may also be used to lower the PWM/RAMP
switching frequency or to synchronize multiple amplifiers. 5 8 +VS
Current sensing is provided for each half of the bridge giving GND 6 7 B OUT
amplitude and direction data. A shutdown input turns off all ILIM/SHDN I SENSE B
four drivers of the H bridge output. A high side current limit and
the programmable low side current limit protect the amplifier
from shorts to supply or ground in addition to load shorts. The
H bridge output MOSFETs are protected from thermal over- Case tied to pin 5. Allow no current in case. Bypassing of supplies
loads by directly sensing the temperature of the die. The 12- is required. Package is Apex MO-127 (STD). See Outline
pin hermetic MO-127 power package occupies only 3 square Dimensions/Packages in Apex data book.
inches of board space.
If +PWM > RAMP/PWM then A OUT > B OUT.
BLOCK DIAGRAM AND TYPICAL APPLICATION * See text.
Vcc
10 CURRENT 9
LIMIT +VS
+PWM
3
PWM
4
PWM/RAMP B OUT
470pF
OUTPUT 8
56K DRIVERS MOTOR
11
CLK OUT
A OUT
2 OSC 2 1K
I SENSE A
SHUTDOWN 12
CLK IN 5K RSENSE
CONTROL 6
1 .01F
ILIM/SHDN 1K
5
7
CONTROL GND
SIGNAL I SENSE B RSENSE
3/7V
5V
5V
68
SA03 SPECIFICATIONS

SUPPLY VOLTAGE, VCC 16V
POWER DISSIPATION, internal 300W
INPUT VOLTAGE, +PWM 0 to +11V
INPUT VOLTAGE, PWM 0 to +11V
SPECIFICATIONS INPUT VOLTAGE, ILIM 0 to +10V
CLOCK (CLK)
CLK OUT, high level4 IOUT 1mA 4.8 5.3 V
CLK OUT, low level4 IOUT 1mA 0 .4 V
FREQUENCY 44 45 46 kHz
RAMP, center voltage 5 V
RAMP, P-P voltage 4 V
CLK IN, low level4 0 .9 V
CLK IN, high level4 3.7 5.4 V
OUTPUT
TOTAL RON .16
SWITCHING FREQUENCY OSC in 2 22 22.5 23 kHz
CURRENT, continuous4 60C case 30 A
CURRENT, peak4 40 A
POWER SUPPLY
VOLTAGE, VS Full temperature range 165 60 100 V
CURRENT, VCC IOUT = 0 80 mA
CURRENT, VCC, shutdown 50 mA
CURRENT, VS No Load 50 mA
ILIM/SHUTDOWN
TRIP POINT 90 110 mV
THERMAL3
RESISTANCE, junction to case Full temperature range, for each die .83 C/W
NOTES: 1. Each of the two active output transistors can dissipate 150W.
2. Unless otherwise noted: TC = 25C, VS, VCC at typical specification.
3. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power
dissipation to achieve high MTTF. For guidance, refer to the heatsink data sheet.
5. If 100% duty cycle is not required VS(MIN) = 0V.
CAUTION
The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush,
machine, or subject to temperatures in excess of 850C to avoid generating toxic fumes.
69
TYPICAL PERFORMANCE
GRAPHS SA03

150 100 102.0

101.5
125
99
101.0
100
98 100.5
75 100
97 99.5
50
99.0
25 96
EACH ACTIVE
OUTPUT TRANSISTOR 98.5
F NOMINAL = 45kHz
0 95 98.0
0 25 50 75 100 125 10K 100K 1M 50 25 0 25 50 75 100 125
REVERSE DIODE TOTAL VOLTAGE DROP

3 10
2 CASE TEMPERATURE
60C
8
10 85C
9
7 100C
6 6
5
125C
4
3
4
2
1 2
8
25C
7
25C
6 55C
5 0
0.6 0.8 1.0 1.2 1.4 1.6 0 5 10 15 20 25 30
SOURCE TO DRAIN DIODE VOLTAGE OUTPUT CURRENT, (A)

30 100 100
A OUT
28
80 95
CONTINUOUS AMPS
DUTY CYCLE, (%)
26
24 60 90
22
40 85
20
20 80
18
B OUT
16 0 75
25 50 75 100 125 150 3 4 5 6 7 5 10 15 20 25

115 180 100

Vcc = 15V Vs = 60V, NO LOAD
110 F = 22.5 kHz 160
90
140
105
NORMAL 80
120
100 OPERATION 55C
100 70
95 125C
80
60
90 60
SHUTDOWN 50
85 OPERATION 40
80 20 40
50 25 0 25 50 75 100 125 0 20 40 60 80 100 5 10 15 20 25
CASE TEMPERATURE, (C) Vs, (V) SWITCHING FREQUENCY, F (kHz)
70
OPERATING
CONSIDERATIONS SA03
GENERAL I SENSE A noise spikes could trip the cur-

1K rent limit threshold which is only
Helpful information about power supplies, heatsinking and
mounting can be found in the General Operating Consider- 100 mV. RFILTER and C FILTER
ations section of the Apex data book. For information on the R LIMIT should be adjusted so as to
package outline, heatsinks, and mounting hardware see the I SENSE B reduce the switching noise well
Package Outlines and Accessories section of the data below 100 mV to prevent false
book. Also see Application Note 30 on PWM Basics. current limiting. The sum of the
R LIMIT DC level plus the noise peak
will determine the
CLOCK CIRCUIT AND RAMP GENERATOR current limiting
The clock frequency is internally set to a frequency of FILTER SIGNAL value. As in most
approximately 45kHz. The CLK OUT pin will normally be tied switching circuits
R SHDN
to the CLK IN pin. The clock is divided by two and applied to an C FILTER
it may be difficult
RC network which produces a ramp signal at the PWM/ to determine the
RAMP pin. An external clock signal can be applied to the CLK true noise ampli-
FIGURE B. CURRENT LIMIT WITH
IN pin for synchronization purposes. If a clock frequency lower SHUTDOWN CURRENT MODE. tude without
than 45kHz is chosen an external capacitor must be tied to the careful attention
PWM/RAMP pin. This capacitor, which parallels an internal to grounding of the oscilloscope probe. Use the shortest
capacitor, must be selected so that the ramp oscillates 4 volts possible ground lead for the probe and connect exactly at the
p-p with the lower peak 3 volts above ground. GND terminal of the amplifier. Suggested starting values are
CFILTER = .01uF, RFILTER = 5k .
PWM INPUTS
The full bridge driver may be accessed via the pwm input The required value of RLIMIT in voltage mode may be calcu-
comparator. When +PWM > -PWM then A OUT > B OUT. A lated by:
motion control processor which generates the pwm signal can RLIMIT = .1 V / ILIMIT
drive these pins with signals referenced to GND. where RLIMIT is the required resistor value, and ILIMIT is the
PROTECTION CIRCUITS of each RLIMIT is 2 times this value since the sense voltage is
In addition to the externally programmable current limit there divided down by 2 (see Figure B). If RSHDN is used it will further
is also a fixed internal current limit which senses only the high divide down the sense voltage. The shutdown divider network
side current. It is nominally set to 140% of the continuous rated will also have an effect on the filtering circuit.
output current. Should either of the outputs be shorted to
ground the high side current limit will latch off the output BYPASSING
transistors. Also, the temperature of the output transistors is Adequate bypassing of the power supplies is required for
continually monitored. Should a fault condition occur which proper operation. Failure to do so can cause erratic and low
raises the temperature of the output transistors to 165C the efficiency operation as well as excessive ringing at the outputs.
thermal protection circuit will activate and also latch off the The Vs supply should be bypassed with at least a 1F ceramic
output transistors. In either case, it will be necessary to remove capacitor in parallel with another low ESR capacitor of at least
the fault condition and recycle power to VCC to restart the circuit. 10F per amp of output current. Capacitor types rated for
CURRENT LIMIT ered. The bypass capacitors must be physically connected
There are two load current sensing pins, I SENSE A and I directly to the power supply pins. Even one inch of lead length
SENSE B. The two pins can be shorted in the voltage mode will cause excessive ringing at the outputs. This is due to the
connection but both must be used in the current mode connec- very fast switching times and the inductance of the lead
tion (see figures A and B). It is recommended that RLIMIT connection. The bypassing requirements of the Vcc supply are
resistors be non-inductive. Load current flows in the I SENSE less stringent, but still necessary. A .1F to .47F ceramic
pins. To avoid errors due to lead lengths connect the I LIMIT/ capacitor connected directly to the Vcc pin will suffice.
SHDN pin directly to
the R LIMIT resistors I SENSE A STARTUP CONDITIONS
(through the filter net- The high side of the all N channel output bridge circuit is
work and shutdown di- R LIMIT driven by bootstrap circuit and charge pump arrangement. In
I SENSE B
vider resistor) and con- order for the circuit to produce a 100% duty cycle indefinitely
nect the RLIMIT resis- the low side of each half bridge circuit must have previously
tors directly to the GND I LIMIT/SHDN 1K SHUTDOWN
R FILTER
been in the ON condition. This means, in turn, that if the input
pin. SIGNAL
signal to the SA03 at startup is demanding a 100% duty cycle,
Switching noise R SHDN the output may not follow the command and may be in a tri-
C FILTER
spikes will invariably state condition. The ramp signal must cross the input signal at
be found at the I some point to correctly determine the output state. After the
SENSE pins. The FIGURE A. CURRENT LIMIT WITH ramp crosses the input signal level one time, the output state
SHUTDOWN VOLTAGE MODE. will be correct thereafter.
sheet has been carefully checked TELEPHONE
and is believed to be reliable,(520) 690-8600
however, FAXis(520)
for possible inaccuracies
ORDERS (520) 690-8601
SA03U REV. D DECEMBER 1998 1998 Apex Microtechnology Corp.
71
EVALUATION KIT FOR SA03/SA04/SA23/SA24 PIN-OUT
EK03
components except the switching amplifier. 3. Apply TW05 thermal washer to the bottom of the amplifier.
HS18 Heatsink 1
EVAL09 PC Board 1
TW05 Thermal Washer 1 Box/10 each
OX7R105KWN 1F Cap 1825B105K201N, 6
Novacap

Cage Jack
Spacer Grommet
TW05 thermal washer
Heatsink
FIGURE 1.
72
EVALUATION KIT
A block diagram of the amplifier is shown in

Figure 2 along with pcb connections of all the
commonly used external components. Your
application circuit will not use all of the compo-
nents. Add those components required by your
circuit. You may have to jumper some compo-
nents to make the desired electrical connec-
tions. J1 is an optional way to connect the clock
circuit. Power supply bypassing is particularly
important and that is why high quality ceramic
chip capacitors are supplied with the kit. In
addition you may need to add a 10-50 uF or
larger capacitor on the +Vs pin. This additional
capacitor needs to be rated for switching opera-
tion. Note that the signal ground and power
ground are separated and tie together only at
the ground pin (5). A breadboarding area is
supplied which can accomodate 1 or 2 IC
amplifiers and associated components. The
large terminal pads can be used to solder wire
connections or bannana jacks.
SA03 SA04/
SA23 SA24
* *
73
EVALUATION KIT
The schematic of Figure 3 can be used to

verify the functionality of your amplifier and help
you gain a familiarity with proper operation. At
either A Out or B Out, with respect to ground,
you should observe a square wave approxi-
mately 30 V in amplitude with a fixed frequency
and duty cycle that varies from approximately 0
to 100% at a rate of 1 Hz. The current limit is set
to 2 amps.
SA03 SA04/
SA23 SA24
74
EK03
however, FAXis(520)
ORDERS (520) 690-8601
EK03U REV. D APRIL 1998 1998 Apex Microtechnology Corp.
75
SA04
FEATURES

TE9493 BeO
11
ANALOG OR DIGITAL INPUTS
APPLICATIONS
MOTORS TO 4HP
REACTIVE LOADS
LOW FREQUENCY SONAR
LARGE PIEZO ELEMENTS EXTERNAL CONNECTIONS
OFF-LINE DRIVERS
C-D WELD CONTROLLER
DESCRIPTION ISENSE A
The SA04 is a pulse width amplifier that can supply 4000W CLK IN 1 12
A OUT
to the load. An internal 45kHz oscillator requires no external CLK OUT 2 11
components. The clock input stage divides the oscillator +PWM 3 10
* VCC
frequency by two, which provides the basic switching of 22.5 TOP
4 VIEW 9 *
kHz. External oscillators may also be used to lower the PWM/RAMP
switching frequency or to synchronize multiple amplifiers. 5 8 +VS
Current sensing is provided for each half of the bridge giving GND 6 7 B OUT
amplitude and direction data. A shutdown input turns off all ILIM/SHDN I SENSE B
four drivers of the H bridge output. A high side current limit and
the programmable low side current limit protect the amplifier
from shorts to supply or ground in addition to load shorts. The
H bridge output MOSFETs are protected from thermal over- Case tied to pin 5. Allow no current in case. Bypassing of supplies
loads by directly sensing the temperature of the die. The 12- is required. Package is Apex MO-127 (STD). See Outline
pin hermetic MO-127 power package occupies only 3 square Dimensions/Packages in Apex data book.
inches of board space. If +PWM > RAMP/PWM then A OUT > B OUT.
BLOCK DIAGRAM AND TYPICAL APPLICATION *See text.
TORQUE MOTOR DRIVER
Vcc
10 CURRENT 9
LIMIT +VS
+PWM
3
PWM
4
PWM/RAMP B OUT
470pF
OUTPUT 8
56K DRIVERS MOTOR
11
CLK OUT
A OUT
2 OSC 2 1K
I SENSE A
SHUTDOWN 12
CLK IN 5K RSENSE
CONTROL 6
1 .01F
ILIM/SHDN 1K
5
7
CONTROL GND
3/7V
5V
5V
76
SA04 SPECIFICATIONS

INPUT VOLTAGE, ILIM 0 to +10V
SPECIFICATIONS
CLOCK (CLK)
FREQUENCY 44.10 45.00 46.90 kHz
OUTPUT
TOTAL RON .22
SWITCHING FREQUENCY OSC in 2 22.05 22.50 22.95 kHz
CURRENT, peak4 30 A
POWER SUPPLY
ILIM/SHUTDOWN
THERMAL3
CAUTION
77
TYPICAL PERFORMANCE
GRAPHS SA04

150 100 102.0

101.5
125
99
101.0
100
98 100.5
75 100
97 99.5
50
99.0
25 96
EACH ACTIVE
OUTPUT TRANSISTOR 98.5
F NOMINAL = 45kHz
0 95 98.0
0 25 50 75 100 125 10K 100K 1M 50 25 0 25 50 75 100 125

2 10
CASE TEMPERATURE
10
8 8 85C
7
6
5
4 100C
3 6
2 125C
4
1
8
7
6
5 2
4 60C
3 25C
2 0 55C 25C
0.6 0.8 1.0 1.2 1.4 1.6 0 5 10 15 20

20 100 100
A OUT
80 95
CONTINUOUS AMPS
18
DUTY CYCLE, (%)
60 90
16
40 85
14
20 80
B OUT
12 0 75
25 50 75 100 125 150 3 4 5 6 7 5 10 15 20 25

115 140 100

110 F = 22.5 kHz 120
80
105
NORMAL 100
100 OPERATION
80 60
95
60
90
40
SHUTDOWN 40
85 OPERATION
80 20 20
50 25 0 25 50 75 100 125 0 25 50 75 100 125 150 175 200 5 10 15 20 25
78
OPERATING
CONSIDERATIONS SA04

will determine the
R SHDN
it may be difficult
PWM INPUTS
I SENSE B
R FILTER
pin. SIGNAL
C FILTER
This data
APEX sheet has been carefully CORPORATION
MICROTECHNOLOGY checked and is believed to be reliable,(520)
TELEPHONE however, no responsibility
690-8600 FAXis(520)
assumed for possibleinaccuracies
888-3329 or omissions.
ORDERS (520) All specifications
690-8601 EMAILare subject to change without notice.
prodlit@apexmicrotech.com
SA04U REV. C DECEMBER 1998 1998 Apex Microtechnology Corp.
79
SA06
FEATURES
ANALOG OR DIGITAL INPUTS TE9493
11
BeO

APPLICATIONS
MOTORS
REACTIVE LOADS
LOW FREQUENCY SONAR
LARGE PIEZO ELEMENTS EXTERNAL CONNECTIONS
OFF-LINE DRIVERS
C-D WELD CONTROLLER
ISENSE A
DESCRIPTION CLK IN 1 12
A OUT
The SA06 is a pulse width modulation amplifier that can CLK OUT 2 11
supply 5000W to the load. An internal oscillator requires no +PWM * VCC
3 10
external components. The clock input stage divides the oscil- TOP
lator frequency by two, which provides the switching fre- 4 VIEW 9 *
PWM/RAMP
quency of 22.5 kHz. External oscillators may also be used to 5 8 +VS
lower the switching frequency or to synchronize multiple GND 6 7 B OUT
amplifiers. Current sensing is provided for each half of the
ILIM/SHDN I SENSE B
bridge giving amplitude and direction data. A shutdown input
turns off all four drivers of the H bridge output. A high side
current limit and the programmable low side current limit
protect the amplifier from shorts to supply or ground in addition Case tied to pin 5. Allow no current in case. Bypassing of supplies
to load shorts. The H bridge output MOSFETs are protected is required. Package is Apex MO-127/40S. See Outline
from thermal overloads by directly sensing the temperature of Dimensions/Packages in Apex data book.
the die. The 12-pin hermetic MO-127/40S power package
If +PWM > RAMP/PWM then A OUT > B OUT.
occupies only 3 square inches of board space.
*See text.
BLOCK DIAGRAM AND TYPICAL APPLICATION
MOTOR TORQUE CONTROL Vcc
10 CURRENT 9
LIMIT
+PWM +VS
3
PWM
4
PWM/RAMP 100pF B OUT
OUTPUT 8
45K DRIVERS MOTOR
11
CLK OUT
A OUT
2 OSC 2 1K
I SENSE A
SHUTDOWN 12
CLK IN 5K RSENSE
CONTROL 6
1 .01F
ILIM/SHDN 1K
5
7
CONTROL GND
2.5 / 7.5V
5V
5V
80
SA06 SPECIFICATIONS

SPECIFICATIONS
CLOCK (CLK)
FREQUENCY 44.10 45.00 46.90 kHz
OUTPUT
TOTAL RON .95
CURRENT, peak4 15 A
POWER SUPPLY
ILIM/SHUTDOWN
THERMAL3
CAUTION
81
TYPICAL PERFORMANCE
GRAPHS SA06

150 100 102.0

101.5
125
99
101.0
100
98 100.5
75 100
97 99.5
50
96 99.0
25 EACH ACTIVE
0 95 98.0
0 25 50 75 100 125 10K 100K 1M 50 25 0 25 50 75 100 125

10 20
CASE TEMPERATURE 75C
85C
15
100C
10 125C
1 5
25C
25C
55C
0
0.6 0.8 1.0 1.2 1.4 0 2 4 6 8 10

10 100 100
A OUT
9 80 95
CONTINUOUS AMPS
DUTY CYCLE, (%)
8 60 90
7 40 85
6 20 80
B OUT
5 0 75
25 50 75 100 125 3 4 5 6 7 5 10 15 20 25

115 140 100

110 F = 22.5 kHz
120 80
105
NORMAL
100 OPERATION
100 60
95
90 80 40
SHUTDOWN
85 OPERATION
80 60 20
50 25 0 25 50 75 100 125 0 100 200 300 400 500 5 10 15 20 25
82
OPERATING
CONSIDERATIONS SA06

will determine the
R SHDN
it may be difficult
PWM INPUTS
I SENSE B
R FILTER
pin. SIGNAL
C FILTER
however, FAXis(520)
ORDERS (520) 690-8601
SA06U REV. D DECEMBER 1998 1998 Apex Microtechnology Corp.
83
EK05
components except the switching amplifier. 3. Apply TW05 thermal washer to the bottom of the SA06.
HS18 Heatsink 1
EVAL10 PC Board 1
TW05
OX7R105KTN
Thermal Washer
1F Cap 3530B105K501N,
1 Box/10 each
1
C
Novacap
OX7R105KWN 1F Cap 1825B105K201N, 1
Novacap

* Check for oscillations. Cage Jack
Spacer Grommet
TW05 thermal washer
Heatsink
FIGURE 1.
84
EK05 EVALUATION KIT
FOR SA06 PIN-OUT
A block diagram of the SA06 is shown in

SA06
*
* *
85
EVALUATION KIT

either A Out or B Out, with respect to ground,
you should observe a square wave approxi-
mately 30 V in amplitude with a fixed frequency
and duty cycle that varies from approximately 0
to 100% at a rate of 1 Hz. The current limit is set
to 2 amps.
SA06
86
EK05
no responsibility assumed for ARIZONA 85741 or
without notice.
87
SA07
FEATURES
500kHz SWITCHING SA
07
FULL BRIDGE OUTPUT 5-40V (80V P-P) Q

93
17
5A OUTPUT MB

9
3 0 USA 2 4
6 0 0
O
1 IN2 FOOTPRINT Be
FAULT PROTECTION
SHUTDOWN CONTROL
SYNCHRONIZABLE CLOCK
HERMETIC PACKAGE
APPLICATIONS
HIGH FIDELITY AUDIO AMPLIFIER
VIBRATION CANCELLING AMPLIFIER
5V OUT 1 18 CLK OUT*
DESCRIPTION INT 2 17 CLK IN
+INT 3 16 Ilim/SHDN
The SA07 amplifier is a 40 volt, 500kHz PWM amplifier. The
Isense B
full bridge output circuit provides 5 amps of continuous drive INT OUT* 4 15
current for applications as diverse as high fidelity audio and B OUT Rlimit*
+PWM 5 14
brush type motors. Clock output and input pins can be used for RAMP/PWM 6 13
+Vs
synchronization with other amplifiers or an externally gener- *
GND 7 12 A OUT
ated clock. An integrator amplifier is provided. Direct access Isense A
to the pwm input is provided for connection to digital motion NC 8 11
control circuits. Protection circuits guard against thermal over- Vcc Rlimit*
NC 9 10
loads as well as shorts to supply or ground. The current limit *
is programmable with one or two external resistors depending
on the application. A shutdown input disables all output bridge
drivers. The 18 pin steel package is hermetically sealed. Case tied to Pin 7. Allow no current in case. Bypassing of supplies is
required. Package is Apex DIP6. See Outline Dimensions/Packages. If
+PWM > RAMP then A OUT > B OUT.
BLOCK DIAGRAM AND
* See text.
TYPICAL APPLICATION
CONNECTIONS THERMAL,
5V OUT
1
HIGH FIDELITY SHORT
CIRCUIT
PROTECT.
+VS
13
AUDIO +PWM
Vcc
5
10
6
B REG.
RAMP/PWM 18K R
I
100pF D A OUT
CLK OUT G 5V
E 12
18
D B OUT
R
I 14 LOAD
OSC CLK/2
V 5V
E
R
CLK IN ILIM/SHDN R FILTER R SHDN
17 16
C FILTER 1K
GND I SENSE A
7
11
SA07
INT OUT
15
4
I SENSE B R LIMIT
INT +
3
INT
2
SIGNAL
88
SA07 SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS SUPPLY VOLTAGE, +VS to GND, 10mS surge 60V
SUPPLY VOLTAGE, VCC to GND 16V
OUTPUT CURRENT, peak 7.5A
INPUTS .4/+5.4V
SPECIFICATIONS
ERROR AMP, CLOCK REF3

OFFSET VOLTAGE 10 mV
BIAS CURRENT 50 pA
OFFSET CURRENT 30 pA
COMMON MODE VOLTAGE RANGE 0 3 V
COMMON MODE REJECTION, DC 70 dB
SLEW RATE 12 V/S
OPEN LOOP GAIN 100 dB
GAIN BANDWIDTH PRODUCT 10 MHz
CLOCK OUT .98 1 1.02 MHz
CLOCK OUT, high level 4.7 5.3 V
CLOCK OUT, low level 0 .2 V
5V OUT LOAD 5mA 4.988 5 5.012 V
OUTPUT
SWITCHING FREQUENCY 500 kHz
CURRENT, peak3 100 ms, 10% duty cycle 7 A
RDS(ON)3 .55
POWER SUPPLY
VOLTAGE, VS Full temperature range 5 40 V
CURRENT, VCC Switching 50 mA
CURRENT, VS Switching, No Load 90 mA
INPUTS3
ILIM/SHDN, trip point 90 110 mV
PWM, +PWM, low level 0 .8 V
PWM, +PWM, high level 2.7 Vcc V
CLOCK IN, low level 0 .3 V
CLOCK IN, high level 3 5.6 V
THERMAL4
RESISTANCE, junction to case Full temperature range 3.5 C/W
TEMPERATURE RANGE, case Meets full range specifications 25 85 C
NOTES: 1. 40W in each of the two active output transistors on at any one time.
3. Min max values guaranteed but not tested.
CAUTION
89
OPERATING
CONSIDERATIONS SA07
40 100 102.0

101.5
99.5
30 101.0
99.0 100.5
20 100
98.5 99.5
10
98.0 99.0
EACH ACTIVE
OUTPUT TRANSISTOR F NOMINAL = 1M 98.5
0 97.5 98.0
0 25 50 75 100 125 100 1K 10K 50 25 0 25 50 75 100 125
REVERSE DIODE INTEGRATOR GAIN INTEGRATOR PHASE

5 100 0
4
3
OPEN LOOP PHASE, ()

80
2 45
60
1.0
40 90
5
4
20
3
135
2 0
20 180
0.6 1.0 1.4 1.8 2.2 2.4 100 1K 10K 100K 1M 10M 10 100 1K 10K 100K 1M 10M
SOURCE TO DRAIN DIODE VOLTAGE FREQUENCY, F (Hz) FREQUENCY, F (Hz)

5 100 100
B OUTPUT
80 90
4
CONTINUOUS AMPS
DUTY CYCLE, (%)
80
3 60
70
2 40
60
1 20
50
A OUTPUT
0 0 40
25 50 75 100 125 150 1 2 3 4 0 100 200 300 400 500

125 120 100

Vcc = 12V 90
F = 500kHz 125C
100 80
100 85C
70
NORMAL OPERATION
80 60
25C
75 50
60 40
55C
30
50 40 20
10
SHUTDOWN OPERATION
25 20 0
50 25 0 25 50 75 100 125 10 15 20 25 30 35 40 0 100 200 300 400 500
CASE TEMPERATURE, TC (C) Vs, (V) SWITCHING FREQUENCY, F (kHz)
90
OPERATING
SA07 CONSIDERATIONS
TOTAL VOLTAGE DROP NOISE FILTERING

6
Switching noise can enter the SA07 through the INT OUT to
5 +PWM connection. A wise precaution is to low pass filter this

125C connection. Adjust the pass band of the filter to 10 times the
4 bandwidth required by the application. Keep the resistor value
100C to 100 ohms or less since this resistor becomes part of the
85C hysteresis circuit on the pwm comparator.
3
2 PCB LAYOUT
The designer needs to appreciate that the SA07 combines
1 in one circuit both high speed high power switching and low
55C 25C 25C level analog signals. Certain layout rules of thumb must be
0 considered when a circuit board layout is designed using the
0 1 2 3 4 5 SA07:
OUTPUT, I (A)
1. Bypassing of the power supplies is critical. Capacitors must
be connected directly to the power supply pins with very
GENERAL short lead lengths (well under 1 inch). Ceramic chip capaci-
Helpful information about power supplies, heatsinking and tors are best.
ations section of the Apex data book. For information on the 2. Make all ground connections with a star pattern at pin 7.
package outline, heatsinks, and mounting hardware see the 3. Beware of capacitive coupling between output connections
Package Outlines and Accessories section of the data book. and signal inputs through the parasitic capacitance be-
Also see Application Note 30 on PWM Basics.
tween layers in multilayer PCB designs.
4. Do not run small signal traces between the pins of the output
CLOCK CIRCUIT AND RAMP GENERATOR section (pins 11-16).
5. Do not allow high currents to flow into the ground plane.
approximately 1MHZ. The CLK OUT pin will normally be tied
to the CLK IN pin. The clock is divided by two and applied to an 6. Separate switching and analog grounds and connect the
RC network which produces a ramp signal at the RAMP pin. An two only at pin 7 as part of the star pattern.
external clock signal can be applied to the CLK IN pin for
synchronization purposes. If a clock frequency lower than INTEGRATOR
1MHz is chosen an external capacitor must be tied to the
The integrator provides the inverted signal for negative
RAMP pin. This capacitor, which parallels an internal capaci-
feedback and also the open loop gain for the overall application
tor, must be selected so that the ramp oscillates 2.5 volts p-p
circuit accuracy. Recommended value of CINT is 10 pF for
with the lower peak 1.25 volts above ground.
stability. However, poles and zeroes can be added to the circuit
for overall loop stability as required.
BYPASSING
Adequate bypassing of the power supplies is required for CURRENT LIMIT
proper operation. Failure to do so can cause erratic and low
There are two load current sensing pins, I SENSE A and I
efficiency operation as well as excessive ringing at the outputs.
SENSE B. The two pins can be shorted in the voltage mode
connection but both must be used in the current mode connec-
tion (see figures A and B). It is recommended that RLIMIT
resistors be non-inductive. Load current flows in the I SENSE
pins. To avoid errors due to lead lengths connect the I LIMIT/
ered. The bypass capacitors must be physically connected
SHDN pin directly to the RLIMIT resistors (through the filter
directly to the power supply pins. Even one inch of lead length
network and shutdown divider resistor) and connect the RLIMIT
will cause excessive ringing at the outputs. This is due to the
resistors directly to the GND pin. Do not connect RLIMIT sense
very fast switching times and the inductance of the lead
resistors to the ground plane.
connection. The bypassing requirements of the Vcc supply are
less stringent, but still necessary. A .1F to .47F ceramic
capacitor connected directly to the Vcc pin will suffice.
91
OPERATING
SA07 CONSIDERATIONS
I SENSE A SHUTDOWN
The shutdown circuitry makes use of the internal current
R LIMIT
I SENSE B limiting circuitry. The two functions may be externally com-
bined in voltage and current modes as shown below in Figures
1K A and B. The RLIMIT resistors will normally be very low values
FILTER SIGNAL and can be considered zero for this application. In Figure A,
RSHDN and 1K form a voltage divider for the shutdown signal.
R SHDN
C FILTER After a suitable noise filter is designed for the current limit,
adjust the value of RSHDN to give a minimum 110 mV of
FIGURE A. CURRENT LIMIT WITH shutdown signal at the I LIMIT/SHDN pin when the shutdown
SHUTDOWN VOLTAGE MODE. signal is high. Note that CFILTER will filter both the current limit
noise spikes and the shutdown signal. Shutdown and current
I SENSE A limit operate on each cycle of the internal switching rate. As
1K
long as the shutdown signal is high the output will be disabled.
R LIMIT PROTECTION CIRCUITS

I SENSE B
1K Circuits monitor the temperature and load on each of the
bridge output transistors. On each cycle should any fault
R LIMIT condition be detected all output transistors in the bridge are
shut off. Faults protected against are: shorts across the out-
SHUTDOWN puts, shorts to ground, and over temperature conditions.
I LIMIT/SHDN R
FILTER SIGNAL Should any of these faults be detected, the output transistors
R SHDN
will be latched off.* In addition there is a built in dead time
C FILTER
during which all the output transistors are off. The dead time
removes the possibility of a momentary conduction path through
FIGURE B. CURRENT LIMIT WITH the upper and lower transistors of each half bridge during the
SHUTDOWN CURRENT MODE. switching interval. Noise or flyback may be observed at the
outputs during this time due to the high impedance of the
Switching noise spikes will invariably be found at the I outputs in the off state. This will vary with the nature of the load.
SENSE pins. The noise spikes could trip the current limit
threshold which is only 100 mV. RFILTER and CFILTER should be * To restart the SA07 remove the fault and recycle VCC or,
adjusted so as to reduce the switching noise well below 100 alternatively, toggle the ILIMIT/SHDN (PIN16) with a shut down
mV to prevent false current limiting. The sum of the DC level pulse.
plus the noise peak will determine the current limiting value. As
in most switching circuits it may be difficult to determine the
true noise amplitude without careful attention to grounding of
the oscilloscope probe. Use the shortest possible ground lead
for the probe and connect exactly at the GND terminal of the
amplifier. Suggested starting values are CFILTER = .001uF,
RFILTER = 5k .
The required value of RLIMIT in voltage mode may be calcu-
lated by:
RLIMIT = .1 V / ILIMIT
where RLIMIT is the required resistor value, and ILIMIT is the
of each RLIMIT is 2 times this value since the sense voltage is
divided down by 2 (see Figure B). If RSHDN is used it will further
divide down the sense voltage. The shutdown divider network
will also have an effect on the filtering circuit.
This data
APEX sheet has been carefully checked
MICROTECHNOLOGY and is believed
CORPORATION to be reliable,
5980 NORTH however,
SHANNONno responsibility
ROAD isTUCSON,
assumed forARIZONA
possible inaccuracies
85741 or USA
omissions. All specifications are
APPLICATIONS subject to 1
HOTLINE: change
(800)without notice.
546-2739
SA07U REV. B DECEMBER 1998 1998 Apex Microtechnology Corp.
92
NOTES:
93
EK07
This easy-to-use kit provides a platform for the evaluation of 1. From the DUT side of the PCB push the spacer grommets in the
PWM amplifiers using the SA07 pin-out configuration. It can be used PC board until fully seated. Grommets will snug when screws are
to analyze a multitude of standard or proprietary circuit configura- inserted for heat sink mounting.
tions, and is flexible enough to do most standard amplifier test 2. Apply a thin coat of thermal grease to the bottom of the amplifier.
configurations. The board is designed for surface or through hole 3. Slip 1/8" lengths of #22 sleeving over the pins at the four corners
mounting all components except the switching amplifier. of the amplifier.
The schematic is shown in Figure 2. Note that all of the compo- 4. Mount the amplifier to the heat sink with #6 x 1/4" machine
nents shown on the schematic will probably not be used for any screws through the HK03 clamps and into the threaded holes in
single circuit. Some components will simply be omitted, while others the heat sink.
require installation of a jumper to complete the signal path. 5. Mount the application circuit components as required.
Only components unique to the EK07 are provided in this kit. 6. Mount the amplifier/heat sink assembly to the PCB and solder
Hardware similar to that shown in Figure 1 must be obtained locally. the amplifier pins to the PCB.
7. Secure the heat sink to the PCB as shown in Figure 1.
PARTS LIST
HS18-1 Heatsink 1
EVAL12 PC Board 1
OX7R105KWN 1F Capacitor 2
1825B105K201N/Novacap
HK03 Clamp 1 Bag/2 each

* Always use thermal grease between the amplifier and heatsink.
FIGURE 1.
94
EVALUATION KIT
A block diagram of the SA07 is shown

in Figure 2 along with pcb connections
of all the commonly used external com-
ponents. Your application circuit will
not use all of the components. Add
those components required by your
circuit. You may have to jumper some
components to make the desired elec-
trical connections. J3 is an optional
way to connect the clock circuit. Power
supply bypassing is particularly impor-
tant and that is why high quality ce-
ramic chip capacitors are supplied with
the kit. In addition you may need to add
a 10-50 uF or larger capacitor on the
+Vs pin. This additional capacitor needs
to be rated for switching operation.
Note that the signal ground and power
ground are separated and tie together
only at the ground pin (7). A bread-
boarding area is supplied which can
C
accomodate 1 or 2 IC amplifiers and
associated components. The large ter-
minal pads can be used to solder wire
95
EVALUATION KIT
The schematic of Figure 3 can

be used to verify the functionality
of your amplifier and help you gain
a familiarity with proper operation.
At either A Out or B Out, with
respect to ground, you should ob-
serve a square wave approximately
30 V in amplitude with a fixed fre-
quency and duty cycle that varies
from approximately 0 to 100% at a
rate of 1 Hz. The current limit is set
to 2 amps.
APEX
This MICROTECHNOLOGY CORPORATION
data sheet has been carefully 5980
checked and is believed to beNORTH SHANNON
reliable, however, ROAD TUCSON,
no responsibility is assumed ARIZONA 85741 USA
for possible inaccuracies APPLICATIONS
or omissions. HOTLINE:
All specifications are subject 1 (800) without
to change 546-2739
notice.
EK07U REV. A MARCH 1998 1998 Apex Microtechnology Corp.
96
NOTES:
97
SA13
FEATURES
HALF BRIDGE OUTPUT SA13
WIDE SUPPLY RANGE16-100V
30A CONTINUOUS TO 60 C CASE USA
3 PROTECTION CIRCUITS TE9493
11
BeO

APPLICATIONS
MOTORS TO 4HP
REACTIVE LOADS
LOW FREQUENCY SONAR EXTERNAL CONNECTIONS
OFF-LINE DRIVERS
C-D WELD CONTROLLER
NC
NC
The SA13 is a half bridge pulse width modulation amplifier CLK OUT 2 11
that can supply 3000W to the load. Flexible frequency control +PWM 3 10
* VCC
TOP
is provided. An internal 45kHz oscillator requires no external 4 VIEW 9 *
PWM/RAMP
components and can be used to synchronize multiple ampli- 5 8 +VS
fiers. The oscillator output may be divided down and con- SIG GND 6 7 OUT
nected to the clock input to lower the switching frequency . The
clock input stage divides by two and determines the output SHDN PWR GND
switching rate (normally 22.5 kHz). A shutdown input turns off
both output drivers. High side current sensing protects the
amplifier from shorts to ground. In addition, the half bridge Case tied to pin 5. Allow no current in case. Bypassing of supplies
output MOSFETs are protected from thermal overloads by is required. Package is Apex MO-127 (STD). See Outline
directly sensing the temperature of the die. The 12-pin her- Dimensions/Packages in Apex data book.
metic MO-127 power package occupies only 3 square inches If +PWM < RAMP/PWM then OUT = HIGH.
of board space.
*See text.
PROGRAMMABLE POWER SUPPLY
Vcc
10 CURRENT 9
LIMIT +VS
+PWM
3
PWM
4
PWM/RAMP 10V OUT
470pF
P-P OUTPUT 8 LOAD
56K DRIVERS
12
CLK OUT
NC
2 OSC 2
NC
SHUTDOWN 11
CLK IN CONTROL 5K
6
1
SHDN .01F
5
7
CONTROL SIG GND
SIGNAL PWR GND RSENSE
3/7V
5V
5V
98
SA13 SPECIFICATIONS

SPECIFICATIONS
CLOCK (CLK)
OUTPUT
RON Each output driver .08
CURRENT, peak4 40 A
POWER SUPPLY
ILIM/SHUTDOWN
THERMAL3
NOTES: 1. Each of the two output transistors can dissipate 150W.

CAUTION
99
TYPICAL PERFORMANCE
GRAPHS SA13
150 100 102.0

101.5
125
99
101.0
100
98 100.5
75 100
97 99.5
50
99.0
25 96
EACH OUTPUT TRANSISTOR 98.5
F NOMINAL = 45kHz
0 95 98.0
0 25 50 75 100 125 10K 100K 1M 50 25 0 25 50 75 100 125

3 5
2 CASE TEMPERATURE
60C
4
10 85C
9
7 100C
6 3
5
125C
4
3
2
2
1 1
8
25C
7
25C
6 55C
5 0
0.6 0.8 1.0 1.2 1.4 1.6 0 5 10 15 20 25 30

30 100 100
A OUT
28
80 95
CONTINUOUS AMPS
DUTY CYCLE, (%)
26
24 60 90
22
40 85
20
20 80
18
B OUT
16 0 75
25 50 75 100 125 150 3 4 5 6 7 5 10 15 20 25

115 180 100

110 F = 22.5 kHz 160
90
140
105
NORMAL 80
120
100 OPERATION 55C
100 70
95 125C
80
60
90 60
SHUTDOWN 50
85 OPERATION 40
80 20 40
50 25 0 25 50 75 100 125 0 20 40 60 80 100 5 10 15 20 25
100
OPERATING
CONSIDERATIONS SA13
GENERAL An external shutdown command can be mixed with the

Helpful information about power supplies, heatsinking and protection circuit of Figure A. In figure B a 5V shutdown
mounting can be found in the General Operating Consider- command signal is divided down by R2, R1 to the 100 mV
ations section of the Apex data book. For information on the threshold level of the SHDN pin of the SA13. As long as the
package outline, heatsinks, and mounting hardware see the shutdown command remains high both output transistors will
Package Outlines and Accessories section of the data remain off.
book. Also see Application Note 30 on PWM Basics.
PWR GND
CLOCK CIRCUIT AND RAMP GENERATOR
R2 SHUTDOWN
approximately 45kHz. The CLK OUT pin will normally be tied
SHDN SIGNAL
to the CLK IN pin. The clock is divided by two and applied to an R1
RC network which produces a ramp signal at the PWM/
C1
RAMP pin. An external clock signal can be applied to the CLK
IN pin for synchronization purposes. If a clock frequency lower RSENSE
than 45kHz is chosen an external capacitor must be tied to the
PWM/RAMP pin. This capacitor, which parallels an internal
capacitor, must be selected so that the ramp oscillates 4 volts
FIGURE B. ADDING SHUTDOWN CONTROL.
p-p with the lower peak 3 volts above ground.
PWM INPUTS BYPASSING

The half bridge driver may be accessed via the pwm input Adequate bypassing of the power supplies is required for
comparator. When +PWM < -PWM then OUT is HIGH. A proper operation. Failure to do so can cause erratic and low
motion control processor which generates the pwm signal can efficiency operation as well as excessive ringing at the outputs.
drive these pins with signals referenced to SIG GND. The Vs supply should be bypassed with at least a 1F ceramic
PROTECTION CIRCUITS 10F per amp of output current. Capacitor types rated for
A high side current monitor will latch off the output transistors switching applications are the only types that should be consid-
when the high side current rises to approximately 150% of ered. The bypass capacitors must be physically connected
rated output. The temperature of the output transistors is also directly to the power supply pins. Even one inch of lead length
monitored. When either of the output transistors reaches will cause excessive ringing at the outputs. This is due to the
approximately 165C both are latched off. In either case, it will very fast switching times and the inductance of the lead
be necessary to remove the fault condition and recycle power connection. The bypassing requirements of the Vcc supply are
to Vcc to restart the circuit. A short to +Vs can be protected less stringent, but still necessary. A .1F to .47F ceramic
against by inserting a sensing resistor into the PWR GND capacitor connected directly to the Vcc pin will suffice.
circuit as shown in Figure A.
STARTUP CONDITIONS
The high side of the all N channel output half bridge circuit
PWR GND is driven by a bootstrap circuit and charge pump arrangement.
In order for the circuit to produce a 100% duty cycle indefinitely
the low side transistor must have previously been in the ON
SHDN
R1 condition. This means, in turn, that if the input signal to the
SA13 at startup is demanding a 100% duty cycle, the output
C1 R SENSE may not follow the command and may be in a tri-state condi-
tion. The ramp signal must cross the input signal at some point
to correctly determine the output state. After the ramp crosses
FIGURE A. PROTECTING AGAINST SHORTS TO +Vs. the input signal level one time, the output state will be correct
thereafter.
In Figure A, the sense resistor inserted into the PWR GND

connection is tied to the SHDN pin. When the current from a
short to +Vs develops 100 mV across the sense resistor the
shutdown circuit will shut off the output transistors for the
remainder of the switching cycle. The SA13 will restart at the
beginning of a new cycle and retest for this condition. This
circuit does not test for shorts to ground. The RC circuit R1, C1
filters out any switching spikes and may need to be adjusted to
ignore normal current spikes in the application circuit.
however, FAXis(520)
no responsibility 888-3329
ORDERS (520) 690-8601
101
EVALUATION KIT FOR SA13/SA14 PIN-OUT
EK10
This easy-to-use kit provides a platform for the evaluation of (See Figure 1)
PWM amplifiers using the SA13 or SA14 pin-out configuration. It
can be used to analyze a multitude of standard or proprietary circuit 1. From the non-silk screen side, insert and solder cage jacks. Be
configurations, and is flexible enough to do most standard amplifier sure each one is fully seated.
test configurations. The board is designed for surface mounting all 2. From the non-silk screen side, push spacer grommets into PC
components except the switching amplifier. board until fully seated. Grommets will snug when screws are
The schematic is shown in Figure 2. Note that all of the compo- inserted for heatsink mounting.
nents shown on the schematic will probably not be used for any 3. Apply TW05 thermal washer to the bottom of the SA13 or SA14.
single circuit. Some components will simply be omitted, while others 4. Use #14 sleeving to insulate and align at least 2 opposite pins of
require installation of a jumper to complete the signal path. the amplifier.
Only components unique to the EK10 are provided in this kit. 5. Mount amplifier to heatsink using #6 screws and nuts. Torque the
Hardware similar to that shown in figure 1 must be obtained locally. part to the specified 8 to 10 in-lbs (.9 to 1.13 N*M). Do not over
torque.
PARTS LIST 6. Install components as needed. External connections may be
Part # Description Quantity these pads.
HS18 Heatsink 1 7. Insert amplifier pins into cage jacks and fasten board to heatsink.
EVAL 09 PC Board 1
TW05
OX7R105KWN
Thermal Washer
1F Cap 1825B105K201N,
1 Box/10 each
6
C
Novacap

* All Apex amplifiers should be handled using proper ESD precau-
tions.
Cage Jack
Spacer Grommet
TW05 thermal washer
Heatsink
FIGURE 1.
102
EK10 EVALUATION KIT
FOR SA13/SA14 PIN-OUT
A block diagram for both the SA13 and SA14

is shown in Figure 2 along with pcb connections
of all the commonly used external components.
Your application circuit will not use all of the
components. Add those components required
by your circuit. You may have to jumper some
components to make the desired electrical con-
nections. J1 is an optional way to connect the
clock circuit. Power supply bypassing is par-
ticularly important and that is why high quality
ceramic chip capacitors are supplied with the
kit. In addition you may need to add a 10-50 uF
or larger capacitor on the +Vs pin. This addi-
tional capacitor needs to be rated for switching
operation. Note that the signal ground and
power ground are separated and tie together
only at the ground pin (5). A breadboarding
area is supplied which can accomodate 1 or 2
IC amplifiers and associated components. The
connections or banana jacks.
Note that the EK10 Evaluation Kit uses the
same circuit board as the EK03 Evaluation kit
intended for the Apex models SA03 and SA04.
The SA13 and SA14 are half bridge versions of
the SA03 and SA04 and are indentical in design
except for that fact. Some of the pin designa-
SA13/SA14 tions of the SA13 and SA14 are, however,
different. The SA13 and SA14's OUT (PIN 8)
are equivalent to the SA03 and SA04's B OUT
(PIN 8). The SA13 and SA14's PWR GND (PIN
7) are equivalent to the SA03 and SA04's
I SENSE B (PIN7). Pins 11 and 12 of the SA13
and SA14 are not connected. The designations
on the PCB are those used for the SA03 and
SA04. See the SA13 or SA14 data sheet for
specific operating considerations.
*
* *
103
EVALUATION KIT
FOR SA13/14 PIN-OUT EK10

Out, with respect to ground, you should ob-
serve a square wave approximately 30 V in
amplitude with a fixed frequency and duty cycle
that varies from approximately 0 to 100% at a
rate of 1 Hz.
SA13/SA14
104
EK10
without notice.
EK10U REV. B JANUARY 1998 1998 Apex Microtechnology Corp.
105
SA14
FEATURES

TE9493 BeO
11
3 PROTECTION CIRCUITS
APPLICATIONS
MOTORS
REACTIVE LOADS
OFF-LINE DRIVERS
C-D WELD CONTROLLER
NC
NC
that can supply 4000W to the load. Flexible frequency control +PWM 3 10
* VCC
TOP
components and can be used to synchronize multiple ampli- PWM/RAMP
5 8 +VS
fiers. The oscillator output may be divided down and con-
SIG GND 6 7 OUT
nected to the clock input to lower the switching frequency . The
clock input stage divides by two and determines the output SHDN PWR GND
output MOSFETs are protected from thermal overloads by is required. Package is Apex MO-127 (STD). See Outline
directly sensing the temperature of the die. The 12-pin her- Dimensions/Packages in Apex data book.
metic MO-127 power package occupies only 3 square inches
of board space. If +PWM < RAMP/PWM then OUT = HIGH.
*See text.
Vcc
10 CURRENT 9
LIMIT +VS
+PWM
3
PWM
4
PWM/RAMP 10V OUT
470pF
P-P OUTPUT 8 LOAD
56K DRIVERS
12
CLK OUT
NC
2 OSC 2
NC
SHUTDOWN 11
CLK IN CONTROL 5K
6
1
SHDN .01F
5
7
CONTROL SIG GND
3/7V
5V
5V
106
SA14 SPECIFICATIONS

SPECIFICATIONS
CLOCK (CLK)
OUTPUT
CURRENT, peak4 30 A
POWER SUPPLY
ILIM/SHUTDOWN
THERMAL3

CAUTION
107
TYPICAL PERFORMANCE
GRAPHS SA14

150 100 102.0

101.5
125
99
101.0
100
98 100.5
75 100
97 99.5
50
96 99.0
25 EACH ACTIVE
0 95 98.0
0 25 50 75 100 125 10K 100K 1M 50 25 0 25 50 75 100 125

2 5
CASE TEMPERATURE
10
8 4 85C
7
6
5
4 100C
3 3
2 125C
2
1
8
7
6
5 1
4 60C
3 25C
2 0 55C 25C
0.6 0.8 1.0 1.2 1.4 1.6 0 5 10 15 20

20 100 100
A OUT
80 95
CONTINUOUS AMPS
18
DUTY CYCLE, (%)
60 90
16
40 85
14
20 80
B OUT
12 0 75
25 50 75 100 125 150 3 4 5 6 7 5 10 15 20 25

115 140 100

110 F = 22.5 kHz 120
80
105
NORMAL 100
100 OPERATION
80 60
95
60
90
40
SHUTDOWN 40
85 OPERATION
80 20 20
50 25 0 25 50 75 100 125 0 25 50 75 100 125 150 175 200 5 10 15 20 25
108
OPERATING
CONSIDERATIONS SA14

book. Also see Application Note 30 on PWM Basics. PWR GND

R2
The clock frequency is internally set to a frequency of SHUTDOWN
SHDN SIGNAL
approximately 45kHz. The CLK OUT pin will normally be tied R1
to the CLK IN pin. The clock is divided by two and applied to an
C1
RC network which produces a ramp signal at the PWM/
RAMP pin. An external clock signal can be applied to the CLK RSENSE
IN pin for synchronization purposes. If a clock frequency lower
FIGURE B. ADDING SHUTDOWN CONTROL.
capacitor, must be selected so that the ramp oscillates 4 volts
BYPASSING
PWM INPUTS
Adequate bypassing of the power supplies is required for
The half bridge driver may be accessed via the pwm input proper operation. Failure to do so can cause erratic and low
comparator. When +PWM < -PWM then OUT is HIGH. A efficiency operation as well as excessive ringing at the outputs.
motion control processor which generates the pwm signal can The Vs supply should be bypassed with at least a 1F ceramic
drive these pins with signals referenced to SIG GND. capacitor in parallel with another low ESR capacitor of at least
PROTECTION CIRCUITS switching applications are the only types that should be consid-
A high side current monitor will latch off the output transistors ered. The bypass capacitors must be physically connected
when the high side current rises to approximately 150% of directly to the power supply pins. Even one inch of lead length
rated output. The temperature of the output transistors is also will cause excessive ringing at the outputs. This is due to the
monitored. When either of the output transistors reaches very fast switching times and the inductance of the lead
approximately 165C both are latched off. In either case, it will connection. The bypassing requirements of the Vcc supply are
be necessary to remove the fault condition and recycle power less stringent, but still necessary. A .1F to .47F ceramic
to Vcc to restart the circuit. A short to +Vs can be protected capacitor connected directly to the Vcc pin will suffice.
against by inserting a sensing resistor into the PWR GND
circuit as shown in Figure A. STARTUP CONDITIONS
The high side of the all N channel output half bridge circuit
PWR GND is driven by a bootstrap circuit and charge pump arrangement.
the low side transistor must have previously been in the ON
SHDN condition. This means, in turn, that if the input signal to the
R1
SA14 at startup is demanding a 100% duty cycle, the output
C1 R SENSE may not follow the command and may be in a tri-state condi-
to correctly determine the output state. After the ramp crosses
FIGURE A. PROTECTING AGAINST SHORTS TO +Vs. the input signal level one time, the output state will be correct
thereafter.

This data
APEX sheet has been carefully CORPORATION
MICROTECHNOLOGY checked and is believed to be reliable,(520)
TELEPHONE however, no responsibility
690-8600 FAXis(520)
assumed888-3329
for possibleinaccuracies or omissions.
ORDERS (520) All specifications
690-8601 EMAILare subject to change without notice.
prodlit@apexmicrotech.com
109
SA16
FEATURES
BeO
3 PROTECTION CIRCUITS TE9493
11

APPLICATIONS
MOTORS
REACTIVE LOADS
OFF-LINE DRIVERS
C-D WELD CONTROLLER
NC
NC
+PWM * VCC
that can supply 5000W to the load. Flexible frequency control 3
TOP
10
PWM/RAMP
components and can be used to synchronize multiple ampli- 5 8 +VS
fiers. The oscillator output may be divided down and con- SIG GND 6 7 OUT
nected to the clock input to lower the switching frequency . The SHDN
clock input stage divides by two and determines the output PWR GND
output MOSFETs are protected from thermal overloads by is required. Package is Apex MO-127/40S. See Outline
Dimensions/Packages in Apex data book.
directly sensing the temperature of the die. The 12-pin her-
metic MO-127/40S power package occupies only 3 square If +PWM < RAMP/PWM then OUT = HIGH.
inches of board space.
*See text.
Vcc
10 CURRENT 9
LIMIT +VS
+PWM
3
PWM
4
PWM/RAMP 10V OUT
470pF
P-P OUTPUT 8 LOAD
56K DRIVERS
12
CLK OUT
NC
2 OSC 2
NC
SHUTDOWN 11
CLK IN CONTROL 5K
6
1
SHDN .01F
5
7
CONTROL SIG GND
3/7V
5V
5V
110
SA16 SPECIFICATIONS

SPECIFICATIONS
CLOCK (CLK)
OUTPUT
CURRENT, peak4 14 A
POWER SUPPLY
ILIM/SHUTDOWN
THERMAL3

CAUTION
111
TYPICAL PERFORMANCE
GRAPHS SA16
150 100 102.0

101.5
125
99
101.0
100
98 100.5
75 100
97 99.5
50
96 99.0
25 EACH ACTIVE
0 95 98.0
0 25 50 75 100 125 10K 100K 1M 50 25 0 25 50 75 100 125

10 10
CASE TEMPERATURE 75C
85C
7.5 100C
5 125C
1 2.5
25C
25C
55C
0
0.6 0.8 1.0 1.2 1.4 0 2 4 6 8 10

10 100 100
A OUT
9 80 95
CONTINUOUS AMPS
DUTY CYCLE, (%)
8 60 90
7 40 85
6 20 80
B OUT
5 0 75
25 50 75 100 125 3 4 5 6 7 5 10 15 20 25

115 140 100

110 F = 22.5 kHz
120 80
105
NORMAL
100 OPERATION
100 60
95
90 80 40
SHUTDOWN
85 OPERATION
80 60 20
50 25 0 25 50 75 100 125 0 100 200 300 400 500 5 10 15 20 25
112
OPERATING
CONSIDERATIONS SA16

book. Also see Application Note 30 on PWM Basics.
PWR GND
The clock frequency is internally set to a frequency of R2 SHUTDOWN
approximately 45kHz. The CLK OUT pin will normally be tied SHDN SIGNAL
to the CLK IN pin. The clock is divided by two and applied to an R1
RC network which produces a ramp signal at the PWM/ C1

RAMP pin. An external clock signal can be applied to the CLK
RSENSE
IN pin for synchronization purposes. If a clock frequency lower
capacitor, must be selected so that the ramp oscillates 4 volts FIGURE B. ADDING SHUTDOWN CONTROL.
PWM INPUTS
The half bridge driver may be accessed via the pwm input BYPASSING
comparator. When +PWM < -PWM then OUT is HIGH. A Adequate bypassing of the power supplies is required for
motion control processor which generates the pwm signal can proper operation. Failure to do so can cause erratic and low
drive these pins with signals referenced to SIG GND. efficiency operation as well as excessive ringing at the outputs.
PROTECTION CIRCUITS capacitor in parallel with another low ESR capacitor of at least
A high side current monitor will latch off the output transistors 10F per amp of output current. Capacitor types rated for
when the high side current rises to approximately 150% of switching applications are the only types that should be consid-
rated output. The temperature of the output transistors is also ered. The bypass capacitors must be physically connected
monitored. When either of the output transistors reaches directly to the power supply pins. Even one inch of lead length
approximately 165C both are latched off. In either case, it will will cause excessive ringing at the outputs. This is due to the
be necessary to remove the fault condition and recycle power very fast switching times and the inductance of the lead
to Vcc to restart the circuit. A short to +Vs can be protected connection. The bypassing requirements of the Vcc supply are
against by inserting a sensing resistor into the PWR GND less stringent, but still necessary. A .1F to .47F ceramic
circuit as shown in Figure A. capacitor connected directly to the Vcc pin will suffice.
STARTUP CONDITIONS
PWR GND The high side of the all N channel output half bridge circuit
is driven by a bootstrap circuit and charge pump arrangement.
SHDN the low side transistor must have previously been in the ON
R1
condition. This means, in turn, that if the input signal to the
C1 R SENSE SA16 at startup is demanding a 100% duty cycle, the output
may not follow the command and may be in a tri-state condi-
FIGURE A. PROTECTING AGAINST SHORTS TO +Vs. to correctly determine the output state. After the ramp crosses
the input signal level one time, the output state will be correct
thereafter.
however, FAXis(520)
ORDERS (520) 690-8601
113
EK08
This easy-to-use kit provides a platform for the evaluation of (See Figure 1)
PWM amplifiers using the SA16 pin-out configuration. It can be used
to analyze a multitude of standard or proprietary circuit configura- 1. From the non-silk screen side, insert and solder cage jacks. Be
tions, and is flexible enough to do most standard amplifier test sure each one is fully seated.
configurations. The board is designed for surface mounting all 2. From the non-silk screen side, push spacer grommets into PC
components except the switching amplifier. board until fully seated. Grommets will snug when screws are
The schematic is shown in Figure 2. Note that all of the compo- inserted for heatsink mounting.
nents shown on the schematic will probably not be used for any 3. Apply TW05 thermal washer to the bottom of the SA16.
single circuit. Some components will simply be omitted, while others 4. Use #14 sleeving to insulate and align at least 2 opposite pins of
require installation of a jumper to complete the signal path. the amplifier.
Only components unique to the EK08 are provided in this kit. 5. Mount amplifier to heatsink using #6 screws and nuts. Torque the
Hardware similar to that shown in figure 1 must be obtained locally. part to the specified 8 to 10 in-lbs (.9 to 1.13 N*M). Do not over
torque.
PARTS LIST 6. Install components as needed. External connections may be
Part # Description Quantity these pads.
HS18 Heatsink 1 7. Insert amplifier pins into cage jacks and fasten board to heatsink.
EVAL10 PC Board 1
TW05
OX7R105KTN
Thermal Washer
1F Cap 3530B105K501N,
1 Box/10 each
1
C
Novacap
OX7R105KWN 1F Cap 1825B105K201N, 1
Novacap

Cage Jack
Spacer Grommet
TW05 thermal washer
Heatsink
FIGURE 1.
114
EK08 EVALUATION KIT
FOR SA16 PIN-OUT
A block diagram of the SA16 is shown in

connections or banana jacks.
Note that the EK08 Evaluation Kit uses the
same circuit board as the EK05 Evaluation kit
intended for Apex's model SA06. The SA16 is
a half bridge version of the SA06 and is
indentical in design except for that fact. Some of
the pin designations of the SA16 are, however,
different. The SA16's OUT (PIN 8) is equivalent
SA16 to the SA06's B OUT (PIN 8). The SA16's PWR
GND (PIN 7) is equivalent to the SA06's I SENSE
B (PIN7). Pins 11 and 12 of the SA16 are not
connected. The designations on the PCB are
those used for the SA06. See the SA16 data
sheet for specific operating considerations.
* *
115
EVALUATION KIT

Out, with respect to ground, you should ob-
serve a square wave approximately 30 V in
amplitude with a fixed frequency and duty cycle
that varies from approximately 0 to 100% at a
rate of 1 Hz.
SA16
116
EK08
omissions. HOTLINE:
without notice.
117
H/BRIDGE MOTOR DRIVER/AMPLIFIER
SA50
FEATURES
LOW COST COMPLETE H-BRIDGE
SELF-CONTAINED SMART LOWSIDE/HIGHSIDE DRIVE
CIRCUITRY
WIDE SUPPLY RANGE: UP TO 80V
HERMETIC SEALED PACKAGE
HIGH EFFICIENCY: 97%
FOUR QUADRANT OPERATION, TORQUE
CONTROL CAPABILITY
INTERNAL PWM GENERATION
TYPICAL APPLICATION
APPLICATIONS
+VS
Vcc
CLASS D SWITCHMODE AMPLIFIER
REACTIVE LOADS
MAGNETIC COILS (MRI)
ACTIVE MAGNETIC BEARING
AUDIO
C
VIBRATION CANCELLING SA50
INPUT
SPEAKER
DESCRIPTION
The SA50 is a pulse width modulation amplifier that can
supply 5A continuous current to the load. The full bridge GND
amplifier can be operated over a wide range of supply volt-
ages. All of the drive/control circuitry for the lowside and
highside switches are internal to the hybrid. The PWM circuitry
is internal as well, leaving the user to only provide an analog +VS
Vcc
signal for the motor speed/direction, or audio signal for
switchmode audio amplification. The SA50 is packaged in a
space efficient isolated 8-pin TO-3 that can be directly con-
nected to a heatsink.
ANALOG
INPUT SA50
+VS
BLOCK DIAGRAM DC MOTOR
GND
(LOAD)
B A EXTERNAL CONNECTIONS
VCC
(+12V) B OUT
+VS
2
45KHz 3
PWM 1 RSENSE B
GENERATOR H-BRIDGE RSENSE B RSENSE A
A OUT 4
DRIVE (CURRENT)
INPUT CIRCUITRY TOP VIEW
RSENSE A 5
8
GND 6 INPUT
7
Vcc
GND
118
SA50 SPECIFICATIONS

LOGIC SUPPLY VOLTAGE, Vcc 16V
INPUT VOLTAGE +1 to Vcc 1.5 Vdc
SPECIFICATIONS
INPUT
ANALOG INPUT VOLTAGES Vcc = 12V
MOTOR A, B = 50% Duty Cycle 6 Vdc
MOTOR A = 100% Duty Cycle High 8 Vdc
MOTOR B = 100% Duty Cycle High 4 Vdc
OUTPUT
Vds (ON) VOLTAGE, each MOSFET Ids = 5A 1.25 1.8 Vdc
TOTAL Ron, both MOSFETs 0.5
EFFICIENCY, 5A OUTPUT +VS = 80V 97 %
SWITCHING FREQUENCY 40 45 50 Khz
CURRENT, peak t = 100 msec 7 A
SWITCHING CHARACTERISTICS4 +VS = 28V, Vcc = 12V, Ic =2A
RISE TIME 36 54 nS
FALL TIME 170 250 nS
DEAD TIME 100 nS
POWER SUPPLY
+VS VOLTAGE +VS Current = Load Current 80 Vdc
Vcc VOLTAGE 9 12 16 Vdc
Vcc CURRENT Vcc = 12Vdc 15 20 mA
3
THERMAL
TEMPERATURE RANGE, case 25 +85 C
2. Unless otherwise noted: TC = 25C, Vcc = 12Vdc.
CAUTION
WARNINGAMPLIFIER PROTECTION
The SA50 contains an internal logic chip that turns on and time, thus destroying the SA50. A well laid out PC board with
turns off output MOSFET drivers at a certain sequence. Noises low impedance copper ground plane is necessary for the
or oscillation caused by external wiring inductance, lack of SA50 to function properly. The Apex EK-SA50 evaluation
proper power supply bypass capacitors, ground, supply and board is recommended for fast and easy breadboarding of
local internal loops, may be fed back to this logic chip and circuits using the SA50.
cause it to turn on one or more MOSFET drivers at the wrong
119
TYPICAL PERFORMANCE
GRAPHS SA50
POWER DERATING INPUT CURRENT VS TEMP EFFICIENCY CONTOURS
60 1.05 80
%
0.95 70 97
PWM BIAS CURRENT, (A)
SUPPLY VOLTAGE, VS (V)

50
0.85 60
40
0.75 50
95%
30 0.65 40
0.55 30
20 90%
0.45 20
10 80%
0.35 10
EACH OUTPUT TRANSISTOR
0 70%
0.25 0
0 25 50 75 100 125 40 20 0 20 40 60 80 100 120 1 2 3 4 5
CASE TEMPERATURE, T C (C) CASE TEMPERATURE, (C) LOAD CURRENT, (A)
EFFICIENCY VS TEMP @ 80V EFFICIENCY VS TEMP @ 20V EFFICIENCY VS LOAD CURRENT

100 100 100
99 95 VS = 80
IOUT = 1 IOUT = 1 V
A, V = 80V A, V = 20V 97
98 S S
EFFICIENCY, (%)
EFFICIENCY, (%)
EFFICIENCY, (%)
90 VS =
60V
97 IO VS =
85 IO 94
96
UT
=
5A
UT
=
5A
40V
C
,V 80 ,V 91
95 S = S
80 = V
V 75 20 S
94 V =2
88 0V
93 70
92 65 85
60 20 20 60 100 140 180 60 20 20 60 100 140 180 1 2 3 4 5
JUNCTION TEMPERATURE (C) JUNCTION TEMPERATURE (C) LOAD CURRENT, (A)
OUTPUT RESISTANCE DRIFT H-BRIDGE FET CAPACITANCE QUIESCENT CURRENT VS VOLTAGE

OUTPUT RESISTANCE, (NORMALIZED)
2.5 500
14.0
DRAIN-TO-SOURCE CAP, (pF)
QUIESCENT CURRENT, (mA)
2 400
12.0
1.5 300 10.0
8.0
1 200
6.0
0.5 100
4.0
0 0 2.0
60 20 20 60 100 140 180 1 2 5 10 20 50 100 8 9 10 11 12 13 14 15
JUNCTION TEMPERATURE (C) DRAIN-TO-SOURCE VOLTAGE, (V) Vcc VOLTAGE (V)
VOLTAGE DROP (BOTH MOSFETS) QUIESCENT CURRET VS PWM FREQ

5 15
CASE TEMPERATURE
4 14
VOLTAGE DROP, (V)
85C
3 110C 13
2 12
60C
1 35C 11
0 10
0 1 2 3 4 5 0 200 400 600
OUTPUT CURRENT, (A) PWM FREQUENCY (Hz)
120
OPERATING
SA50 CONSIDERATIONS
GENERAL TYPICAL SYSTEM OPERATION

Helpful information about power supplies, heatsinking and +VS
+12V
ations section of the Apex data book. For information on the 3
package outline, heatsinks, and mounting hardware see the 6 +VS
Vcc SNUBBER NETWORK
Package Outlines and Accessories section of the data 22F MOTOR A
4 MOTOR
book. Also see Application Note 30 on PWM Basics. 100
SA50 2W
8 1000pF
INPUT
PIN DESCRIPTION 2 200V
7 MOTOR B
MYLAR
VCC - is the low voltage supply for powering internal logic GND 6.8F
RSENSE A 5 100V
and drivers for the lowside and highside MOSFETS. The POLY
supplies for the highside drivers are derived from this voltage. RSENSE B
1 SENSE
VS - is the higher voltage H-bridge supply. The MOSFETS RESISTORS
obtain the output current from this supply pin. The voltage on 0.1
R
this pin is limited to +80V by the drive IC. The MOSFETS are
rated at 100 volts. Proper by-passing to GND with sufficient NO OUTPUT
R SWITCHING +12V
capacitance to suppress any voltage transients, and to ensure GND CURRENT
removing any drooping during switching, should be done as RDIVIDE
+12V RIN
close to the pins on the hybrid as possible. (VCC2)
A OUT - is the output pin for one half of the bridge. Increasing RDIVIDE RDIVIDE = 2X Rf
ANALOG
the input voltage causes increasing duty cycle at this output. INPUT
B OUT - is the output pin for the other half of the bridge.
Decreasing the input voltage causes increasing duty cycles at
Rf RIN
this point.
RSENSE A - This is the connection for the bottom of the A
half bridge. This can have a sense resistor connected to the VS
return ground for current limit sensing, or can be connected CURRENT CONTROL
directly to ground. The maximum voltage on this pin is 2 volts
This is a diagram of a typical application of the SA50. The
with respect to GND.
design Vcc voltage is +12 volts and should have a good low
GND - is the return connection for the input logic and Vcc.
ESR bypass capacitor such as a tantalum electrolytic. The
RESENSE B - This is the connection for the bottom of the B
analog input can be an analog speed control voltage from a
half bridge. This can have a sense resistor connection to the
potentiometer, other analog circuitry or by microprocessor and
VS return ground for current limit sensing, or can be connected
a D/A converter. This analog input gets pulled by the current
directly to ground. The maximum voltage on this pin is 2 volts
control circuitry in the proper direction to reduce the current
with respect to GND.
flow in the bridge if it gets too high. The gain of the current
INPUT - is an analog input for controlling the PWM pulse
control amplifier will have to be set to obtain the proper amount
width of the bridge. A voltage higher than Vcc/2 will produce
of current limiting required by the system.
greater than 50% duty cycle pulses out of A OUT. A voltage
Current sensing is done in this case by a 0.1 sense resistor
lower than Vcc/2 will produce greater than 50% duty cycle
to sense the current from both legs of the bridge separately. It
pulses out of B OUT.
is important to make the high current traces as big as possible
to keep inductance down. The storage capacitor connected to
the VS and the hybrid GND should be large enough to provide
the high energy pulse without the voltage sagging too far. A
low ESR capacitor will be required. Mount capacitor as close
to the hybrid as possible. The connection between GND and
the VS return should not be carrying any motor current. The
sense resistor signal is common mode filtered as necessary to
feed the limiting circuitry. This application will allow full four
quadrant torque control for a closed loop servo system.
A snubber network is usually required, due to the inductance
in the power loop. It is important to design the snubber network
to suppress any positive spikes above +VS and negative spikes
below 2V with respect to pin 7 (GND).
without notice.
121
EVALUATION KIT FOR SA50
EK-SA50
INTRODUCTION EQUIVALENT SCHEMATIC

Fast, easy breadboarding of circuits using the SA50 are possible J1
with the EK-SA50 PC board. Mounting holes are provided and the R1 1
provision for standard banana jacks simplifies connection and RSENSE A
8
0.1 3W INPUT INPUT
testing. Components are labeled on both sides of the board for ease
in probing. A OUT
2
A OUT GND
7
*D2 R3 R4
10K *D1 10K
*D4 *D3 SA50
TYPICAL COMPONENT FUNCTIONS R5
TO-3
1/4W 1/4W
100 3 +VS VCC 6

C2, C3, C4 Power supply bypass capacitors 2W VCC
C1
R3, R4 Resistor divider to set the input voltage at 1000pF *D5
+
C2 C3
4 B OUT
50% of Vcc under nominal conditons B OUT
RSENSE B 5
22F
TANT
0.1F
*D6
R5, C1 Snubber network
R2
R1, R2 Current sensing resistors or jumpered to ground +Vs
C4
0.1 J2
3W
6.8F
POLY
PARTS LIST
Part # Description Quantity * D1 and D2 Input protection, high speed such as IN4148.
D3 through D6 Flyback protection, high speed (<200nS).
EK-SA50PC P.C. Board 1
Solder as close to SA50 as possible.
HS14 Heatsink 1
MS03 Mating Socket 1
TW03 Thermal Washers 1 bag of 10 3"
76.2mm
C
5.2"
132.1mm
NOTE: Illustration only, not to exact scale.
however, FAXis(520)
ORDERS (520) 690-8601
EK-SA50U REV. C JANUARY 1998 1998 Apex Microtechnology Corp.
122
TABLE 4 GROUP A INSPECTION
SA50M
SG PARAMETER SYMBOL TEMP. POWER TEST CONDITIONS MIN MAX UNITS
1 Quiescent Current IQ 25C +28Vdc VIN = 6Vdc 20 mA

1 ON Voltage VDS 25C +28Vdc ID = 5A 1.8 V
1 OFF Leakage IDSS 25C +70Vdc Output off, VDS = 70V 25 A


2 OFF Leakage IDSS 125C +70Vdc Output OFF, VDS = 70V 250 A
4 Switching Frequency FS 25C +28Vdc VIN = 6Vdc 41 49 Khz

4 Duty Cycle A DC A 25C +28Vdc VIN = 6Vdc 40 60 %
4 Duty Cycle B DC B 25C +28Vdc VIN = 6Vdc 40 60 %
6 Switching Frequency FS 55C +28Vdc VIN = 6Vdc 40 50 Khz
5 Switching Frequency FS 125C +28Vdc VIN = 6Vdc 40 50 Khc
7 Duty Cycle A DC A 25C +28Vdc VIN = 3Vdc, verify 0% duty cycle Pass/Fail
7 Duty Cycle A DC A 25C +28Vdc VIN = 9Vdc, verify 100% duty cycle Pass/Fail
7 Duty Cycle B DC B 25C +28Vdc VIN = 3Vdc, verify 0% duty cycle Pass/Fail
7 Duty Cycle B DC B 25C +28Vdc VIN = 9 Vdc, verify 100% duty cycle Pass/Fail
1/VCC=+12Vdc, RSENSE A, B = Ground, RL = 1K ohm, AOUT to BOUT
BURN IN CIRCUIT +12V
R1
1 8 DEVICE
INPUT
2 7 R2
DEVICE
OUTPUT
+28V
3 DUT 6
+12V
C2
C1
R3
4 5
without notice.
SA50MU REV. A JANUARY 1998 1998 Apex Microtechnology Corp.
123
H/BRIDGE MOTOR DRIVER/AMPLIFIER
SA51
FEATURES
LOW COST COMPLETE H-BRIDGE
SELF-CONTAINED SMART LOWSIDE/HIGHSIDE DRIVE
CIRCUITRY
WIDE SUPPLY RANGE: UP TO 80V
HIGH EFFICIENCY: 97%
FOUR QUADRANT OPERATION, TORQUE
CONTROL CAPABILITY
APPLICATIONS
BRUSH TYPE MOTOR CONTROL TYPICAL APPLICATION
CLASS D SWITCHMODE AMPLIFIER +VS
REACTIVE LOADS
MAGNETIC COILS (MRI) Vcc
ACTIVE MAGNETIC BEARING
VIBRATION CANCELLING PWM C
INPUT
SA51
DESCRIPTION
The SA51 is a pulse width modulation amplifier that can DISABLE
SPEAKER
supply 5A continuous current to the load. The full bridge INPUT
amplifier can be operated over a wide range of supply volt-
ages. All of the drive/control circuitry for the lowside and
GND
highside switches are internal to the hybrid. The user provides
a TTL compatible PWM signal for simultaneous amplitude and
direction control in four quadrant mode. The internal circuitry
will provide proper deadtime protection for each half bridge. All +VS
N-channel FETs mean the best efficiency for the size, both in Vcc
terms of on-resistance and switching capability. For an idle/
sleep mode or for fault protection, a TTL compatible disable pin
is provided so as to shut down all four transistors. The SA51 PWM
is packaged in a space efficient isolated 8-pin TO-3 that can be INPUT
directly connected to a heatsink. SA51
DISABLE DC MOTOR
BLOCK DIAGRAM +VS
INPUT
GND
(LOAD) EXTERNAL CONNECTIONS

B A B OUT
VCC 2
3 +VS
1
VCC
(+12V) DISABLE 4
TOP VIEW
DISABLE GND 5
H-BRIDGE RSENSE 8
DRIVE (CURRENT) 6 RSENSE
(PWM) INPUT CIRCUITRY INPUT 7
A OUT
GND
124
SA51 SPECIFICATIONS

LOGIC SUPPLY VOLTAGE, Vcc 16V
INPUT VOLTAGE, INPUT 0 to Vcc
INPUT VOLTAGE, DIS 0 to Vcc
SPECIFICATIONS
INPUT
PWM PULSE LOW VOLTAGE 0 0.6 Vdc
PWM PULSE HIGH VOLTAGE 3.6 5.0 Vdc
PWM FREQUENCY 45 500 KHz
DISABLE ON 3.6 VCC Vdc
DISABLE OFF 0 0.6 Vdc
OUTPUT
Vds (ON) VOLTAGE, each MOSFET Ids = 5A 1.25 1.8 Vdc
TOTAL Ron, both MOSFETs 0.5
EFFICIENCY, 5A OUTPUT +VS = 80V 97 %
CURRENT, peak T = 100ms 7 A
SWITCHING CHARACTERISTICS4 +VS = 28V, Vcc = 12V, Ic =2A
RISE TIME 36 54 nS
FALL TIME 170 250 nS
DEAD TIME 100 nS
POWER SUPPLY
+VS VOLTAGE +VS Current = Load Current 80 Vdc
Vcc VOLTAGE 9 12 16 Vdc
Vcc CURRENT Vcc = 12Vdc 11 18 mA
THERMAL3
TEMPERATURE RANGE, case 25 +85 C
2. Unless otherwise noted: TC = 25C, Vcc = 12Vdc.
CAUTION
WARNINGAMPLIFIER PROTECTION
The SA51 contains an internal logic chip that turns on and thus destroying the SA51. A well laid out PC board with low
turns off output MOSFET drivers at a certain sequence. Noise impedance copper ground plane is necessary for the
or oscillation caused by external wiring inductance, lack of SA51 to function properly. The Apex EK-SA51 evaluation
proper power supply bypass capacitors, ground, supply, and board is recommended for fast and easy breadboarding of
local internal loops may be fed back to this logic chip and cause circuits using the SA51.
it to turn on one or more MOSFET drivers at the wrong time,
125
TYPICAL PERFORMANCE
GRAPHS SA51
Typical performance curves with Vcc = 12V, PWM at 45kHZ and case temperature at 25C, unless otherwise specified.
POWER DERATING INPUT CURRENT VS TEMP EFFICIENCY CONTOURS
60 1.05 80
%
0.95 70 97
PWM BIAS CURRENT, (A)
SUPPLY VOLTAGE, VS (V)

50
0.85 60
40
0.75 50
95%
30 0.65 40
0.55 30
20 90%
0.45 20
10 80%
0.35 10
EACH OUTPUT TRANSISTOR
0 70%
0.25 0
0 25 50 75 100 125 40 20 0 20 40 60 80 100 120 1 2 3 4 5
CASE TEMPERATURE, T C (C) CASE TEMPERATURE, (C) LOAD CURRENT, (A)
EFFICIENCY VS TEMP @ 80V EFFICIENCY VS TEMP @ 20V EFFICIENCY VS LOAD CURRENT

100 100 100
99 95 VS = 80
IOUT = 1 IOUT = 1 V
A, V = 80V A, V = 20V 97
98 S S
EFFICIENCY, (%)
EFFICIENCY, (%)
EFFICIENCY, (%)
90 VS =
60V
97 IO
UT 85 IO 94 VS =
40V
C
96 = UT
5A =
,V 80 5A
,V 91
95 S = S
80 = V
V 75 20 S
94 V =2
88 0V
93 70
92 65 85
60 20 20 60 100 140 180 60 20 20 60 100 140 180 1 2 3 4 5
JUNCTION TEMPERATURE (C) JUNCTION TEMPERATURE (C) LOAD CURRENT, (A)
OUTPUT RESISTANCE DRIFT H-BRIDGE FET CAPACITANCE QUIESCENT CURRENT VS VOLTAGE

OUTPUT RESISTANCE, (NORMALIZED)
2.5 500
14.0
DRAIN-TO-SOURCE CAP, (pF)
2 400
12.0
1.5 300 10.0
8.0
1 200
6.0
0.5 100
4.0
0 0 2.0
60 20 20 60 100 140 180 1 2 5 10 20 50 100 8 9 10 11 12 13 14 15
JUNCTION TEMPERATURE (C) DRAIN-TO-SOURCE VOLTAGE, (V) Vcc VOLTAGE (V)
VOLTAGE DROP (BOTH MOSFETS) QUIESCENT CURRET VS PWM FREQ

5 15
CASE TEMPERATURE
4 14
VOLTAGE DROP, (V)
85C
3 110C 13
2 12
60C
1 35C 11
0 10
0 1 2 3 4 5 0 200 400 600
OUTPUT CURRENT, (A) PWM FREQUENCY (Hz)
126
OPERATING
SA51 CONSIDERATIONS
GENERAL Below is a diagram of a typical application of the SA51. The

design Vcc voltage is +12 volts and should have a low ESR
bypass capacitor such as a tantalum electrolytic. The PWM
mounting can be found in the General Operation Consider-
and DISABLE signals are typically provided by some type of
ations section of the Apex data book. For information on the
microprocessor control. The PWM signal will be a TTL signal
package outline, heatsinks, and mounting hardware, see the
with a pulse frequency required by the system, and pulse duty
Package Outlines and Accessories section of the data
cycles according to the required direction/speed. A 0% duty
book. Also see application Note 30 on PWM Basics.
cycle (continuous TTL low) will mean full voltage to the motor
in one direction. A 100% duty cycle (continuous TTL high) will
PIN DESCRIPTION mean full voltage to the motor in the other direction. A 50% duty
VCC - is the low voltage supply for powering internal logic cycle will hold the motor at 0 RPM.
and drivers for the lowside and highside MOSFETS. The Current sensing is done in this case by a 0.1 ohm sense
supplies for the highside drivers are derived from this voltage. resistor to sense current from either leg of the bridge. It is
VS - is the higher voltage H-bridge supply. The MOSFETS important to make the high current traces as wide as possible
obtain the output current from this supply pin. The voltage on to keep inductance down. The storage capacitor connected to
this pin is limited to +80V by the drive IC. The MOSFETS are the +Vs and the hybrid GND should be large enough to provide
rated at 100 volts. Proper by-passing to GND with sufficient the high energy pulse without the voltage sagging too far. The
capacitance to suppress any voltage transients, and to ensure storage capacitor should be a low ESR ceramic capacitor or
removing any drooping during switching, should be done as large polypropylene capacitor. Mount capacitor as close to the
close to the pins on the hybrid as possible. hybrid as possible. The connection between GND and the +Vs
A OUT - is the output pin for one half of the bridge. When the return should not be carrying any motor current. The sense
PWM input is high, this output will be pulled up to Vs. resistor signal is common mode filtered as necessary to feed
B OUT - is the output pin for the other half of the bridge. the limiting circuitry for the microprocessor. This application
When the PWM input is low, this output will be pulled up to Vs. will allow full four quadrant torque control for a closed loop
RSENSE - This is the common connection for the bottom of servo system.
the bridge. This can have a sense resistor connected to the Vs A snubber network is usually required, due to the inductance
return ground for current limit sensing, or can be connected in the power loop. It is important to design the snubber network
directly to ground. The maximum voltage on this pin is 2 volts to suppress any positive spikes above +VS and negative spikes
with respect to GND. below -2V with respect to Pin 5 (GND) of the hybrid.
GND - is the return connection for the input logic and Vcc.
PWM INPUT - is a TTL compatible input pin for providing the
PWM signal to modulate the output switches. The duty cycle
can be between 0% (DC low) and 100% (DC high).
DISABLE INPUT - is a TTL compatible input for providing a
shutdown signal to the hybrid for disabling all four switches in
the bridge regardless of the PWM input level. A digital 1
disables, a digital 0 enables. +12V +VS
TYPICAL SYSTEM OPERATION 1

3 +VS
Vcc SNUBBER NETWORK
22F MOTOR A
7 100
MOTOR
SA51 2W
6 PWM 1000pF
INPUT 200V
MICRO- 2
CONTROLLER MOTOR B
4 DISABLE MYLAR 6.8F
INPUT 100V
POLY
5 GND RSENSE 8
CURRENT SENSE
SENSE 270 RESISTOR
4700pF
AMP 270 0.1
A/D CONV.
DIGITAL
CURRENT NO OUTPUT
INFORMATION SWITCHING V+ RETURN
IF LONG LENGTH, GND CURRENT
TWISTED PAIR
This data sheet has been carefullyCORPORATION 5980
checked and is believed NORTH
without notice.
127
SA51M
1 Quiescent Current IQ 25C +28Vdc PWM Not switching 18 mA

1 Input Voltage Threshold VINTH 25C +28Vdc Input increased until AOUT and BOUT change 0.8 2.7 V
state

state

2 OFF Leakage IDSS 125C +70Vdc Output OFF, VDS = 70V 250 A
state
4 Operating Supply Current IS 25C +28Vdc PWM = 500khz TTL 60 mA
7 Disable Function DIS 25C +28Vdc Disable > 3.6V, PWM input=500KHz, Pass/Fail C
verify no switching
1/VCC=+12Vdc, RSENSE = Disable = Ground, RL = 1K ohm, AOUT to BOUT
BURN IN CIRCUIT
R2
12V +12V
1 8 1
+28V
C2 7 DEVICE CELL 2 R1
2 OUTPUT
DUT NE555
DEVICE CELL
3 INPUT R3
+12V 6 3
C3
4 5 C4 C5
4
12V
C1
however, FAXis(520)
ORDERS (520) 690-8601
SA51MU REV. A JANUARY 1998 1998 Apex Microtechnology Corp.
128
EVALUATION KIT FOR SA51
EK-SA51

Fast, easy breadboarding of circuits using the SA51 are possible
with the EK-SA51 PC board. Mounting holes are provided and the +Vs Vs
R4
provision for standard banana jacks simplifies connection and C4 J1
*D4 100
*D1 6.8F
testing. Components are labeled on both sides of the board for ease POLY R1
2W
1 8
in probing. +Vs RSENSE C1
0.1 3W 1000pF
2 7
B OUT B OUT A OUT
TYPICAL COMPONENT FUNCTIONS *D2 SA51 *D3 A OUT
TO-3
C2, C3, C4 Power supply bypass capacitors VCC
3
VCC INPUT
6
INPUT
R4, C1 Snubber network +
4
DISABLE GND 5 R3
R1 Current sensing resistor or jumpered to ground C3
22F
C2
0.1F
10K
1/4W
R2, R3 Input resistors TANT
DISABLE
R2
PARTS LIST 10K * High Speed (<200 nS) for flyback protection.
1/4W Voltage and current to suit application.
Part # Description Quantity Solder as close to SA51 as possible.
EK-SA51PC P.C. Board 1
HS14 Heatsink 1
TW03 Thermal Washers 1 bag of 10
3"
76.2mm
5.2"
132.1mm
without notice.
EK-SA51U REV. C JANUARY 1998 1998 Apex Microtechnology Corp.
129
PA01 PA73
FEATURES
LOW COST, ECONOMY MODEL PA01
SECOND SOURCEABLE PA73
HIGH OUTPUT CURRENT Up to 5A PEAK
EXCELLENT LINEARITY PA01
HIGH SUPPLY VOLTAGE Up to 30V
ISOLATED CASE 300V
APPLICATIONS
MOTOR, VALVE AND ACTUATOR CONTROL TYPICAL APPLICATION
MAGNETIC DEFLECTION CIRCUITS UP TO 4A CF
POWER TRANSDUCERS UP TO 20kHz +6V RCL +
TEMPERATURE CONTROL UP TO 180W VIN R IN .33
PROGRAMMABLE POWER SUPPLIES UP TO 48V 3W
AUDIO AMPLIFIERS UP TO 50W RMS 0/+5V PA01
1N4148
RCL
DESCRIPTION
The PA01 and PA73 are high voltage, high output current 30V
.33 C
3W
operational amplifiers designed to drive resistive, inductive OPTO
F/V PULSE M 24V
and capacitive loads. For optimum linearity, the PA01 has a RF GEN.
class A/B output stage. The PA73 has a simple class C output 0/5V
stage (see Note 1) to reduce cost for motor control and other UNSYMMETRICAL SUPPLIES FOR EFFICIENCY
applications where crossover distortion is not critical and to
provide interchangeability with type 3573 amplifiers. The safe Unidirectional Optical Speed Control
operating area (SOA) can be observed for all operating condi- The pulse output of a non-contact optical sensor drives a
tions by selection of user programmable current limit resistors. voltage-to-frequency converter which generates feedback for
These amplifiers are internally compensated for all gain set- the op amp. With the loop closed in this manner, the op amp
tings. For continuous operation under load, a heatsink of corrects for any variations in the speed due to changing load.
proper rating is recommended. Because of operation in only one direction, an unsymmetrical
This hybrid integrated circuit utilizes thick film (cermet) supply is used to maximize efficiency of both power op amp
resistors, ceramic capacitors and semiconductor chips to and power supply. High speed diodes at the input protect the
maximize reliability, minimize size and give top performance. op amp from commutator noise which may be generated by
Ultrasonically bonded aluminum wires provide reliable inter- the motor.
connections at all operating temperatures. The 8-pin TO-3
package is hermetically sealed and electrically isolated. The EQUIVALENT SCHEMATIC
use of compressible thermal washers and/or improper mount-
3
ing torque will void the product warranty. Please see General
Operating Considerations. Q2A
D1 * * Q2B
EXTERNAL CONNECTIONS 2
Q1 *
Q3
R CL+
CL+ 1
+VS
2 OUT *
3
1 Q4 * Q5
OUTPUT 8
+IN
4
TOP VIEW 4 *
Q6B
A1 Q6A
IN 5
5
8
CL R CL C1
6
7
VS 6
N.C. NOTE 1: * Indicates not used in PA73. Open base of Q2A connected to
output of A1.
130
PA01 PA73 SPECIFICATIONS
PA01 PA73
ABSOLUTE MAXIMUM RATINGS SUPPLY VOLTAGE, +VS to VS 60V 68V
OUTPUT CURRENT, within SOA 5A 5A
POWER DISSIPATION, internal 67W 67W
INPUT VOLTAGE, differential VS 3V VS 3V
INPUT VOLTAGE, common-mode VS VS
TEMPERATURE, junction1 200C 200C
TEMPERATURE, pin solder -10s 300C 300C
TEMPERATURE RANGE, storage 65 to +150C 65 to +150C
OPERATING TEMPERATURE RANGE, case 25 to +85C 25 to +85C
SPECIFICATIONS PA01 PA73

2
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
INPUT
OFFSET VOLTAGE, initial TC = 25C 5 12 * 10 mV
OFFSET VOLTAGE, vs. temperature Full temperature range 10 65 * * V/C
OFFSET VOLTAGE, vs. supply TC = 25C 35 * 200 V/V
OFFSET VOLTAGE, vs. power TC = 25C 20 * V/W
BIAS CURRENT, initial TC = 25C 15 50 * 40 nA
BIAS CURRENT, vs. temperature Full temperature range .05 .4 * * nA/C
BIAS CURRENT, vs. supply TC = 25C .02 * nA/V
OFFSET CURRENT, initial TC = 25C 5 15 * 10 nA
OFFSET CURRENT, vs. temperature Full temperature range .01 * nA/C
INPUT IMPEDANCE, common-mode TC = 25C 200 * M
INPUT IMPEDANCE, differential TC = 25C 10 * M
INPUT CAPACITANCE TC = 25C 3 * pF
COMMON MODE VOLTAGE RANGE3 Full temperature range VS6 VS3 * * V
COMMON MODE REJECTION, DC3 TC = 25C, VCM = VS 6V 70 110 * * dB
GAIN
OPEN LOOP GAIN at 10Hz Full temp. range, full load 91 113 * * dB
GAIN BANDWIDTH PRODUCT @ 1MHz TC = 25C, full load 1 * MHz
POWER BANDWIDTH TC = 25C, IO = 4A, VO = 40VPP 15 23 * * kHz
PHASE MARGIN Full temperature range 45 *
OUTPUT
VOLTAGE SWING3 TC = 25C, IO = 5A VS10 VS5 VS8 * V
VOLTAGE SWING3 Full temp. range, IO = 2A VS6 VS5 * * V
VOLTAGE SWING3 Full temp. range, IO = 46mA VS5 * V
CURRENT, peak TC = 25C 5 * A
SETTLING TIME to .1% TC = 25C, 2V step 2 * s
SLEW RATE TC = 25C, RL = 2.5 1.0 2.6 * * V/s
CAPACITIVE LOAD, unity gain Full temperature range 3.3 * nF
CAPACITIVE LOAD, gain > 4 Full temperature range SOA *
POWER SUPPLY
VOLTAGE Full temperature range 10 28 28 * * 30 V
CURRENT, quiescent TC = 25C 20 50 2.6 5 mA
THERMAL
RESISTANCE, AC, junction to case4 F > 60Hz 1.9 2.1 * * C/W
RESISTANCE, DC, junction to case F < 60Hz 2.4 2.6 * * C/W
RESISTANCE, junction to air 30 * C/W
TEMPERATURE RANGE, case Meets full range specifications 25 25 +85 * * * C
NOTES: * The specification of PA73 is identical to the specification for PA01 in applicable column to the left.
to achieve high MTTF.
2. The power supply voltage specified under the TYP rating applies unless otherwise noted as a test condition.
3. +VS and VS denote the positive and negative supply rail respectively. Total VS is measured from +VS to VS.
4. Rating applies if the output current alternates between both output transistors at a rate faster than 60Hz.
CAUTION subject to temperatures in excess of 850C to avoid generating toxic fumes.
131
TYPICAL PERFORMANCE
GRAPHS PA01 PA73
POWER DERATING BIAS CURRENT CURRENT LIMIT

INTERNAL POWER DISSIPATION, P(W)
70
NORMALIZED BIAS CURRENT, I B (X)

2.8 3.5
60 2.5 3.0
CURRENT LIMIT, I LIM (A)

50 2.2 2.5
R CL = 0.3
40 1.9 2.0
T = TC
30 1.6 1.5 R CL = 0.6
20 1.3 1.0
10 T = TA 1.0 .5
0 .7 0
0 20 40 60 80 100 120 140 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125
TEMPERATURE, T(C) CASE TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C)
SMALL SIGNAL RESPONSE PHASE RESPONSE POWER RESPONSE

120 0 100
OUTPUT VOLTAGE, VO (VPP )

OPEN LOOP GAIN, AOL (dB)
100 30 68
|+VS | + |-VS | = 60V
60 46
80
PHASE, ()
32
60 90 C
22
40 120
15
20 150
10
0 180
6.8
20 210 4.6
1 10 100 1K 10K .1M 1M 10M 1 10 100 1K 10K .1M 1M 10M 10K 20K 30K 50K 70K .1M
FREQUENCY, F (Hz) FREQUENCY, F (Hz) FREQUENCY, F (Hz)
COMMON MODE REJECTION PULSE RESPONSE INPUT NOISE

COMMON MODE REJECTION, CMR (dB)
INPUT NOISE VOLTAGE, VN (nV/ Hz)
120 8 100
VIN = 5V, t r = 100ns
6
OUTPUT VOLTAGE, VO (V)
100 70
PA01
4
50
80
2 40
60 0 30
for PA73
2
40 20
4
20
6
0 8 10
1 10 100 1K 10K .1M 1M 0 2 4 6 8 10 12 10 100 1K 10K .1M
FREQUENCY, F (Hz) TIME, t (s) FREQUENCY, F (Hz)
HARMONIC DISTORTION QUIESCENT CURRENT OPEN LOOP GAIN

3 1.3 +6
W W
m m
1 50 50 1.2 +4
NORMALIZED, AOL (dB)
= =
NORMALIZED, IQ (X)
PO PO
DISTORTION (%)
.3 @ @ 1.1 +2
73 0 1 T C = 25C
C
PA PA @ 85
.1 1.0 PA01
C 0
W
to +25 C TC = 25C
32
@ 25 85 TC = 85C
W
VS = 28V PA01 @ 25 to +
=
32
.03 RL = 8 .9 2
PA73
O
P
=
@
AV = 10
O
P
73
.01 .8 4
PA
0 1
PA
.003 .7 6
100 300 1K 3K 10K 30K .1M 20 30 40 50 60 70 80 20 30 40 50 60 70 80
FREQUENCY, F (Hz) TOTAL SUPPLY VOLTAGE, VS (V) TOTAL SUPPLY VOLTAGE, VS (V)
132
OPERATING
PA01 PA73 CONSIDERATIONS
GENERAL
Please read the General Operating Considerations sec- supply rail with ILIM = 5A or 20V below the supply rail with ILIM
tion, which covers stability, supplies, heatsinking, mounting, = 2A while the amplifier is current limiting, the inductor
current limit, SOA interpretation, and specification interpreta- should be capacitively coupled or the current limit must be
tion. Additional information can be found in the application lowered to meet SOA criteria.
notes. For information on the package outline, heatsinks, and
mounting hardware, consult the Accessory and Package ** Second breakdown effect imposes no limitation but thermal
Mechanical Data section of the handbook. limitations must still be observed.
SAFE OPERATING AREA (SOA) 2. EMF generating or reactive load and short circuits to the
supply rail or shorts to common are safe if the current limits
The output stage of most power amplifiers has three distinct
are set as follows at TC = 85C.
limitations:
1. The current handling capability of the transistor geometry SHORT TO VS SHORT TO
and the wire bonds. VS C, L, OR EMF LOAD COMMON
2. The second breakdown effect which occurs whenever the
34V .50A 1.2A
simultaneous collector current and collector-emitter voltage
30V .60A 1.3A
exceeds specified limits.
25V .75A 1.6A
3. The junction temperature of the output transistors.
20V 1.0A 2.1A
15V 1.3A 2.8A
5.0
OUTPUT CURRENT FROM +V S OR VS (A)
4.0 T
C =2 These simplified limits may be exceeded with further analysis
t=
5C
1m
3.0 TC
using the operating conditions for a specific application.
s
=8
t=
5C
5m
3. The output stage is protected against transient flyback.

s
2.0
However, for protection against sustained, high energy
1.5 flyback, external fast-recovery diodes should be used.
st
ea
dy
1.0 st CURRENT LIMIT
at
e
Proper operation requires the use of two current limit resis-
.7 tors, connected as shown, in the external connection diagram.
.5 The minimum value for RCL is 0.12 ohm; however, for optimum
reliability it should be set as high as possible. Refer to the
.4 General Operating Considerations section of the handbook
PA01 LIMIT
.3 for current limit adjust details.
10 20 25 30 35 40 50 60 70
SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE V S VO (V)
The SOA curves combine the effect of these limits. For a

given application, the direction and magnitude of the output
current should be calculated or measured and checked against
the SOA curves. This is simple for resistive loads but more
complex for reactive and EMF generating loads. The following
guidelines may save extensive analytical efforts.
1. Capacitive and dynamic* inductive loads up to the following
maximums are safe with the current limits set as specified:
CAPACITIVE LOAD INDUCTIVE LOAD
VS ILIM = 2A ILIM = 5A ILIM = 2A ILIM = 5A
30V 1,200F 500F 250mH 24mH
25V 4000F 1,600F 400mH 38mH
20V 20,000F 5,000F 1,500mH 75mH
15V ** 25,000F ** 100mH
* If the inductive load is driven near steady state conditions,

allowing the output voltage to drop more than 8V below the
omissions. HOTLINE:
change 546-2739
without notice.
PA01, 73U REV. N DECEMBER 1997 1997 Apex Microtechnology Corp.
133
PA73M
1 Quiescent Current IQ 25C 28V VIN = 0, AV = 100 5 mA

1 Input Offset Voltage VOS 25C 28V VIN = 0, AV = 100 10 mV
1 Input Offset Voltage VOS 25C 10V VIN = 0, AV = 100 17.2 mV
1 Input Bias Current, +IN +IB 25C 28V VIN = 0 40 nA
1 Input Bias Current, IN IB 25C 28V VIN = 0 40 nA
1 Input Offset Current IOS 25C 28V VIN = 0 10 nA

3 Input BiasCurrent, IN IB 55C 28V VIN = 0 72 nA

2 Input Bias Current, +IN +IB 125C 28V VIN = 0 80 nA C
4 Output Voltage, IO = 5A VO 25C 18.3V RL = 2.07 10.3 V

4 Output Voltage, IO = 50mA VO 25C 30V RL = 500 25 V
4 Output Voltage, IO = 2A VO 25C 30V RL = 12 24 V
4 Current Limits ICL 25C 18V RL = 12, RCL = 1 .54 .86 A
4 Stability/Noise EN 25C 28V RL = 500, AV = 1, CL = 10nF 1 mV
4 Slew Rate SR 25C 28V RL = 500 1 10 V/s
4 Open Loop Gain AOL 25C 28V RL = 500, F = 10Hz 91 dB
4 Common Mode Rejection CMR 25C 15V RL = 500, F = DC, VCM = 9V 70 dB


5 Stability/Noise EN 125C 28V RL = 500, AV= 1, CL = 10nF 1 mV
100K
BURN IN CIRCUIT * These components are used to stabilize device

+15V due to poor high frequency characteristics of
1
100K burn in board.
5 3
2
* 1 ** Input signals are calculated to result in internal
U.U.T power dissipation of approximately 2.1W at
** * 4 8 case temperature = 125C.
6 20
1
15V
however, FAXis(520)
ORDERS (520) 690-8601
PA73MU REV. E FEBRUARY 1998 1998 Apex Microtechnology Corp.
134
NOTES:
135
PA02 PA02A
FEATURES
HIGH POWER BANDWIDTH 350kHz
HIGH SLEW RATE 20V/s
FAST SETTLING TIME 600ns
LOW CROSSOVER DISTORTION Class A/B
LOW INTERNAL LOSSES 1.2V at 2A
HIGH OUTPUT CURRENT 5A PEAK
LOW INPUT BIAS CURRENT FET Input
ISOLATED CASE 300 VDC
TYPICAL APPLICATION
APPLICATIONS
Vehicular Sound System Power Stage
MOTOR, VALVE AND ACTUATOR CONTROL 100K
MAGNETIC DEFLECTION CIRCUITS UP TO 5A +12 RCL+
POWER TRANSDUCERS UP TO 350 kHz
.47F 16K
AUDIO AMPLIFIERS UP TO 30W RMS .27
1K
DESCRIPTION .001F
PA02
IN
The PA02 and PA02A are wideband, high output current
operational amplifiers designed to drive resistive, inductive 3.2 C
.47F RCL 16W
and capacitive loads. Their complementary collector output 16K
stage can swing close to the supply rails and is protected .27
against inductive kickback. For optimum linearity, the output 12
stage is biased for class A/B operation. The safe operating LOW INTERNAL LOSS MAXIMIZES EFFICIENCY
area (SOA) can be observed for all operating conditions by
selection of user programmable, current limiting resistors
(down to 10mA). Both amplifiers are internally compensated When system voltages are low and power is at a premium,
but are not recommended for use as unity gain followers. For the PA02 is a natural choice. The circuit above utilizes not only
continuous operation under load, mounting on a heatsink of the feature of low internal loss of the PA02, but also its very low
proper rating is recommended. distortion level to implement a crystal clear audio amplifier
These hybrid integrated circuits utilize thick film (cermet) suitable even for airborne applications. This circuit uses AC
resistors, ceramic capacitors and semiconductor chips to coupling of both the input signal and the gain circuit to render
maximize reliability, minimize size and give top performance. DC voltage across the speaker insignificant. The resistor and
Ultrasonically bonded aluminum wires provide reliable inter- capacitor across the inputs form a stability enhancement
connections at all operating temperatures. The 8-pin TO-3 network. The 0.27 ohm current limit resistors provide protec-
package is hermetically sealed and electrically isolated. tion in the event of an output short circuit.
Isolation washers are not recommended. The use of com-
pressible thermal washers and/or improper mounting torque
will void the product warranty. Please see General Operat- EXTERNAL CONNECTIONS
ing Considerations.
RCL+
EQUIVALENT SCHEMATIC +VS
OUT 2
2 3 CL+
R1 1
Q1 D1
R5
4
R2 R3 R7 OUT
R6
Q2 TOP VIEW
1
R4 Q3 5
Q4 3 IN
8
6 6
R15 CL RCL
A1 +IN 7
5 VS
4
Q5
R8 Q6
8
Q7 R13 R14
R9 R10 R12
Q8
D2
R11
7
136
PA02 PA02A SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS SUPPLY VOLTAGE, +VS to VS 38V

OUTPUT CURRENT, within SOA 5A
POWER DISSIPATION, internal1 48W
INPUT VOLTAGE, differential VS 5V
INPUT VOLTAGE, common mode VS 2V
TEMPERATURE RANGE, storage 65 to +150C
SPECIFICATIONS PA02 PA02A

2, 6
INPUT
OFFSET VOLTAGE, initial TC = 25C 5 10 1 3 mV
OFFSET VOLTAGE, vs. temperature Full temperature range 10 50 * 25 V/C
OFFSET VOLTAGE, vs. supply TC = 25C 10 * V/V
BIAS CURRENT, initial TC = 25C 50 200 25 100 pA
BIAS CURRENT, vs. temperature TC = 85C 200 * pA/C
BIAS CURRENT, vs. supply TC = 25C .01 * pA/V
OFFSET CURRENT, initial TC = 25C 25 100 15 50 pA
OFFSET CURRENT, vs. temperature TC = 85C 100 * pA/C
INPUT IMPEDANCE, DC TC = 25C 1000 * G
COMMON MODE VOLT. RANGE5, Pos. Full temperature range +VS 6 +VS 3 * * V
COMMON MODE VOLT. RANGE5, Neg. Full temperature range VS +6 VS +5 * * V
COMMON MODE REJECTION, DC Full temperature range 70 100 * * dB
GAIN
OPEN LOOP GAIN at 10Hz TC = 25C, 1k load 103 * dB
OPEN LOOP GAIN at 10Hz Full temp. range, 10k load 86 100 * * dB
GAIN BANDWIDTH PRODUCT at 1MHz TC = 25C, 10 load 4.5 * MHz
POWER BANDWIDTH TC = 25C, 10 load 350 * kHz
PHASE MARGIN Full temp. range, 10 load 30 *
OUTPUT
VOLTAGE SWING3 TC = 25C, IO = 5A, RCL = .08 VS 4 VS 3 * * V
VOLTAGE SWING3 Full temp. range, IO = 2A VS 2 VS 1.2 * * V
SETTLING TIME to .1% TC = 25C, 2V step .6 * s
SLEW RATE TC = 25C 13 20 * * V/s
CAPACITIVE LOAD Full temp. range, AV > 10 SOA *
HARMONIC DISTORTION PO = .5W, F = 1kHz, RL = 10 .004 * %
SMALL SIGNAL rise/fall time RL = 10, AV = 1 100 * ns
SMALL SIGNAL overshoot RL = 10, AV = 1 10 * %
POWER SUPPLY
VOLTAGE Full temperature range 7 15 19 * * * V
CURRENT, quiescent TC = 25C 27 40 * * mA
THERMAL
RESISTANCE, AC junction to case4 F > 60Hz 1.9 2.1 * * C/W
RESISTANCE, DC junction to case F < 60Hz 2.4 2.6 * * C/W
TEMPERATURE RANGE, case Meets full range specifications 25 +85 55 +125 C
NOTES: * The specification of PA02A is identical to the specification for PA02 in applicable column to the left.
2. The power supply voltage for all specifications is the TYP rating unless otherwise noted as a test condition.
5. Exceeding CMV range can cause the output to latch.
6. Full temperature specifications are guaranteed but not 100% tested.
137
TYPICAL PERFORMANCE
GRAPHS PA02 PA02A
POWER DERATING OUTPUT VOLTAGE SWING CURRENT LIMIT

50 3.5 3.0
SATURATION VOLTAGE, VS VO (V)

3.0 2.5
40

T=TC RCL = 0.3
2.5 2.0
30 TC = 25 to 85C
2.0 1.5
20 RCL = 0.62
1.5 1.0
VO
10 1.0 .5
T=TA
0 .5 0
0 25 50 75 100 125 150 0 1 2 3 4 5 25 0 25 50 75 100 125
TEMPERATURE, T (C) OUTPUT CURRENT, I O(A) CASE TEMPERATURE, TC (C)

120 0 30
| +VS | + | VS | = 36V

100 30 23
80 60 18
PHASE, ()
60 90 | +VS | + | VS | = 30V C
13
40 120
10
20 150
0 180 7.8
20 210 6
1 10 100 1K 10K .1M 1M 10M 1 10 100 1K 10K .1M 1M 10M .1M .2M .3M .5M .7M 1M
BIAS CURRENT COMMON MODE REJECTION POWER SUPPLY REJECTION

POWER SUPPLY REJECTION, PSR (dB)
256 120 140

64 120
100
100
16
80 +VS
80
4
60
60
1 VS
40
40
.25 20
.06 20 0
15 5 25 45 65 85 105 1 10 100 1K 10K .1M 1M 10M 10 100 1K 10K .1M 1M 10M
CASE TEMPERATURE, TC (C) FREQUENCY, F (Hz) FREQUENCY, F(Hz)
NORMALIZED QUIESCENT CURRENT, IQ (X)
INPUT NOISE QUIESCENT CURRENT SETTLING TIME

INPUT NOISE VOLTAGE, en (nV/ Hz)
40 1.6 3
35
1.5
30 2.5
AD
1.4 LO
25 2 NO
TIME, t (S)
V
1.3 1m
20 1.5 AD
1.2 O LO
VN
1 10m
15 1.1 AD
0 LO
10mV 1
1.0 .5
10 .9 0
10 100 1K 10K .1M 25 0 25 50 75 100 125 1 2 3 4 5 6 7 8
FREQUENCY, F (Hz) CASE TEMPERATURE, TC (C) OUTPUT CHANGE FROM ZERO, VOLTS
138
OPERATING
PA02 PA02A CONSIDERATIONS
HARMONIC DISTORTION GENERAL

1
GAIN = 1
LOAD = 10 Please read the General Operating Considerations section which covers stability,
.3 supplies, heatsinking, mounting, current limit, SOA interpretation, and specification
DISTORTION, THD (%)
interpretation. Additional information can be found in the application notes. For

.1 information on the package outline, heatsinks, and mounting hardware, consult the
W Accessory and Package Mechanical Data section of the handbook.
m
.03 50
=
PO
W
SAFE OPERATING AREA (SOA)
.5
.01 = The SOA curves combine the
PO
OUTPUT CURRENT FROM +V OR VS (A)

W
effect of all limits for this Power 5.0 TC
.003 =5 Op Amp. For a given applica- 4.0 =2
t= O O
BR
PO 5C
SE AK
T
tion, the direction and magni-
5 m ND WN
3.0 C
E
=7
C
T
s
.001 tude of the output current should 0
C C
D
100 300 1K 3K 10K 30K .1M .3M 2.0 =1
be calculated or measured and 00
ST
FREQUENCY, F (Hz) T C
1.5
EA
checked against the SOA C =1
DY
curves. This is simple for resis- 25
PULSE RESPONSE 1.0 C
ST
15 tive loads but more complex for
AT
VIN = 1V, tr = 100ns reactive and EMF generating 0.7
E
LOAD = 10 TH
10 loads. The following guidelines 0.5 ER
MA
may save extensive analytical L
5 efforts: 0.3
1. Under transient conditions, 0.2
0 capacitive and dynamic* 2 3 5 7 10 15 20 25 30 40
loads up to the following maxi- SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE VS VO (V)
5 mums are safe:
10 CAPACITIVE LOAD INDUCTIVE LOAD
15 VS ILIM = 2A ILIM = 5A ILIM = 2A ILIM = 5A
0 1 2 3 4 5 18V 2mF 0.7mF .2H 10mH
TIME, t (S) 15V 10mF 2.2mF .7H 25mH
10V 25mF 10mF 5H 50mH
PULSE RESPONSE
.3
* If the inductive load is driven near steady state conditions, allowing the output voltage to drop more than 8V
VIN = .2V, tr = 50ns below the supply rail with ILIM = 5A, or 17V below the supply rail with ILIM = 2A while the amplifier is current
.2
limiting, the inductor should be capacitively coupled or the current limit must be lowered to meet SOA criteria.
.1 2. The amplifier can handle any EMF generating or reactive load and short circuits to
the supply rails or shorts to common if the current limits are set as follows at
0 TC = 85C.
SHORT TO VS SHORT TO
.1 VS C, L OR EMF LOAD COMMON
.2 18V .5A 1.7A
15V .7A 2.8A
.3 10V 1.6A 4.2A
0 .5 1.0 1.5
TIME, t (S) These simplified limits may be exceeded with further analysis using the operating
conditions for a specific application.
LOADING EFFECTS
0 CURRENT LIMIT
DELTA GAIN WITH LOAD, A (dB)
Proper operation requires the use of two current limit resistors, connected as shown
.3 in the external connection diagram. The minimum value for RCL is 0.12 ohm, however
IO = 150mA for optimum reliability it should be set as high as possible. Refer to the General
.6 Operating Considerations section of the handbook for current limit adjust details.
DEVICE MOUNTING
.9
The case (mounting flange) is electrically isolated and should be mounted directly to
IO = 400mA a heatsink with thermal compound. Screws with Belville spring washers are recom-
1.2 mended to maintain positive clamping pressure on heatsink mounting surfaces. Long
periods of thermal cycling can loosen mounting screws and increase thermal resis-
tance.
1.5
100 1K 10K .1M Since the case is electrically isolated (floating) with respect to the internal circuits it
FREQUENCY, F (Hz) is recommended to connect it to common or other convenient AC ground potential.
omissions. HOTLINE:
without notice.
PA02U REV. L FEBRUARY 1998 1998 Apex Microtechnology Corp.
139
PA02M
1 Quiescent current IQ 25C 15V VIN = 0, AV = 100, RCL = .2 40 mA

1 Input offset voltage VOS 25C 15V VIN = 0, AV = 100 10 mV
1 Input offset voltage VOS 25C 7V VIN = 0, AV = 100 11.6 mV
1 Input bias current, +IN +IB 25C 15V VIN = 0 200 pA
1 Input bias current, IN IB 25C 15V VIN = 0 200 pA
1 Input offset current IOS 25C 15V VIN = 0 100 pA


2 Input bias current, +IN +IB 125C 15V VIN = 0 30 nA C
2 Input bias current, IN IB 125C 15V VIN = 0 30 nA
2 Input offset current IOS 125C 15V VIN = 0 10 nA
4 Output voltage, IO = 5A VO 25C 9V RL = 1, RCL = 0 5 V

4 Output voltage, IO = 36mA VO 25C 19V RL = 500 18 V
4 Current limits ICL 25C 9V RL = 5, RCL = 1 .54 .86 A
4 Stability/noise EN 25C 15V RL = 500, AV = 1, CL = 1.5nF 1 mV
4 Slew rate SR 25C 18V RL = 500 13 100 V/s
4 Open loop gain AOL 25C 15V RL = 500, F = 10Hz 86 dB
4 Common mode rejection CMR 25C 8.25V RL = 500, F = DC, VCM = 2.25V 70 dB


5 Slew rate SR 125C 18V RL = 500 8.5 100 V/s
100K
BURN IN CIRCUIT
* These components are used to stabilize device due
+15V
1 to poor high frequency characteristics of burn in
100K board.
5
2
* 1 3,4 ** Input signals are calculated to result in internal
U.U.T power dissipation of approximately 2.1W at case
** 8
* 6 temperature = 125C.
7 20
1
15V
however, FAXis(520)
ORDERS (520) 690-8601
PA02MU REV. I FEBRUARY 1998 1998 Apex Microtechnology Corp.
140
REPLACING THE LH0101 WITH THE APEX PA02
PA02 DESIGN IDEAS

Background
In 1985, Apex first addressed inquiries on how the PA02 could be used to second source the LH0101. Now, because of Apexs
commitment to continue production of the PA02, it is the part of choice for most new designs. For retrofit situations, the PA02 can
be substituted for the LH0101 without requiring a PC layout change.
Comparing The LH0101 And The PA02

The PA02 can satisfy the majority of applications now using the 0101, and can often do it with improved frequency response,
linearity and distortion. The table below and the notes that follow compare the two devices.
Key Specification Comparison

LH0101 LH0101 LH0101 LH0101
K AK CK ACK PA02 PA02A PA02M Units
VOS, Initial 10 3 10 3 10 3 10 mV
VOS, vs. Temp 15 7 15 7 13 5.5 15 mV
Bias Current, Initial 1000 300 1000 300 200 100 200 pA
Offset Current, Initial 250 75 250 75 100 50 100 pA
Temp Range 55/+125 55/+125 25/+85 25/+85 25/+85 55/+125 55/+125 C
Power Bandwidth 300 300 300 300 350 350 350 kHz
Slew Rate (minimum) N/A 7.5 N/A 7.5 13 13 13 V/s
Distortion @ 0.5w, 0.008 0.008 0.008 0.008 0.004 0.004 0.004 %
1 kHz, 10 ohms (typical)
Note: The LH0101 is rated from 5V to 22V. The PA02 is rated from 7V to 19V. Do not use the PA02 below 7V
(14V total) or above 19V (38V total).
Pin-Out Comparison
LH0101 Function Pin No. PA02 Function
SC+ 1 RCL+
V+ 2 +VS
Feedback 3 Out
(Note 1) 4 Out
IN 5 IN
+IN 6 +IN
V 7 VS
SC 8 RCL
Out Case Isolated
Note 1: May be Out or N/C, depending on data sheet revision

The PA02 can often drop into the LH0101 socket and improve performance in the areas noted above. This drop in status applies
when the LH0101 does not employ the swing enhancement network. More simply stated, where Pin No. 3 is tied directly to the
output (i.e., the case), the 0101 and PA02 are often interchangeable. For circuits which do employ the swing enhancement, one
resistor should be removed and another replaced with a jumper. This retrofit saves parts and assembly cost and improves circuit
efficiency by eliminating the drop across each of the two resistors. In both cases, the case of the PA02 is tied to the output. This
is acceptable.
141
DROP IN EXAMPLE
LH0101 PA02
+VS +VS
CASE CASE
3 3
RL RL
5 5
VS VS
MODIFICATION EXAMPLE
LH0101 PA02
+VS +VS
CASE CASE
3 3
51 RL RL
J1
5 5
100
VS VS
C
REMOVE
Questions?
If you have questions, or would like further assistance converting your design to the
PA02, please call the Apex Applications Hotline at 1-800-546-2739.
however, FAXis(520)
ORDERS (520) 690-8601
or omissions. EMAIL are
PA02DIU REV. FEBRUARY 1998 1998 Apex Microtechnology Corp.
142
NOTES:
143
PA03 P03A
FEATURES
MO-127 COPPER POWER DIP PACKAGE
HIGH INTERNAL POWER DISSIPATION
500 watts
HIGH VOLTAGE OPERATION 75V
VERY HIGH CURRENT 30 amps
INTERNAL SOA PROTECTION
OUTPUT SWINGS CLOSE TO SUPPLY RAILS
EXTERNAL SHUTDOWN CONTROL
APPLICATIONS
LINEAR AND ROTARY MOTOR DRIVES TYPICAL APPLICATION
YOKE/MAGNETIC FIELD DEFLECTION POSITION
FEEDBACK
PROGRAMMABLE POWER SUPPLIES to 68V +VS
TRANSDUCER/AUDIO TO 1000W
RBAL
DESCRIPTION OBJECT
+ TOOL
The super power PA03 advances the state of the art in both
brute force power and self protection against abnormal oper-
+5V +S
C
SHUT DOWN S PA03
ating conditions. Its features start with a copper dip package
0/10V
developed by Apex to extend power capabilities well beyond DAC
those attainable with the familiar TO-3 package. The in- R1
creased pin count of the new package provides additional DESIRED VS
POSITION
control features, while the superior thermal conductivity of C1
copper allows substantially higher power ratings.
The PA03 incorporates innovative current limiting circuits R2
limiting internal power dissipation to a curve approximating the The PA03 output power stages contain fast reverse recov-
safe operating area of the power transistors. The internal ery diodes for sustained high energy flyback protection.
current limit of 35A is supplemented with thermal sensing This hybrid integrated circuit utilizes thick film resistors,
which reduces the current limit as the substrate temperature ceramic capacitors and silicon semiconductors to maximize
rises. Furthermore, a subcircuit monitors actual junction tem- reliability, minimize size and give top performance. Ultrasoni-
peratures and with a response time of less than ten millisec- cally bonded aluminum wires provide reliable interconnec-
onds reduces the current limit further to keep the junction tions at all operating temperatures. The MO-127 Copper,
temperature at 175C. 12-pin Power Dip package (see Package Outlines), is
The PA03 also features a laser trimmed high performance hermetically sealed and isolated from the internal circuits.
FET input stage providing superior DC accuracies both initially Insulating washers are not recommended.
and over the full temperature range. IMPORTANT: Observe mounting precautions.
+V
EQUIVALENT 8
BAL
SCHEMATIC 11
BAL
Q1 Q4
12
D1
Q2 Q3 Q6 Q7 Q9 D2
Q12
Q5 4 Q14
+SHUT 9 Q16 +
7
Q17 Q18 DOWN COMP OUT
Q19
1 Q20 Q20 10 6
Q22
A B Q24
3
SHUT
DOWN D3
+ Q30
2 Q29 Q32 Q26
Q31
Q34
D4
V
5
144
ABSOLUTE MAXIMUM RATINGS EXTERNAL CONNECTIONS

SUPPLY VOLTAGE, +VS to VS 150V
OUTPUT CURRENT, within SOA Internally limited
Pins 6 & 7 must be
POWER DISSIPATION, internal 500W INPUT BALANCE CONTROL connected together.
INPUT VOLTAGE, differential 25V +INPUT
1 12
BALANCE CONTROL If unused, tie Pins
INPUT VOLTAGE, common mode VS 2
TOP
11
PHASE COMP. 11 & 12 to +SUPPLY.
SHUT DN 3
TEMPERATURE, pin solder-10s 300C VIEW 10
+SHUT DN 4 9 PHASE COMP. IMPORTANT: OBSERVE
TEMPERATURE, junction1 175C MOUNTING PRECAUTIONS.
SUPPLY 5 8 +SUPPLY
TEMPERATURE RANGE, storage 65 to +150C REVERSE INSERTION
6 7 +OUTPUT
OPERATING TEMP. RANGE, case 55 to +125C OUTPUT WILL DESTROY UNIT.
SHUTDOWN VOLTAGE, differential 5V
SHUTDOWN VOLTAGE, common mode VS

PARAMETER TEST CONDITIONS 2 MIN TYP MAX MIN TYP MAX UNITS
INPUT
OFFSET VOLTAGE, initial TC = 25C .5 2 .25 .5 mV
OFFSET VOLTAGE, vs. temperature Full temperature range 10 30 5 10 V/C
OFFSET VOLTAGE, vs. power Full temperature range 20 10 V/W
OFFSET CURRENT, initial TC = 25C 2.5 50 1.5 10 pA
INPUT IMPEDANCE, DC TC = 25C 1011 *
COMMON MODE VOLTAGE RANGE3 Full temperature range VS 10V * V
COMMON MODE REJECTION, DC Full temp. range, VCM = 20V 86 108 * * dB
SHUTDOWN CURRENT4 Full temperature range 100 * A
SHUTDOWN VOLTAGE Full temp. range, amp enabled .85 * V
SHUTDOWN VOLTAGE Full temp. range, amp disabled 3.5 * V
GAIN
GAIN BANDWIDTH PRODUCT at 1MHz TC = 25C, full load 1 * MHz
POWER BANDWIDTH TC = 25C, IO = 15A, VO = 88VPP 30 * kHz
PHASE MARGIN Full temp. range, CC = 1.8nF 65 *
OUTPUT
VOLTAGE SWING3 TC = 25C, IO = 30A VS 7 6.2 * * V
VOLTAGE SWING3 Full temp. range, IO = 12A VS 5 4.2 * * V
VOLTAGE SWING3 Full temp. range, IO = 146mA VS 4 3.5 * * V
SLEW RATE TC = 25C, CC - open 8 * V/s
CAPACITIVE LOAD Full temp. range, AV = 1 2 * nF
SHUTDOWN DELAY TC = 25C, disable 10 * s
TC = 25C, operate 20 * s
POWER SUPPLY
CURRENT, quiescent6 TC = 25C 125 300 * * mA
CURRENT, disable mode Full temperature range 25 40 * * mA
THERMAL
RESISTANCE, AC junction to case5 Full temp. range, F>60Hz .22 .28 * * C/W
RESISTANCE, DC junction to case Full temp. range, F<60Hz .25 .3 * * C/W
RESISTANCE, junction to ambient Full temperature range 14 * C/W
TEMPERATURE, junction Sustained operation 150 * C
TEMPERATURE RANGE, case Meets full range specification 25 85 * * C
1. Long term operation at the maximum junction temperature will result in reduced product life. Derate power dissipation to
achieve high MTTF.
2. The power supply voltage for all specifications is the TYP rating unless noted as a test condition.
4. Rating applies if both shutdown inputs are least 1V inside supply rails. If one of the shutdown inputs is tied to a supply rail, the
current in that pin may increase to 2.4mA.
6. The PA03 must be used with a heatsink or the quiescent power may drive the unit into thermal shutdown.
145
TYPICAL PERFORMANCE
GRAPHS PA03 PA03A

500 256 50

64 40
400

16
300 30
4
200 20
1
100 10
.25
0 .06 0
0 40 80 120 160 200 15 5 25 45 65 85 105 50 25 0 25 50 75 100 125
CASE TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C)
SMALL SIGNAL RESPONSE PHASE RESPONSE OUTPUT VOLTAGE SWING

120 0 7
VOLTAGE DROP FROM SUPPLY (V)

CC
CC
100
30 6
=O
C
=1
55
PE
=
80
80 60 5
N
TC
0p
PHASE, ()
C
F
CC
60 90
=
CC = 470pF 4
O
5 C
PE
40 120
=2
N
CC
3 TC
C
=
20 150 25
18
=1
00
2 TC
pF
0 180
20 210 1
1 10 100 1K 10K .1M 1M 10M 1 10 100 1K 10K .1M 1M 10M 0 5 10 15 20 25 30
FREQUENCY, F (Hz) FREQUENCY, F (Hz) OUTPUT CURRENT, IO (A)

7.5
120 20
VIN = .5V, AV = 10
RL =.5
100 5.0
10
80 2.5
VOLTS
60 0 6
40 2.5
4
20 5.0
0 7.5 2
1 10 100 1K 10K .1M 1M 0 5 10 15 20 25 30 10 100 1K 10K .1M
FREQUENCY, F (Hz) TIME, t (S) FREQUENCY, F (Hz)
HARMONIC DISTORTION QUIESCENT CURRENT POWER RESPONSE

1.0 1.4 150
VS = 50V
OUTPUT VOLTAGE, VO (VPP)
100
0.3
25
AV = 10 1.2 C
=1 5 C
NORMALIZED, IQ (X)
PO = 200W
CC
RL = 4 TC =2 C
DISTORTION, (%)
TC 25
CC
=O
0.1 1.0 = 50
TC
=4
CC
PE
40
70
=1
5C
pF
.03 TC = 8 30
80
.8
0pF
20
.01 .6
.003 .4 10
30 100 300 1K 3K 10K 30K 40 60 80 100 120 140 3K 5K 10K 50K 100K 300K
FREQUENCY, F (Hz) TOTAL SUPPLY VOLTAGE, VS (V) FREQUENCY, F (Hz)
146
OPERATING
GENERAL OUTPUT STAGE SHUTDOWN

Please read the General Operating Considerations section, The entire power stage of the PA03 may be disabled using one
which covers stability, supplies, heatsinking, mounting, current of the circuits shown in Figure 1. There are many applications for
limit, SOA interpretation, and specification interpretation. Addi- this function. One is a load protection based on power delivered to
tional information can be found in the application notes. For the load or thermal rise. Another one is conservation of power
information on the package outline, heatsinks, and mounting when using batteries. The control voltage requirements accom-
hardware, consult the Accessory and Package Mechanical Data modate a wide variety logic drivers.
section of the handbook. 1. CMOS operating at +5V can drive the control pins directly.
2. CMOS operating at greater than 5V supplies need a voltage
MOUNTING PRECAUTIONS divider.
3. TTL logic needs a pull up resistor to +5V to provide a swing to
The PA03 copper base is very soft and easily bent. Do not put the fully disabled voltage (3.5V). When not using the shutdown
any stress on the mounting ears of this package. This calls for
caution when pushing the amplifier into certain types of packaging feature, connect both pins 3 and 4 to common.
foam and particularly when inserting the device into a socket.
Insert the amplifier into the socket only by pushing on the perimeter PHASE COMPENSATION
of the package lid. Pushing the unit into the socket by applying At low gain settings an external compensation capacitor is
pressure to the mounting tabs will bend the base due to the high required to insure stability. In addition to the resistive feedback
insertion force required. The base will then not contact the heatsink network, roll off or integrating capacitors must also be considered.
evenly resulting in very poor heat transfer. To remove a unit from A frequency of 1 MHz is most appropriate to calculate gain.
a socket, pry the socket away from the heatsink so that the Operation at gains below 10, without the external compensation
heatsink will support the amplifier base evenly. Recommended capacitor opens the possibility of oscillations near output satura-
mounting torque is 810 in.-lbs. (.91.13 Nm). tion regions when under load, the improper operation of the
thermal shutdown circuit. This can result in amplifier destruction.
SAFE OPERATING AREA (SOA) At gains of 10 or more:
Due to the internal (non-adjustable) current limit of the PA03, 1. No external components are required.
worst case power dissipation calculations must assume current 2. Typical slew rate will be 8V/s.
capability of 46 amps. Application specific circuits should be 3. Typical phase margin will be 70.
checked against the SOA curve when relying upon current limit for At a gain of 3:
fault protection. 1. Connect a 470pF compensation capacitor between pins 9 and
10.
SAFE OPERATING AREA CURVES 2. Typical slew rate will be 5V/s.
3. Typical phase margin will be 45.
Second breakdown limitations do apply to the PA03 but are At unity gain:
less severe, since junction temperature limiting responds 1. Connect a 1.8nF compensation capacitor between pins 9 and
within 10ms. Stress levels shown as being safe for more than 10.
10ms duration 2. Typical slew rate will be 1.8V/s.
OUTPUT CURRENT FROM +VS OR VS (A)
40
will merely CURRENT LIMIT ZONE 3. Typical phase margin will be 65.
30
cause thermal TH 100
mS 1.0
ER mS
shutdown. MA
L
FIGURE 1a. +5V
PA03
10 DIRECT DRIVE
Under nor- m S OF SHUTDOWN
500
4 Q14
mal operating 10
dc * NOT REQUIRED
conditions, ac- 1K 1K WHEN USING
CMOS LOGIC
SE
tivation of the 5 *
CO
0 = OPERATE 500
thermal shut-
ND
3 Q22
1 = SHUT DN
BR
down is a sign
EA
TC = 25C
KD
that the inter-

OW
nal junction
N
1 +15V
temperatures 10 20 50 100 150 PA03
have reached SUPPLY TO OUTPUT DIFFERENTIAL VS VO (V) 0 = SHUT DN 2R 500
CMOS 4 Q14
approximately 1 = OPERATE
175C. Thermal shutdown is a short term safety feature. If the R 1K
conditions remain that cause thermal shutdown, the amplifier
500
will oscillate in and out of shutdown, creating peak high power FIGURE 1b. 3 Q22
stresses, destroying useful signals, and reducing the reliability HIGH VOLTAGE
LOGIC INTERFACE
of the device.
FIGURE 1c.
BALANCE CONTROL THERMALLY
+VS
4
500
Q14
PA03
ACTIVATED
The voltage offset of the PA03 may be externally adjusted to SHUTDOWN R1 R2
1K
zero. To implement this adjustment install a 100 to 200 ohm ** 4.7K
potentiometer between pins 11 and 12 and connect the wiper arm 500
3 Q22
to the positive supply. Bypass pins 11 and 12 each with at least a R4
.01F ceramic capacitor. 360 30K
400mV
If the optional adjust provision is not used, connect both pins 11 LOAD
and 12 to the positive supply. R3 THERMAL SENSE
** SELECT SHUTOFF 360 TRANSISTOR
TEMPERATURE
SELECT R4 FOR 5V
DROP ON R2
without notice.
PA03U REV. I FEBRUARY 1998 1998 Apex Microtechnology Corp.
147
PA04 PA04A
FEATURES
PA04
HIGH INTERNAL DISSIPATION 200 WATTS
HIGH VOLTAGE, HIGH CURRENT 200V, 20A

HIGH SLEW RATE 50V/S USA
TE9493
11
BeO
4 WIRE CURRENT LIMIT SENSING

LOW DISTORTION
EXTERNAL SLEEP MODE CONTROL
OPTIONAL BOOST VOLTAGE INPUTS
EVALUATION KIT SEE EK04
APPLICATIONS
TYPICAL APPLICATION
SONAR TRANSDUCER DRIVER
LINEAR AND ROTARY MOTOR DRIVES The high power bandwidth and high voltage output of the
YOKE/MAGNETIC FIELD EXCITATION PA04 allows driving sonar transducers via a resonant circuit
PROGRAMMABLE POWER SUPPLIES TO 95V including the transducer and a matching transformer. The load
AUDIO UP TO 400W circuit appears resistive to the PA04. Control logic turns off the
amplifier in sleep mode.
Rf
DESCRIPTION
The PA04 is a high voltage MOSFET power operational C
amplifier that extends the performance limits of power ampli- CONTROL
fiers in slew rate and power bandwidth, while maintaining high LOGIC
current and power dissipation ratings.
ULTRA- Ri 1
The PA04 is a highly flexible amplifier. The sleep mode SONIC
12
feature allows ultra-low quiescent current for standby opera- DRIVE 7
tion or load protection by disabling the entire amplifier. Boost 2 PA04 R CL
voltage inputs allow the small signal portion of the amplifier to
11
operate at a higher voltage than the high current output stage.
10
The amplifier is then biased to achieve close linear swings to
the supply rails at high currents for extra efficient operation. TUNED
External compensation tailors performance to user needs. A TRANSFORMER
four wire sense technique allows precision current limiting Sonar Transducer Driver
without the need to consider internal or external milliohm
parasitic resistance in the output line.
The JEDEC MO-127 12-pin Power Dip package (see EXTERNAL CONNECTIONS
Package Outlines) is hermetically sealed and isolated from the
internal circuits. The use of compressible thermal washers will
void product warranty.
-INPUT SLEEP
EQUIVALENT SCHEMATIC 1 12
SLEEP +INPUT CURRENT LIMIT
12 +Vs 8 2 11
COMP
3 10 CURRENT LIMIT
9 R TOP
+VBOOST D1 CC C 4 VIEW 9 +V BOOST
Q5 COMP
D2 Q6 5 8 *+SUPPLY
Q10 -V BOOST
D3 6 7
D4
Q12 I LIM
-SUPPLY
* OUTPUT
Q13
11
D5 D6
10
IN +IN Q17 I LIM
1 2 PHASE COMPENSATION
Q14 Q15 Q19 Q18
D7 7
COMP D8
D9
OUT
Gain CC RC
3 Q7 1 470pF 120
>3 220pF 120
Q21 Q22 Q26 10 100pF 120
4
Q20
CC RATED FOR FULL SUPPLY VOLTAGE
V BOOST COMP
Vs 6 *See BOOST OPERATION paragraph.
5
148

BOOST VOLTAGE SUPPLY VOLTAGE +20V
INPUT VOLTAGE, differential 20V
INPUT VOLTAGE, common mode VS

INPUT
OFFSET VOLTAGE, initial 5 10 2 5 mV
OFFSET VOLTAGE, vs. supply 15 * V/V
BIAS CURRENT, initial 10 50 5 20 pA
BIAS CURRENT, vs. supply .01 * pA/V
OFFSET CURRENT, initial 10 50 5 20 pA
INPUT IMPEDANCE, DC 1011 *
INPUT CAPACITANCE 13 * pF
COMMON MODE VOLTAGE RANGE Full temperature range VB-8 * V
INPUT NOISE 100kHz BW, RS = 1K 10 * Vrms
GAIN
OPEN LOOP, @ 15Hz Full temperature range, CC = 100pF 94 102 * * dB
GAIN BANDWIDTH PRODUCT IO = 10A 2 * MHz
POWER BANDWIDTH RL = 4.5, VO = 180V p-p 90 * kHz
CC = 100pF, RC = 120
OUTPUT
VOLTAGE SWING IO = 15A VS-8.8 VS-7.5 * * V
VOLTAGE SWING VBOOST = Vs + 5V, IO = 20A VS-6.8 VS-5.5 * * V
CURRENT, peak 20 * A
SETTLING TIME to .1% AV = 1, 10V step, RL = 4 2.5 * s
SLEW RATE AV = 10, CC = 100pF, RC = 120 40 50 * V/s
CAPACITIVE LOAD Full temperature range, AV = +1 10 * nF
RESISTANCE 2 *
POWER SUPPLY
CURRENT, quiescent, boost supply 30 40 * * mA
CURRENT, quiescent, total 70 90 * * mA
CURRENT, quiescent, total, sleep mode Full temperature range 3 5 * * mA
THERMAL
RESISTANCE, AC, junction to case3 Full temperature range, F>60Hz .3 .4 * * C/W
RESISTANCE, DC, junction to case Full temperature range, F<60Hz .5 .6 * * C/W
RESISTANCE4, junction to air Full temperature range 12 * C/W
1. Unless otherwise noted: TC = 25C, CC = 470pF, RC = 120 ohms. DC input specifications are value given. Power supply
voltage is typical rating. VBOOST = VS.
3. Rating applies if the output current alternates between both output transistors at a rate faster than 60 Hz.
4. The PA04 must be used with a heatsink or the quiescent power may drive the unit to junction temperatures higher than 150C.
The PA04 is constructed from MOSFET transistors. ESD handling procedures must be observed.
CAUTION
149
TYPICAL PERFORMANCE
GRAPHS PA04 PA04A
POWER DERATING POWER SUPPLY REJECTION SLEW RATE

200 100 60
SLEW RATE, SR (V/s)

80
150
T = TC 40
60
100
4 LOAD
40
20
50
20
T = TA
RC = 120
0 0 0
0 25 50 75 100 125 150 10 100 1K 10K 100K 1M 10M 100 200 300 400 500
TEMPERATURE, T (C) FREQUENCY F (Hz) EXT. COMPENSATION CAPACITOR C C (pF)
VOLTAGE DROP FROM SUPPLY, VSVO (V)

SMALL SIGNAL GAIN SMALL SIGNAL PHASE OUTPUT VOLTAGE SWING
OPEN LOOP GAIN RESPONSE, A(dB)
120 0 12
R C = 120
R L = 4
OPEN LOOP PHASE, ()
CC
45 10
=
CC
80
10
0p
=
47
8
C
0p
90
F
CC = 470pF = VS
T
40 OO
S
CC
CC = 220pF 6 VB
=
135 CC = 100pF
22
0p
F
4
0 RC = 120 + 5V
180 = VS
RL = 4 V BO OST
2
1 10 100 1K 10K 100K 1M 10M 1 10 100 1K 10K 100K 1M 10M 0 5 10 15 20
FREQUENCY,Ff (Hz) FREQUENCY, F (Hz) OUTPUT CURRENT, I O (A)
COMMON MODE REJECTION PULSE RESPONSE CURRENT LIMIT

100 7.5 130

NORMALIZED CURRENT LIMIT, (%)
A V = +1 C C = 470pF
5 120
80
110
2.5
60
100
0
90
40
2.5
80
20 5 70
0 7.5 60
10 100 1K 10K 100K 1M 0 5 10 15 20 25 30 50 25 0 25 50 75 100 125
FREQUENCY, F (Hz) TIME, t (s) CASE TEMPERATURE, T C (C)
NORMALIZED QUIESCENT CURRENT, I Q (X)

.2 1.2 200
A V = 10 180
W

00
.1 R L =4 150
=3
DISTORTION, THD (%)
.05 C C = 100pF, R C = 120 1.1 120

O
Vs = 62V
P
100
CC
CC
CC
80
=4
=2
=1
.02
1.0
70
20
00
60
pF
pF
pF
.01 PO = 1W
.005 40
0W .9
20
= R C =120
.002 PO
R L = 4.0
.001 .8 20
30 100 300 1K 3K 10K 30K 30 50 100 150 200 10K 20K 50K .2M .6M 1M
150
OPERATING
GENERAL SLEEP MODE OPERATION

Please read the General Operating Considerations sec- In the sleep mode, pin 12 (sleep) is tied to pin 9 (+VBOOST).
tion, which covers stability, supplies, heatsinking, mounting, This disables the amplifiers internal reference and the ampli-
current limit, SOA interpretation, and specification interpreta- fier shuts down except for a trickle current of 3 mA which flows
tion. Additional information can be found in the application into pin 12. Pin 12 should be left open if the sleep mode is not
notes. For information on the package outline, heatsinks, and required.
mounting hardware, consult the Accessory and Package Several possible circuits can be built to take advantage of
Mechanical Data section of the handbook. The EK04 Evalu- this mode. In Figure 2A a small signal relay is driven by a logic
ation Kit makes prototype circuits a snap by providing an gate. This removes the requirement to deal with the common
EK04PC proto circuit board, MS05 mating socket, HS11 mode voltage that exists on the shutoff circuitry since the sleep
heatsink and hardware kit. mode is referenced to the +VBOOST voltage.
CURRENT LIMIT In Figure 2B, circuitry is used to level translate the sleep
mode input signal. The differential input activates sleep mode
The two current limit sense lines are to be connected directly with a differential logic level signal and allows common mode
across the current limit sense resistor. For the current limit to
voltages to VBOOST.
work correctly pin 11 must be connected to the amplifier
output side and pin 10 connected to the load side of the
current limit resistor, RCL, as shown in Figure 1. This LOGIC K1 9
+VBOOST
connection will bypass any parasitic resistances, Rp, formed
by sockets and solder joints as well as internal amplifier losses.
The current limiting resistor may not be placed anywhere in the
output circuit except where shown in Figure 1. 12
SLEEP
The value of the current limit resistor can be calculated as
follows:
.76 Figure 2A. Sleep mode circuit. 9
RCL = +VBOOST
ILIMIT 560
Rf
Figure 1. 470 12
SLEEP
Current Limit. Ri 1
10
11
+ Q1
CL RP RCL LOGIC
INPUT CL 7 1K
2 PA04 INPUT
RL 470
- Q2
Figure 2B. VBOOST

Sleep mode circuit.
The MOSFET output stage of this power operational ampli- BOOST OPERATION
fier has two distinct limitations:
1. The current handling capability of the MOSFET geometry With the VBOOST feature the small signal stages of the
and the wire bonds. amplifier are operated at higher supply voltages than the
2. The junction temperature of the output MOSFETs. amplifiers high current output stage. +VBOOST (pin 9) and
VBOOST (pin 5) are connected to the small signal circuitry of the
NOTE: The output stage is protected against transient flyback.
However, for protection against sustained, high energy amplifier. +VS (pin 8) and VS (pin 6) are connected to the high
flyback, external fast-recovery diodes should be used. current output stage. An additional 5V on the VBOOST pins is
20
sufficient to allow the small signal stages to drive the output
t=
transistors into saturation and improve the output voltage
t= 1m swing for extra efficient operation when required. When close
10 10 s
m swings to the supply rails is not required the +VBOOST and +VS
D s
C pins must be strapped together as well as the VBOOST and VS
Tc
OUTPUT CURRENT (A)
5.0 D
C
Tc
=
25
pins. The boost voltage pins must not be at a voltage lower than
D C
C =
85 the VS pins.
Tc C
=
2.0 12
5 COMPENSATION
C
The external compensation components CC and RC are
1.0
connected to pins 3 and 4. Unity gain stability can be achieved
at any compensation capacitance greater than 330 pF with at
.5 least 60 degrees of phase margin. At higher gains more phase
shift can be tolerated in most designs and the compensation
.2
capacitance can accordingly be reduced, resulting in higher
2 5 10 20 50 100 200 bandwidth and slew rate. Use the typical operating curves as
SUPPLY TO OUTPUT DIFFERENTIAL (V) a guide to select CC and RC for the application.
without notice.
PA04U REV. I DECEMBER 1997 1997 Apex Microtechnology Corp.
151
EVALUATION KIT FOR PA04 PIN-OUT
EK04
INTRODUCTION
This easy-to-use kit provides a platform for the evaluation of connection pads on the edge of the PC board for easy intercon-
power op amps using the PA04 pin-out configuration. It can be used nects.
to analyze a multitude of standard or proprietary circuit configura- The hardware required to mount the PC board and the device
tions, and is flexible enough to do most standard amplifier test under evaluation to the heatsink are included in the kit. Because of
configurations. the limitless combination of configurations and component values
The schematic of the PC board is shown in Figure 2. Note that that can be used, no other parts are included in this kit. However,
all of the components shown on the schematic will probably not be generic formulas and guidelines are included in the APEX
used for any single circuit. The component locations on the PC DATABOOK.
board (See Figure 3) provide maximum flexibility for a variety of
configurations. Also included are loops for current probes as well as
ASSEMBLY HINTS ASSEMBLY

The mating socket included with this kit has recessed nut sockets 1. Insert a #6 x 1/4" hex nut in each of the nut socket recesses
for mounting the device under evaluation. This allows assembly located on the bottom of the mating socket.
from one side of the heatsink, making it easy to swap devices under 2. Insert the socket into the PC board until it is firmly pressed
evaluation. The sizes of the stand-offs were selected to allow proper against the ground plane side of the PC board.
spacing of the board-to-heatsink and allow enough height for 3. Solder the socket in place (Figure 1). Be sure the nuts are in the
components when the assembly is inverted. recesses prior to soldering.
4. Mount the PC board assembly to the heatsink using the stand-
PARTS LIST offs and spacers included.

5. Apply thermal grease or a TW05 to the bottom of the device
under evaluation. Insert into the mating socket through the
C
HS11 Heatsink 1 heatsink.
EK04PC PC Board 1 6. Use the #6 x 1.25" panhead screws to mount the amplifier to the
MS05 Mating Socket 1 heat sink. Do not overtorque. Recommended mounting torque
HWRE01 Hardware Kit 1 is 8-10 in-lbs (.90-1.13 NM).
TW05 Hardware Kit 1
Mounting precautions, general operating considerations, and
HWRE01 contains the following: heatsinking information may be found in the APEX DATABOOK.
4 #8 Panhead Screws 4 #6 x 1.25" Panhead Screws
4 #8 .375" Hex Spacers 4 #6 x 5/16" Hex Nuts
4 #8 1.00" Hex Stand Offs 2 #6 x 1/4" Hex Nuts NOTE: Refer to HS11 in Accessories Section.
FIGURE 1.
Heatsink
Power Op Amp
Package
#6 Screw
#8 Screw
Recessed Nuts #8 .375"

Hex Spacer
#8 1.00"
Teflon Tubing PC Board Hex Standoff
(2 Opposite Pins Mating Socket
Minimum)

All Apex amplifiers should be handled using proper ESD precau- Do not change connections while the circuit is under power.
tions! Never exceed any of the absolute maximums listed in the device
Initially set all power supplies to the minimum operating levels data sheet.
allowed in the device data sheet. Always use adequate power supply bypassing.
Check for oscillations. Remember that internal power does not equal load power.
Always use the heatsink included in this kit with thermal grease Do not count on internal diodes to protect the output against
or TW05 and torque the part to the specified 8-10 in-lbs sustained, high frequency, high energy kickback pulses.
(.90-1.13 NM).
152
EVALUATION KIT
EK04 FOR PA04 PIN-OUT
FIGURE 2. OPTIONAL VBOOST

L1 CIRCUIT
C2 4 5
CR1
1 IC1 C3
S Max632 +V BOOST
R3 G
7 3 C19
Q4 R2
D
C6 Q1
R4
J1 Q2 6
C5 LOGIC
C4 R5 LEVEL
J3 C7 C8 SHUTDOWN
C9 C1 R1 R6
1
R8 8 Q3 7
2 9
R7 1 12
CR3 CR4 10 R9
3 C10 11
CR5 CR6 D.U.T. 7
R11 R10 5 10W
CR7 CR8 6
4 2 4 +V
R12 3 CR2
R13 C11
C12 C13 C14
5 R14 J2
V BOOST
Q5 7 8 CR9
CR10
6 IC2 1
Max636 5 C15 C17 V
CR11
3 4 C16
L2 C20
C18
OPTIONAL VBOOST CIRCUIT

COMPONENT FUNCTION OPTIONAL Vboost COMPONENT FUNCTIONS
AND RECOMMENDED VALUES
R1 Feedback resistor
R2 Logic shutdown C2 100F 25V Regulator Input Capacitor
R4 Input resistor logic input C3 100F 100V Boost Output Filter Capacitor
R5 Current setting resistor C6 10F 200V Bias Filter Capacitor
R6 Input resistor logic input C15 100F 100V Boost Output Filter Capacitor
R7 Input resistor C18 100F 25V Regulator Input Capacitor
R8 Input bias current measurement (Note 4) C19 1F X7R 100V Boost Output Filter Capacitor
R9 Current limit C20 1F X7R 100V Boost Output Filter Capacitor
R10 Noise gain compensation (Note 1)
R11 Resistor divider network for biasing CR1 1N5242 Positive Input Boost Reference
inputs (Note 2) CR10 1N5819 Negative Boost Flyback Diode
R12 Input bias current measurement (Note 4) CR11 1N5242 Negative Input Boost Reference
R13 Resistor divider network for IC1 MAX632 Positive Boost Regulator
biasing inputs (Note 2) IC2 MAX636 Negative Boost Regulator
R14 Compensation resistor
C1 AC gain or stability (Note 1) L1 330H Positive Boost Output Inductor
C4 Power supply bypass (Note 3) L2 330H Negative Boost Output Inductor
C5 Power supply bypass (Note 3) Q4 IRF9240 Positive Pass Element
C7 Input coupling Q5 IRF240 Negative Pass Element
C8 AC gain set R3 50K 1Watt Reference Bias Resistor
C9 Power supply bypass (Note 3)
C10 Noise gain compensation (Note 1) NOTE: Q4 and Q5 can optionally be attached to heatsinks, Apex
C11 Power supply bypass (Note 3) part # HS01. This should be done when the total supply
C12 Bias node noise bypass (Note 2) voltage to the PA04 exceeds 60 Vdc.
C13 Bias node noise bypass (Note 2)
C14 Compensation NOTES: Please refer to the following sections of the APEX
C16 Power supply bypass (Note 3) DATABOOK as noted.
C17 Power supply bypass (Note 3) 1. See Stability section of General Operating Considerations.
CR2 Flyback protection (Note 5) 2. See General Operating Considerations.
CR3-8 Input protection (Note 5) 3. See Power Supplies section of General Operating Consider-
CR9 Flyback protection (Note 5) ations.
CR11 Zener reference for MAX636 4. See Parameter Definitions and Test Methods.
5. See Amplifier Protection section of General Operating Consid-
erations.
153
EVALUATION KIT
FOR PA04 PIN-OUT EK04
FIGURE 3.
4
C12
C7
C13
R4
R6
R1
C8
R13
R5
R7
B
R11
C
E
C10
Q3
B
Q2
E
R10
R12
C
C1
R8
CR5
CR3 CR7
B
R2
C
E
C19
C3
Q1
CR4 CR8 C
R3
CR6
Q5
S
C6
C9
R14
L1
D
C14 8"
IC1
CR11
C11
J1
J2
C18
C4 C17 IC2
R9
Q5-D
Q4
L2
G
C16
C5
D
CR10
J3
CR1
C15 C20
C2
CR9
CR2
+V
V
OUT
+VB
VB
6"
154
EVALUATION KIT
TYPICAL APPLICATION
The PA04 is well suited for wideband, low distortion, high power avoids any concern of common mode effects. Typical specs of such
applications. The circuit in Figure 4 displays the simplicity of use a circuit would read as follows:
offered by the PA04. The circuit is in an inverting gain of 10. This Po = 200W
relatively low gain allows the amplifier to have more than adequate F = 10kHz
loop gain available, resulting in extremely low distortion at the RL = 4 Ohms
power levels delivered. The use of the inverting configuration THD = .0061
10R
FIGURE 4. +VS R1
C4 C5
CR2
C9 J1
NC
8
R R8 9
2 1
CR3 CR4 12 R9
R7 10
CR5 CR6 DUT 11
V IN 5 7
CR7 CR8 6
2 4
3
R12 C11
4 R14
J2 CR9
C14
C16 C17
VS
OPTIONAL V BOOST
One of many inexpensive ways to acquire V boost for the PA04 common mode range of the amplifier. The ground connection of J3
has been included as an option on this evaluation kit. The addition needs to be made when assembled.
of these parts not only increases swing, but also extends the
FIGURE 5. OPTIONAL VBOOST

L1 CIRCUIT
C2 4 5
CR1
1 IC1 C3
S Max632 +V BOOST
R3 G
7 3 C19
Q4 R2
D
C6 Q1
R4
Q2 6
C5 LOGIC
C4 R5 LEVEL
R1 SHUTDOWN
C9 R6
R8 8 Q3 7
2 9
R7 1 12
CR3 CR4 10 R9
CR5 CR6 D.U.T. 11
5 7 10W
CR7 CR8 6
4 2 4 +V
3 CR2
C11
C14
R14
V BOOST
Q5
7 8 CR9
CR10
6 IC2 1
Max636 5 C15 C17 V
CR11
3 4 C16
C20
L2
C18
OPTIONAL VBOOST CIRCUIT
HS11 HEATSINK NOTE

The HS11 Heatsink is overkill for the average application. Once maximum power dissipation for the application is determined (refer to
General Operating Considerations and Application Note 11 in the APEX DATABOOK), the final mechanical design will probably require
substantially less heatsinking.
APEX MICROTECHNOLOGY makes no representation that the use or interconnection of the circuits described herein will not infringe
on existing or future patent rights, nor do the descriptions contained herein imply the granting of licenses to make, use, or sell equip
ment constructed in accordance therewith.
155
COMMON
CONFIGURATIONS EK04
VOLTAGE-TO-CURRENT CONVERSION VOLTAGE-TO-CURRENT CONVERSION

NON-INVERTING CONFIGURATION
SINGLE SUPPLY, BRIDGE MODE
RI RF VS
IO R
CF
RD
VIN VS VS
RD LOAD R R
CF
RS
RI LOAD VS
V RS 2
I O = IN VIN CB
RS R
RF
DIFFERENCE AMPLIFIER
RF
VOLTAGE FOLLOWER WITH GAIN
RI SINGLE SUPPLY, BRIDGE MODE
V1 VS
RI RF R
RI VO
V2 C VS VS
R R
RF CI
RF LOAD
VO = ( V2 V1 ) VS
RI
2
VOLTAGE-TO-CURRENT CONVERSION
INVERTING CONFIGURATION
VIN CB R C
RI RB
IO
INTEGRATION SINGLE SUPPLY
NON-INVERTING CONFIGURATION
VIN
VS RF
RD LOAD
CF R1 VS
V1 RB
RI
R2 C1
RF V2 VS
RS VO
VIN RF R3 VO RB
IO = V3 RI
RS RI RX
VX
VOLTAGE-TO-CURRENT CONVERSION VIN RF
(
T V1 V2 V3 VX
IMPROVED HOWLAND CURRENT PUMP
RI RF
VO =
T
C1 O R1
+
R2
+
R3
+
RX ) dt
IO RF
i) VO =
SUMMING / SCALING RI
VIN
ii) For VIN = 0
R1 RF
RI V1 V (R I //R F )
RS VCM = S
RD RB + ( R I //R F )
ZL R2
RF V2 VIN (RB //R F )
CF iii) VCM =
R3 R I + (RB //R F )
VO
RF V3 iv) For VIN > 0
I O = VIN
R I RS RX VCM = VCM + VCM
VX @ VIN = 0
INVERTING CONFIGURATION VO = RF ( RV
1
1
+
V2
R2
+
V3
R3
+
VX
RX ) PARALLEL OPERATION
RI RF RF
INVERTER
VS VS RI
VIN RF
RS
RI
RA VIN
VO
I
VO VIN 2I
RB
RL
VO (Bias) = (VS RB
RA + RB )(
1+
RF
RI ) VO = ( RR ) V F
I
IN RS
RF
VO (Signal) = VIN
RI( ) I
however, FAXis(520)
ORDERS (520) 690-8601
EK04U REV. F JANUARY 1998 1998 Apex Microtechnology Corp.
156
NOTES:
157
PA05 PA05A
FEATURES
PA05A
HIGH INTERNAL DISSIPATION 250 WATTS
HIGH VOLTAGE, HIGH CURRENT 100V, 30A USA
HIGH SLEW RATE 100V/S TE9493
11
BeO
4 WIRE CURRENT LIMIT SENSING

LOW DISTORTION
EXTERNAL SHUTDOWN CONTROL
OPTIONAL BOOST VOLTAGE INPUTS
EVALUATION KIT SEE EK04
APPLICATIONS The JEDEC MO-127 12-pin Power Dip package (see
Package Outlines) is hermetically sealed and isolated from
LINEAR AND ROTARY MOTOR DRIVES the internal circuits. The use of compressible thermal washers
SONAR TRANSDUCER DRIVER and/or improper mounting torque will void the product war-
YOKE/MAGNETIC FIELD EXCITATION ranty. Please see General Operating Considerations.
PROGRAMMABLE POWER SUPPLIES TO 45V
AUDIO UP TO 500W TYPICAL APPLICATION
The high power bandwidth of the PA05 allows driving sonar
DESCRIPTION transducers via a resonant circuit including the transducer and
The PA05 is a high voltage MOSFET power operational a matching transformer. The load circuit appears resistive to
amplifier that extends the performance limits of power ampli- the PA05. Control logic turns off the amplifier's output during C
fiers in slew rate and power bandwidth, while maintaining high shutdown.
current and power dissipation ratings.
Rf
The PA05 is a highly flexible amplifier. The shutdown control
feature allows the output stage to be turned off for standby
operation or load protection during fault conditions. Boost
CONTROL
voltage inputs allow the small signal portion of the amplifier to LOGIC
operate at a higher voltage than the high current output stage.
The amplifier is then biased to achieve close linear swings to ULTRA- Ri 1 12
the supply rails at high currents for extra efficient operation. SONIC
DRIVE 7
External compensation tailors slew rate and bandwidth perfor- PA05
2 R CL
mance to user needs. A four wire sense technique allows
precision current limiting without the need to consider internal 11
10
or external milliohm parasitic resistance in the output line. The
output stage is protected by thermal limiting circuits above TUNED
junction temperatures of 175C. TRANSFORMER
EQUIVALENT SCHEMATIC EXTERNAL CONNECTIONS
SHUTDOWN +Vs 8
12 INPUT SHUTDOWN
9 1 12
D1 +INPUT CURRENT LIMIT
+VBOOST 2 11
Q8 COMP
Q1 Q4 3 10 CURRENT LIMIT
R TOP
D6
Q5 CC C 4 VIEW 9 +V BOOST
Q12 Q13 4
COMP D9 COMP
3 D5
OUT 5 8 *+SUPPLY
7 V BOOST
Q10 6 7
Q14 Q18 ILIM * OUTPUT
Q16 Q17 11
SUPPLY
Q22
IN 10
1 ILIM
Q24
D19 D20 Q25
BIAS
Q21 PHASE COMPENSATION
+IN
Q29 Gain CC RC
2 D27
D31
1 470pF 120
Q30 Q33 >3 220pF 120
10 82pF 120
VBOOST D4
5 CC RATED FOR FULL SUPPLY VOLTAGE
6 Vs *See BOOST OPERATION paragraph.
158

BOOST VOLTAGE SUPPLY VOLTAGE +20V
OUTPUT CURRENT, continuous within SOA 30A
INPUT VOLTAGE, common mode VB
INPUT
OFFSET VOLTAGE, vs. supply 10 30 * * V/V
BIAS CURRENT, initial 10 50 5 20 pA
OFFSET CURRENT, initial 10 50 5 20 pA
COMMON MODE VOLTAGE RANGE Full temperature range VB8 * V
INPUT NOISE 100KHz BW, RS = 1K 10 * Vrms
GAIN
OPEN LOOP, @ 15Hz Full temperature range, CC = 82pF 94 102 * * dB
GAIN BANDWIDTH PRODUCT RL = 10 3 * MHz
POWER BANDWIDTH RL = 4, VO = 80VP-P, AV = 10 400 * kHz
CC = 82pF, RC = 120
PHASE MARGIN Full temperature range, CC = 470pF 60 *
OUTPUT
VOLTAGE SWING IO = 20A VS9.5 VS8.7 * * V
VOLTAGE SWING VBOOST = Vs + 5V, IO = 30A VS5.8 VS5.0 * * V
CURRENT, peak 30 * A
SETTLING TIME to .1% AV = +1, 10V step, RL = 4 2.5 * s
SLEW RATE AV = 10, CC = 82pF, RC = 120 80 100 * V/s
CAPACITIVE LOAD Full temperature range, AV = +1 2.2 * nF
RESISTANCE IO = 0, No load, 2MHz 5 *
IO = 1A, 2MHz 2 *
POWER SUPPLY
CURRENT, quiescent, boost supply 46 56 * * mA
CURRENT, quiescent, total, shutdown 46 56 * * mA
THERMAL
RESISTANCE, AC, junction to case3 Full temperature range, F>60Hz .3 .4 * * C/W
RESISTANCE, DC, junction to case Full temperature range, F<60Hz .4 .5 * * C/W
RESISTANCE, junction to air4 Full temperature range 12 * C/W
1. Unless otherwise noted: TC = 25C, CC = 470pF, RC = 120 ohms. DC input specifications are value given. Power supply
voltage is typical rating. VBOOST = VS.
3. Rating applies if the output current alternates between both output transistors at a rate faster than 60 Hz.
4. The PA05 must be used with a heatsink or the quiescent power may drive the unit to junction temperatures higher than 150C.
CAUTION
159
TYPICAL PERFORMANCE
GRAPHS PA05 PA05A
POWER DERATING POWER SUPPLY REJECTION SLEW RATE VS. COMP.

250 100 100
SLEW RATE, SR (V/s)

200 80
80
150 60
60
100 40
40
50 20
0 0 20
0 25 50 75 100 125 150 10 100 1K 10K 100K 1M 10M 100 200 300 400 500
CASE TEMPERATURE, T(C) FREQUENCY f (Hz) EXT. COMPENSATION CAPACITOR C C (pF)

SMALL SIGNAL RESPONSE PHASE RESPONSE OUTPUT VOLTAGE SWING
100 0 12
R L = 8 CC = 82pf
R C = 120
OPEN LOOP GAIN, A(dB)
80 45 10
CC = 82pf
CC = 220pf CC = 470pf
PHASE, ()
60 90
CC = 470pf
8
=V
S
C
CC = 220pf CC = 220pf T
S
VBOO
40 135 6
CC = 470pf CC = 82pf
20 180
R L = 8 4 + 5V
= VS
R C = 120 V BOO
ST
0 225 2
10 100 1K 10K 100K 1M 10M 10 100 1K 10K 100K 1M 10M 0 5 10 15 20 25 30
FREQUENCY, f (Hz) FREQUENCY, f (Hz) OUTPUT CURRENT, I O (A)
COMMON MODE REJECTION PULSE RESPONSE CURRENT LIMIT

7.5 130
100
A V = +1 C C = 470pF
5 120
80
110
2.5
60
100
0
40 90
2.5
80
20 5 70
0 7.5 60
10 100 1K 10K 100K 1M 0 5 10 15 20 25 30 50 25 0 25 50 75 100 125
FREQUENCY, f (Hz) TIME, t (s) CASE TEMPERATURE, T C (C)

.2 1.2 100
A V = 10
W

00
.1 R L = 2 60
=3
DISTORTION, THD (%)
C C = 82pF, R C = 120 40
CC
.05 1.1
O
P
Vs = 31V
=
CC
82
=
pF
.02 20
22
CC
0p
1.0
F
=
.01
47
PO = 1W 10
0p
F
.005
0W .9
6
20
= 4
.002 PO
.001 .8 2
30 100 300 1K 3K 10K 30K 20 40 60 80 100 40K 100K .4M 1M 4M
FREQUENCY, f (Hz) TOTAL SUPPLY VOLTAGE, VS (V) FREQUENCY, f (Hz)
160
OPERATING
GENERAL SHUTDOWN OPERATION

Please read the General Operating Considerations section, To disable the output stage, pin 12 is connected to ground
which covers stability, supplies, heatsinking, mounting, cur- via relay contacts or via an electronic switch. The switching
rent limit, SOA interpretation, and specification interpretation. device must be capable of sinking 2mA to complete shutdown
Additional information can be found in the application notes.
For information on the package outline, heatsinks, and mount- and capable of standing off the supply voltage +VS. See Figure
ing hardware, consult the Accessory and Package Mechanical 2 for suggested circuits.
Data section of the handbook. The EK04 Evaluation Kit makes
prototype circuits a snap by providing an EK04PC proto circuit LOGIC K1
board, MS05 mating socket, HS11 heatsink and hardware kit. 12 SHUTDOWN
CURRENT LIMIT
The two current limit sense lines are to be connected directly
across the current limit sense resistor. For the current limit to A
work correctly, pin 11 must be connected to the amplifier
output side and pin 10 connected to the load side of the current
limit resistor, RCL, as shown in Figure 1. This connection will
bypass any parasitic resistances, RP formed by sockets and
solder joints as well as internal amplifier losses. The current 12 SHUTDOWN
limiting resistor may not be placed anywhere in the output
circuit except where shown in Figure 1. If current limiting is not LOGIC
Q1
used, pins 10 and 11 must be tied to pin 7.
The value of the current limit resistor can be calculated as 470
follows: Rf B
Ri 10 FIGURE 2. SHUTDOWN OPERATION

1 11
CL RP RCL
INPUT CL 7
2 PA05 From an internal circuitry standpoint, shutdown is just a
RL special case of current limit where the allowed output current
ILIMIT = .7/RCL
is zero. As with current limit, however, a small current does flow
in the output during shutdown. A load impedance of 100 ohms
FIGURE 1. CURRENT LIMIT or less is required to insure the output transistors are turned off.
Note that even though the output transistors are off the output
pin is not open circuited because of the shutdown operating
current.
The MOSFET output stage of this power operational ampli-
fier has two distinct limitations: BOOST OPERATION
1. The current handling capability of the MOSFET geometry With the VBOOST feature, the small signal stages of the
and the wire bonds.
amplifier are operated at higher supply voltages than the
2. The junction temperature of the output MOSFETs.
amplifiers high current output stage. +VBOOST (pin 9), and
NOTE: The output stage is protected against transient flyback. VBOOST (pin 5) are connected to the small signal circuitry of
However, for protection against sustained, high energy the amplifier. +VS (pin 8) and VS (pin 6) are connected to the
flyback, external fast-recovery diodes should be used.
high current output stage. An additional 5V on the VBOOST pins
is sufficient to allow the small signal stages to drive the output
30 transistors into saturation and improve the output voltage
t=
20 swing for extra efficient operation when required. When close
0m
D
15 swings to the supply rails is not required the +VBOOST and +VS
C
s
12
Tc
D
pins must be strapped together as well as the VBOOST and VS

OUTPUT CURRENT (A)
9
Tc
25
pins. The boost voltage pins must not be at a voltage lower than
C
D
=
C
85
6 the VS pins.
Tc
C
=
12
COMPENSATION
5
3
C
The external compensation components CC and RC are

1.5 connected to pins 3 and 4. Unity gain stability can be achieved
1.2 at any compensation capacitance greater than 470 pF with at
.9 least 60 degrees of phase margin. At higher gains, more phase
.6
shift can be tolerated in most designs and the compensation
capacitance can accordingly be reduced, resulting in higher
bandwidth and slew rate. Use the typical operating curves as
.3
1 2 3 4 5 10 20 30 40 50 100 a guide to select CC and RC for the application.
SUPPLY TO OUTPUT DIFFERENTIAL (V)
without notice.
PA05U REV. F DECEMBER 1997 1997 Apex Microtechnology Corp.
161
FET INPUT POWER OPERATIONAL AMPLIFIERS
PA07 PA07A
FEATURES
LOW BIAS CURRENT FET Input
PROTECTED OUTPUT STAGE Thermal Shutoff
EXCELLENT LINEARITY Class A/B Output
WIDE SUPPLY RANGE 12V TO 50V
HIGH OUTPUT CURRENT 5A Peak
APPLICATIONS
MOTOR, VALVE AND ACTUATOR CONTROL TYPICAL APPLICATION
MAGNETIC DEFLECTION CIRCUITS UP TO 4A
POWER TRANSDUCERS UP TO 100kHz CL R F1 CF
+32V
TEMPERATURE CONTROL UP TO 180W RL R F2
R CL+ V = 28
PROGRAMMABLE POWER SUPPLIES UP TO 90V EMF = 14V
.68 R W = 14
AUDIO AMPLIFIERS UP TO 60W RMS
PA07 MOTOR
DESCRIPTION R CL
+V
The PA07 is a high voltage, high output current operational .68 LIGHT
amplifier designed to drive resistive, inductive and capacitive C
loads. For optimum linearity, especially at low levels, the
output stage is biased for class A/B operation using a ther- 32V
mistor compensated base-emitter voltage multiplier circuit. A V
thermal shutoff circuit protects against overheating and mini- PD1 PD2
mizes heatsink requirements for abnormal operating condi-
tions. The safe operating area (SOA) can be observed for all
operating conditions by selection of user programmable cur- Negates optoelectronic instabilities
rent limiting resistors. Both amplifiers are internally compen-
Lead network minimizes overshoot
sated for all gain settings. For continuous operation under
load, a heatsink of proper rating is recommended. SEQUENTIAL POSITION CONTROL
This hybrid circuit utilizes thick film (cermet) resistors, ce-
ramic capacitors and semiconductor chips to maximize reli- Position is sensed by the differentially connected photo
ability, minimize size and give top performance. Ultrasonically diodes, a method that negates the time and temperature
bonded aluminum wires provide reliable interconnections at all variations of the optical components. Off center positions
operating temperatures. The 8-pin TO-3 package is hermeti- produce an error current which is integrated by the op amp
cally sealed and electrically isolated. The use of compressible circuit, driving the system back to center position. A momen-
washers and/or improper mounting torque will void the product tary switch contact forces the system out of lock and then the
warranty. Please see General Operating Considerations. integrating capacitor holds drive level while both diodes are in
a dark state. When the next index point arrives, the lead
EQUIVALENT SCHEMATIC network of C1 and R1 optimize system response by reducing
overshoot. The very low bias current of the PA07 augments
performance of the integrator circuit.
3
7 C1
Q1 Q2 D1 Q3
Q4 Q6A R CL+
Q6B CL+
Q5 +VS
2 OUT
2 3
C2 1
Q8 Q9 Q7 RT OUTPUT
+IN
1 4
C3 Q10 Q19 TOP VIEW
Q11
5 C4 8
Q12A Q12B RS
4 D3 IN 5 R CL
Q17B
8
Q17A
Q15 6 CL
Q16 7
VS
BAL RS= ( VS+ + VS ) RT/1.6
Q18
D2
NOTE: Input offset voltage trim optional. RT = 10K MAX
6
8-pin TO-3 package
162


2
INPUT

BIAS CURRENT, initial3 TC = 25C 5 50 3 10 pA
BIAS CURRENT,vs. supply TC = 25C .01 * pA/V
OFFSET CURRENT, initial3 TC = 25C 2.5 50 1.5 10 pA
COMMON MODE VOLTAGE RANGE4 Full temperature range VS10 * V
COMMON MODE REJECTION, DC Full temperature range, VCM = 20V 120 * dB
GAIN
OPEN LOOP GAIN at 10Hz TC = 25C, RL = 15 92 98 * * dB

GAIN BANDWIDTH PRODUCT @ 1MHz TC = 25C, RL = 15 1.3 * MHz
POWER BANDWIDTH TC = 25C, RL = 15 18 * kHz
PHASE MARGIN Full temperature range, RL = 15 70 *
OUTPUT
VOLTAGE SWING4 Full temp. range, IO = 5A VS5 * V

SETTLING TIME to .1% TC = 25C, 2V step 1.5 * s
SLEW RATE TC = 25C 5 * V/s
CAPACITIVE LOAD, unity gain Full temperature range 10 * nF
CAPACITIVE LOAD, gain>4 Full temperature range SOA *
POWER SUPPLY

THERMAL
RESISTANCE, AC, junction to case5 F>60Hz 1.9 2.1 * * C/W

RESISTANCE, DC, junction to case F<60Hz 2.4 2.6 * * C/W
TEMPERATURE RANGE, case Meets full range specifications 25 25 +85 * * * C
2. The power supply voltage for all specifications is the TYP rating unless otherwise noted as a test condition.
3. Doubles for every 10C of temperature increase.
163
TYPICAL PERFORMANCE
GRAPHS PA07 PA07A

70 256

3.0
60 64 2.5

T = TC R CL = 0.3
50
16 2.0
40
4 1.5
R CL = 0.6
30
1 1.0
20
.25 .5
10 T = TA
0 .06 0
0 20 40 60 80 100 120 140 15 5 25 45 65 85 105 50 25 0 25 50 75 100
TEMPERATURE, TC (C) TEMPERATURE, T C (C) CASE TEMPERATURE, TC (C)

120 0 100
|+VS | + |-VS | = 100V

OPEN LOOP GAIN, A OL (dB)
100 30 68
|+VS | + |-VS | = 70V
80 46
60
PHASE, ()
32
60 90
22
C
40 120
15
20 150
10
0 180 6.8
20 210 4.6

120 8 20
VIN = 5V, t r = 100ns

6
100
4
10
80
2
60 0 6
40 2
4
4
20
6
0 8 2
1 10 100 1K 10K .1M 1M 0 2 4 6 8 10 12 10 100 1K 10K .1M
HARMONIC DISTORTION QUIESCENT CURRENT

VOLTAGE DROP FROM SUPPLY, VSAT (V)
OUTPUT VOLTAGE SWING

10 1.6 6
G =10
3 1.4 5 C
DISTORTION, THD (%)
T C = 25C 25
4
TC=
8
1.2
=
1 4
L
,R
L
=
,R
C
5V
T C = 25C 25
L
,R
W
TC =
2
m
6V
.3 1.0 3
50
C
S
,V
=
TC = 85C 85
TC =
=
O
W
P
S
,V
.1
50
.8 2
W
=
60
C
O
T C = 125
P
.03 .6 1
O
P
.01 .4 0
100 300 1K 3K 10K 30K .1M 40 50 60 70 80 90 100 0 1 2 3 4 5 6
FREQUENCY, F (Hz) TOTAL SUPPLY VOLTAGE, VS (V) OUTPUT CURRENT, I O (A)
164
OPERATING
GENERAL *If the inductive load is driven near steady state conditions,
Please read the General Operating Considerations sec- allowing the output voltage to drop more than 12V below the
tion, which covers stability, supplies, heatsinking, mounting, supply rail with ILIM = 5A or 32V below the supply rail with ILIM =
current limit, SOA interpretation, and specification interpreta- 2A while the amplifier is current limiting, the inductor must be
tion. Additional information can be found in the application capacitively coupled or the current limit must be lowered to
notes. For information on the package outline, heatsinks, and meet SOA criteria.
mounting hardware, consult the Accessory and Package
Mechanical Data section of the handbook. 2. The amplifier can handle any reactive or EMF generating
load and short circuits to the supply rail or common if the
current limits are set as follows at TC = 85C:
The output stage of most power amplifiers has three distinct SHORT TO VS SHORT TO
limitations: VS C, L, OR EMF LOAD COMMON
1. The current handling capability of the wire bonds.
2. The second breakdown effect which occurs whenever the 50V .25A .82A
simultaneous collector current and collector-emitter volt- 40V .37A 1.4A
age exceed specified limits. 30V .65A 2.1A
3. The junction temperature of the output transistors. 20V 1.4A 3.3A
15V 2.1A 4.5A
SAFE OPERATING AREA CURVES
5.0 These simplified limits may be exceeded with further analysis
t=
TH
ER
0.5
Tc MA
t=
=2 L
ms
3.0 3. The output stage is protected against transient flyback.

1m
5C
Tc
s

t=
=8
5C
5m
2.0 flyback, external fast-recovery diodes should be used.

Tc
ste
=1
ad
1.5 25
ys
C
THERMAL SHUTDOWN PROTECTION
ta
te
SE
1.0 The thermal protection circuit shuts off the amplifier when
CO
steady state the substrate temperature exceeds approximately 150C. This

ND
.7 allows heatsink selection to be based on normal operating

BR
EA
conditions while protecting the amplifier against excessive

KD
.5
junction temperature during temporary fault conditions.
OW
Thermal protection is a fairly slow-acting circuit and there-

N
.3
fore does not protect the amplifier against transient SOA
violations (areas outside of the TC = 25C boundary). It is
designed to protect against short-term fault conditions that
.2
10 15 20 25 30 35 40 50 60 70 80 100 result in high power dissipation within the amplifier. If the
SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE V S VO (V) conditions that cause thermal shutdown are not removed, the
amplifier will oscillate in and out of shutdown. This will result in
The SOA curves combine the effect of these limits. For a high peak power stresses, will destroy signal integrity and
given application, the direction and magnitude of the output reduce the reliability of the device.
the SOA curves. This is simple for resistive loads but more CURRENT LIMIT
complex for reactive and EMF generating loads. However, the
following guidelines may save extensive analytical efforts.
tors, connected as shown in the external connections diagram.
The minimum value for RCL is .12, however, for optimum
1. Under transient conditions, capacitive and inductive* loads reliability it should be set as high as possible. Refer to the
up to the following maximum are safe:
General Operating Considerations section of the handbook
for current limit adjust details.
50V 80F 75F 55mH 7.5mH

40V 250F 150F 150mH 11mH
30V 1,200F 500F 250mH 24mH
20V 20mF 5mF 1.5H 75mH
15V 25mF 100mH
without notice.
PA07U REV. K DECEMBER 1997 1997 Apex Microtechnology Corp.
165
PA07M

1 Input Bias Current, +IN +IB 25C 35V VIN = 0 50 pA
1 Input Bias Current, IN IB 25C 35V VIN = 0 50 pA
1 Input Offset Current IOS 25C 35V VIN = 0 50 pA

3 Input BiasCurrent, IN IB 55C 35V VIN = 0 50 pA


4 Current Limits ICL 25C 19V RL = 12, RCL= 1 .54 .86 A
4 Slew Rate SR 25C 35V RL = 500 2.5 10 V/s
4 Common Mode Rejection CMR 25C 34.5V RL = 500, F = DC, VCM = 24.5V 80 dB


100K

1
100K burn in board.
5 3
2
6 20
1
15V
however, FAXis(520)
ORDERS (520) 690-8601
PA07MU REV. F FEBRUARY 1998 1998 Apex Microtechnology Corp.
166
NOTES:
167
PA08 PA08A
FEATURES
WIDE SUPPLY RANGE 15V to 150V
PROGRAMMABLE OUTPUT CURRENT LIMIT
HIGH OUTPUT CURRENT Up to 150mA
APPLICATIONS
HIGH VOLTAGE INSTRUMENTATION
ELECTROSTATIC TRANSDUCERS & DEFLECTION TYPICAL APPLICATION
PROGRAMMABLE POWER SUPPLIES UP TO 290V +132V
ANALOG SIMULATORS
DESCRIPTION +132V
110K
+VS
The PA08 is a high voltage operational amplifier designed
for output voltage swings of up to 145V with a dual () supply DAC
1mA
or 290V with a single supply. High accuracy is achieved with 8.2
a cascode input circuit configuration. All internal biasing is PA08 D.U.T.
referenced to a zener diode fed by a FET constant current
source. As a result, the PA08 features an unprecedented 8.2
C
supply range and excellent supply rejection. The output
-132V -VS
stage is biased-on for linear operation. Internal phase com-
pensation assures stability at all gain settings. The safe
-132V
operating area (SOA) can be observed with all types of loads
by choosing the appropriate current limiting resistors. For
ATE PIN DRIVER
operation into inductive loads, two external flyback pulse
protection diodes are recommended. A heatsink may be
necessary to maintain the proper case temperature under The PA08 as a pin driver is capable of supplying high test
normal operating conditions. voltages to a device under test (DUT). Due to the possibility of
This hybrid integrated circuit utilizes beryllia (BeO) sub- short circuits to any terminal of the DUT, current limit must be
strate, thick film resistors, ceramic capacitors and semicon- set to be safe when limiting with a supply to output voltage
ductor chips to maximize reliability, minimize size and give differential equal to the amplifier supply plus the largest
top performance. Ultrasonically bonded aluminum wires pro- magnitude voltage applied to any other pin of the DUT. In
vide reliable interconnections at all operating temperatures. addition, flyback diodes are recommended when the output of
The 8-pin TO-3 package is hermetically sealed and electri- the amplifier exits any equipment enclosure to prevent dam-
age due to electrostatic discharges. Refer to Application Note
cally isolated. The use of compressible thermal isolation
7 for details on accuracy considerations of this circuit.
washers and/or improper mounting torque will void the prod-
uct warranty. Please see General Operating Considerations.
EQUIVALENT SCHEMATIC
3 R CL+
CL+
+VS
2 OUT
7 D1 3
C1 1
Q1 Q2 Q3 RT OUTPUT
+IN
Q4 4
Q5 C3 Q6 TOP VIEW
2
IN 5
Q7
Q8 Q9 C2 RS 8
1 R CL
6 CL
Q10 7
C4 Q11 Q19 VS
5 8
BAL RS = ( +V S
+ VS )R T /1.6
Q12A Q12B
4 Q17 NOTE: Input offset voltage trim optional. R T = 10K MAX
Q15 Q16
D2
168

OUTPUT CURRENT, within SOA 200mA
POWER DISSIPATION, internal at TC = 25C 17.5W
TEMPERATURE, pin solder - 10s max 300C

2
INPUT
OFFSET VOLTAGE, vs. temperature TC = 25C to +85C 15 30 5 10 V/C
OFFSET VOLTAGE, vs. supply TC = 25C .5 * 2 V/V
OFFSET VOLTAGE, vs. time TC = 25C 75 * V/kh
INPUT IMPEDANCE, DC TC = 25C 105 * M
COMMON MODE VOLTAGE RANGE4 TC = 25C to +85C VS10 * V
COMMON MODE REJECTION, DC TC = 25C to +85C, VCM = 90V 130 * dB
GAIN
OPEN LOOP GAIN at 10Hz TC = 25C, RL = 118 * dB
OPEN LOOP GAIN at 10Hz TC = 25C, RL = 1.2K 96 111 * * dB
GAIN BANDWIDTH PRODUCT at 1MHz TC = 25C, RL = 1.2K 5 * MHz
POWER BANDWIDTH TC = 25C, RL = 1.2K 90 * kHz
PHASE MARGIN TC = 25 to +85C 60 *
OUTPUT
VOLTAGE SWING4 TC = 25C, IO = 150mA VS15 VS8 * * V
VOLTAGE SWING4 TC = 25o C to +85oC, IO = 75mA VS10 VS5 * * V
VOLTAGE SWING4 TC = 25o C to +85oC, IO = 20mA VS5 VS3 * * V
CURRENT, peak TC = 85C 150 * mA
SLEW RATE TC = 25C 30 20 * V/s
CAPACITIVE LOAD, AV = 1 TC = 25 to +85C 10 * nF
CAPACITIVE LOAD, AV > 4 TC = 25 to +85C SOA *
SETTLING TIME to .1% TC = 25C, RL= 1.2K, 2V step 1 * s
POWER SUPPLY
VOLTAGE TC = 55 to +125C 15 100 150 * * * V
CURRENT, quiescent TC = 25C 6 8.5 * * mA
THERMAL
RESISTANCE, AC junction to case5 TC = 55 to +125C, F > 60Hz 3.8 * C/W
RESISTANCE, DC junction to case TC = 55 to +125C, F < 60Hz 6.0 6.5 * * C/W
RESISTANCE, junction to air TC = 55 to +125C 30 * C/W
achieve high MTTF.
2. The power supply voltage specified under typical (TYP) applies unless otherwise noted.
3. Doubles for every 10oC of temperature increase.
4. +VS and VS denote the positive and negative supply rail respectively.
5. Rating applies only if output current alternates between both output transistors at a rate faster than 60Hz.
169
TYPICAL PERFORMANCE
GRAPHS PA08 PA08A
POWER DERATING CURRENT LIMIT OPEN LOOP GAIN

250
RELATIVE OPEN LOOP GAIN, A (dB)

30 6
R L =1.2K

25 200 4
T
C =
TC -25
20 R CL = 4.7 2 =8
5C C
150
TC = -2
15 0 5C
100
10 R CL = 10 2
5 50
4
0 0 6
0 25 50 75 100 125 150 -55 -25 0 25 50 75 100 125 30 50 100 150 200 250 300
TEMPERATURE, T(C) CASE TEMPERATURE, TC (C) TOTAL SUPPLY VOLTAGE, VS (V)

120 0 300
R L =1.2K R L =1.2K |+VS | + |VS | = 300V

100 30 200
80 60
PHASE, ()
100
60 90 C
40 120 60
20 150 |+VS | + |VS | = 100V

30
0 180
-20 210 15
1 10 100 1K 10K .1M 1M 10M 0 10 100 1K 10K .1M 1M 10M 50K .1M .2M .3M .5M .7M 1M
PULSE RESPONSE SLEW RATE INPUT NOISE

6 1.6 20
NORMALIZED SLEW RATE (X)
RL =1.2K 15
OUTPUT VOLTAGE, Vo (V)
4 1.4
10
2 1.2
0 1.0 6
2 .8
4
4 .6
VIN = 5V, t r = 100ns
6 .4 2
0 .5 1 1.5 2.0 2.5 30 50 100 150 200 250 300 10 100 1K 10K .1M
TIME, t (s) TOTAL SUPPLY VOLTAGE, VS (V) FREQUENCY, F (Hz)
COMMON MODE REJECTION POWER SUPPLY REJECTION COMMON MODE VOLTAGE

COMMON MODE REJECTION CMR (dB)
COMMON MODE VOLTAGE, VCM (Vpp)
140 140 300

|+VS | + |V S | = 300V
120 120 200
100 100
100
80 80 +VS
60 60 60
40 40
VS |+VS | + |VS | = 100V
30
20 20
0 0 15
1 10 100 1K 10K .1M 1M 1 10 100 1K 10K .1M 1M 10K 20K 50K .1M .2M .5M 1M
170
OPERATING
GENERAL 3. The output stage is protected against transient flyback.

Please read the General Operating Considerations, which However, for protection against sustained, high energy
covers stability, supplies, heatsinking, mounting, current limit, flyback, external fast-recovery diodes should be used.
SOA interpretation, and specification interpretation. Additional
information can be found in the application notes. For informa-
tion on the package outline, heatsinks, and mounting hardware,
INDUCTIVE LOADS
see the Package Outlines and Accessories sections of the Two external diodes as shown in Figure 1, are required to
handbook. protect these amplifiers from flyback (kickback) pulses
exceeding the supply voltages of the amplifier when driving
SAFE OPERATING AREA (SOA) inductive loads. For component selection, these external
The output stage of most power amplifiers has two distinct diodes must be very quick, such as ultra fast recovery diodes
limitations: with no more than 200 nanoseconds of reverse recovery time.
1. The current handling capability of the transistor geometry The diode will turn on to divert the flyback energy into the supply
and the wire bonds. rails thus protecting the output transistors from destruction due
2. The second breakdown effect which occurs whenever the to reverse bias.
simultaneous collector current and collector-emitter voltage A note of caution about the supply. The energy of the flyback
pulse must be absorbed by the power supply. As a result, a
exceeds specified limits. transient will be superimposed on the supply voltage, the
200 magnitude of the transient being a function of its transient
t= impedance and current sinking capability. If the supply voltage
150
t = 200
OUTPUT CURRENT FROM
plus transient exceeds the maximum supply rating or if the AC

0.5 s impedance of the supply is unknown, it is best to clamp the
t= ms
+V S OR VS (mA)
100 1m
s output and the supply with a zener diode to absorb the transient.
t=
80 ste 5m
ad
ys
s INPUT PROTECTION
50 tat The input is protected against common mode voltages up to
e
40 the supply rails and differential voltages up to 50V. Increased
protection against differential input voltages can be obtained by
30
adding 2 resistors, 2 capacitors and 4 diode connected FETs
as shown in Figure 2.
20
80 100 120 150 170 200 250 300
Fig. 1 +VS Fig. 2 100pf/200V
SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE (V)
150K _
The SOA curves combine the effect of these limits. For a +IN
given application, the direction and magnitude of the output IN4936 OR
UES1106 Q1 Q3
Q2 Q4
following guidelines may save extensive analytical efforts. IN +
150K
VS
1. Under transient conditions, the following capacitive and
100pf/200V
inductive loads are safe with the current limits set to the
PROTECTION, INDUCTIVE LOAD PROTECTION, OVERVOLTAGE
maximum:
VS C(MAX) L(MAX)
CURRENT LIMITING
150V .4F 280mH Proper operation requires the use of two current limit resis-
125V .9F 380mH tors, connected as shown in the external connection diagram.
100V 2F 500mH The minimum value for RCL is 3.24. However, for optimum
75V 10F 1200mH reliability it should be set as high as possible. Refer to the
50V 100F 13H General Operating Considerations section of the handbook
2. The amplifier can handle any EMF generating or reactive for current limit adjust details.
load and short circuits to the supply rails or simple shorts to
common if the current limits are set as follows:
SHORT TO VSC, SHORT TO
VS C, L, OR EMF LOAD COMMON
150V 20mA 67mA
125V 27mA 90mA
100V 42mA 130mA
75V 67mA 200mA
50V 130mA 200mA
These simplified limits may be exceeded with further analysis
without notice.
PA08U REV. I FEBRUARY 1998 1998 Apex Microtechnology Corp.
171
PA08M
1 Quiescent Current IQ 25C 100V VIN = 0, AV = 100 8.5 mA




4 Output Voltage, IO = 29mA VO 25C 150V RL = 5K 145 V
4 Current Limits ICL 25C 30V RL = 100 75 125 mA
4 Stability/Noise EN 25C 100V RL = 5K, AV = 1, CL = 10nF 1 mV
4 Slew Rate SR 25C 100V RL = 5K 20 100 V/s
4 Open Loop Gain AOL 25C 100V RL = 5K, F = 10Hz 96 dB
4 Common Mode Rejection CMR 25C 32.5V RL = 5K, F = DC, VCM = 22.5V 90 dB
6 Output Voltage, IO = 100mA VO 55C 31V RL =100 10 V


100K * These components are used to stabilize device

BURN IN CIRCUIT
due to poor high frequency characteristics of
+50V burn in board.
5
100K 5 3
2 ** Input signals are calculated to result in internal
* 1
power dissipation of approximately 2.1W at
U.U.T case temperature = 125C.
** * 4 8
6 60
5
50V
however, FAXis(520)
ORDERS (520) 690-8601
PA08MU REV. H FEBRUARY 1998 1998 Apex Microtechnology Corp.
172
POWER OPERATIONAL AMPLIFIER
PA08V
FEATURES
EXTENDED SUPPLY RANGE
UP TO 175V or
350V TOTAL
PROVIDES PA08 PERFORMANCE
UP TO 150mA
PROGRAMMABLE CURRENT LIMIT
LOW DRIFT FET INPUT
APPLICATIONS Please consult the PA08 data sheet for basic information on
this amplifier, plus the application notes in this APEX DATA
PROGRAMMABLE POWER SUPPLIES UP TO 340V BOOK, for recommendations on stability, current limiting,
ELECTROSTATIC TRANSDUCERS & DEFLECTION heatsinks, bypassing, and suggestions for circuit functions.
PIEZO ELECTRIC TRANSDUCERS
SAFE OPERATING AREA CURVE (SOA)
OUTPUT CURRENT FROM +VS OR VS (mA)

150
DESCRIPTION t=
The PA08V is an extended supply range operational ampli- 100 20
0
fier capable of output voltage swings of 170V with dual 80 t= s
supplies or 340V total supply voltage on single or non-symmet- 0.5
ms
ric supplies. t=
1m
High accuracy is achieved with a cascode input circuit configu- 50 t= s
ration. All internal biasing is referenced to a zener diode fed by 5m
40 ste s
a FET constant current source. As a result, the PA08 features an ad
ys
unprecedented supply range and excellent supply rejection. The tat
30 e
output stage is biased class A-B for linear operation. Internal
phase compensation assures stability at all gain settings. The
safe operating area (SOA) can be observed with all types of 20
loads by choosing the appropriate current limiting resistors. For
operation into inductive loads, two external flyback pulse protec- 15
90 100 125 150 175 200 250 300 350
tion diodes are recommended. A heatsink may be necessary to
maintain the proper case temperature under normal operating SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE (V)
conditions.
This hybrid integrated circuit utilizes a beryllia (BeO) sub-
strate, thick film resistors, ceramic capacitors, and semicon- EQUIVALENT SCHEMATIC
ductor chips to maximize reliability, minimize size and give top
3
performance. Ultrasonically bonded aluminum wires provide
reliable interconnections at all operating temperatures. The
8-pin to TO-3 package is hermetically sealed and electrically 7 D1 C1
isolated. The use of compressible thermal isolation washers Q1 Q2 Q3
and/or improper mounting torque will void the product war- Q4
ranty. Please see General Operating Considerations. Q5 C3 Q6
2
SPECIFICATIONS Q8 Q9 C2
Q7
1
Specifications of the standard PA08 apply with the benefit of Q10
supply ratings being extended to 175V. Design changes C4 Q11 Q19
enabling the total supply rating of 350V have no effect on the 5 8
shape of the typical performance graphs. Q12A Q12B Q17
4
GENERAL CONSIDERATIONS Q15 Q16
SAFE OPERATING AREA D2

The extended safe operating area is as follows:
When operating on 175V, maximum safe values of capaci- 6
tive and inductive loading are .2F and 200mH. Maximum safe
current limit for a short to common is 50mA, and for a short to
supply rails, the maximum is 15mA.
omissions. HOTLINE:
change 546-2739
without notice.
PA08VU REV. F FEBRUARY 1998 1998 Apex Microtechnology Corp.
173
VIDEO POWER OPERATIONAL AMPLIFIERS
PA09 PA09A
FEATURES
POWER MOS TECHNOLOGY 2A peak rating
HIGH GAIN BANDWIDTH PRODUCT 150MHz
VERY FAST SLEW RATE 400V/s
PROTECTED OUTPUT STAGE Thermal shutoff
EXCELLENT LINEARITY Class A/B output
LOW BIAS CURRENT, LOW NOISE FET input
APPLICATIONS DEFLECTION AMPLIFIER (Figure 1)
The deflection amplifier circuit of Figure 1 achieves arbitrary
VIDEO DISTRIBUTION AND AND AMPLIFICATION beam positioning for a fast heads-up display. Maximum tran-
HIGH SPEED DEFLECTION CIRCUITS sition times are 4s while delivering 2A pk currents to the
POWER TRANSDUCERS TO 5MHz 13mH coil. The key to this circuit is the sense resistor (RS)
COAXIAL LINE DRIVERS which converts yoke current to voltage for op amp feedback.
This negative feedback forces the coil current to stay exactly
POWER LED OR LASER DIODE EXCITATION proportional to the control voltage. The network consisting of
RD, RF and CF serves to shift from a current feedback via RS to
DESCRIPTION a direct voltage feedback at high frequencies. This removes
The PA09 is a high voltage, high output current operational the extra phase shift caused by the inductor thus preventing
amplifier optimized to drive a variety of loads from DC through oscillation. See Application Note 5 for details of this and other C
the video frequency range. Excellent input accuracy is precision magnetic deflection circuits.
achieved with a dual monolithic FET input transistor which is
cascoded by two high voltage transistors to provide outstand- EQUIVALENT SCHEMATIC
ing common mode characteristics. All internal current and
voltage levels are referenced to a zener diode biased on by 2
a current source. As a result, the PA09 exhibits superior DC 3
and AC stability over a wide supply and temperature range. D1 C1

High speed and freedom from second breakdown is as- Q5
sured by a complementary Power MOS output stage. For Q3
Q1 Q2
optimum linearity, especially at low levels, the Power MOS Q4 Q6
transistors are biased in the class A/B mode. Thermal shutoff 7
provides full protection against overheating and limits the 8

Q7
heatsink requirements to dissipate the internal power losses Q13
under normal operating conditions. A built-in current limit
Q8 Q9 Q11 1
protects the amplifier against overloading. Transient induc-
tive load kickback protection is provided by two internal Q12A
C2
Q12B Q14
Q17
clamping diodes. External phase compensation allows the 5
user maximum flexibility in obtaining the optimum slew rate Q10

and gain bandwidth product at all gain settings. For continu- 4 D3 Q19
ous operation under load, a heatsink of proper rating is Q15 Q16
recommended.
Q18 D2
This hybrid integrated circuit utilizes thick film (cermet) resistors,
ceramic capacitors and silicon semiconductor chips to maximize
6
reliability, minimize size and give top performance. Ultrasonically
bonded aluminum wires provide reliable interconnections at all
operating tempera-
tures. The 8-pin TO-3 EXTERNAL CONNECTIONS
+37V di
package is hermetically CC 2pF = 15A /s
sealed and electrically 3 dt
+VS BAL PHASE COMPENSATION
isolated. The use of V 4 7 i = Vi /RS 2
8 3
OUT
com-pressible thermal I 1 RT 1 GAIN CC RC
washers and/or im- PA09 4
5 CF LY +IN
TOP VIEW 1 100pF 200
proper mounting torque 470pF 10 15pF 0
13H RS 5
will void the product 6
IN 100 5pF 0
RD 1 8
1000 none none
warranty. Please see 37V RF 6
7 CC
12K VS
General Operating RC CC
Considerations. 100 R RC
S
.5 RS = (| +VS | + | VS |) RT /1.6
FIGURE 1. PA09 AS DEFLECTION AMPLIFIER NOTE: Input offset voltage trim optional. RT = 10K MAX
174


2
INPUT

OFFSET VOLTAGE, vs. temperature TC = 25 to +85C 10 30 5 10 V/C
OFFSET VOLTAGE, vs. power TC = 25 to +85C 20 * V/W
OFFSET CURRENT, initial TC = 25C 2.5 50 1.5 10 pA
COMMON MODE VOLTAGE RANGE3 TC = 25 to +85C VS10 VS8 * * V
COMMON MODE REJECTION, DC TC = 25 to +85C, VCM = 20V 104 * dB
GAIN
OPEN LOOP GAIN at 10Hz TC = 25C, RL = 1k 90 * dB

GAIN BANDWIDTH PRODUCT at 1MHz TC = 25C, RL = 15, CC = 5pF 150 * MHz
POWER BANDWIDTH, gain of 100 comp TC = 25C, RL = 15, CC = 5pF 1.2 * MHz
POWER BANDWIDTH, unity gain comp TC = 25C, RL = 15, CC = 100pF .75 * MHz
OUTPUT
VOLTAGE SWING3 TC = 25 to +85C, IO = 2A VS 8 VS 7 * * V

CURRENT, PEAK TC = 25C 4.5 * A
SLEW RATE, gain of 100 comp TC = 25C, CC = 5pF 400 * V/s
SLEW RATE, unity gain comp TC = 25C, CC = 100pF 75 * V/s
POWER SUPPLY
VOLTAGE TC = 25 to +85C 12 35 40 * * * V
THERMAL
RESISTANCE, AC junction to case4 TC = 25 to +85C, F > 60Hz 1.2 1.3 * * C/W

RESISTANCE, DC junction to case TC = 25 to +85C, F < 60Hz 1.6 1.8 * * C/W
TEMPERATURE RANGE, case Meets full range specifications 25 25 + 85 * * * C
achieve high MTTF.
2. The power supply voltage for all tests is 35V unless otherwise specified as a test condition.
3. +VS and -VS denote the positive and negative supply rail respectively. Total VS is measured from +VS to VS.
175
TYPICAL PERFORMANCE
GRAPHS PA09 PA09A

POWER DERATING CURRENT LIMIT QUIESCENT CURRENT
80 9 1.6
70 8
1.4
CURRENT LIMIT, ILIM (A)

60 7
50 6 1.2
40 5
30 4 1.0
20 3
.8
10 2
0 1 .6
0 25 50 75 100 125 150 55 25 0 25 50 75 100 125 30 40 50 60 70 80
CASE TEMPERATURE, TC (C) JUNCTION TEMPERATURE, Tj (C) TOTAL SUPPLY VOLTAGE, VS (V)
SMALL SIGNAL RESPONSE OUTPUT VOLTAGE SWING POWER RESPONSE

100 10 70
CC = 5pF

80 9 50
40
CC = 15pF 8
60 30
7 C
CC
40
20
CC
CC = 100pF 6
=1
=1
5pF
20 15
5
00p
F
0 10
4
| +VS | + | VS | = 80V
20 3 7
100 1K 10K 100K 1M 10M 100M 0 1 2 3 4 5 100K 300K 1M 3M 10M 30M
FREQUENCY, F (Hz) OUTPUT CURRENT, IO (A) FREQUENCY, F (Hz)
SLEW RATE VS. COMP. PULSE RESPONSE INPUT NOISE

600 30 30
500 Vin = 2V, AV = 10, tr = 10ns

20
20
400
SLEW RATE, (V/s)
10 15
300
0 10
200 7
10
150 5
20
100 30 3
5 10 20 30 50 100 0 .1 .2 .3 .4 .5 .6 .7 .8 10 100 1K 10K 100K 1M
COMPENSATION CAPACITOR, CC(pF) TIME, t (s) FREQUENCY, F (Hz)

COMMON MODE VOLTAGE, VCM (VPP)
120 100 70
50
100 80 | +VS | + | VS | = 80V
40
60 30
80
20
60 40 CC= 100pF
15
40 20
10
20 0 7
1K 10K 100K 1M 10M 100M 1K 10K 100K 1M 10M 100M 100K 300K 1M 3M 10M 30M
FREQUENCY, F (Hz) FREQUENCY, F(Hz) FREQUENCY, F(Hz)
176
OPERATING
GENERAL tantalum capacitor of at least 47F in parallel with a .47F

ceramic capacitor directly connected from the power supply
Please read the General Operating Considerations sec- pins to the ground plane.
tion, which covers stability, supplies, heatsinking, mounting,
current limit, SOA interpretation, and specification interpreta- OUTPUT LEADS
tion. Additional information can be found in the application
notes. For information on the package outline, heatsinks, and Keep the output leads as short as possible. In the video
mounting hardware, consult the Accessory and Package frequency range, even a few inches of wire have significant
Mechanical Data section of the handbook. inductance, raising the interconnection impedance and limit-
ing the output current slew rate. Furthermore, the skin effect
SUPPLY VOLTAGE increases the resistance of heavy wires at high frequencies.
Multistrand Litz Wire is recommended to carry large video
The specified voltage (VS) applies for a dual () supply currents with low losses.
having equal voltages. A nonsymmetrical (ie. +70/10V) or a
single supply (ie. 80V) may be used as long as the total voltage GROUNDING
between the +VS and VS rails does not exceed the sum of the
voltages of the specified dual supply. Single point grounding of the input resistors and the input
signal to a common ground plane will prevent undesired
SAFE OPERATING AREA (SOA) current feedback, which can cause large errors and/or insta-
bilities.
The MOSFET output stage of this power operational ampli-
fier has two distinct limitations: THERMAL SHUTDOWN PROTECTION
1. The current handling capability of the MOSFET geometry
and the wire bonds. The thermal protection circuit shuts off the amplifier when
2. The junction temperature of the output MOSFETs. the substrate temperature exceeds approximately 150C. This
allows heatsink selection to be based on normal operating
SAFE OPERATING AREA CURVES conditions while protecting the amplifier against excessive
junction temperature during temporary fault conditions.
5.0 Thermal protection is a fairly slow-acting circuit and there-

TC = 25C fore does not protect the amplifier against transient SOA
4.0 violations (areas outside of the TC = 25C boundary). It is
t=
3.5 10 designed to protect against short-term fault conditions that
0m result in high power dissipation within the amplifier, If the
3.0 t= s
30 conditions that cause thermal shutdown are not removed, the
2.5 0m
s amplifier will oscillate in and out of shutdown. This will result in
high peak power stresses, destroy signal integrity, and reduce
2.0 st
ea the reliability of the device.
dy
st
1.5 at
e STABILITY
Due to its large bandwidth the PA09 is more likely to oscillate
than lower bandwidth Power Operational Amplifiers. To pre-
vent oscillations a reasonable phase margin must be main-
15 20 25 30 35 40 50 60 70 80 tained by:
INTERNAL VOLTAGE DROP SUPPLY TO OUTPUT VS VO (V) 1. Selection of the proper phase compensation capacitor and
The SOA curves combine the effect of these limits and allow resistor. Use the values given in the table under external
for internal thermal delays. For a given application, the direc- connections on the first page of this data sheet and interpo-
tion and magnitude of the output current should be calculated late if necessary. The phase margin can be increased by
or measured and checked against the SOA curves. This is using a larger capacitor and a smaller resistor than the slew
simple for resistive loads but more complex for reactive and rate optimized values listed in the table.
EMF generating loads. The following guidelines may save 2. Keeping the external sumpoint stray capacitance to ground
extensive analytical efforts: at a minimum and the sumpoint load resistance (input and
1. Capacitive and inductive loads up to the following maxi- feedback resistors in parallel) below 500. Larger sumpoint
mums are safe: load resistances can be used with increased phase com-
pensation and/or bypassing of the feedback resistor.
VS CAPACITIVE LOAD INDUCTIVE LOAD 3. Connect the case to a local AC ground potential.
40V .1F 11mH
30V 500F 24mH CURRENT LIMIT
20V 2500F 75mH
Internal current limiting is provided in the PA09. Note the
15V 100mH
current limit curve given under typical performance graphs is
2. Short circuits to ground are safe with dual supplies up to based on junction temperature. If the amplifier is operated at
20V. cold junction temperatures, current limit could be as high as 8
3. The output stage is protected against transient flyback. amps. This is above the maximum allowed current on the SOA
However, for protection against sustained, high energy curve of 5 amps. Systems using this part must be designed to
flyback, external fast-recovery diodes should be used. keep the maximum output current to less than 5 amps under
all conditions. The internal current limit only provides this
BYPASSING OF SUPPLIES protection for junction temperatures of 80C and above.
Each supply rail must be bypassed to common with a
omissions. HOTLINE:
change 546-2739
without notice.
PA09U REV. H FEBRUARY 1998 1998 Apex Microtechnology Corp.
177
PA09M

1 Inout Bias Current, IN IB 25C 35V VIN = 0 100 pA



4 Current Limits ICL 25C 32.2V RL = 3.75 3.4 6 A
4 Stability/Noise EN 25C 35V RL = 500, AV = 1, CL = 1.5nF 1 mV


5 Output Voltage, IO = 1A VO 125C 23.5V RL = 15 15 V
5 Slew Rate SR 125C 35V RL = 500, 20 500 V/s

BURN IN CIRCUIT
+15V burn in board.
100K 5 3 ** Input signals are calculated to result in internal
* 1 power dissipation of approximately 2.1W at
7
** * 4 8 20
100pF
220
15V
however, FAXis(520)
ORDERS (520) 690-8601
178
NOTES:
179
PA10 PA10A
FEATURES
GAIN BANDWIDTH PRODUCT 4MHz
TEMPERATURE RANGE 55 to +125 C (PA10A)
APPLICATIONS
MOTOR, VALVE AND ACTUATOR CONTROL
MAGNETIC DEFLECTION CIRCUITS UP TO 4A TYPICAL APPLICATION
POWER TRANSDUCERS UP TO 100kHz
R2A
TEMPERATURE CONTROL UP TO 180W
PROGRAMMABLE POWER SUPPLIES UP TO 90V +42V
AUDIO AMPLIFIERS UP TO 60W RMS R1A .82
RS
PA10
DESCRIPTION
The PA10 and PA10A are high voltage, high output current CONTROL C
operational amplifiers designed to drive resistive, inductive and .82 LOAD
capacitive loads. For optimum linearity, the output stage is R1B 42V R2B 0-24
biased for class A/B operation. The safe operating area (SOA)
can be observed for all operating conditions by selection of user
programmable current limiting resistors. Both amplifiers are
internally compensated for all gain settings. For continuous
operation under load, a heatsink of proper rating is recom- FIGURE 1. VOLTAGE-TO-CURRENT CONVERSION
mended.
This hybrid integrated circuit utilizes thick film (cermet) DC and low distortion AC current waveforms are delivered
resistors, ceramic capacitors and semiconductor chips to maxi- to a grounded load by using matched resistors (A and B
mize reliability, minimize size and give top performance. Ultra- sections) and taking advantage of the high common mode
sonically bonded aluminum wires provide reliable interconnec- rejection of the PA10.
tions at all operating temperatures. The 8-pin TO-3 package is Foldover current limit is used to modify current limits based
hermetically sealed and electrically isolated. The use of com- on output voltage. When load resistance drops to 0, the current
pressible isolation washers voids the warranty. is limited based on output voltage. When load resistance
drops to 0, the current limit is 0.79A resulting in an internal
EQUIVALENT SCHEMATIC dissipation of 33.3 W. When output voltage increases to 36V,
the current limit is 1.69A. Refer to Application Note 9 on
3 foldover limiting for details.
D1 EXTERNAL CONNECTIONS
Q2A
Q1 Q2B R CL+
CL+
+VS
2 OUT
2 3
Q3 1
+IN OUTPUT
4
Q4 1 TOP VIEW
7
Q5 IN 5
8 8
6 CL R CL
4 7
Q6B VS
FO
A1 Q6A
5 C1
180


2, 5
INPUT
OFFSET VOLTAGE, vs. supply TC = 25C 30 200 * * V/V
OFFSET VOLTAGE, vs. power TC = 25C 20 * VW
BIAS CURRENT, initial TC = 25C 12 30 10 20 nA
BIAS CURRENT, vs. temperature Full temperature range 50 500 * * pA/C
OFFSET CURRENT, initial TC = 25C 12 30 5 10 nA
OFFSET CURRENT, vs. temperature Full temperature range 50 * pA/C
COMMON MODE REJECTION, DC3 Full temp. range, VCM = VS 6V 74 100 * * dB
GAIN
OPEN LOOP GAIN at 10Hz TC = 25C, 1K load 110 * dB
OPEN LOOP GAIN at 10Hz Full temp. range, 15 load 96 108 * * dB
GAIN BANDWIDTH PRODUCT @ 1MHz TC = 25C, 15 load 4 * MHz
POWER BANDWIDTH TC = 25C, 15 load 10 15 * * kHz
OUTPUT
SLEW RATE TC = 25C 2 3 * * V/s
CAPACITIVE LOAD Full temperature range, AV = 1 .68 * nF
CAPACITIVE LOAD Full temperature range, AV = 2.5 10 * nF
CAPACITIVE LOAD Full temperature range, AV > 10 SOA * nF
POWER SUPPLY
CURRENT, quiescent TC = 25C 8 15 30 * * * mA
THERMAL
RESISTANCE, AC, junction to case4 TC = 55 to +125C, F > 60Hz 1.9 2.1 * * C/W
RESISTANCE, DC, junction to case TC = 55 to +125C 2.4 2.6 * * C/W
2. The power supply voltage for all tests is 40, unless otherwise noted as a test condition.
5. Full temperature range specifications are guaranteed but not tested.
181
TYPICAL PERFORMANCE
GRAPHS PA10 PA10A

70

2.5 3.5
60 2.2 3.0

T = TC
50 1.9 2.5
R CL = 0.3
40 1.6 2.0
30 1.3 1.5
R CL = 0.6
PA10 PA10A
20 1.0 1.0
10 T = TA .7 .5
0 .4 0
0 20 40 60 80 100 120 140 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125
TEMPERATURE, T (C) CASE TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C)

120 0 100
|+VS | + |VS | = 100V

100 30 68
|+VS | + |VS | = 80V

60 46
80
PHASE, ()
32
60 90 C
22
40 120
|+VS | + |VS | = 30V
15
20 150
10
0 180
6.8
20 210 4.6

120 8 100
6 VIN = 5V, t r = 100ns

100 70
4
50
80
2 40
60 0 30
40 2
20
4
20
6
0 8 10
0 10 100 1K 10K .1M 1M 0 2 4 6 8 10 12 10 100 1K 10K .1M
HARMONIC DISTORTION QUIESCENT CURRENT OUTPUT VOLTAGE SWING

3
VOLTAGE DROP FROM SUPPLY, (V)
1.6 6
AV =10
1 VS = 38V 1.4
R L =8 TC = -2
5C 5 25C
TC =
DISTORTION (%)
.3 1.2
5C
W C 4 VO 25 to 8
.1 m T C = 25 TC =
50 1.0
= 2W
PO = TC = 85
C
3 25C
.03
PO
.8 TC = 5C
W +VO to 8
60 5C = 25
= T C = 12 2 TC
.01 PO .6
.003 .4 1
100 300 1K 3K 10K 30K .1M 40 50 60 70 80 90 100 0 1 2 3 4 5
FREQUENCY, F (Hz) TOTAL SUPPLY VOLTAGE, V S (V) OUTPUT CURRENT, I O (A)
182
OPERATING
GENERAL SHORT TO VS SHORT TO

Please read the General Operating Considerations section, VS C, L, OR EMF LOAD COMMON
which covers stability, supplies, heatsinking, mounting, current
limit, SOA interpretation, and specification interpretation. Addi- 50V .26A .84A
tional information can be found in the application notes. For 40V .38A 1.1A
information on the package outline, heatsinks, and mounting 35V .49A 1.2A
hardware, consult the Accessory and Package Mechanical Data 30V .65A 1.4A
section of the data book. 25V .84A 1.7A
20V 1.1A 2.2A
SAFE OPERATING AREA (SOA) 15V 1.4A 2.9A
The output stage of most power amplifiers has three distinct These simplified limits may be exceeded with further analysis using the operat-
limitations: ing conditions for a specific application.
1. The current handling capability of the transistor geometry and
the wire bonds.
CURRENT LIMITING
2. The second breakdown effect which occurs whenever the Refer to Application Note 9, "Current Limiting", for details of both
simultaneous collector current and collector-emitter voltage fixed and foldover current limit operation. Visit the Apex web site
exceeds specified limits. at www.apexmicrotech.com for a copy of llimit.xls which plots
3. The junction temperature of the output transistors. current limits vs. steady state SOA. Beware that current limit
should be thought of as a +/20% function initially and varies about
5.0
2:1 over the range of 55C to 125C.

For fixed current limit, leave pin 7 open and use equations 1 and 2.
t=
TH
t=
3.0
t=
ER
0.
MA
1m
RCL = 0.65/LCL (1)

5m
5m
Tc L
=2
s
2.0 Tc
5C ICL = 0.65/RCL (2)
=8
1.5 5C SE Where:
Tc CO
=1 ICL is the current limit in amperes.
25 ND
1.0 C RCL is the current limit resistor in ohms.
BR
.7 EA
KD For certain applications, foldover current limit adds a slope to
steady state
.5 O
W the current limit which allows more power to be delivered to the
N load without violating the SOA. For maximum foldover slope,
ground pin 7 and use equations 3 and 4.
.3
.2
0.65 + (Vo * 0.014)
10 15 20 25 30 35 40 50 60 70 80 100 ICL = (3)
RCL
The SOA curves combine the effect of these limits. For a given 0.65 + (Vo * 0.014)
application, the direction and magnitude of the output current RCL = (4)
should be calculated or measured and checked against the SOA ICL
curves. This is simple for resistive loads but more complex for
reactive and EMF generating loads. However, the following guide- Where:
lines may save extensive analytical efforts. Vo is the output voltage in volts.
1. Capacitive and dynamic* inductive loads up to the following Most designers start with either equation 1 to set RCL for the
maximum are safe with the current limits set as specified. desired current at 0v out, or with equation 4 to set RCL at the
maximum output voltage. Equation 3 should then be used to plot
CAPACITIVE LOAD INDUCTIVE LOAD the resulting foldover limits on the SOA graph. If equation 3 results
VS ILIM = 2A ILIM = 5A ILIM = 2A ILIM = 5A in a negative current limit, foldover slope must be reduced. This
can happen when the output voltage is the opposite polarity of the
50V 80F 75F 55mH 7.5mH supply conducting the current.
40V 250F 150F 150mH 11mH In applications where a reduced foldover slope is desired, this
35V 500F 250F 200mH 15mH can be achieved by adding a resistor (RFO) between pin 7 and
30V 1,200F 500F 250mH 24mH ground. Use equations 4 and 5 with this new resistor in the circuit.
25V 4,000F 1,600F 400mH 38mH
20V 20,000F 5,000F 1,500mH 75mH 0.65 + Vo * 0.14
15V ** 25,000F ** 100mH 10.14 + RFO
ICL = (5)
*If the inductive load is driven near steady state conditions, allowing the output RCL
voltage to drop more than 8V below the supply rail with ILIM = 5A or 20V below
the supply rail with ILIM = 2A while the amplifier is current limiting, the inductor
must be capacitively coupled or the current limit must be lowered to meet SOA 0.65 + Vo * 0.14
criteria. 10.14 + RFO
**Second breakdown effect imposes no limitation but thermal limitations must
RCL = (6)
still be observed. ICL
Where:
2. The amplifier can handle any EMF generating or reactive load RFO is in K ohms.
and short circuits to the supply rail or shorts to common if the
current limits are set as follows at TC = 85C:
without notice.
PA10U REV. K JANUARY 1998 1998 Apex Microtechnology Corp.
183
PA10M

1 Input bias current, +IN +IB 25C 40V VIN = 0 30 nA


4 Output voltage, IO = 5A VO 25C 18V RL = 2.07 10 V

4 Output voltage, IO = 2A VO 25C 30V RL = 12 24 V
4 Stability/noise EN 25C 40V RL = 500, AV = 1, CL = .68nF 1 mV
4 Common mode rejection CMR 25C 15V RL = 500, F = DC, VCM = 9V 74 dB
6 Output voltage, IO = 5A VO 55C 18V RL = 2.07 10 V

6 Open loop gain AOL 55C 40V RL = 500, F = 10Hz 96 db
5 Output voltage, IO = 3A VO 125C 14.3V RL = 2.07 6.3 V

100K
BURN IN CIRCUIT
+15V
* These components are used to stabilize device due
1 to poor high frequency characteristics of burn in
100K 5 board.
3 2
U.U.T power dissipation of approximately 2.1W at case
** * 4 temperature = 125C.
6 8 20
1
15V
without notice.
PA10MU REV. J FEBRUARY 1998 1998 Apex Microtechnology Corp.
184
PA12 PA12A
FEATURES
LOW THERMAL RESISTANCE 1.4 C/W
CURRENT FOLDOVER PROTECTION NEW
HIGH TEMPERATURE VERSION PA12H
HIGH OUTPUT CURRENT Up to 15A Peak
APPLICATIONS
MOTOR, VALVE AND ACTUATOR CONTROL POWER RATING
MAGNETIC DEFLECTION CIRCUITS UP TO 10A Not all vendors use the same method to rate the power
POWER TRANSDUCERS UP TO 100kHz handling capability of a Power Op Amp. APEX rates the
TEMPERATURE CONTROL UP TO 360W internal dissipation, which is consistent with rating methods
PROGRAMMABLE POWER SUPPLIES UP TO 90V used by transistor manufacturers and gives conservative
results. Rating delivered power is highly application depen-
AUDIO AMPLIFIERS UP TO 120W RMS dent and therefore can be misleading. For example, the 125W
internal dissipation rating of the PA12 could be expressed as
an output rating of 250W for audio (sine wave) or as 440W if
DESCRIPTION using a single ended DC load. Please note that all vendors rate C
The PA12 is a state of the art high voltage, very high output maximum power using an infinite heatsink.
current operational amplifier designed to drive resistive, induc-
tive and capacitive loads. For optimum linearity, especially at
low levels, the output stage is biased for class A/B operation
THERMAL STABILITY
using a thermistor compensated base-emitter voltage multi- APEX has eliminated the tendency of class A/B output
plier circuit. The safe operating area (SOA) can be observed stages toward thermal runaway and thus has vastly increased
for all operating conditions by selection of user program- amplifier reliability. This feature, not found in most other Power
mable current limiting resistors. For continuous operation Op Amps, was pioneered by APEX in 1981 using thermistors
under load, a heatsink of proper rating is recommended. which assure a negative temperature coefficient in the quies-
This hybrid integrated circuit utilizes thick film (cermet) cent current. The reliability benefits of this added circuitry far
resistors, ceramic capacitors and semiconductor chips to outweigh the slight increase in component count.
maximize reliability, minimize size and give top performance.
Ultrasonically bonded aluminum wires provide reliable inter- EXTERNAL CONNECTIONS
connections at all operating temperatures. The 8-pin TO-3
package is hermetically sealed and electrically isolated. The
R CL+
use of compressible isolation washers voids the warranty.
+VS CL+
EQUIVALENT SCHEMATIC 2
3 OUT
1
+IN 4 OUTPUT
3
TOP VIEW
Q2A
D1 Q2B
IN 5
8
Q1 2
6 CL R CL
Q3 7
VS
F.O.
1
7
Q4 Q5
8
4
Q6B
A1 Q6A
5
C1
6
185
PA12/PA12A
SUPPLY VOLTAGE, +Vs to Vs 100V
ABSOLUTE MAXIMUM RATINGS OUTPUT CURRENT, within SOA 15A
TEMPERATURE, pin solder -10s 300C

2, 5
INPUT
BIAS CURRENT, vs. temperature Full temperature range 50 500 * * pA/C
BIAS CURRENT, vs. supply TC = 25C 10 * pA/V
OFFSET CURRENT, vs. temperature Full temperature range 50 * pA/C
COMMON MODE VOLTAGE RANGE3 Full temperature range VS 5 VS 3 * * V
COMMON MODE REJECTION, DC Full temp. range, VCM = VS 6V 74 100 * * dB
GAIN
OPEN LOOP GAIN at 10Hz TC = 25C, 1K load 110 * dB
OPEN LOOP GAIN at 10Hz Full temp. range, 8 load 96 108 * * dB
GAIN BANDWIDTH PRODUCT @ 1MHz TC = 25C, 8 load 4 * MHz
POWER BANDWIDTH TC = 25C, 8 load 13 20 * * kHz
OUTPUT
VOLTAGE SWING3 TC = 25C, PA12 = 10A, PA12A = 15A VS 6 * V
VOLTAGE SWING3 TC = 25C, IO = 5A VS 5 * V
CURRENT, peak TC = 25C 10 15 A
SLEW RATE TC = 25C 2.5 4 * * V/s
CAPACITIVE LOAD Full temperature range, AV = 1 1.5 * nF
CAPACITIVE LOAD Full temperature range, AV > 10 SOA *
POWER SUPPLY
THERMAL
RESISTANCE, AC, junction to case4 TC = 55 to +125C, F > 60Hz .8 .9 * * C/W
RESISTANCE, DC, junction to case TC = 55 to +125C 1.25 1.4 * * C/W
TEMPERATURE RANGE, case Meets full range specification 25 +85 55 +125 C
2. The power supply voltage for all tests is 40, unless otherwise noted as a test condition.
5. Full temperature range specifications are guaranteed but not 100% tested.
186
TYPICAL PERFORMANCE
GRAPHS PA12 PA12A

140

2.5 17.5
120 2.2 15.0

100 1.9 12.5
RCL = .06 ,RFO =
80 1.6 10.0
VO
RCL = .18 ,RFO = 0 =0
60 1.3 7.5
PA12 PA12A
40 1.0 5.0 VO =
24V
VO = 2 VO = 0
20 .7 2.5 4V
0 .4 0
0 20 40 60 80 100 120 140 50 25 0 25 50 75 100 125 50 25 0 25 50 75 100 125
CASE TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C)

120 0 100
| +VS | + | VS | = 100V

100 68
30
46
80 60
PHASE, ()
32
60 90 | +VS | | VS | = 80V C
22
40 120
15 | +VS | + | VS | = 30V
20 150
10
0 180 6.8
20 210 4.6

120 8 100
VIN = 5V, t r = 100ns
6
100 70
4
50
80
2 40
60 0 30
-2
40 20
-4
20
-6
0 -8 10
1 10 100 1K 10K .1M 1M 0 2 4 6 8 10 12 10 100 1K 10K .1M

3 6
1.6
AV =10
1 VS = 37V 1.4 5
RL = 4
NORMALIZED, IQ (X)
DISTORTION, (%)
C
.3 1.2 TC = 25 V0
W 4
W =4 T C = 25
C
.1 0m PO 1.0
10 5C
= TC = 8 3
.03 PO .8 +V0
5C
W T C = 12
.01 120 .6 2
=
PO
.003 .4 1
100 300 1K 3K 10K 30K .1M 40 50 60 70 80 90 100 0 3 6 9 12 15
FREQUENCY, F (Hz) TOTAL SUPPLY VOLTAGE, VS (V) OUTPUT CURRENT, I O (A)
187
OPERATING
GENERAL SHORT TO VS SHORT TO

Please read Application Note 1, which covers stability, supplies, VS C, L, OR EMF LOAD COMMON
heatsinking, mounting, current limit, SOA interpretation, and speci- 50V .30A 2.4A
fication interpretation. Additional information can be found in the
40V .58A 2.9A
application notes. For information on the package outline, heatsinks,
35V .87A 3.7A
and mounting hardware, consult the Accessory and Package
30V 1.5A 4.1A
Mechanical Data section of the handbook. 25V 2.4A 4.9A
SAFE OPERATING AREA (SOA) 20V 2.9A 6.3A
15V 4.2A 8.0A
The output stage of most power amplifiers has three distinct
These simplified limits may be exceeded with further analysis using the operat-
limitations: ing conditions for a specific application.
1. The current handling capability of the transistor geometry and
the wire bonds.
simultaneous collector current and collector-emitter voltage CURRENT LIMITING
exceeds specified limits. Refer to Application Note 9, "Current Limiting", for details of both
3. The junction temperature of the output transistors. fixed and foldover current limit operation. Visit the Apex web site
The SOA curves combine the effect of all limits for this Power Op at www.apexmicrotech.com for a copy of llimit.xls which plots
15 current limits vs. steady state SOA. Beware that current limit
should be thought of as a +/20% function initially and varies about

t=
10 2:1 over the range of 55C to 125C.

TH
0.5
ER For fixed current limit, leave pin 7 open and use equations 1 and 2.
t=
MA
ms
L TC
t=
1m
=2
5.0 5C RCL = 0.65/LCL (1)
5m
ICL = 0.65/RCL (2)

s
TC
=8
3.0 5C
Where:
2.0 TC ICL is the current limit in amperes.
=1
1.5 25 RCL is the current limit resistor in ohms.
ste
C
ad
1.0 For certain applications, foldover current limit adds a slope to

ys
the current limit which allows more power to be delivered to the

tat
.7
e
load without violating the SOA. For maximum foldover slope,

.5 ground pin 7 and use equations 3 and 4.
SECOND BREAKDOWN
.3
10 15 20 25 30 35 40 50 60 70 80 100 0.65 + (Vo * 0.014)
ICL = (3)
RCL
Amp. For a given application, the direction and magnitude of the 0.65 + (Vo * 0.014)
output current should be calculated or measured and checked RCL = (4)
against the SOA curves. This is simple for resistive loads but more ICL
following guidelines may save extensive analytical efforts. Where:
Vo is the output voltage in volts.
1. Capacitive and dynamic* inductive loads up to the following
maximum are safe with the current limits set as specified. Most designers start with either equation 1 to set RCL for the
desired current at 0v out, or with equation 4 to set RCL at the
CAPACITIVE LOAD INDUCTIVE LOAD maximum output voltage. Equation 3 should then be used to plot
VS ILIM = 5A ILIM = 10A ILIM = 5A ILIM = 10A the resulting foldover limits on the SOA graph. If equation 3 results
in a negative current limit, foldover slope must be reduced. This
50V 200F 125F 5mH 2.0mH
can happen when the output voltage is the opposite polarity of the
40V 500F 350F 15mH 3.0mH supply conducting the current.
35V 2.0mF 850F 50mH 5.0mH In applications where a reduced foldover slope is desired, this
30V 7.0mF 2.5mF 150mH 10mH can be achieved by adding a resistor (RFO) between pin 7 and
25V 25mF 10mF 500mH 20mH ground. Use equations 4 and 5 with this new resistor in the circuit.
20V 60mF 20mF 1,000mH 30mH
15V 150mF 60mF 2,500mH 50mH
0.65 + Vo * 0.14
*If the inductive load is driven near steady state conditions, allowing the output 10.14 + RFO
voltage to drop more than 8V below the supply rail with ILIM = 15A or 25V below
the supply rail with ILIM = 5A while the amplifier is current limiting, the inductor
ICL = (5)
must be capacitively coupled or the current limit must be lowered to meet SOA RCL
criteria.
0.65 + Vo * 0.14
2. The amplifier can handle any EMF generating or reactive load 10.14 + RFO
and short circuits to the supply rail or common if the current RCL = (6)
limits are set as follows at TC = 25C: ICL
Where:
RFO is in K ohms.
without notice.
PA12U REV. L DECEMBER 1997 1997 Apex Microtechnology Corp.
188
PA12M

1 Inout bias current,IN IB 25C 40V VIN = 0 30 nA

3 Input bias current,IN IB 55C 40V VIN = 0 115 nA




BURN IN CIRCUIT 100K * These components are used to stabilize device due to
poor high frequency characteristics of burn in board.
+15V
1
100K
** Input signals are calculated to result in internal power
5 3 dissipation of approximately 2.1W at case temperature
2
* 1
= 125C.
U.U.T
** * 4 8
6 20
1
15V
however, FAXis(520)
ORDERS (520) 690-8601
189
PA12H
FEATURES
LOW COST 200 C VERSION OF PA12
OUTPUT CURRENT at 200 C 1A
FULL SPECIFICATIONS 25 C to +125 C
WIDE SUPPLY RANGE 10 to 45V
CURRENT FOLDOVER PROTECTION
APPLICATIONS
SPECIFICATIONS
MOTOR, VALVE AND ACTUATOR CONTROL Specifications of the standard PA12 apply to the PA12H
POWER TRANSDUCERS UP TO 100kHz with the exception of the temperature range extensions
PROGRAMMABLE POWER SUPPLIES UP TO 80V 1. The operating and storage temperature ABSOLUTE MAXI-
TRANSMISSION LINE DRIVER MUM RATINGS extend to +200C.
2. Static and dynamic tests are performed at +125C as
shown in SG 2 and SG 5 of the military PA12M data sheet.
DESCRIPTION 3. Additional tests at TC = 200C:
The PA12H is a low cost, high temperature Power Op Amp A. Quiescent current = 100mA max at VS = 45.
made especially for short term use in extreme environmental B. Voltage swing = VS 4 (IO = 1A, VS = 15)
situations such as down hole instrumentation. The amplifier
can power mechanical or electronic transducers and can drive GENERAL CONSIDERATIONS
the long transmission lines associated with these applications. The primary aim of the PA12H is to provide a reasonable
The PA12H, based on the standard PA12s very high power level of power output at a minimum cost. To achieve this end,
level, leaves a six watt capability after being derated for full dynamic tests are performed up to 125C, with only
operation at a case temperature of 200C. To meet the high minimal 100% testing at 200C. This approach saves nearly
temperature requirements for up to 200 hours, polyimid has an order of magnitude over the cost of a fully tested long life
replaced the standard epoxy for attaching the small signal product, but does require recognition of two limitations.
devices. First, input parameters such as voltage offset and bias
These hybrid integrated circuits utilize thick film conductors, current are not tested above 125C. This could lead to accu-
ceramic capacitors and silicon semiconductors to maximize racy problems if the PA12H is used as a precision computa-
reliability, minimize size and give top performance. Ultrasoni- tional element. Solutions to this limitation include contacting
cally bonded aluminum wires provide reliable interconnec- the factory regarding additional testing at higher temperatures
tions at all operating temperatures. The 8-pin TO-3 package or using high temperature small signal amplifiers for computa-
(see Package Outlines) is hermetically sealed and isolated. tional tasks.
The use of compressible thermal washers and/or improper The second limitation of life span requires the PA12H to be
mounting torque will void the product warranty. Please see used in short term applications. This requirement is mandated
General Operating Considerations. by the low cost design concept. At 200C component degra-
dation is nearly as severe during storage as during actual
operation. This must be taken into account when scheduling
CALCULATED LIFE EXPECTANCY actual implementation of the finished package.
1000 Please consult the PA12 data sheet for basic information on
EXPECTED LIFE, HOURS
this amplifier; the PA12M data sheet for details on +125C

tests, and Power Operational Amplifier handbook section
General Operating Considerations, for recommendations on
supplies, stability, heatsinks and bypassing.
100
R CL+
CL+
+VS 2
3 OUT
10 1
188 192 196 200 OUTPUT
+IN 4
TOP VIEW
5
IN 8
6 CL R CL
7
VS
F.O.
omissions. HOTLINE:
change 546-2739
without notice.
PA12HU REV. H FEBRUARY 1998 1998 Apex Microtechnology Corp.
190
VIDEO POWER OPERATIONAL AMPLIFIERS
PA19 PA19A
FEATURES
VERY FAST SLEW RATE 900 V/s
POWER MOS TECHNOLOGY 4A peak rating
LOW INTERNAL LOSSES 2V at 2A
PROTECTED OUTPUT STAGE Thermal Shutoff
WIDE SUPPLY RANGE 15V TO 40V
APPLICATIONS
VIDEO DISTRIBUTION AND AMPLIFICATION
HIGH SPEED DEFLECTION CIRCUITS TYPICAL APPLICATION
POWER TRANSDUCERS UP TO 5 MHz This fast power driver utilizes the 900V/s slew rate of the
MODULATION OF RF POWER STAGES PA19 and provides a unique interface with a current output
POWER LED OR LASER DIODE EXCITATION DAC. By using the DACs internal 1K feedback resistor,
temperature drift errors are minimized, since the temperature
DESCRIPTION drift coefficients of the internal current source and the internal
feedback resistor of the DAC are closely matched. Gain of
The PA19 is a high voltage, high current operational ampli-
VOUT to IIN is 6.5/mA. The DACs internal 1K resistor together
fier optimized to drive a variety of loads from DC through the with the external 500 and 110 form a tee network in the
video frequency range. Excellent input accuracy is achieved feedback path around the PA19. This effective resistance
with a dual monolithic FET input transistor which is cascoded
by two high voltage transistors to provide outstanding com-
equals 6.5K . Therefore the entire circuit can be modeled as
6.5K feedback resistor from output to inverting input and a
C
mon mode characteristics. All internal current and voltage 5mA current source into the inverting input of the PA19. Now
levels are referenced to a zener diode biased on by a current we see the familiar current to voltage conversion for a DAC
source. As a result, the PA19 exhibits superior DC and AC where VOUT = IIN x RFEEDBACK.
stability over a wide supply and temperature range.
High speed and freedom from second breakdown is as- EQUIVALENT SCHEMATIC
sured by a complementary power MOS output stage. For
3
optimum linearity, especially at low levels, the power MOS
transistors are biased in a class A/B mode. Thermal shutoff Q1 Q2
provides full protection against overheating and limits the Q3 Q4 2
heatsink requirements to dissipate the internal power losses
Q7
under normal operating conditions. A built-in current limit of Q5
Q8
0.5A can be increased with the addition of two external 8
resistors. Transient inductive load kickback protection is pro- Q9

Q10
vided by two internal clamping diodes. External phase com- Q11
pensation allows the user maximum flexibility in obtaining the Q15
1
Q12 Q13
optimum slew rate and gain bandwidth product at all gain
Q16 D1
settings. A heatsink of proper rating is recommended.
Q19
This hybrid circuit utilizes thick film (cermet) resistors, 5 Q20
ceramic capacitors, and silicon semiconductor chips to maxi- Q17A Q17B
mize reliability, minimize size, and give top performance. Q21
Ultrasonically bonded aluminum wires provide reliable inter- 4
Q22
connections at all operating temperatures. The 8-pin TO-3 Q23 7
Q24
use of compressible thermal washers and/or improper mount- Q25
D2
ing torque will void the product warranty. Please see General 6
Operating Considerations.
TYPICAL +40V 110 EXTERNAL CONNECTIONS

APPLICATION RCL+
RCL+ 500 PHASE COMPENSATION
5mA +V 3
2
OUT
1
GAIN CC
1K 32.5V
DAC PA19 4
Up to 4A +IN TOP CC 1 330pF
VIEW 10 22pF
5
RCL 5.6pF 100 2.2pF
IN 8
1000 none
6
7
V
40V RCL
PA19 AS FAST POWER DRIVER
191

TEMPERATURE, pin solder 10 sec 300C
TEMPERATURE, storage 65 to 155C
OPERATING TEMPERATURE RANGE, case 55 to 125C

2
INPUT
OFFSET VOLTAGE, vs. temperature TC = 25C to +85C 10 30 5 10 V/C
OFFSET VOLTAGE, vs. power TC = 25C to +85C 20 * V/W
OFFSET CURRENT, initial TC = 25C 5 100 3 25 pA
COMMON MODE VOLTAGE RANGE3 TC = 25C to +85C VS15 VS12 * * V
COMMON MODE REJECTION, DC TC = 25C to +85C, VCM = 20V 70 104 * * dB
GAIN
OPEN LOOP GAIN at 10Hz TC = 25C, RL = 1K 111 * dB
GAIN BANDWIDTH PRODUCT at 1MHz TC = 25C, CC = 2.2pF 100 * MHz
POWER BANDWIDTH, AV = 100 TC = 25C, CC = 2.2pF 3.5 * MHz
POWER BANDWIDTH, AV = 1 TC = 25C, CC = 330pF 250 * kHz
OUTPUT
VOLTAGE SWING3 TC = 25C, IO = 4A VS5 VS4 * * V
VOLTAGE SWING3 TC = 25C to +85C, IO = 2A VS3 VS2 * * V
VOLTAGE SWING3 TC = 25C to +85C, IO = 78mA VS1 VS.5 * * V
SLEW RATE, AV = 100 TC = 25C, CC = 2.2pF 600 900 800 * V/s
SLEW RATE, AV = 10 TC = 25C, CC = 22pF 650 * V/s
POWER SUPPLY
VOLTAGE TC = 25C to +85C 15 35 40 * * * V
THERMAL
RESISTANCE, AC, junction to case4 TC = 25C to +85C, F > 60Hz 1.2 1.3 * * C/W
RESISTANCE, DC, junction to case TC = 25C to +85C, F < 60Hz 1.6 1.8 * * C/W
RESISTANCE, junction to air TC = 25C to +85C 30 * C/W
TEMPERATURE RANGE, case Meets full range specifications 25 +85 * * C
192
TYPICAL PERFORMANCE
GRAPHS PA19 PA19A

POWER DERATING CURRENT LIMIT QUIESCENT CURRENT
80 3.5 1.6
70 R
3.0 CL =0
.27 1.4

60
2.5
50 1.2
2.0
40
1.5
30 RCL = 1.0
1.2
1.0
20 RCL = .8
10 .5
0 0 .6
0 25 50 75 100 125 150 50 25 0 25 50 75 100 125 30 40 50 60 70 80
CASE TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C) TOTAL SUPPLY VOLTAGE, VS (V)

100 4V 80

58
80
RL = 15
CC
3V 41
60
=2
2. +V
C
CC
2p
.2p
30
CC
22 F
V
F
=2
40 pF
= 33
33
2pF
0p 2V 21
F
0pF
20
15
0 11
1V
| +VS | + | VS | = 80V
20 8
100 1K 10K 100K 1M 10M 100M 0 1 2 3 4 5 100K 200K 600K1M 2M 4M 8M 20M
FREQUENCY, F (Hz) OUTPUT CURRENT, IO (A) FREQUENCY, F (Hz)
SLEW RATE VS. COMP. PULSE RESPONSE INPUT NOISE

1000 30 30
800 VIN = 2V
AV = 10
600 20
t r = 10ns 20
RL = 15
RL = 15
SLEW RATE, (V/s)
400 15
10
200 0 10
10 7
100
80 5
20
40 30 3
2 4 6 10 20 40 60 100 200 400 50 0 50 100 150 200 250 300 10 100 1K 10K 100K 1M
COMPENSATION CAPACITOR, CC (pF) TIME, t (ns) FREQUENCY, F (Hz)

COMMOM MODE REJECTION, CMR (dB)
120 100 70
80 65
100
60
80 60
55
60 40
50
40 20
45
20 0 40
1K 10K 100K 1M 10M 100M 1K 10K 100K 1M 10M 100M 10 100 1K 10K 100K 1M 10M
193
OPERATING
GENERAL 2. Safe short circuit combinations of voltage and current are limited to
a power level of 100W.
Please read the General Operating Considerations section, which 3. The output stage is protected against transient flyback. However,
covers stability, supplies, heatsinking, mounting, current limit, SOA for protection against sustained, high energy flyback, external fast-
interpretation, and specification interpretation. Additional information recovery diodes should be used.
can be found in the application notes. For information on the package
outline, heatsinks, and mounting hardware, consult the Accessory SUPPLY CURRENT
and Package Mechanical Data section of the handbook.
The PA19 features a class A/B driver stage to charge and discharge
gate capacitance of Q7 and Q19. As these currents approach 0.5A, the
CURRENT LIMIT savings of quiescent current over that of a class A driver stage is
Q2 (and Q25) limit output current by turning on and removing gate considerable. However, supply current drawn by the PA19, even with
drive when voltage on pin 2 (pin 7) exceeds .65V differential from the no load, varies with slew rate of the output signal as shown below.
positive (negative) supply rail. With internal resistors equal to 1.2, SUPPLY CURRENT
current limits are approximately 0.5A with no external current limit 400
SUPPLY CURRENT, IS (mA)

resistors. With the addition of external resistors current limit will be: VOUT = 60VPP SINE
ILIM = .65V +.54A RL = 500
RCL 300
To determine values of external current limit resistors:
RCL = .65V
200
ICL .54A
PHASE COMPENSATION 100

At low gain settings, an external compensation capacitor is required
to insure stability. In addition to the resistive feedback network, roll off
or integrating capacitors must also be considered when determining 0
gain settings. The capacitance values listed in the external connection 30K 100K 300K 1M 3M 10M
diagram, along with good high frequency layout practice, will insure FREQUENCY, F (Hz)
stability. Interpolate values for intermediate gain settings.
OUTPUT LEADS
SAFE OPERATING AREA (SOA) Keep the output leads as short as possible. In the video frequency
range, even a few inches of wire have significant inductances, raising
The MOSFET output stage of this power operational amplifier has the interconnection impedance and limiting the output current slew
two distinct limitations: rate. Furthermore, the skin effect increases the resistance of heavy
1. The current handling capability of the MOSFET geometry and the wires at high frequencies. Multistrand Litz Wire is recommended to
wire bonds. carry large video currents with low losses.
THERMAL SHUTDOWN
OUTPUT CURRENT FROM VS OR VS(A)
5.0
TC = 25C The thermal protection circuit shuts off the amplifier when the
4.0 t= substrate temperature exceeds approximately 150C. This allows the
10 heatsink selection to be based on normal operating conditions while
3.5 0m
t= s protecting the amplifier against excessive junction temperature during
3.0 30
0m temporary fault conditions.
s Thermal protection is a fairly slow-acting circuit and therefore does
2.5
ST not protect the amplifier against transient SOA violations (areas
EA
2.0 DY outside of the steady state boundary). It is designed to protect against
ST short-term fault conditions that result in high power dissipation within
AT the amplifier. If the conditions that cause thermal shutdown are not
E
1.5 removed, the amplifier will oscillate in and out of shutdown. This will
result in high peak power stresses, destroy signal integrity, and reduce
the reliability of the device.
15 20 25 30 35 40 50 60 70 80
INTERNAL VOLTAGE DROP SUPPLY TO OUTPUT VSVO(V)
STABILITY
The SOA curves combine the effect of these limits and allow for Due to its large bandwidth, the PA19 is more likely to oscillate than
internal thermal delays. For a given application, the direction and lower bandwidth power operational amplifiers. To prevent oscillations
magnitude of the output current should be calculated or measured and a reasonable phrase margin must be maintained by:
checked against the SOA curves. This is simple for resistive loads but 1. Selection of the proper phase compensation capacitor. Use the
more complex for reactive and EMF generating loads. The following values given in the table under external connections and interpo-
guidelines may save extensive analytical efforts: late if necessary. The phase margin can be increased by using a
1. Capacitive and inductive loads up to the following maximums are larger capacitor at the expense of slew rate. Total physical length
safe: (pins of the PA19, capacitor leads plus printed circuit traces) should
be limited to a maximum of 3.5 inches.
VS CAPACITIVE LOAD INDUCTIVE LOAD 2. Keep the external sumpoint stray capacitance to ground at a
minimum and the sumpoint load resistance (input and feedback
40V .1F 11mH resistors in parallel) below 500. Larger sumpoint load resistances
30V 500F 24mH can be used with increased phase compensation and/or by bypass-
20V 2500F 75mH
ing the feedback resistor.
15V 100mH
3. Connect the case to any AC ground potential.
omissions. HOTLINE:
without notice.
194
POWER DUAL OPERATIONAL AMPLIFIERS
PA21/25/26 PA21A/25A
FEATURES
LOW COST
WIDE COMMON MODE RANGE
Includes negative supply
WIDE SUPPLY VOLTAGE RANGE
Single supply: 5V to 40V
Split supplies: 2.5V to 20V
HIGH EFFICIENCY |Vs2.2V| at 2.5A typ
HIGH OUTPUT CURRENT 3A min (PA21A)
R2 R3
INTERNAL CURRENT LIMIT +28V
LOW DISTORTION 9K 10K
+28V R4
10K
APPLICATIONS R1
R5
10K
HALF & FULL BRIDGE MOTOR DRIVERS 5K A M B
+ +
AUDIO POWER AMPLIFIER 1/2 PA21 1/2 PA21
STEREO 18W RMS per channel R6
BRIDGE 36W RMS per package COMMAND 10K
INPUT
IDEAL FOR SINGLE SUPPLY SYSTEMS 0/10V
5V Peripherals C
12V Automotive
28V Avionic FIGURE 1: BIDIRECTIONAL SPEED CONTROL FROM
A SINGLE SUPPLY
DESCRIPTION
The amplifiers are especially well-suited for this application.
The amplifiers consist of a monolithic dual power op amp The extended common mode range allows command inputs
in a 8-pin hermetic TO-3 package (PA21 and PA25) and a 12- as low as 0V. Its superior output swing abilities let it drive within
pin SIP package (PA26). Putting two power op amps in one 2V of supply at an output current of 2A. This means that a
package and on one die results in an extremely cost effective command input that ranges from 0V to 10V will drive a 24V
solution for applications requiring multiple amplifiers per motor from full scale CCW to full scale CW at up to 2A. A
board or bridge mode configurations. single power op amp with an output swing capability of Vs 6
The wide common mode input range includes the negative would require 30V supplies and would be required to swing
rail, facilitating single supply applications. It is possible to 48V p-p at twice the speed to deliver an equivalent drive.
have a ground based input driving a single supply amplifier
with ground acting as the second or bottom supply of the
amplifier. EXTERNAL CONNECTIONS
The output stages are also well protected. They possess
internal current limit circuits. While the device is well pro- PA26
tected, the Safe Operating Area (SOA) curve must be ob-
Connect pins
served. Proper heatsinking is required for maximum reliabil- 3 and 10 to pin 7
ity. and connect pins + +
This hybrid integrated circuit utilizes thick film (cermet) 4 and 9 to pin 6 A B
resistors, ceramic capacitors and semiconductor chips to SUB
unless special
maximize reliability, minimize size and give top performance. functions are re-
Ultrasonically bonded aluminum wires provide reliable inter- quired.
connections at all operating temperatures. The 8-pin TO-3 1 2 3 4 5 6 7 8 9 10 11 12

+IN A
IN A
VBOOST/+VS
ISENSE/VS
OUT A
VS
+VS
OUT B
ISENSE/VS
VBOOST/+VS
IN B
+IN B
use of compressible isolation washers voids the warranty.

The tab of the SIP12 plastic package is tied to VS.
TYPICAL APPLICATION +VS

+VS
+IN, A 2 2
R1 and R2 set up amplifier A in a non-inverting gain of 2.8. OUT, B IN, A 3 OUT, A
3
Amp B is set up as a unity gain inverter driven from the output 1 1
A
of amp A. Note that amp B inverts signals about the reference IN, A
4 4
node, which is set at mid-supply (14V) by R5 and R6. When the + +IN, A
command input is 5V, the output of amp A is 14V. Since this is A B B
equal to the reference node voltage, the output of amp B is also +
5
14V, resulting in 0V across the motor. Inputs more positive 5
OUT, A TOP VIEW 8 +IN, B 8
than 5V result in motor current flow from left to right (see Figure OUT, B
VS 6 IN, B 6
1). Inputs less positive than 5V drive the motor in the opposite 7 IN, B 7
direction. PA25 +IN, B PA21 VS
195
PA21/25/26 PA21A/25A SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS SUPPLY VOLTAGE, total 5V to 40V

OUTPUT CURRENT SOA
POWER DISSIPATION, internal (per amplifier) 25W
POWER DISSIPATION, internal (both amplifiers) 36W
INPUT VOLTAGE, differential VS
INPUT VOLTAGE, common mode +VS, -VS.5V
JUNCTION TEMPERATURE, max1 150C
TEMPERATURE, pin solder10 sec max 300C
TEMPERATURE RANGE, storage 65C to 150C
OPERATING TEMPERATURE RANGE, case 55C to 125C
SPECIFICATIONS PA21/25/26 PA21A/PA25A
INPUT
OFFSET VOLTAGE, initial 1.5 10 .5 4 mV
OFFSET VOLTAGE, vs. temperature Full temperature range 15 10 V/C
BIAS CURRENT, initial 35 1000 * 250 nA
COMMON MODE RANGE Full temperature range VS.3 +VS2 * * V
COMMON MODE REJECTION, DC Full temperature range 60 85 * * dB
POWER SUPPLY REJECTION Full temperature range 60 80 * * dB
CHANNEL SEPARATION IOUT = 1A, F = 1kHz 50 68 * * dB
GAIN
OPEN LOOP GAIN Full temperature range 80 100 * * dB
GAIN BANDWIDTH PRODUCT AV = 40dB 600 * kHz
POWER BANDWIDTH VO(P-P) = 28V 13.6 * kHz
OUTPUT
CURRENT, peak 2.5 3 A
CURRENT, limit 3.0 4.0 A
SLEW RATE .5 1.2 * * V/s
CAPACITIVE LOAD DRIVE AV = 1 .22 * F
VOLTAGE SWING Full temp. range, IO = 100mA |VS| 1.0 |VS| 0.8 * * V
VOLTAGE SWING Full temp. range, IO = 1A |VS| 1.8 |VS| 1.4 * * V
VOLTAGE SWING IO = 2.5A (PA21, 25) |VS| 3.0 |VS| 2.8 V
VOLTAGE SWING IO = 3.0A (PA21A, PA25A) |VS| 4.0 |VS| 3.5 V
POWER SUPPLY
VOLTAGE, VSS3 54 30 40 * * * V
THERMAL
RESISTANCE, junction to case
DC, single amplifier 5.0 * C/W
DC, both amplifiers5 3.4 * C/W
AC, single amplifier 3.7 C/W
AC, both amplifiers5 2.4 C/W
TEMPERATURE RANGE, case Meets full range specifications 25 85 25 85 C
NOTES: * The specification of PA21A/PA25A is identical to the specification for PA21/PA25 in applicable column to the left.
2. Unless otherwise noted, the following conditions apply: VS = 15V, TC = 25C.
3. +VS and VS denote the positive and negative supply rail respectively. VSS denotes the total rail-to-rail supply voltage.
4. Current limit may not function properly below VSS = 6V, however SOA violations are unlikely in this area.
5. Rating applies when power dissipation is equal in the two amplifiers.
CAUTION subject to temperatures in excess of 850C to avoid generating toxic fumes. (PA21 and PA25 only. PA26 does not contain
BeO).
196
TYPICAL PERFORMANCE
GRAPHS PA21/25/26 PA21A/25A
POWER DERATING BIAS CURRENT CROSSTALK


40 1.75 80
35
1.5 75 AMP 1
30 I OUT = 1A
CROSSTALK (dB)
BOTH 1.25 70 AV = 100
25 AMPLIFIERS
20 1.0 65
15 SINGLE AMP 2
AMPLIFIER .75 60 I OUT = 0
10 AV = 100
.5 55
5
0 .25 50
0 25 50 75 100 125 150 50 25 0 25 50 75 100 125 10 100 1K 10K 20K
TEMPERATURE, T (C) CASE TEMPERATURE, TC (C) FREQUENCY, F (Hz)

100 0 50
40

30
80
30
60
60 25
PHASE, ()
40
90 20 C
120 15
20
150 10
0 |+VS | + |VS | = 40V
180
20 210 5
1 10 100 1K 10K 100K 1M 0 10 100 1K 10K .1M 1M 1K 10K 100K
POWER SUPPLY REJECTION PULSE RESPONSE CURRENT LIMIT

NORMALIZED CURRENT LIMIT, I LIM (A)
89 1.6
AV = 1
86 10
R L =10
1.4
83
80 5
1.2
77
74 0 1.0
71
5 .8
69
66
.6
63 10
60 .4
0 10 100 1K 10K 100K 1M 0 200 400 600 800 1K 50 25 0 25 50 75 100 125
FREQUENCY, F (Hz) TIME, t (s) CASE TEMPERATURE, TC (C)
TOTAL HARMONIC DISTORTION, THD (%)

3 125
VOLTAGE DROP FROM SUPPLY, (V)
40 3.5
TOTAL SUPPLY VOLTAGE, VSS (V)
AV = 10
CASE TEMPERATURE, TC (C)
1 V OUT = 16VPP 35 100 3

RL = 8
30 75 2.5
.1 25 50 2
20 25 1.5
.01 15 0 1
10 25 .5
.001 5 50 0
10 100 1K 10K 40K .7 .8 .9 1 1.1 1.2 1.3 1.4 0 .5 1 1.5 2 2.5 3 3.5
FREQUENCY, F (Hz) NORMALIZED QUIESCENT CURRENT, I Q (X) OUTPUT CURRENT, I O (A)
197
OPERATING
PA21/25/26 PA21A/25A CONSIDERATIONS
GENERAL MONOLITHIC AMPLIFIER

Please read the General Operating Considerations sec- STABILITY CONSIDERATIONS
tion, which covers stability, supplies, heatsinking, mounting, All monolithic power op amps use output stage topologies
current limit, SOA interpretation, and specification interpreta- that present special stability problems. This is primarily due to
tion. Additional information can be found in the application non-complementary (both devices are NPN) output stages
notes. For information on the package outline, heatsinks, and with a mismatch in gain and phase response for different
mounting hardware, consult the Accessory and Package polarities of output current. It is difficult for the op amp manu-
Mechanical Data section of the handbook. facturer to optimize compensation for all operating conditions.
The recommended R-C network of 1 ohm in series with
0.1F from output to AC common (ground or a supply rail, with
CURRENT LIMIT adequate bypass capacitors) will prevent local output stage
oscillations.
Current limit is internal to the amplifier, the typical value is
This network is provided internally on the PA21 but must be
shown in the current limit specification.
supplied externally on the PA25 and PA26. The amplifiers are
internally compensated for unity gain stability, no additional
SAFE OPERATING AREA (SOA) compensation is required.
4
3
THERMAL CONSIDERATIONS
EA
CH Although R JC is the same for PA21/25/26 there are differ-
2 ,O
1
EA ences in the thermal interface between case and heatsink

m
CH NE
s
,B LO which will limit power dissipation capability. Thermal grease or

OT AD
1 H
LO ED an Apex TW03 thermal washer, R CS = .1-.2C/W, is the only
AD recommended interface for the PA21/25. The PA26 may
ED
require a thermal washer which is electrically insulating since
the tab is tied to VS. This can result in thermal impedances for
R CS of up to 1C/W or greater.
ADDITIONAL PA26 PIN FUNCTIONS VBOOST
T C = 25C
.1
1 2 3 4 5 6 10 20 30 40 50 +VS
The SOA curves combine the effect of all limits for this power
op amp. For a given application, the direction and magnitude IN +IN OUT
of the output current should be calculated or measured and
checked against the SOA curves. This is simple for resistive
loads but more complex for reactive and EMF generating ISENSE
loads. The following guidelines may save extensive analytical
efforts. RS
Under transient conditions, capacitive and dynamic* induc-
VS
tive loads up to the following maximum are safe:
FIGURE 2. PA26 EQUIVALENT SCHEMATIC (ONE CHANNEL)
Vs CAPACITIVE LOAD INDUCTIVE LOAD
VBOOST
20V 200F 7.5mH
The VBOOST pin is the positive terminal for the load of the
15V 500F 25mH
second stage of the amplifier. When that terminal is connected
10V 5mF 35mH
to a voltage greater than +VS it will provide more drive to the
5V 50mF 150mH
upper output transistor, which is a darlington connected emit-
* If the inductive load is driven near steady state conditions, ter follower. This will better saturate the output transistor.
allowing the output voltage to drop more than 6V below the When VBOOST is about 5 Volts greater than +VS the positive
supply rail while the amplifier is current limiting, the inductor output can swing 0.5 Volts closer to the rail. This is as much
should be capacitively coupled or the supply voltage must be improvement as is possible.
lowered to meet SOA criteria. VBOOST pin requires approximately 1012mA of current.
Dynamically it represents 1K impedance. The maximum
NOTE: For protection against sustained, high energy flyback, voltage that can be applied to VBOOST is 40 volts with respect to
external fast-recovery diodes should be used. VS . There is no limit to the difference between +VS and VBOOST.
198
+VS 20V Figure 4 shows the PA26 ISENSE feature being used to obtain
DB1 DB2 a Transconductance function. In this example, amplifier "A" is
the master and amplifier "B" is the slave. Feedback from
7 3 10 sensing resistors RS is applied to the summing network and
CB1 scaled to the inverting input of amplifier "A" where it is com-
pared to the input voltage. The current sensing feedback
PA26A 5 imparts a Transconductance feature to the amplifiers transfer
CB2
function. In other words, the voltage developed across the
SPEAKER
sensing resistors is directly proportional to the output current.
Using this voltage as a feedback source allows expressing the
PA26B 8
gain of the circuit in amperes vs input voltage. The transfer
funcion is approximately:
FIGURE 3. SIMPLE BOOTSTRAPPING IMPROVES POSITIVE
OUTPUT SWING. CONNECT PINS 3 AND 10 TO VS IF NOT IL + (VIN VREF) = RIN
USED. TYPICAL CURRENTS ARE 12mA EACH.
RFB * RS
Figure 3 shows a bootstrap which dynamically couples the
output waveform onto the VBOOST pin. This causes VBOOST to
swing positive from it's initial value, which is equal to +VS -0.7 V In the illustration, resistors RIN, RFB and RS determine gain.
(one diode drop), an amount equal to the output. In other
words, if VBOOST was initially 19.3, and the output swings MOUNTING PRECAUTIONS
positive 18 Volts, the voltage on the VBOOST pin will swing to 19.3
-0.7 + 18 or 36.6. The capacitor needs to be sized based on a 1. Always use a heat sink. Even unloaded, the PA26 can
1K impedance and the lowest frequency required by the dissipate up to 3.6 watts. A thermal washer or thermal
circuit. For example, 20Hz will require > 8uF. grease should always be used.
2. Avoid bending the leads. Such action can lead to internal
damage.
ISENSE 3. Always fasten the tab to the heat sink before the leads are
The ISENSE pin is in series with the negative half of the output soldered to fixed terminals.
stage only. Current will flow through this pin only when nega- 4. Strain relief must be provided if there is any probability of C
tive current is being outputted. The current that flows in this pin axial stress to the leads.
is the same current that flows in the output (if 1A flows in the
output, the ISENSE pin will have 1A of current flow, if +1A flows
in the output the ISENSE pin will have 0 current flow).
The resistor choice is arbitrary and is selected to provide
whatever voltage drop the engineer desires, up to a maximum
of 1.0 volt. However, any voltage dropped across the resistor
will subract from the swing to rail. For instance, assume a +/
12 volt power supply and a load that requires +/1A. With no
current sense resistor the output could swing +/10.2 volts. If
a 1 resistor is used for current sense (which will drop 1 Volt
at 1 Amp) then the output could swing +10.2, 9.2 Volts.
+VS
PA26
B
VREF
R
RL IL
VIN R
A
RFB
RIN
RS RIN
RS RS
VS OR GND VREF
FIGURE 4. ISENSE TRANSCONDUCTANCE BRIDGING

AMPLIFIER
sheet has been carefully checked TELEPHONE
and is believed to be reliable,(520) 690-8600
however, FAXis(520)
ORDERS (520) 690-8601
PA21/25/26U REV. F FEBRUARY 1998 1998 Apex Microtechnology Corp.
199
PA21M
1 Quiesent Current IQ 25C 15 VIN = 0, AV = 100 75 mA

1 Input Offset Voltage VOS 25C 2.5 VIN = 0, AV = 100 10 mV
1 Input Offset Voltage VOS 25C 15 VIN = 0, AV = 100 10 mV
1 Input Bias Current + IN + IB 25C 15 VIN = 0 1000 nA
1 Input Bias Current IN IB 25C 15 VIN = 0 1000 nA
1 Input Offset Current IOS 25C 15 VIN = 0 500 nA


4 Output Voltage IO= 2A VO 25C 9.5 RL = 3 6.0 V

4 Output Voltage IO= 100mA VO 25C 11 RL = 100 10 V
4 Stability/Noise EN 25C 15 RL = 500, AV = 1 CL = 1.5nF 1.0 mV
4 Crosstalk XTLK 25C 15 RL = 3 50 dB
4 Slew Rate SR 25C 15 RL = 500 .5 V/S
4 Open Loop Gain AOL 25C 15 RL = 500, F =10Hz 75 dB
4 Common-mode Rejection CMR 25C 17 RL = 500, VCM = 14V 60 dB

6 Output Voltage IO= 100mA VO 55C 11 RL = 100 10 V
6 Stability/Noise EN 55C 15 RL = 500, AV = 1, CL = 1.5nF 1.0 mV
6 Open Loop Gain AOL 55C 15 RL = 500, F = 10Hz 75 dB

5 Output Voltage IO= 100mA VO 125C 11 RL = 100 10.0 V
5 Output Voltage IO= 750mA VO 125C 4.0 RL = 3 2.25 V
5 Stability/Noise EN 125C 15 RL = 500, AV = 1, CL = 1.5nF 1.0 mV
5 Open Loop Gain AOL 125C 15 RL = 500, F = 10Hz 75 dB
BURN IN CIRCUIT
10K
10K
+15V * These components are used to stabilize device due
10K to poor high frequency characteristics of burn in
10K
3 2 6
board.
1 8 *
* 4
A B 5 ** Input signals are calculated to result in internal
** power dissipation of approximately 2.1W at case
* U.U.T. 7 * temperature = 125C.
15V
200 200
without notice.
PA21MU REV. F DECEMBER 1997 1997 Apex Microtechnology Corp.
200
POWER DUAL OPERATIONAL AMPLIFIERS
PA21/25/26 DESIGN IDEAS

+VS 10K 10K

TYPICAL CIRCUITS: (12V or +14.4V
10K 28V) .1F +14.4 10K
2K 10K
1K 22F 1K
10K
+VS
(12V or 1/2 PA26 10K A B
28V) 1 1/2 PA26 RL = 4 1/2 PA26
5V 20F
A B 1 1
Reference
1/2 PA26 .1F .1F
1 1 2.2F
VIN .1F .1F
10K
10K 2K 10K VIN 100K 100F 1K
.5Vrms PO = 14W rms
Rd Thd = 0.1%
< 0.5% THD
Cf Pbw = 20Hz - 20kHz
AUDIO BRIDGE
CURRENT CONTROL
SOLENOID OR LINEAR ACTUATOR DRIVE
200mA/V current output R2 R3
+28V
9K 10K
RI RF R4
+28V
+VS
R1
10K
R5
C
1/2
PA26 10K
RS VO 5K A M B
A + +
.2 1/2 PA26 1/2 PA26
1 2I
I R6
.1F 1 1
VIN COMMAND 10K
LOAD INPUT .1F .1F
0/10V
1/2
PA26 RS
B BIDIRECTIONAL MOTOR DRIVE
.2
1
I 39K 61.5K +VS
VS .1F
+VS 1K
10F 10K
PARALLEL CONNECTION
yields single 6A amplifier A B 9.5K
1/2 1/2
10F PA26 1 1 PA26 8.2K
10K VIN 10K .1F .22F .1F
+VS
10K (+12 or 8.2K .22F
28V)
1
A
10K 1/2 PA26 1 1K
VIN Rd 10F .1F
.1F LOAD
Cf
60Hz 3 PHASE MOTOR DRIVE
Single Supply
10K
10K
+VCC
10K R
1 (+VS/2)
B 1/2 PA26
10K 1 VS
VIN 1/2 PA26 Rd
.1F LOAD .1F
Cf
R
1
10K VCC
(VS/2)
DUAL UNIPOLAR SOLENOID DRIVER
1A/V current output ARTIFICIAL GROUND (SUPPLY SPLITTER)
however, FAXis(520)
ORDERS (520) 690-8601
PA21/25/26DIU REV. C FEBRUARY 1998 1998 Apex Microtechnology Corp.
201
EK26
INTRODUCTION
Fast, easy breadboarding of circuits using the PA26 are possible The following locations should be jumpered unless used (their
with the EK26 PC board. Mounting holes are provided and the most common anticipated function is listed).
provision for standard banana jacks simplifies connection and
testing. The amplifier may be mounted horizontally or vertically. R2, R10 Input protection.
Components are labeled on both sides of the board for ease in CR1 VBOOST.
probing. R5, R6, R9 Output current sense.
A multitude of circuit configurations are possible, so only several
component locations have specific functions and will usually be The function of any other components is up to the designers
necessary: needs and imagination.
C5,C8 Power supply bypasses MUST be used. Usually

ceramic types of 0.01 to 1.0F.
C2, C9 Power supply bypass. Suggest 10F per ampere of
output current.
R1 Feedback resistor.
R3 Input resistor.
R8, C10 Snubber network.
R4, C7 Noise gain compensation. Necessary only occasion
ally, see Application Notes 19 and 25.
R101
GND
C101 C102
C103 C104 +V
C105
CR101
IN 1 C106 CR102
R103 7
2
VCC 35 R105 R106
R104 R102 OUT 1
1 VEE 4
R107 C107 R110 6 GND
R109 R108 CR103
R111 C108 C110
C111 C112
+IN 1 V
C109
GND
R201
C201
C203 C204
CR201
IN 2 C206 CR202
R203 11 10
VCC 8 R205 R206
R204 R202 OUT2
12 VEE 9
R207 C2107 R210
GND
R209 R208 CR203
R211 C210
C211 C212
+IN 2
202
EVALUATION KIT
7"
C212
C112
CR201
R210 CR101 R110
C211 C111
R111
R107
R207
R211
C207 C107
+IN2 +IN1
R204 R104
C102 C109
GND2 GND1
C203 C103
R203 R202 C105 C108 R102 R103
R201 CR102 CR103 R101 C104
C204
CR202 CR203
C201 C101 5"
IN2 IN1
R205 R105
C206 C106
OUT2 R206 R106 OUT1
R208 R108
C
C210 C110
R209 R109
EK26
REV A
GND
+V
1
C212
C112
R107
R111
R211
R207
R110 CR201 R210
CR101
C107 C207
+IN1 R109 R102 +IN2
C111 R104 R204 C211
GND1 GND2
C103 C203
R103 R102 C108 C105 R202 R203
CR103 CR102 R201 C204
C104 R101
CR203 CR202
C101 C201
IN1 IN2
C105 R205
OUT1 C106 C206 OUT2
R106 R206
R108 R208
C110 C210
R109 R209
EK262 REV A
COMP. SIDE
GND
+V
V
NOTE: Illustration only, not to scale.
however, FAXis(520)
ORDERS (520) 690-8601
EK26U REV. B FEBRUARY 1998 1998 Apex Microtechnology Corp.
203
EK21
INTRODUCTION
This easy-to-use kit provides a platform for the evaluation of Figure 3) provide maximum flexibility for a variety of configurations.
power op amps that use the PA21 pin-out configuration. It can be Also included are loops for current probes as well as connection
used to analyze a multitude of standard or proprietary circuit pads on the edge of the PC board for easy interconnects.
configurations. In addition, it is flexible enough to do most standard The hardware required to mount the PC board and the device
amplifier test configurations. under evaluation to the heatsink are included in the kit. Because of
The schematic for 1/2 of the PC board is shown in Figure 2. The the limitless combination of configurations and component values
schematic for the other half is identical except part reference that can be used, no other parts are included in this kit. However,
designators are primed (i.e. R1 = R1'). Note that all of the compo- generic formulas and guidelines are included in the APEX
nents shown on the schematic will probably not be used for any DATABOOK and this evaluation kit documentation.
single circuit. The component locations on the PC board (See
ASSEMBLY HINTS ASSEMBLY

The mating sockets included with this kit have recessed nut 1. Insert a #6 x 5/16" hex nut in each of the nut socket recesses
sockets for mounting the device under evaluation. This allows located on the bottom of the mating socket.
assembly from one side of the heatsink, making it easy to swap 2. Insert the socket into the pc board until it is firmly pressed against
devices under evaluation. The sizes of the stand-offs were se- the ground plane side of the pc board.
lected to allow proper spacing of the board-to-heatsink and allow 3. Solder the socket in place (see Figure 1). Be sure the nuts are
enough height for components when the assembly is inverted. in the recesses prior to soldering.
4. Mount the PC board assembly to the heatsink using the stand-
PARTS LIST offs and spacers included.
5. Apply thermal grease or a TW03 to the bottom of the device
Part # Description Quantity under evaluation. Insert into the mating socket through the
HS11 Heatsink 1 heatsink.
EK21PC PC Board 1 6. Use the #6 x 1.25" panhead screws to mount the amplifier to the
MS03 Mating Socket 2 heat sink. Do not overtorque. Recommended mounting torque is
HWRE01 Hardware Kit 1 4-7 in-lbs (.45-.79 NM).
TW03 Thermal Washer 1 Box/10
Mounting precautions, general operating considerations, and
HWRE01 contains the following: heatsinking information may be found in the APEX DATA BOOK.
4 #8 Panhead Screw 4 #6 x 1.25" Panhead Screw
4 #8 .375" Hex Spacer 4 #6 x 5/16" Hex Nut NOTE: Refer to HS11 Heatsink in Accessories section
4 #8 1.00" Hex Stand Off 2 #6 x 1/4" Hex Nut
Figure 1
Heatsink
Power Op Amp
Package
#6 Screw
#8 Screw
Recessed Nuts #8 .375"

Hex Spacer
#8 1.00"
Teflon Tubing PC Board Hex Standoff
(2 Opposite Pins Mating Socket
Minimum)

All Apex amplifiers should be handled using proper ESD precau- Do not change connections while the circuit is under power.
tions! Never exceed any of the absolute maximums listed in the device
Initially set all power supplies to the minimum operating levels data sheet.
allowed in the device data sheet. Always use adequate power supply bypassing.
Check for oscillations. Remember that internal power does not equal load power.
Always use the heatsink included in this kit with thermal grease Do not count on internal diodes to protect the output against
or a TW03 and torque the part to the specified 4-7 in-lbs sustained, high frequency, high energy kickback pulses.
(.45-.79 NM).
204
EVALUATION KIT
Figure 2 C3 J1 R2
R1 +VS
C6
C1 C2 C4 C5 R3 C7 C8
2 +VS 7
R5 R4
1 D1 D2 6
13 C10 R6 R9 C9 8
A B
R12 R13 A B R10 R11
3 R7 R8 9
R14 R15
R17 D3 D4 R16
C15 C16 C13 C14
4 10
C11 C12 VS
VS
Figure 3. (Actual size 6" x 8")

COMPONENT FUNCTION
R1 Feedback resistor, A side
R2 Input resistor, B side, bridge mode
R3
R4
Feedback resistor, B side
Input resistor, B side
C
R5 Input resistor, A side
R6 Input bias current measurement
(Note 4)
R7 Output current sense resistor or
loop for current probe
R8 Output current sense resistor or
loop for current probe
(Note 4)
R10 Noise gain compensation
(Note 1)
R11 Resistor divider network for
single supply bias (Note 2)
R13 Noise gain compensation
(Note 1)
C1 Input coupling
C2 AC gain set
C3 AC gain or stability (Note 1)
C4 Power supply bypass
C5 Power supply bypass
C6 AC gain or stability (Note 1)
C7 AC gain set
C8 Input coupling
C9 Noise gain compensation
(Note 1)
C10 Noise gain compensation NOTES: Refer to the following sections of the APEX DATA BOOK
(Note 1) as noted.
C11 Power supply bypass (Note 3)
C12 Power supply bypass (Note 3) 1. See Stability section of General Operating Considerations.
D1,2,3,4 Flyback protection (Note 5) 2. See Gen. Operating Considerations, and AN3 Bridge Circuit Drives.
C13-16 Bias node noise bypass (Note 2) 3. See Power Supplies section of General Operating Considerations.
4. See Parameter Definitions and Test Methods.
5. See Amplifier Protection section of Gen. Operating Considerations.
205
EVALUATION KIT
FOR PA 21 PIN-OUT EK21
BRIDGE MODE OPERATION

There are two types of bridge mode operation that will be covered should be shorts. The available output voltage swing is Vss
in this section; dual (or split) supply and single supply. The PA21 is (2*Vsat). If operating a PA21A at 3 Amps and 30 Volts total supply
well suited for both types of bridge mode operation. If another this translates to:
vendors pin compatible part is to be compared to the PA21, a close
look at output swing and input common mode range is in order. The VAB(max) = 30(2*3.5) = 23
features that make the PA21 an excellent choice for bridge opera- Of course this 23 volts may be applied in either direction across
tion are not included in most other amplifiers. A lack of common the load. To set the gain of the circuit you must determine the
mode range may cause permanent damage to other pin compatible desired voltage across the load at Vin = full scale. Inserting these
parts and the inability of other amplifiers to swing close to the supply values into the following equation will yield the ratio of R1 to R5.
rails may cause a lack of available output voltage at the load as well
(VAB /(2*Vin)) = R1/R5
as increase internal dissipation.
The circuit shown in Figure 4 is a dual supply bridge using the The values of R 1,2,3, and 5 should be chosen such that input bias
master-slave configuration. Resistors R 6,7,8,9,14,15 and J1 current will not cause an error voltage that is unacceptable. Set R2
J1 R2
Figure 4
Dual R1 +VS
1 R5
Supply
Bridge C4 C5 R3
+VS
VIN
D1 D2
R6 R9
A B
3 A B
9
R7 R8
R14 R15
D3 D4
C11 C12 VS
VS
2 C1 J1 R2
Figure 5
Single R1 +VS
Supply 1 R5
Bridge C4 C5 R3
+VS
+VS
D1 D2
13
R6 R9
A B
R12 A B
3 R7 R8
C15 C16 R14 R15
R17 D3 D4
4
equal to R3 to configure the slave amplifier as a unity gain inverter. The gain and output voltage capability for the single supply bridge
Figure 5 shows a typical single supply bridge circuit for an AC are determined the same way as the dual supply bridge (see AN#2).
coupled input signal. DC coupled inputs may require a different The difference is the bias requirement for the slave amplifier. The
topology to accommodate proper gain and offset terms for a desired noninverting input of the slave amplifier should be biased at mid
transfer function. supply, and must be bypassed.
HS11 HEATSINK NOTE

The HS11 Heatsink is provided in this evaluation kit to guarantee adequate thermal design through heat removal from the part under
evaluation. Once maximum power dissipation for the application is determined (refer to General Operating Considerations and
Application Note 11 in the APEX DATA BOOK), the final mechanical design will probably require substantially less heatsinking.
APEX MICROTECHNOLOGY makes no representation that the use or interconnection of the circuits described herein will not infringe
on existing or future patent rights, nor do the descriptions contained herein imply the granting of licenses to make, use or sell equipment
constructed in accordance therewith.
without notice.
EK21U REV. G DECEMBER 1997 1997 Apex Microtechnology Corp.
206
DUAL OPERATIONAL AMPLIFIER
PA25DIE

OUTPUT CURRENT, continuous 2.5A
INPUT VOLTAGE, differential VS
INPUT VOLTAGE, common mode +VS VS0.3
TEMPERATURE, junction 150C
NOTE: Refer to parent product data sheet PA21/25/26 for typical AC electrical characteristics,
precautions, applications and other test parameters.
TYPICAL SPECIFICATIONS
POWER SUPPLY VOLTAGE +VS to VS 5 12 40 V

OFFSET VOLTAGE VOUT = 0, IOUT = 0 2 mV
QUIESCENT CURRENT +IS Total 35 mA
BIAS CURRENT VOUT = 0 80 nA
OPEN LOOP GAIN F = 0 Hz 100 dB
COMMON MODE REJECTION RATIO Delta VCM = 3V 85 dB
SLEW RATE A =1, VOUT = 6VP-P 1 V/s
CHANNEL SEPARATION
VOLTAGE SWING
IOUT = 100mA, F = 1kHz
IOUT = 1A, VCC = 6V
60
10.0
dB
VP-P
C
VOLTAGE SWING IOUT = 1A, VCC = VCC = 6VBOOST = 9V 10.5 VP-P
POWER SUPPLY REJECTION RATIO VS = 15V 80 dB
NOTES: 1. VS = 15 V unless otherwise stated. TA = 25C.
TYPICAL EXTERNAL CONNECTIONS DIE LAYOUT

9 8 7 7 6
RF Is 2 Vo 2 +Vs +Vs Vo 1 Is 1 5
+VS
RI 7
3
4 117 Mil
6
2972
VIN
2 5
1
Vb 2 Vb 1
10 4
Vi 2 Vi 1
VS 11 3
+Vi 2 Vs +Vi 1
Pad Function
12 1 2
2 Non-inverting Input AMP 1 143 Mil
3 Inverting Input AMP 1 3632
4 VBOOST Input AMP 1
5 Current Sense Output AMP 1 Thickness: 18 Mil 2 Mil
6 Output AMP 1 Backside: Ni Ag 20,000 (min)
12 Non-inverting Input AMP 2 Bond pad: 10 Mil sq (254)
11 Inverting Input AMP 2 NOTE: Backside at VS potential.
10 VBOOST Input AMP 2
9 Current Sense Output AMP 2
8 Output AMP 2
7 Positive Supply Input Both Amplifiers
1 Negative Supply Input Both Amplifiers
however, FAXis(520)
ORDERS (520) 690-8601
PA25DIEU REV. A FEBRUARY 1998 1998 Apex Microtechnology Corp.
207
NOTES:
208
HIGH VOLTAGE POWER OPERATIONAL AMPLIFIERS
PA41/PA42 PA41A/PA42A
FEATURES
MONOLITHIC MOS TECHNOLOGY
LOW COST
HIGH VOLTAGE OPERATION350V
LOW QUIESCENT CURRENT2mA
NO SECOND BREAKDOWN
HIGH OUTPUT CURRENT120 mA PEAK
AVAILABLE IN DIE FORMPA41DIE
TYPICAL APPLICATION
R 20R 20R
APPLICATIONS
20R
V IN
PIEZO ELECTRIC POSITIONING +175
+175
ELECTROSTATIC TRANSDUCER & DEFLECTION 2.2K 2.2K
DEFORMABLE MIRROR FOCUSING 10pF

10pF
BIOCHEMISTRY STIMULATORS A1 A2
PA41/42 PA41/42
COMPUTER TO VACUUM TUBE INTERFACE R CL R CL Rn
PIEZO
180 TRANSDUCER 180
100 Cn
100
DESCRIPTION 330pF 330pF
The PA41/42 are high voltage monolithic MOSFET opera-

tional amplifiers achieving performance features previously LOW COST 660V p-p
found only in hybrid designs while increasing reliability. Inputs 175 PIEZO DRIVE 175
are protected from excessive common mode and differential Two PA41/42 amplifiers operated as a bridge driver for a
mode voltages. The safe operating area (SOA) has no second piezo transducer provides a low cost 660 volt total drive capa-
breakdown limitations and can be observed with all type loads bility. The RN CN network serves to raise the apparent gain of A2
by choosing an appropriate current limiting resistor. External at high frequencies. If RN is set equal to R the amplifiers can be
compensation provides the user flexibility in choosing compensated identically and will have matching bandwidths.
optimum gain and bandwidth for the application.
The PA41 is packaged in a hermetically sealed TO-3 and all EXTERNAL CONNECTIONS
circuitry is isolated from the case by an aluminum nitride (AlN)
R CL
substrate.
The PA42 is packaged in APEXs hermetic ceramic SIP10 PHASE
CC
RC COMPENSATION
package. Gain CC RC
2 COMP
1 18pF 2.2K
COMP 3 I LIM
1 10 10pF 2.2K
OUT 4 30 3.3pF 2.2K
8 (6)
TOP VIEW CS
+VS 330pF
D1
5
8 C S , C C ARE NPO RATED
Q1 IN RS
Q2 FOR FULL SUPPLY VOLTAGE.
Q3 6
7 +VS 100
I LIM VS R CL = 3
+IN
1 (7) PA41 I LIM
Q4 Q5 Q7
(1) 5 (8) 2 Q6 TOP VIEW
COMP 4 (10)
IN PA42
Q9 OUT 1 2 3 4 5 6 7 8 9 10
D2 D3 D4 D5 COMP Q8
(2) 6 (9) 3 NC NC VS +VS I LIM CC CC OUT
+IN RS RC
Q11 Q10 100
Q12 Q13 IN +IN CS CC
330pf
Q14
RCL
VS
7
NOTE: PA41 Recommended mounting torque is 4-7 inlbs
(5) (.45 -.79 Nm)
5 PA41 PIN NUMBER
(1) PA42 PIN NUMBER CAUTION: The use of compressible, thermally conductive
insulators may void warranty.
209
PA41/PA42 PA41A/PA42A SPECIFICATIONS
PA41/PA41A PA42/PA42A
OUTPUT CURRENT, continuous within SOA 60 mA 60 mA
OUTPUT CURRENT, peak 120 mA 120 mA
POWER DISSIPATION, continuous @ TC = 25C 12W 9W
INPUT VOLTAGE, differential 16 V 16 V
INPUT VOLTAGE, common mode VS VS
TEMPERATURE, pin solder 10 sec 300C 220C
2
TEMPERATURE, junction 150C 150C
TEMPERATURE, storage 65 to +150C 65 to +150C
TEMPERATURE RANGE, powered (case) 40 to +125C 40 to +125C
SPECIFICATIONS PA41/PA42 PA41A/PA42A
INPUT
OFFSET VOLTAGE, vs. temperature4, 7 Full temperature range 70 130 40/* 65/* V/C
OFFSET VOLTAGE, vs supply 20 32 * * V/V
OFFSET VOLTAGE, vs time 75 * V kh
BIAS CURRENT, initial 7 5/100 50/2000 * * pA
BIAS CURRENT, vs supply .2/.5 .5/50 * * pA/V
OFFSET CURRENT, initial 7 2.5/100 50/400 * * pA
COMMON MODE, voltage range VS12 * V
COMMON MODE REJECTION, DC VCM = 90V DC 84 94 * * dB
NOISE, broad band 10kHz BW, RS = 1K 50 * V RMS
NOISE, low frequency 1-10 Hz 110 * V p-p
GAIN
OPEN LOOP at 15Hz RL = 5K 94 106 * * dB
BANDWIDTH, open loop 1.6 * MHz
POWER BANDWIDTH CC = 10pf, 280V p-p 26 * kHz
OUTPUT
VOLTAGE SWING IO = 40mA VS12 VS10 VS10 VS8.5 V
CURRENT, peak5 120 * mA
CURRENT, continuous 60 * mA
SETTLING TIME to .1% CC = 10pF, 10V step, AV = 10 12 * s
SLEW RATE CC = OPEN 40 * V/s
CAPACITIVE LOAD AV = +1 10 * nF
RESISTANCE 6, no load RCL = 0 150 *
RESISTANCE 6, 20mA load RCL = 0 25 *
POWER SUPPLY
VOLTAGE3 See Note 3 50 150 175 * * * V
CURRENT, quiescent 1.6 2.0 .9 1.4 1.8 mA
THERMAL
PA41 RESISTANCE, AC junction to case F > 60Hz 5.4 6.5 * * C/W
PA42 RESISTANCE, AC junction to case F > 60Hz 7 10 * * C/W
PA41 RESISTANCE, DC junction to case F < 60Hz 9 10.4 * * C/W
PA42 RESISTANCE, DC junction to case F < 60Hz 12 14 * * C/W
PA41 RESISTANCE, junction to air Full temperature range 30 * C/W
PA42 RESISTANCE, junction to air Full temperature range 55 * C/W
NOTES: * The specification for PA41A/PA42A is identical to the specification for PA41/PA42 in applicable column to the left.
1. Unless otherwise noted TC = 25C, CC = 18pF, RC = 2.2K. DC input specifications are value given. Power supply voltage is
typical rating.
to achieve high MTTF. For guidance, refer to heatsink data sheet.
3. Derate maximum supply voltage .5 V/C below case temperature of 25C. No derating is needed above TC = 25C.
4. Sample tested by wafer to 95%.
6. The selected value of RCL must be added to the values given for total output resistance.
7. Specifications separated by / indicate values for the PA41 and PA42 respectively.
CAUTION The PA41/PA42 is constructed from MOSFET transistors. ESD handling procedures must be observed.
210
TYPICAL PERFORMANCE
GRAPHS PA41/PA42 PA41A/PA42A
POWER DERATING CURRENT LIMIT CURRENT LIMIT

15 140 60
CURRENT LIMIT RANGE, I (mA)

T = TC 130
12 40
PA41 +I LIM
T = TC PA42 120 20
9
110 I LIM 0
6 +I LIM
T = TA 100 20
-I LIM
3 40
90
T = TA
0 80 60
0 25 50 75 100 125 50 25 0 25 50 75 100 125 0 100 200 300 400 500
TEMPERATURE, T (C) CASE TEMPERATURE, TC (C) CURRENT LIMIT RESISTOR, R CL ( )

120 0 400
R L = 10K

100 30 CC = 3.3pF
CC = 3.3pF 200
80 60 CC = 10pF
CC = 18pF
CC = 10pF
PHASE, ()
60 CC = 10pF 90
100
CC = 18pF CC = 3.3pF
40 120 80
CC = 18pF CC = 3.3pF 60
20 150
40
0 180
CC = 10pF CC = 18pF
20 210 20
1 10 100 1K 10K .1M 1M 10M 1 10 100 1K 10K .1M 1M 10M 10K 20K30K 50K .1M .2M .3M .5M 1M
NORMALIZED QUIESCENT CURRENT, (%)
HARMONIC DISTORTION SLEW RATE QUIESCENT CURRENT

1.0 60 150
.6 AV = 20
.4 CC = 3.3pf
50
R L = 2K 130
.2
SLEW RATE, V/s
DISTORTION, (%)
40
.1 VO = 30VPP 110
.06 5C
.04
VO = 180VPP 30 =8
T C
VO = 60VPP 90
.02 20 5C
=2
.01 TC
70 5C
.006 10 = -2
.004 TC
.002 0 50
100 200 1K 3K 10K 30K 100K 0 4 8 12 16 20 100 150 200 250 300 350
FREQUENCY, F (Hz) COMPENSATION CAPACITANCE, C C (pf) TOTAL SUPPLY VOLTAGE, VS (V)
VOLTAGE DROP FROM SUPPLY, VS VO (V)
COMMON MODE REJECTION POWER SUPPLY REJECTION OUTPUT VOLTAGE SWING

120 120 18
16
100 100
14 T
OU
+VS 85C
80 80 12
OUT
60
10 25C
60 VS OUT
8 25C
40 40 6 T
25C +OU
4
20 20 85C +OUT
2
0 0 25C +OUT
0
1 10 100 1K 10K .1M 1M 1 10 100 1K 10K .1M 1M 0 20 40 60 80 100 120
FREQUENCY, F (Hz) FREQUENCY, F (Hz) OUTPUT CURRENT, I O (mA)
211
OPERATING
PA41/PA42 PA41A/PA42A CONSIDERATIONS
GENERAL resistor. The time constant of the feedback resistor and

bypass capacitor combination should match the time constant
Please read the General Operating Considerations sec- of the sumpoint resistance and sumpoint capacitance.
tion of the data book, which covers stability, supplies, The PA41/42 is externally compensated and performance
heatsinking, mounting, SOA interpretation and specification can be tailored to the application. Use the graphs of small
interpretation. For information on the package outline, heatsinks signal gain and phase response as well as the graphs for slew
and mounting hardware, consult the "Packages and Accesso- rate and power response as a guide. The compensation
ries" section of the data book. See "PA41/PA42 Design Ideas" capacitor CC must be rated at 350V working voltage. The
for a detailed discussion of support components. Apex Appli- compensation capacitor and associated resistor RC must be
cation Notes contain a wealth of information on specific types mounted closely to the amplifier pins to avoid spurious oscilla-
of applications. See www.apexmicrotech.com for design tools tion. An NPO capacitor is recommended for compensation.
automating several application notes.
CURRENT LIMIT The MOSFET output stage of this power operational ampli-
For proper operation the current limit resistor, RCL, must be fier has two distinct limitations:
connected as shown in the external connection diagram. The
minimum value is 18 ohms, however for optimum reliability the 1. The current handling capability of the die metallization.
resistor value should be set as high as possible. The value can 2. The temperature of the output MOSFETs.
be estimated as follows with the maximum practical value of NOTE: The output stage is protected against transient
500 ohms. flyback. However, for protection against sustained, high en-
3
RCL = ergy flyback, external fast-recovery diodes should be used.
ILIM
Use the typical performance graphs as a guide for expected 200
PA41 SOA
variations in current limit value with a given RCL and variations
over temperature. The selected value of RCL must be added to 120
OUTPUT CURRENT FROM +VS OR VS, (mA)
200mS
the specified typical value of output resistance to calculate the 100
300mS
total output resistance. Since the load current passes through
RCL the value selected also affects * the output voltage swing
50 DC
according to: 40 DC
VR = IO RCL 30 ,T
C =
85
where VR is the voltage swing reduction. 20 DC C
,T
When the amplifier is current limiting, there may be small C =
12
signal spurious oscillation present during the current limited 10 5
C
portion of the negative half cycle. The frequency of the oscil-
lation is not predictable and depends on the compensation,
5
gain of the amplifier, and load. The oscillation will cease as the 4
amplifier comes out of current limit. 3
PULSE CURVES @ 10% DUTY CYCLE MAX
INPUT PROTECTION 2
10 20 30 50 100 200 300 500
The PA41/42 inputs are protected against common mode SUPPLY TO OUTPUT DIFFERENTIAL, VS -VO (V)
voltages up the supply rails and differential voltages up to 16
PA42 SOA
volts as well as static discharge. Differential voltages exceed- 200
ing 16 volts will be clipped by the protection circuitry. However,
120
if more than a few milliamps of current is available from the 10

100 30 0 m
overload source, the protection circuitry could be destroyed. 0m 20 S
S 0m
The protection circuitry includes 300 ohm current limiting S
resistors at each input, but this may be insufficient for severe 50
overloads. It may be necessary to add external resistors to the 40 DC
DC
application circuit where severe overload conditions are ex- 30 ,T
pected. Limiting input current to 1mA will prevent damage. DC C =
20 ,T 85
C
C
=
STABILITY 12
5
10 C
The PA41/42 has sufficient phase margin when compen-
sated for unity gain to be stable with capacitive loads of at least
10 nF. However, the low pass circuit created by the sumpoint 5
(in) capacitance and the feedback network may add phase 4
shift and cause instabilities. As a general rule, the sumpoint 3
load resistance (input and feedback resistors in parallel) PULSE CURVES @ 10% DUTY CYCLE MAX
2
should be 5K ohm or less at low gain settings (up to 10). 10 20 30 50 100 200 300 500
Alternatively, use a bypass capacitor across the feedback SUPPLY TO OUTPUT DIFFERENTIAL, VS -VO (V)
This data
5980 NORTH however, no responsibility
SHANNON ROAD is TUCSON,
assumed forARIZONA
85741 or omissions. All specifications are
USA APPLICATIONS subject to change
HOTLINE: 1 (800)without notice.
546-2739
PA41/42U REV. G JANUARY 1999 1999 Apex Microtechnology Corp.
212
PA41M




4 Slew Rate SR 25C 150V RL = 5K, CC = 18pF 5 V/s
4 Common Mode Rejection CMR 25C 102V RL = 5K, F = DC, VCM = 90V 84 dB



BURN IN CIRCUIT
+50V 2.2K burn in board.
100K 5 8 18pf
3
** Internal power dissipation of approximately
* 2 2.1W at case temperature = 125C.
4
U.U.T
1
** * 6
RCL 60
7 100
50V 330pf
50V
however, FAXis(520)
ORDERS (520) 690-8601
PA41MU REV. C JANUARY 1999 1999 Apex Microtechnology Corp.
213
HIGH VOLTAGE OPERATIONAL AMPLIFIER
PA41DIE

OUTPUT CURRENT, continuous 60mA
NOTE: Refer to parent product data sheet PA41 for typical AC electrical characteristics, precautions,
applications and other test parameters.
DC WAFER PROBED SPECIFICATIONS

OFFSET VOLTAGE, initial 15 30 mV

OFFSET VOLTAGE, vs. supply VS = 50 V to 175 V 20 32 V/V
OFFSET VOLTAGE, vs. temperature2 TA = 25-85C 50 130 V/C
BIAS CURRENT, initial 10 50 pA
COMMON MODE REJECTION VCM = 90 V DC 84 94 dB
VOLTAGE SWING IO = 40mA VS12 VS9 V
SUPPLY CURRENT, quiescent .9 1.4 2.0 mA
NOTES: 1. Unless otherwise stated VS = 150 V, TA = 25C, DC input specification value given.
TYPICAL EXTERNAL CONNECTIONS DIE LAYOUT
20K VS RF
+VS 15 14 13 12 11 10 9 8 7 6
16 5
50K 17 4
50K 18 3
11
35 2 19 2
4 21
20 1
RI 12 * 149 Mil
VIN 3780 21 36
36 19 R CL
22 35
17 *
100
9 RL 23 34
* * 33
330* pF
24
RC CC 25
CS 26 27 28 29 30 3132
LH1243A
VS VS
203 Mil
* Required component and value if given. 5160
Optional balance components are recommended values.
CS, CC are NPO, rated for full supply voltage VS to +VS. Thickness: 20 Mil (508)
NOTE: Diagram for connection illustration only. Backside: Ti (500) Au (3000)
All op amp configurations are possible. Bond pad: 4.9 Mil sq (125) AI
Bond pads 17 and 10 are connected
Pad Function Pad Function Make no connection to bond pads not listed by function
2 Balance 17 Compensation NOTE: Backside at VS potential.
4 Balance 19 Compensation Make no connection.
9 Supply 21 Current Limit
11 + Supply 35 Input
12 Output 36 + Input
CAUTION PA41DIE is a MOSFET amplifier. ESD handling procedures must be observed.
without notice.
214
PA41 PA42 DESIGN IDEAS

TYPICAL CIRCUITS:
RB CF RIS
CF
+350V
CFS
RI RF RI RF
RFS
V IN +335V
+350V
RC +350V
RC RC
CC
VOUT CC
CC +350V
VOUT 660VPP
PA41/42 0 to 325V PA41/42 PA41/42
R CL RB Rn
A1 R CL R CL A2
+350V R
CL CL Cn
R SN D.U.T. RI
RSN D.U.T. RSN
CSN RF
CSN CSN R C
V IN
15V
SINGLE SUPPLY BRIDGE
ASYMMETRICAL OUTPUT
RFC CF RIS C
RF
CFS
CFC RI RI RF
RFS
+15V CF
+175V +15V
V IN +335V
+15V RCL RC RC
VOUT CC
RIC CC
0 to 650V
PA41/42
PA41/42 PA41/42
VIN OP07 CL A1 R CL R CL A2 Rn
RSN CL
D.U.T.
RC RSN Cn
D.U.T. RSN
CSN CSN CSN
Rn 15V CC
Cn 15V 175V 175V

335V UNIPOLAR BRIDGE 15V
HIGH ACCURACY PA41 COMPOSITE
CF CF RIS
RF CFS
RI RI RF
V IN RFS
+175V
V IN +175V
RC +175V
RC RC
CC
VOUT CC
CC
VOUT 660VPP
PA41/42 165V
R CL PA41/42 PA41/42
A1 R CL R CL A2 Rn
CL CL
R SN D.U.T.
RSN RSN Cn
D.U.T.
CSN
CSN CSN
175V
BIPOLAR OUTPUT 175V BIPOLAR BRIDGE 175V
215
MINIMIZING PA41 EXTERNAL RI RF
COMPONENT COUNT RF
100
+V RI
When using PA41 die in hybrid circuits, it is desirable to
minimize the external component count as much as possible. 58
Observing the following guidelines will be useful. 14
67
1.0 EXTERNAL COMPENSATION CL > 330pF < 0.021F
External compensation RC, CC: these are only necessary at PA41 V

gains of 30 or lower. At gains above 30 they may be omitted.
Finished circuit stability should be verified into worst case FIGURE 2. EXAMPLE OF A CORRECT CIRCUIT GAIN OF 100
SHOWN, SEE TEXT REGARDING CONSIDERATIONS FOR
capacitive load with a small amplitude square wave at PA41
OTHER GAINS.
output. Overshoot should not exceed 25% or compensation
will be necessary. (For further details refer to Application Notes
The maximum capacitive load is then defined as the maxi-
19 and 25).
mum capacitance which has a reactance equal to 150 ohms (a
low current output impedance of PA41) at the frequency where
2.0 OUTPUT SNUBBER NETWORK the closed loop gain intersects the open loop gain. For a gain
Output snubber network100 ohm and 330 pF from output of 100 this corresponds to 0.021 F. If the load capacitance
to negative rail: this network is not necessary when driving a exceeds this value, the designer should make an evaluation
large capacitive load as is often the case with piezo drive. using the compensation network RC and CC as a first measure
Obviously the load should exceed 330 pF. If the large capaci- to enhance stability. CC is the smallest range of capacitance
tance induces loop stability problems, then a series resistor of values of any of the capacitors used on the PA41 which helps
100 ohms can be included between the amplifier and load keep the impact on real estate to a minimum. CC should be
assuming the bandwidth tradeoff is acceptable; otherwise, increased to whatever value provides at least a 40 phase
more involved stabilization methods per Application Notes 19 margin.
and 25 must be observed.
SMALL SIGNAL RESPONSE 4.0 CURRENT LIMIT
120
Current limit RCL: in applications where the load will have a
CC = 3.3pF
permanent connection so inadvertent shorts will not occur, and
100 the load has been defined to be well within the SOA (Applica-
CC = 10pF
tion Note 26 is helpful in plotting load lines vs. SOA), then it may
80 be possible to operate the amplifier with the current limit

CC = 18pF
bypassed. Additionally, it is helpful if the power supply has a
60 low current limit of 60mA or less. Note that RCL must be
AV CL = 40db replaced with a short circuit.
40
RI RF
20 RF
CB 30
50KHz +V RI
Z O = 150 RCL
0 1
C= = 0.021 F
Z O 2F
20
1 10 100 1K 10K .1M 1M 10M
FREQUENCY, F (Hz)
RS
Modified AOL due to: CC
RC CS CL < 330pF
FIGURE 1. CL = .021F
MAXIMUM CAPACITIVE LOAD. RO = 150
V
Omitting this 330 pF capacitor will often be desirable since CB
it must have a voltage rating equal to the total rail-to-rail
voltage, as does CC mentioned in Section 1.0 above; however, FIGURE 3. EXAMPLE OF HOW NOT TO REDUCE
CC is a much smaller capacitance value. COMPONENT COUNT.
3.0 MAXIMUM CAPACITIVE LOAD

5.0 POWER SUPPLY BYPASSING
Sections 1.0 and 2.0 require a minimum 330 pF capacitive
load. But what should be obvious to any experienced de- APEX routinely admonishes designers to use good, high
signer of op amp circuits is there also will be a maximum frequency bypass capacitors on the power supply lines in close
capacitive load. To determine maximum capacitive load refer physical proximity to the amplifier. A clean low impedance
to the SMALL SIGNAL RESPONSE graph of Figure 1. Using supply and low impedance current paths for power go a long
a gain of 100, or 40 dB as an example, the additional pole way towards making it possible to eliminate power supply
introduced into the response by the capacitive load must not bypass capacitors. The hybrid package of which the PA41
occur at a frequency less than the frequency where the closed becomes a part will require proper bypassing at its power
loop gain intersects the open loop gain. This will insure that supply pins. It is possible to stretch this rule if the designer
the additional phase shift will not exceed 45 in addition to the evaluates performance on actual working circuitsover tem-
90 already occurring in the op amp and result in a 45 phase
perature if possible.
margin.
without notice.
PA41/42DIU REV. B FEBRUARY 1998 1998 Apex Microtechnology Corp.
216
EVALUATION KIT FOR SIP10 PIN-OUT
EK42

C1
Fast, easy breadboarding of circuits using the PA42 and the
PA87 are possible with the EK42 PC board. Mounting holes are
provided and the provision for standard banana jacks simplifies C2 C3 R1
connection and testing. The amplifier may be mounted horizontally C5 +V
or vertically. Components are labeled on both sides of the board for CR1
IN
ease in probing. R2
A multitude of circuit configurations are possible, so only several GND
R3
component locations have specific functions and will usually always R4
6 10
be necessary: C6 1 7 R5 R6
R7 9 Out
8
C5,C7 Power supply bypasses MUST be used. Usually ceramic 5
types of 0.01 to 0.1F. R8 2 R9 R10
CR2
C10 R11
R1 Feedback resistor. GND
+IN C12
R2 Input resistor.
C7 C11
R9, C11 Compensation (see amplifier data sheet).
R5 Current limit (see amplifier data sheet). V
R7 Most often used as input bias current return for +input in
non-inverting circuits.
R3, C6 Noise gain compensation. Necessary only occasionally,
see Application Notes 19 and 25.
The following locations should be jumpered unless used (their CAUTION
most common anticipated function is listed).
High voltages will be present. C
Use caution in handling and
R4, R8 Input protection. probing when power is applied.
R11 General purpose.
R6 Output current sense.
The function of any other components is up to the designers

needs and imagination. 2.5"
63.5mm
1 1
+ C5 R9 R9 C5 +
R4 R4
C2 C2
C7 + C11 V V C11 + C7
IN R2 R2 IN
CR1 CR1
C3 C3
R3 CR2 CR2
R3
R6 R6
R8 R8
C12 OUT OUT C12
3.5"
C6 R10 88.9mm R10 C6
C1 C1
R7 R5 R5 R7
R1 R1
GND GND GND

GND R11 R11
+IN +V +V +IN
C10 C10
EK422 REV A EK42

COMP. SIDE REV A
however, FAXis(520)
ORDERS (520) 690-8601
EK42U REV. A DECEMBER 1997 1997 Apex Microtechnology Corp.
217
NOTES:
218
HIGH VOLTAGE POWER OPERATIONAL AMPLIFIER
PA44
FEATURES
SURFACE MOUNT PACKAGE
LOW COST
LOW QUIESCENT CURRENT2mA
NO SECOND BREAKDOWN
HIGH OUTPUT CURRENT120 mA PEAK
APPLICATIONS
TELEPHONE RING GENERATOR
13
PIEZO ELECTRIC POSITIONING +VS
ELECTROSTATIC TRANSDUCER & DEFLECTION D1
DEFORMABLE MIRROR FOCUSING Q1
Q2
Q3 I LIM
DESCRIPTION
15
The PA44 is a high voltage monolithic MOSFET operational Q4 Q5 Q7
amplifier achieving performance features previously found 5 19 Q6
COMP 21
only in hybrid designs while increasing reliability. Inputs are IN
protected from excessive common mode and differential mode Q9 OUT
D2 D3 D4 D5 COMP Q8
voltages. The safe operating area (SOA) has no second 7 17
breakdown limitations and can be observed with all type loads +IN
by choosing an appropriate current limiting resistor. External Q11 Q10
compensation provides the user flexibility in choosing Q12 Q13
optimum gain and bandwidth for the application. Q14
The PA44 is packaged in a non-hermetic surface mountable
dual in line package. The metal back of the package is tied to VS
Vs. 12
TYPICAL APPLICATION SUB

140V
2.67K 100K
IN6300A
15V RLIM
2.5K + 15 .22 RLIM 100
MUR130
RC CC *
3.3pF
CS
10K 10K MUR120 2.2K
4 5 6 330pF
21 19 17 15 13
7
90Vrms ILIM +VS
PA44 OUT COMP COMP
2
ICL8038 27
8 IN +IN VS
1 5 7 12
IN6300A 100
10 11
82K .22 330pf
NC TOP VIEW
*
*
MUR120 MUR130
* Supply bypassing required. See General Operating Considerations.
* 1.5 F @ 16Hz 140V
1.2 F @ 20Hz 15V
Telephone Ring Generator
PHASE COMPENSATION
Gain CC RC
The PA44 is set for a gain of 38.5 boosting the 2.33V signal 1 18pF 2.2K
to 90V. The recommended compensation for gains above 30 10 10pF 2.2K
is used. If capacitive loading is at least 330pF at all times, the 30 3.3pF 2.2K
recommended snubber network may be omitted. The 27 ohm
resistor sets current limit to a nominal value of 111mA to insure
peak currents out of at least 78mA.
219
PA44 SPECIFICATIONS

OUTPUT CURRENT, continuous within SOA 60 mA
OUTPUT CURRENT, peak 120 mA
POWER DISSIPATION, continuous @ TC = 25C 12W
INPUT VOLTAGE, differential 16 V
TEMPERATURE RANGE, powered (case) 40 to +125C
SPECIFICATIONS PA44
INPUT
OFFSET VOLTAGE, initial4 15 30 mV
OFFSET VOLTAGE, vs. temperature4 Full temperature range 70 130 V/C
OFFSET VOLTAGE, vs supply 20 32 V/V
OFFSET VOLTAGE, vs time 75 V kh
BIAS CURRENT, vs supply 2 20 pA/V
OFFSET CURRENT, initial 50 200 pA
INPUT IMPEDANCE, DC 1011
INPUT CAPACITANCE 5 pF
COMMON MODE, voltage range VS12 V
COMMON MODE REJECTION, DC VCM = 90V DC 84 94 dB
NOISE, broad band 10kHz BW, RS = 1K 50 V RMS
NOISE, low frequency 1-10 Hz 110 V p-p
GAIN
OPEN LOOP at 15Hz RL = 5K 94 106 dB
BANDWIDTH, open loop 1.6 MHz
POWER BANDWIDTH CC = 10pf, 280V p-p 26 kHz
PHASE MARGIN Full temperature range 60
OUTPUT
VOLTAGE SWING IO = 40mA VS12 VS10 V
CURRENT, peak5 120 mA
CURRENT, continuous 60 mA
SETTLING TIME to .1% CC = 10pF, 10V step, AV = 10 12 s
SLEW RATE CC = OPEN 40 V/s
CAPACITIVE LOAD AV = +1 10 nF
RESISTANCE 6, no load RCL = 0 150
RESISTANCE 6, 20mA load RCL = 0 25
POWER SUPPLY
VOLTAGE3 See Note 3 50 150 175 V
CURRENT, quiescent 1.6 2.0 mA
THERMAL
RESISTANCE, AC junction to case F > 60Hz 6 7 C/W
RESISTANCE, DC junction to case F < 60Hz 9 11 C/W
NOTES: 1. Unless otherwise noted TC = 25C, CC = 18pF, RC = 2.2K. DC input specifications are value given. Power supply voltage is
typical rating.
6. The selected value of RCL must be added to the values given for total output resistance.
CAUTION The PA44 is constructed from MOSFET transistors. ESD handling procedures must be observed.
220
TYPICAL PERFORMANCE
GRAPHS PA44
POWER DERATING CURRENT LIMIT CURRENT LIMIT

15 140 60
CURRENT LIMIT RANGE, I (mA)

T = TC 130
12 40
+I LIM
120 20
9
110 I LIM 0
6 +I LIM
T = TA 100 20
-I LIM
3 40
90
0 80 60
0 25 50 75 100 125 50 25 0 25 50 75 100 125 0 100 200 300 400 500
TEMPERATURE, T (C) CASE TEMPERATURE, TC (C) )
CURRENT LIMIT RESISTOR, R CL (

120 0 400
R L = 10K

100 30 CC = 3.3pF
CC = 3.3pF 200
80 60 CC = 10pF
CC = 18pF
CC = 10pF
PHASE, ()
60 CC = 10pF 90
100
CC = 18pF CC = 3.3pF
40 120 80
CC = 18pF CC = 3.3pF 60
20 150
40
0 180
CC = 10pF CC = 18pF
20 210 20
1 10 100 1K 10K .1M 1M 10M 1 10 100 1K 10K .1M 1M 10M 10K 20K30K 50K .1M .2M .3M .5M 1M
NORMALIZED QUIESCENT CURRENT, (%)

1.0 60 150
.6 AV = 20
.4 CC = 3.3pf
50
R L = 2K 130
.2
SLEW RATE, V/s
DISTORTION, (%)
40
.1 VO = 30VPP 110
.06 5C
.04
VO = 180VPP 30 =8
TC
VO = 60VPP 90
.02 20 5C
=2
.01 TC
70 5C
.006 10 = -2
.004 TC
.002 0 50
100 200 1K 3K 10K 30K 100K 0 4 8 12 16 20 100 150 200 250 300 350
FREQUENCY, F (Hz) COMPENSATION CAPACITANCE, C C (pf) TOTAL SUPPLY VOLTAGE, VS (V)

120 120 18
16
100 100
14 T
OU
+VS 85C
80 80 12
OUT
60
10 25C
60 VS OUT
8 25C
40 40 6 T
25C +OU
4
20 20 85C +OUT
2
0 0 25C +OUT
0
1 10 100 1K 10K .1M 1M 1 10 100 1K 10K .1M 1M 0 20 40 60 80 100 120
FREQUENCY, F (Hz) FREQUENCY, F (Hz) OUTPUT CURRENT, I O (mA)
221
OPERATING
PA44 CONSIDERATIONS
GENERAL resistance (input and feedback resistors in parallel) should be

Please read the General Operating Considerations sec- 1K ohm or less at low gain settings (up to 10). Alternatively, use
tion of the data book, which covers stability, supplies, a bypass capacitor across the feedback resistor. The time
heatsinking, mounting, SOA interpretation and specification constant of the feedback resistor and bypass capacitor com-
interpretation. For information on the package outline, heatsinks bination should match the time constant of the sumpoint
and mounting hardware, consult the "Packages and Accesso- resistance and sumpoint capacitance.
ries" section of the data book. See "PA41/PA42 Design Ideas" The PA44 is externally compensated and performance can
for a detailed discussion of support components. Apex Appli- be tailored to the application. Use the graphs of small signal
cation Notes contain a wealth of information on specific types gain and phase response as well as the graphs for slew rate
of applications. See www.apexmicrotech.com for design tools and power response as a guide. The compensation capacitor
automating several application notes. CC must be rated at 350V working voltage. The compensation
capacitor and associated resistor RC must be mounted closely
CURRENT LIMIT to the amplifier pins to avoid spurious oscillation. An NPO
capacitor is recommended for compensation.
For proper operation the current limit resistor, RCL, must be
connected as shown in the external connection diagram. The
minimum value is 33 ohms, however for optimum reliability the SAFE OPERATING AREA (SOA)
resistor value should be set as high as possible. The value can The MOSFET output stage of this power operational ampli-
be estimated as follows with the maximum practical value of fier has two distinct limitations:
500 ohms. 1. The current handling capability of the die metallization.
3 2. The temperature of the output MOSFETs.
RCL =
ILIM NOTE: The output stage is protected against transient
Use the typical performance graphs as a guide for expected flyback. However, for protection against sustained, high en-
variations in current limit value with a given RCL and variations ergy flyback, external fast-recovery diodes should be used.
over temperature. The selected value* of RCL must be added to
the specified typical value of output resistance to calculate the PA44 SOA
200
total output resistance. Since the load current passes through
RCL the value selected also affects the output voltage swing 120
200mS
according to: 100
300mS
VR = IO RCL
50 DC
where VR is the voltage swing reduction. 40 DC
30 ,T
C =
When the amplifier is current limiting, there may be small 85
20 DC C
signal spurious oscillation present during the current limited ,T
portion of the negative half cycle. The frequency of the oscil- C =
12
lation is not predictable and depends on the compensation, 10 5
C
gain of the amplifier, and load. The oscillation will cease as the
amplifier comes out of current limit. 5
4
INPUT PROTECTION 3
The PA44 inputs are protected against common mode PULSE CURVES @ 10% DUTY CYCLE MAX
2
voltages up the supply rails and differential voltages up to 16 10 20 30 50 100 200 300 500
volts as well as static discharge. Differential voltages exceed- SUPPLY TO OUTPUT DIFFERENTIAL, VS -VO (V)
ing 16 volts will be clipped by the protection circuitry. However,

if more than a few milliamps of current is available from the
overload source, the protection circuitry could be destroyed. HEATSINKING
The protection circuitry includes 300 ohm current limiting The PA44 package has a large exposed integrated copper
resistors at each input, but this may be insufficient for severe heatslug to which the monolithic amplifier is directly attached.
overloads. It may be necessary to add external resistors to the The solder connection of the heatslug to a minimum 1 square
application circuit where severe overload conditions are ex- inch foil area of the printed circuit board will result in thermal
pected. Limiting input current to 1mA will prevent damage. performance of 25C/W junction to air rating of the PA44.
Solder connection to an area of 1 to 2 square inches of foil is
STABILITY recommended. This may be adequate heatsinking but the
The PA44 has sufficient phase margin when compensated large number of variables involved suggest temperature mea-
for unity gain to be stable with capacitive loads of at least 10 nF. surements be made on the top of the package. Do not allow the
However, the low pass circuit created by the sumpoint (in) temperature to exceed 85C. The heatslug is tied internally to
capacitance and the feedback network may add phase shift Vs.
and cause instabilities. As a general rule, the sumpoint load
This data
5980 NORTH however,
ROAD isTUCSON,
assumed forARIZONA
546-2739
PA44U REV. B JANUARY 1999 1999 Apex Microtechnology Corp.
222
EVALUATION KIT FOR PA44
EK13
Fast and easy breadborading of circuits using the PA44 IS The PA44 is a surface mount device and should be assembled to
possible with the EK13 evaluation kit. The amplifier may be surface the EVAL15 PC board using surface mount processes. Solder
mounted directly to the PC board. The PA44 is soldered to a 2- paste may be dispensed or screen-printed on the DUT pads. The
square inch area of foil on the PC board for heat sinking. This foil heat tab on the back of the PA44 provides maximum heat dissipa-
heat sink is connected toVs. Connections are provided for required tion capabilities when soldered to the PCB metalization that runs
power supply bypassing, phase compensation components, and a under the DUT on the DUT side of the board. Solder should be
current limit resistor. A large area for component mounting provides applied here also. For prototype purposes, the tab can be thermally
flexibility and makes a multitude of circuit configurations possible. connected to the PCB metalization using thermal grease.
The PA44 should be reflowed to the PCB using a solder reflow
PARTS LIST furnace. If this is not abailable, a heat plate capable of solder reflow
temperatures may be used. or, though time consuming, the leads
may be soldered individually to the PCB with a soldering iron. In this
Part # Description Quantity case the use of thermal grease under the heat tab is reconnected
instead of solder for the thermal connection.
EVAL15 PC Board 1
OX7R105KWN 1F Ceramic Capacitor 1
CAUTION High voltages will be present. use
caution in handling and probing
when power is applied.
223
EVALUATION KIT
This data
5980 NORTH however, no responsibility
SHANNON ROAD is TUCSON,
assumed for ARIZONA
546-2739
EK13 REV. A MAY 1998 1998 Apex Microtechnology Corp.
224
PA45
FEATURES
LOW COST
HIGH SLEW RATE27V/s
HIGH POWER5A, 85W DISSIPATION
PATENTED
APPLICATIONS
MAGNETIC DEFLECTION TYPICAL APPLICATION
PA AUDIO +80
MOTOR DRIVE
NOISE CANCELLATION RC
CC
3
2
DESCRIPTION VI
4
7 RCL
8
The PA45 is a high power monolithic MOSFET operational RI PA45
amplifier that achieves performance levels unavailable even in 5 1
CF
many hybrid amplifier designs. Inputs are protected from
excessive common mode and differential mode voltages as
6
RD
YOKE C
well as static discharge. The safe operating area (SOA) has no 20
RF
second breakdown limitations and can be observed with all
type loads by choosing an appropriate current limiting resistor.
External compensation provides the user flexibility in choosing RS
2.5A 7Sec Retrace
optimum gain and bandwidth for the application.
Horizontal Deflection Coil Amplifiers
This circuit utilizes a beryllia (BeO) substrate to minimize
thermal resistance. Ultrasonically bonded aluminum wires Horizontal deflection amplifiers require both high speed and
provide reliable interconnections at all operating tempera- low distortion. The speed at which current can be changed in a
tures. The 8-pin TO-3 package is hermetically sealed and deflection coil is a function of the voltage available from the op
electrically isolated. The use of compressible isolation wash- amp. In this application an 80 volt power supply is used for the
ers and/or improper mounting torque will void the product retrace polarity to provide a 7 Sec retrace time, half of which is
warranty. required for amplifier slewing. This circuit can perform 15.75
KHz deflection in up to 50H coils at up to 5A p-p.
3 EXTERNAL CONNECTIONS
+VS
D1 Q2 OUTPUT
+VS CC1 CURRENT
Q24 2 SENSE
Q5 Q6 3
1
Q7 OUTPUT
Q3 DRIVE +IN 4
Q8 Q9 Q10 8 CC
TOP VIEW R CL
D2
D3
D4 RC 5
Q13 1 8
CC1 IN
D5 Q14 CURRENT
IN 2 Q15 6 OUTPUT
Q11 SENSE VS 7
5 DRIVE
Q12 7 CC2 CC2
Q16
4 Q17
+IN
PHASE
Q20 Q21 Q19 C C IS NPO RATED COMPENSATION
FOR FULL SUPPLY VOLTAGE. Gain CC RC
D7
VS 10 10pF 1K
6 1 68pF 1K
225
PA45 SPECIFICATIONS

SPECIFICATIONS
INPUT
BIAS CURRENT, vs supply 2 pA/V
OFFSET CURRENT, initial 200 pA
COMMON MODE REJECTION, DC 90 106 dB
GAIN
OPEN LOOP at 15Hz 94 106 dB
GAIN BANDWIDTH PRODUCT @ 1MHz RL = 500, CC = 10pF 4.5 MHz
POWER BANDWIDTH CC = 10pF, 130V p-p, RL = 8 66 kHz
PHASE MARGIN Full temp range, CC = 68pF, RL = 10 60
OUTPUT
VOLTAGE SWING IO = 5A VS10 VS8 V
SETTLING TIME to .1% 10V step, AV = 10 2 s
SLEW RATE CC = 10pF, RL = 8 27 V/s
CAPACITIVE LOAD AV = +1, CC = 68pF 10 nF
RESISTANCE , no load RCL = 0 150
POWER SUPPLY
CURRENT, quiescent 30 50 mA
THERMAL2
RESISTANCE, AC junction to case F > 60Hz 1.3 C/W
RESISTANCE, DC junction to case F < 60Hz 1.5 C/W
NOTES: 1. Unless otherwise noted TC = 25C, CC = 10pF, RC = 1K. DC input specifications are value given. Power supply voltage is
typical rating.
226
TYPICAL PERFORMANCE
GRAPHS PA45
POWER DERATING CURRENT LIMIT DRIFT ABSOLUTE CURRENT LIMIT

NORMALIZED CURRENT LIMIT, ILIM (X)

100 1.2
80 4
1.1
CURRENT LIMIT, I (A)

+I LIM
60 1.0
0
40 0.9
-I LIM
20 0.8
4
0 0.7
0 25 50 75 100 125 50 25 0 25 50 75 100 125 0.1 1.0 10
CASE TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C)
CURRENT LIMIT RESISTOR, R CL ()

0 200

120
100 CC = 10pF
CC = 10pF
45 80
CC = 10pF 60
PHASE, ()
80
40
CC = 68pF
C
90
40 CC = 68pF 20
CC = 68pF
R L = 8
135 10
RL = 1K 8
0 RL = 500 RL = 500 6
180 4
.1 1 10 100 1K 10K 100K 1M 10M .1 1 10 100 1K 10K 100K 1M 10M 10K 20K 40K 100K 200K 400K 1M
FREQUENCY, f (Hz) FREQUENCY, f (Hz) FREQUENCY, f (Hz)
VOLTAGE DROP FROM SUPPLY, VS VO (V) NORMALIZED QUIESCENT CURRENT, IQ(X)

1.000 50 2.0
AV = 10
.400 CC = 10pf
RL = 8
C
DISTORTION, THD (%)
SLEW RATE, SR(V/s)
5
.200 40
5
1.5
=
.100
C
C
T
No Load 25
.040 =
30 TC
.020 85W
.010 1.0
20
.004 5C
1W +12
.002 8 Load TC =
5W
.001 10 0.5
10 20 40 100 400 1K 2K 4K 10K 20K 0 20 40 60 80 10 30 50 70 90 110 130 150
FREQUENCY, f (Hz) COMPENSATION CAPACITANCE, C C (pF) TOTAL SUPPLY VOLTAGE, VS (V)

100 120 10
100 85C OUT

80 +VS 8
80
85C +OUT
60 60 6
25C +OUT
40
40 25C OUT
VS 4
20
20 0 2
10 100 1K 10K 100K 1M 10 100 1K 10K 100K 1M 0 2 4
227
OPERATING
PA45 CONSIDERATIONS
GENERAL SAFE OPERATING AREA (SOA)

Please read the General Operating Considerations section, The MOSFET output stage of this power operational ampli-
which covers stability, supplies, heat-sinking, mounting, cur- fier has limitations from its channel temperature.
rent limit, SOA interpretation, and specification interpretation. NOTE: The output is protected against transient flyback.
Additional information can be found in the application notes. However, for protection against sustained, high energy flyback,
For information on the package outline, heatsink, and mount- external fast-recovery diodes should be used.
ing hardware, consult the Accessories Information and Pack-
aging mechanical data section of the data book. SAFE OPERATING AREA
6.0
CURRENT LIMIT 4.0
OUTPUT CURRENT FROM +VS OR VS, (A)

Current limiting is achieved by developing 0.83V on the 10
20 0m
amplifiers current sense circuit by way of an internal tie to the 0m S
output drive (pin 8) and an external current sense line (pin 1). 2.0 DC DC S
A sense resistor RCL is used to relate this sense voltage to a ,T
current flowing from output drive. C
=
DC 85
1.0 ,T C
0.83 0.05 * ICL
RCL = 0.8
C
=
ICL 12
5
0.6 C
0.83
ICL =
RCL + 0.05 0.4
with a maximum practical value of 16. RCL is added to the
typical value of output resistance and affects the total possible
swing since it carries the load current. The swing reduction, VR 0.2
can be established VR = IOUT * RCL.
0.1
INPUT PROTECTION 4 6 8 10 20 40 60 100 200
The PA45 inputs are protected against common mode SUPPLY TO OUTPUT DIFFERENTIAL, VS -VO (V)
voltages up to the supply rails, differential voltages up to 16
volts and static discharge. Differential voltages exceeding 16
volts will be clipped by the protection circuitry. However, if
more than a few milliamps of current is available from the input
drive source, the protection circuitry could be destroyed. The
protection circuitry includes 300 ohm current limiting resistors
at each input. This security may be insufficient for severe
overdrive of the input. Adding external resistors to the applica-
tion which limits severe input overdrive current to 1mA, will
prevent damage.
STABILITY
The PA45 has sufficient phase margin when compensated
for unity gain to be stable with capacitive loads of at least 10nF.
However, the low pass circuit created by the sum-point (in)
capacitance and the feedback network may add phase shift
and cause instabilities. As a rule, the sum-point load resis-
tance (input and feedback resistors in parallel) should be 1k
ohm or less. Alternatively, use a bypass capacitor across the
feedback resistor. The time constant of the feedback resistor
and bypass capacitor combination should match the time
constant of the sum-point resistance and sum-point capaci-
tance.
The PA45 is externally compensated and performance can
be tailored to the application. The compensation network CC-
RC must be mounted closely to the amplifier pins 7 and 2 to
avoid noise coupling to these high impedance nodes.
without notice.
PA45U REV. B FEBRUARY 1998 1998 Apex Microtechnology Corp.
228
PA45DIE

OUTPUT CURRENT, continuous 5A
NOTE: Because of wafer probing test limitations, full power tests are not possible. Refer to parent
product data sheet PA45 for typical AC, DC and power performance specifications.
DC WAFER PROBED SPECIFICATIONS

PARAMETER1 TEST CONDITIONS MIN MAX UNITS
OFFSET VOLTAGE, initial VS = 20V to 75 V 25 mV

OFFSET VOLTAGE, vs. supply VS = 20V 25 V/V
BIAS CURRENT, initial VS = 20V 1 nA
OFFSET CURRENT, initial VS = 20V 1 nA
SUPPLY CURRENT, quiescent VS = 20V 26 mA
COMMON MODE REJECTION VCM = 45V, VS = 75V 84 dB
VOLTAGE SWING, positive VS = 50V, IO = 40mA 40 V
VOLTAGE SWING, negative VS = 50V, IO = 40mA 40 V C
ALARM, sink current VS = 20V to 75 V 90 A
ALARM, leakage VS = 20V to 75 V 1 A
NOTES: 1. Current limit, IQ pin, and shutdown verified as operational.
DIE 1 25
Recommended wire is 2 mil aluminum. All large bond pads
LAYOUT 2 24 must be used to avoid excessive current density in the die
23 metalization.
3
4
Pad Function Pad Function
5
22
11
21
1 Input 11-16 Output Drive
6
2 + Input 17-21 +VS
220 Mil 12
3* Alarm 22* IQ
5588 7 20
4* Shutdown 23 Compensation
13
5 NC 24 Compensation
8 19 6-10 VS 25 Current Limit Sense
14
9 * Pad 3 (Alarm) is tied to a switched current source. When an
18
15 over-temperature condition exits the current source turns on
10 and sinks 90A to VS. Pad 4 (Shutdown) will shut off the
16 17
output stage when at least 90A is pulled from pad 4 to any
220 Mil
voltage at least 3 volts less positive than +VS (ground, for
5588 example). When pad 3 is tied to pad 4 an over-temperature
condition will shut off the output stage until power is cycled
and the fault is removed. Normally pad 22 (IQ) is left open.
Thickness: 11 Mil (280) When pad 22 is tied to pad 23 the quiescent current in the
Backside: Silicon (no back metal) output stage is disabled. The result is lower quiescent but
Small Bond pads: 5 Mil sq (127) AI class C biasing of the output stage.
Large Bond pads: 5 x 11 Mil (127 x 280) AI
NOTE: Tie backside to VS through die attach medium. Rec-
ommended die attach material is either conductive
epoxy or silver-glass. Lowest thermal resistance will CAUTION PA45DIE is a MOSFET amplifier. ESD handling
be obtained with silver-glass. procedures must be observed.
however, FAXis(520)
ORDERS (520) 690-8601
229
NOTES:
230
PA46
FEATURES
PROGRAMMABLE IQ (5 or 50 mA MAX)
LOW COST
HIGH SLEW RATE27V/s
HIGH POWER5A, 75W DISSIPATION
APPLICATIONS
MAGNETIC DEFLECTION
PA AUDIO
MOTOR DRIVE
NOISE CANCELLATION
DESCRIPTION TYPICAL APPLICATION

+80
The PA46 is a high power monolithic MOSFET operational
amplifier that achieves performance levels unavailable even in
RC
many hybrid amplifier designs. Inputs are protected from 6 CC
excessive common mode and differential mode voltages as
well as static discharge. The safe operating area (SOA) has no VI
2 8
9 RCL
C
second breakdown limitations and can be observed with all RI PA46
1 5
type loads by choosing an appropriate current limiting resistor. 10 CF
External compensation provides the user flexibility in choosing 4
YOKE
optimum gain and bandwidth for the application. Class C RD
operation with resulting low quiescent current is pin program- 20
RF
mable. A shutdown input turns off the output stage.
This circuit utilizes a beryllia oxide (BeO) substrate to
minimize thermal resistance. The 10-pin power SIP package RS
2.5A 7Sec Retrace
is electrically isolated. Horizontal Deflection Coil Amplifiers
EQUIVALENT SCHEMATIC Horizontal deflection amplifiers require both high speed and
low distortion. The speed at which current can be changed in a
6 deflection coil is a function of the voltage available from the op
+VS
D1
amp. In this application an 80 volt power supply is used for the
Q2
retrace polarity to provide a 7 Sec retrace time, half of which is
Q24 3 required for amplifier slewing. This circuit can perform 15.75
SHDN Q5 Q6 KHz deflection in up to 50H coils at up to 5A p-p.
Q7 OUTPUT
Q3 DRIVE
Q8
7
Q9 Q10 5 EXTERNAL CONNECTIONS
D2
D3 IQ
D4
Q13 10 OUTPUT
CC1 Q14 RCL
IN D5 Q15 CURRENT
Q11 8
1 SENSE
Q12 9 CC2 RC CC
Q16
2 Q17
+IN
1 2 3 4 5 6 7 8 9 10
Q20 Q21 Q19
IN +IN SHDN VS OUT +VS IQ CC1 CC2 ILIM
D7
VS CC is NPO rated for full suppy voltage.
4
Phase Compensation
Gain CC RC
10 10pF 1K
1 68pF 1K
231
PA46 SPECIFICATIONS

SPECIFICATIONS
INPUT
BIAS CURRENT, vs supply 2 pA/V
OFFSET CURRENT, initial 200 pA
COMMON MODE REJECTION, DC 90 106 dB
GAIN
OPEN LOOP at 15Hz 94 106 dB
GAIN BANDWIDTH PRODUCT @ 1MHz RL = 500, CC = 10pF 4.5 MHz
POWER BANDWIDTH CC = 10pF, 130V p-p, RL = 8 66 kHz
PHASE MARGIN Full temp range, CC = 68pF, RL = 10 60
OUTPUT
VOLTAGE SWING IO = 5A VS10 VS8 V
SETTLING TIME to .1% 10V step, AV = 10 2 s
SLEW RATE CC = 10pF, RL = 8 27 V/s
CAPACITIVE LOAD AV = +1, CC = 68pF 10 nF
RESISTANCE , no load RCL = 0 150
POWER SUPPLY
CURRENT, quiescent 30 50 mA
CURRENT, quiescent, class C 5 mA
THERMAL2
RESISTANCE, AC junction to case F > 60Hz 1.3 C/W
RESISTANCE, DC junction to case F < 60Hz 1.7 C/W
NOTES: 1. Unless otherwise noted TC = 25C, CC = 10pF, RC = 1K. DC input specifications are value given. Power supply voltage is
typical rating.
The exposed substrate is beryllia (BeO). Do not crush, machine, or subject to temperatures in excess of 850C to avoid
generating toxic fumes.
232
TYPICAL PERFORMANCE
GRAPHS PA46
POWER DERATING CURRENT LIMIT DRIFT ABSOLUTE CURRENT LIMIT

NORMALIZED CURRENT LIMIT, ILIM (X)

100 1.2
80 4
1.1
CURRENT LIMIT, I (A)

+I LIM
60 1.0
0
40 0.9
-I LIM
20 0.8
4
0 0.7
0 25 50 75 100 125 50 25 0 25 50 75 100 125 0.1 1.0 10
CASE TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C)
CURRENT LIMIT RESISTOR, R CL ()

0 200

120
100 CC = 10pF
CC = 10pF
45 80
CC = 10pF 60
PHASE, ()
80
40
90 CC = 68pF
40 CC = 68pF CC = 68pF
20
R L = 8
C
135 10
RL = 1K 8
0 RL = 500 RL = 500 6
180 4
.1 1 10 100 1K 10K 100K 1M 10M .1 1 10 100 1K 10K 100K 1M 10M 10K 20K 40K 100K 200K 400K 1M
FREQUENCY, f (Hz) FREQUENCY, f (Hz) FREQUENCY, f (Hz)
VOLTAGE DROP FROM SUPPLY, VS VO (V) NORMALIZED QUIESCENT CURRENT, IQ(X)

1.000 50 2.0
AV = 10
.400 CC = 10pf
RL = 8
C
DISTORTION, THD (%)
SLEW RATE, SR(V/s)
5
.200 40
5
1.5
=
.100
C
C
T
No Load 25
.040 =
30 TC
.020 85W
.010 1.0
20
.004 5C
1W +12
.002 8 Load TC =
5W
.001 10 0.5
10 20 40 100 400 1K 2K 4K 10K 20K 0 20 40 60 80 10 30 50 70 90 110 130 150
FREQUENCY, f (Hz) COMPENSATION CAPACITANCE, C C (pF) TOTAL SUPPLY VOLTAGE, VS (V)

100 120 10
100 85C OUT

80 +VS 8
80
85C +OUT
60 60 6
25C +OUT
40
40 25C OUT
VS 4
20
20 0 2
10 100 1K 10K 100K 1M 10 100 1K 10K 100K 1M 0 2 4
233
OPERATING
PA46 CONSIDERATIONS
GENERAL SAFE OPERATING AREA (SOA)

Please read the General Operating Considerations section, The MOSFET output stage of this power operational ampli-
which covers stability, supplies, heat-sinking, mounting, cur- fier has limitations from its channel temperature.
rent limit, SOA interpretation, and specification interpretation. NOTE: The output is protected against transient flyback.
Additional information can be found in the application notes. However, for protection against sustained, high energy flyback,
For information on the package outline, heatsink, and mount- external fast-recovery diodes should be used.
ing hardware, consult the Accessories Information and Pack-
aging mechanical data section of the data book. SAFE OPERATING AREA
6.0
CURRENT LIMIT
4.0
OUTPUT CURRENT FROM +VS OR VS, (A)

Current limiting is achieved by developing 0.83V on the
10
amplifiers current sense circuit by way of an internal tie to the 0m
20 S
output drive (pin 8) and an external current sense line (pin 1). DC 0m
A sense resistor RCL is used to relate this sense voltage to a 2.0 DC S
,T
current flowing from output drive. C
DC =
85
0.83 0.05 * ICL ,T C
RCL = 1.0 C
=
ICL 0.8 12
5
0.6 C
0.83
ICL =
RCL + 0.05
0.4
with a maximum practical value of 16. RCL is added to the
typical value of output resistance and affects the total possible
swing since it carries the load current. The swing reduction, VR 0.2
can be established VR = IOUT * RCL.
INPUT PROTECTION 0.1
4 6 8 10 20 40 60 100 200
The PA46 inputs are protected against common mode
SUPPLY TO OUTPUT DIFFERENTIAL, VS -VO (V)
voltages up to the supply rails, differential voltages up to 16
volts and static discharge. Differential voltages exceeding 16
volts will be clipped by the protection circuitry. However, if
more than a few milliamps of current is available from the input SHUTDOWN
drive source, the protection circuitry could be destroyed. The Pin 3 (SHDN) will shut off the output stage when at least
protection circuitry includes 300 ohm current limiting resistors 90A is pulled from pin 3 to any voltage at least 3 volts less than
at each input. This security may be insufficient for severe +Vs (ground, for example).
overdrive of the input. Adding external resistors to the applica-
tion which limits severe input overdrive current to 1mA, will BIAS CLASS OPTION FOR LOWER
prevent damage.
QUIESCENT CURRENT
STABILITY Normally pin 7 (IQ ) is left open. When pin 7 is tied to pin 8
(CCI ) the quiescent current in the output stage is disabled.
The PA46 has sufficient phase margin when compensated This results in lower quiescent current, but also class C
for unity gain to be stable with capacitive loads of at least 10nF. biasing of the output stage.
However, the low pass circuit created by the sum-point (in)
capacitance and the feedback network may add phase shift
and cause instabilities. As a rule, the sum-point load resis-
tance (input and feedback resistors in parallel) should be 1k
ohm or less. Alternatively, use a bypass capacitor across the
feedback resistor. The time constant of the feedback resistor
and bypass capacitor combination should match the time
constant of the sum-point resistance and sum-point capaci-
tance.
be tailored to the application. The compensation network CC-
RC must be mounted closely to the amplifier pins 8 and 9 to
avoid noise coupling to these high impedance nodes.
This data
APEX sheet has been carefullyCORPORATION
MICROTECHNOLOGY checked and is believed to be reliable,
5980 NORTH however,
ROAD isTUCSON,
assumed forARIZONA
HOTLINE: without
1 (800) notice.
546-2739
PA46U REV. A APRIL 1998 1998 Apex Microtechnology Corp.
234
EVALUATION KIT FOR PA46
EK12
INTRODUCTION PARTS LIST

Fast and easy breadborading of circuits using the PA46 are
possible with the EK12 evaluation kit. The amplifier may be mounted Part # Description Quantity
vertically with the HS20 heat sink, or horizontally. Connections are
provided for required power supply bypassing and phase compen- HS20 Heatsink 1
sation components, as well as an optional current limit resistor. A EVAL14 PC Board 1
large area for component mounting provides flexibility and makes a
multitude of circuit configurations possible.
OX7R105KWN 1F Ceramic Capacitor 2
CAUTION Use thermal grease between the

power amplifier and the heat sink.
however, FAXis(520)
ORDERS (520) 690-8601
EK12 REV. A MAY 1998 1998 Apex Microtechnology Corp.
235
NOTES:
236
PA51 PA51A
FEATURES
SECOND SOURCEABLE OPA501, 8785
CLASS C OUTPUT Low Cost
LOW QUIESCENT CURRENT 2.6mA
APPLICATIONS
DC SERVO AMPLIFIER
MOTOR/SYNCHRO DRIVER TYPICAL APPLICATION
VALVE AND ACTUATOR CONTROL C1
DC OR AC POWER REGULATOR
+28V R3
DESCRIPTION 0/+5V R1 .1
The PA51 and PA51A are high voltage, high output current DAC
4.16K 0/6A
operational amplifiers designed to drive resistive, inductive PA51
and capacitive loads. Their complementary common emitter R2
output stage is the simple class C type optimized for low 2.5K R4
M
C
frequency applications where crossover distortion is not criti- .1
10V
cal. These amplifiers are not recommended for audio, trans-
ducer or deflection coil drive circuits. The safe operating area
(SOA) is fully specified and can be observed for all operating R5
MOTOR CURRENT IS A FUNCTION OF VIN .5
conditions by selection of user programmable current limiting
resistors. Both amplifiers are internally compensated for all PROGRAMMABLE TORQUE CIRCUIT
gain settings. For continuous operation under load, mounting
on a heatsink of proper rating is recommended. Do not use The linear relationship of torque output to current input of the
isolation washers! modern torque motor makes this simple control circuit ideal for
This hybrid integrated circuit utilizes thick film conductors, many material processing and testing applications. The sense
ceramic capacitors and semiconductor chips to maximize resistor develops a feedback voltage proportional to motor
reliability, minimize size and give top performance. Ultrasoni- current and the small signal properties of the Power Op Amp
cally bonded aluminum wires provide reliable interconnec- insure accuracy. With this closed loop operation, temperature
tions at all operating temperatures. The 8-pin TO-3 package is induced impedance variations of the motor winding are auto-
electrically isolated and hermetically sealed. The use of com- matically compensated.
pressible thermal washers and/or improper mounting torque
will void the product warranty. Please see General Operating EXTERNAL CONNECTIONS
Considerations.
EQUIVALENT SCHEMATIC R CL+

CL+
+VS
2 OUT
3 3
1
OUTPUT
Q1A +IN 4
Q1B
TOP VIEW
2
IN 5
Q3
8
4 CL R CL
6
7
A1 1 VS
N.C.
5
Q4
C1 8
Q6B
Q6A
237

TEMPERATURE, pin solder -10s 300C

2, 5
INPUT
BIAS CURRENT, initial TC = 25C 15 40 * 20 nA
BIAS CURRENT, vs. temperature Full temperature range .05 * nA/C
BIAS CURRENT, vs. supply TC = 25C .02 * nA/V
OFFSET CURRENT, vs. temperature Full temperature range .01 * nA/C
INPUT IMPEDANCE, common mode TC = 25C 250 * M
INPUT IMPEDANCE, differential TC = 25C 10 * M
COMMON MODE REJECTION, DC3 TC = 25C, VCM = VS 6V 70 110 80 * dB
GAIN
GAIN BANDWIDTH PRODUCT @ 1MHz TC = 25C, full load 1 * MHz
OUTPUT
VOLTAGE SWING3 TC = 25C, IO = 10A VS8 VS5 * * V
CURRENT TC = 25C 10 * A
SLEW RATE TC = 25C, RL = 6 1.0 2.6 * * V/s
CAPACITIVE LOAD, unity gain Full temperature range 1.5 * nF
CAPACITIVE LOAD, gain > 4 Full temperature range SOA *
POWER SUPPLY
VOLTAGE Full temperature range 10 28 36 * 34 40 V
CURRENT, quiescent TC = 25C 2.6 10 * * mA
THERMAL
2. The power supply voltage specified under the TYP rating applies unless otherwise noted as a test condition.
5. Full temperature range specifications are guaranteed but not 100% tested.
238
TYPICAL PERFORMANCE
GRAPHS PA51 PA51A

100

5.5 7
5.0 6

80 C R CL = .12
5
= 2 5
4.5 TC
+V O 5C
60 to 8
= 25 C
4
4.0 TC
+V O 85
40 to 3
5
3.5 2
= 2
PA51 PA51A TC
20 R CL = 0.3
3.0 O
V 1
0 2.5 0
0 25 50 75 100 125 150 0 2 4 6 8 10 -25 0 25 50 75 100 125
TEMPERATURE, T (C) OUTPUT CURRENT, IO (A) CASE TEMPERATURE, TC (C)

120 0 70
VS = 40V

100 30 50
80 60 36
PHASE, ()
RL = 8
60 90 26 C
40 120 19
20 150 13
RL = 3
0 180 9.7
20 210 7
PULSE RESPONSE COMMON MODE REJECTION BIAS CURRENT

8 120 2.5
GAIN = +1 RL = 5
6
100 2.2
4
80 1.9
2
0 60 1.6
2
40 1.3
4
20 1
6
8 0 .7
0 2 4 6 8 10 12 1 10 100 1K 10K .1M 1M -50 -25 0 25 50 75 100 125
TIME, (s) FREQUENCY, F (Hz) CASE TEMPERATURE, TC (C)
HARMONIC DISTORTION QUIESCENT CURRENT INPUT NOISE

10 1.6 100
VS = 36V
RL = 4
3 1.4 70
GAIN = 10
DISTORTION (%)
1W 50
1 =. 1.2
C
25
PO TC = 1 40
.3 5W 1.0 30
= TC = 125C
PO
.1 W .8 TC = -55C
50 20
=
PO .6
.03
.01 .4 10
30 100 300 1K 3K 10K 30K 20 30 40 50 60 70 80 10 100 1K 10K .1M
239
OPERATING
GENERAL
Please read the General Operating Considerations sec- 1. Under transient conditions, capacitive and dynamic* induc-
tion, which covers stability, supplies, heatsinking, mounting, tive loads up to the following maximums are safe:
current limit, SOA interpretation, and specification interpreta-
notes. For information on the package outline, heatsinks, and VS ILIM = 5A ILIM = 10A ILIM = 5A ILIM = 10A
40V 400F 200F 11mH 4.3mH
Mechanical Data section of the handbook.
35V 800F 400F 20mH 5.0mH
30V 1,600F 800F 35mH 6.2mH
SAFE OPERATING AREA (SOA) 25V 5.0mF 2.5mF 50mH 15mH
The output stage of most power amplifiers has three distinct 20V 10mF 5.0mF 400mH 20mH
limitations: 15V 20mF 10mF ** 100mH
1. The current handling capability of the transistor geometry
and the wire bonds. * If the inductive load is driven near steady state conditions,
2. The second breakdown effect which occurs whenever the allowing the output voltage to drop more than 8V below the
simultaneous collector current and collector-emitter voltage supply rail with ILIM = 10A or 15V below the supply rail with
exceeds specified limits. ILIM = 5A while the amplifier is current limiting, the inductor
3. The junction temperature of the output transistors. should be capacitively coupled or the current limit must be
lowered to meet SOA criteria.
10
** Second breakdown effect imposes no limitation but thermal
t=
7.0
limitations must still be observed.
1m
TC
=2
s
5.0 TH 5C
ER TC
MA =8 2. The amplifier can handle any EMF generating or reactive
L 5C
3.0 load and short circuits to the supply rail or shorts to common
T
t=
C =1 if the current limits are set as follows at TC = 85C.

2.0 25
5m
C
s
1.5
ste
1.0
45V 0.1A 1.3A
ady
0.7 40V 0.2A 1.5A

sta
0.5 35V 0.3A 1.6A

te
30V 0.5A 2.0A

0.3 25V 1.2A 2.4A
20V 1.5A 3.0A
0.2
5 7 10 15 20 30 40 50 70 80 15V 2.0A 4.0A
These simplified limits may be exceeded with further analysis
The SOA curves combine the effect of of all limits for this using the operating conditions for a specific application.
Power Op Amp. For a given application, the direction and
magnitude of the output current should be calculated or 3. The output stage is protected against transient flyback.
measured and checked against the SOA curves. This is simple However, for protection against sustained, high energy
for resistive loads but more complex for reactive and EMF flyback, external fast-recovery diodes should be used.
generating loads. The following guidelines may save exten-
sive analytical efforts. CURRENT LIMIT
tors, connected as shown in the external connection diagram.
The minimum value for RCL is .06 ohm, however for optimum
reliability it should be set as high as possible. Refer to the
General Operating Considerations section of the handbook
for current limit adjust details.
without notice.
240
PA51M



4 Output voltage, IO =10A VO 25C 18V RL = 1 10 V

4 Current limits ICL 25C 16V RCL = 1, RCL = .1 5 7.9 A
4 Stability/noise EN 25C 34V RL = 500, AV = +1, CL = 1.5nF 1 mV
4 Common-mode rejection CMR 25C 15V RL = 500, F = DC, VCM = 9V 70 dB
6 Output voltage, IO =10A VO 55C 18V RL = 1 10 V


100K
BURN IN CIRCUIT
+15V
1
100K 5 3 2 * These components are used to stabilize device due to
* U.U.T
1
** * 4 ** Input signals are calculated to result in internal power
6 8 20 dissipation of approximately 2.1W at case temperature
= 125C.
1
15V 7
however, FAXis(520)
ORDERS (520) 690-8601
PA51MU REV. G FEBRUARY 1998 1998 Apex Microtechnology Corp.
241
NOTES:
242
PA61 PA61A
FEATURES
LOW COST Class C output stage
LOW QUIESCENT CURRENT 3mA
APPLICATIONS
RF1 SENSE HI
MOTOR/SYNCRO DRIVER
VALVE AND ACTUATOR CONTROL +42V
RCL+
DC OR AC POWER REGULATOR 10V RIN1 OUT
FIXED FREQUENCY POWER OSCILLATOR DAC RW
RIN2 PA61
DESCRIPTION RCL
The PA61 and PA61A are high output current operational LOAD
amplifiers designed to drive resistive, inductive and capacitive
42V RF2 SENSE LO
loads. Their complementary emitter follower output stage is
the simple class C type and optimized for low frequency RTN C
applications where crossover distortion is not critical. These
RW
amplifiers are not recommended for audio, transducer or
deflection coil drive circuits above 1kHz or when distortion is FIGURE 1. PROGRAMMABLE POWER SUPPLY
critical. The safe operating area (SOA) is fully specified and WITH REMOTE SENSING
can be observed for all operating conditions by selection of
user programmable current limiting resistors. Both amplifiers TYPICAL APPLICATION
are internally compensated for all gain settings. For continu- Due to its high current drive capability, PA61 applications
ous operation under load, mounting on a heatsink of proper often utilize remote sensing to compensate IR drops in the
rating is recommended. wiring. The importance of remote sensing increases as accu-
This hybrid circuit utilizes thick film conductors, ceramic racy requirements, output currents, and distance between
capacitors, and semiconductor chips to maximize reliability, amplifier and load go up. The circuit above shows wire
minimize size, and give top performance. Ultrasonically resistance from the PA61 to the load and back to the local
bonded aluminum wires provide reliable interconnections at ground via the power return line. Without remote sensing, a
all operating temperatures. The 8-pin TO-3 package is electri- 7.5A load current across only 0.05 ohm in each line would
cally isolated and hermetically sealed. The use of compres- produce a 0.75V error at the load.
sible thermal washers and/or improper mounting torque voids With the addition of the second ratio matched RF/RIN pair and
the product warranty. Please see General Operating Consid- two low current sense wires, IR drops in the power return line
erations. become common mode voltages for which the op amp has a
very high rejection ratio. Voltage drops in the output and power
EQUIVALENT SCHEMATIC return wires are inside the feedback loop. Therefore, as long
3 as the Power Op Amp has the voltage drive capability to
overcome the IR losses, accuracy remains the same. Applica-
Q1A tion Note 7 presents a general discussion of PPS circuits.
Q1B
2
Q3 RCL+
4
A1 1 CL+
5 +VS 3
2
OUT
Q4 1 OUTPUT
4
+IN
C1 8 TOP VIEW
5
Q6B RCL
IN 8
Q6A 6
7 CL
VS
6 N.C.
243

INPUT VOLTAGE, differential VS3V
TEMPERATURE, pin solder-10s 300C

2
INPUT
OFFSET VOLTAGE, vs. temperature Specified temperature range 10 65 * 40 V/C
BIAS CURRENT, vs. temperature Specified temperature range 50 500 * * pA/C
BIAS CURRENT, vs. supply TC = 25C 10 * pA/V
OFFSET CURRENT, vs. temperature Specified temperature range 50 * pA/C
COMMON MODE VOLTAGE RANGE3 Specified temperature range VS5 VS3 * * V
COMMON MODE REJECTION, DC3 Specified temperature range 74 100 * * dB
GAIN
GAIN BANDWIDTH PRODUCT at 1MHz TC = 25C, full load 1 * MHz
OUTPUT
CURRENT TC = 25C 10 * A
SLEW RATE TC = 25C, RL = 6 1.0 2.8 * * V/s
CAPACITIVE LOAD, unit gain Full temperature range 1.5 * nF
CAPACITIVE LOAD, gain>4 Full temperature range SOA *
POWER SUPPLY
THERMAL
TEMPERATURE RANGE, case Meets full range specification 25 25 +85 * * * C
244
TYPICAL PERFORMANCE
GRAPHS PA61 PA61A

100 5.5 7

T = TC 5.0 6

80
5 RC
4.5 L = .1
2
60 C
25 4
4.0 =
TC 5C
40 5 to 8 3
3.5 =2 RCL = 0.3
TC
2
20
3.0 1
0 2.5 0
0 25 50 75 100 125 150 0 2 4 6 8 10 25 0 25 50 75 100 125
TEMPERATURE, TC (C) OUTPUT CURRENT, I O (A) CASE TEMPERATURE, TC (C)

0 80
120
VS = 40V

58
100 30
80 60 41
RL = 8
PHASE, ()
60 90 30 C
40 120 21
20 150 15
RL = 3
0 180 11
20 210 8
PULSE RESPONSE COMMON MODE REJECTION BIAS CURRENT

COMMON MODE REJECTION, CMR(dB)
NORMALIZED BIAS CURRENT, IB (X)
8 120 2.5
AV = +1 RL = 5
6 2.2
100
4
1.9
2 80
1.6
0 60
1.3
2
40
4 1.0
20 .7
6
8 0 .4
0 2 4 6 8 10 12 14 1 10 100 1K 10K .1M 1M 50 25 0 25 50 75 100 125
TIME, t (s) FREQUENCY, F (Hz) CASE TEMPERATURE, TC (C)
HARMONIC DISTORTION QUIESCENT CURRENT INPUT NOISE

10 1.6 100
VS = 36
3 RL = 4 70
1.4
AV = 10
DISTORTION, (%)
50
1 1W 1.2
=. 40
PO
TC = 125C
.3 1.0 30
5W
= T C = 25C 5C
.1 PO .8 5
W = 20
50 TC
=
.03 PO .6
.01 .4 10
30 100 300 1K 3K 10K 30K 20 30 40 50 60 70 80 90 10 100 1K 10K .1M
245
OPERATING
GENERAL 1. Under transient conditions, capacitive and dynamic* induc-

tive loads up to the following maximum are safe:
Please read the General Operating Considerations sec-
tion, which covers stability, supplies, heatsinking, mounting, CAPACITIVE LOAD INDUCTIVE LOAD
notes. For information on the package outline, heatsinks, and 45V 200 F 150 F 8mH 2.8mH
mounting hardware, consult the Accessory and Package 40V 400 F 200 F 11mH 4.3mH
Mechanical Data section of the handbook. 35V 800 F 400 F 20mH 5.0mH
30V 1600 F 800 F 35mH 6.2mH
SAFE OPERATING AREA (SOA) 25V 5.0mF 2.5mF 50mH 15mH
The output stage of most power amplifiers has 3 distinct 20V 10mF 5.0mF 400mH 20mH
limitations: 15V 20mF 10mF ** 100mH
1. The current handling capability of the transistor geometry
* If the inductive load is driven near steady state conditions,
and the wire bonds.
allowing the output voltage to drop more than 8V below the
supply rail with ILIM = 10A or 15V below the supply rail with
simultaneous collector current and collector-emitter voltage
ILIM = 5A while the amplifier is current limiting, the inductor
exceeds specified limits.
should be capacitively coupled or the current limit must be
3. The junction temperature of the output transistors.
lowered to meet SOA criteria.
10 ** Second breakdown effect imposes no limitation but thermal
INPUT CURRENT FROM +VS OR VS (A)
7 TC limitations must still be observed.

=2
t=
5 5C
TC
.5m
=8 2. The amplifier can handle any EMF generating or reactive

5C
s
t=
3 load and short circuits to the supply rail or shorts to common

TC
1m
t=
2 =1 if the current limits are set as follows at TC=85C.

25
ST
s
5m
C
1.5
EA
DY
1
ST
.7
AT
45V 0.1A 1.3A

.5
E
40V 0.2A 1.5A

.3 35V 0.3A 1.6A
.2 30V 0.5A 2.0A
.15 25V 1.2A 2.4A
.1 20V 1.5A 3.0A
8 10 12 15 20 25 30 40 50 60 70 80 90
15V 2.0A 4.0A
SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE VS VO (V)
These simplified limits may be exceeded with further analy-

The SOA curves combine the effect of all limits for this Power
sis using the operating conditions for a specific application.
Op Amp. For a given application, the direction and magnitude
of the output current should be calculated or measured and
3. The output stage is protected against transient flyback.
checked against the SOA curves. This is simple for resistive
loads but more complex for reactive and EMF generating
flyback, external fast-recovery diodes should be used.
loads. The following guidelines may save extensive analytical
efforts.
without notice.
PA61U REV. G DECEMBER 1997 1997 Apex Microtechnology Corp.
246
PA61M


3 Input BiasCurrent, IN IB 55C 32V VIN = 0 115 nA


4 Current Limits ICL 25C 15V RL = 6, RCL = 1 .56 .88 A

6 CommonMode Rejection CMR 55C 15V RL = 500, F = DC, VCM = 9V 74 dB

100K

1
100K burn in board.
5 3
2
6 20
1
15V
however, FAXis(520)
ORDERS (520) 690-8601
PA61MU REV. E FEBRUARY 1998 1998 Apex Microtechnology Corp.
247
NOTES:
248
PA81J PA82J SERIES

FEATURES
HIGH VOLTAGE OPERATION 150V (PA82J)
HIGH OUTPUT CURRENT 30mA (PA81J)
PROTECTED OUTPUT Thermal Shutoff
LOW BIAS CURRENT, LOW NOISE FET Input
APPLICATIONS
HIGH IMPEDANCE BUFFERS UP TO 140V
ELECTROSTATIC TRANSDUCER & DEFLECTION 70K
PROGRAMMABLE POWER SUPPLIES TO 145V +75V
BIOCHEMISTRY STIMULATORS
COMPUTER TO VACUUM TUBE INTERFACE .47
1mA
D/A
DESCRIPTION PA81J
70V
The PA80 series of high voltage operation amplifiers pro-
vides an extremely wide range of supply capability with two
overlapping products. High accuracy is achieved with a cascode .47
input circuit configuration. All internal biasing is referenced to
a zener diode. As a result, these models offer outstanding 75V
C
common mode and power supply rejection. The output stage HIGH VOLTAGE PROGRAMMABLE POWER SUPPLY
operates in the class A/B mode for best linearity. Internal
phase compensation assures stability at all gain settings
without external components. Fixed internal current limits TYPICAL APPLICATION
protect these amplifiers against a short circuit to common at The PA81 and 70K ohm resistor form a current to voltage
most supply voltages. For sustained high energy flyback, converter, accepting 1mA from a 12 bit current output digital
external fast recovery diodes should be used. A built-in ther- to analog converter. The power op amp contribution to the
mal shutoff circuit prevents destructive overheating under error budget is insignificant. At a case temperature of 70C,
most abnormal operating conditions. However, a heatsink the combination of voltage offset and bias errors amounts to
may be necessary to maintain the proper case temperature less than 31ppm of full scale range. Incorporation of the
under normal operating conditions.
optional offset trim can further reduce these errors to under
This hybrid circuit utilizes thick film resistors, ceramic ca-
pacitors and silicon semiconductors to maximize reliability, 9ppm.
minimize size and give top performance. Ultrasonically bonded
aluminum wires provide reliable interconnections at all operat- EQUIVALENT SCHEMATIC
ing temperatures. The 8-pin TO-3 package (see Package
Outlines) is hermetically sealed and isolated from the internal 4
circuits. The use of compressible thermal washers voids the 2

C1
warranty.
D1
3 Q3
EXTERNAL CONNECTIONS Q1 Q2
Q4
Q5
C3
C2 Q6
+VS
BAL 2 Q8 Q9
3 Q7
1 OUTPUT C5 C4 Q11
BAL Q12B
4 1
5 Q12A
TOP VIEW
IN Q13
5
Q14 Q17
8 Q16
6 6 Q15
+IN 7 N.C.
VS Q18
C6 D2
7
NOTE: Input offset trimpot optional.

Recommended value of 100K .
249
PA81J PA82J SPECIFICATIONS
PA81J PA82J
OUTPUT CURRENT, within SOA Internally Limited
POWER DISSIPATION, internal 11.5W 11.5W
INPUT VOLTAGE, differential 150V 300V
INPUT VOLTAGE, common mode VS VS
TEMPERATURE, pin solder - 10 sec 300C 300C
TEMPERATURE, junction 150C 150C
TEMPERATURE RANGE, storage 65 to +125C 65 to +125C
OPERATING TEMPERATURE RANGE, case 55 to +125C 55 to +125C
SPECIFICATIONS PA81J PA82J

2
INPUT
OFFSET VOLTAGE, initial TC = 25C 1.5 3 * * mV
OFFSET VOLTAGE, vs. temperature Full temperature range 10 25 * * V/C
BIAS CURRENT, initial TC = 25C 5 50 * * pA
OFFSET CURRENT, initial TC = 25C 2.5 50 * * pA
COMMON MODE REJECTION, DC VCM = 20V 110 * dB
GAIN
OPEN LOOP GAIN at 10Hz Full load 94 116 100 118 dB
UNITY GAIN BANDWIDTH TC = 25C 5 * MHz
POWER BANDWIDTH TC = 25C, full load 60 30 kHz
OUTPUT
VOLTAGE SWING2 TC = 25C, IPK VS5 * V
CURRENT, peak TC = 25C 30 15 mA
CURRENT, limit TC = 25C 50 25 mA
SLEW RATE4 TC = 25C 20 * V/s
CAPACITIVE LOAD AV = 1 10 * nF
POWER SUPPLY
VOLTAGE Full temperature range 32 75 75 70 150 150 V
CURRENT, quiescent TC = 25C 6.5 8.5 6.5 8.5 mA
THERMAL
RESISTANCE, AC, junction to case3 F > 60Hz 6 * C/W
RESISTANCE, DC, junction to case3 F < 60Hz 9 10 * * C/W
RESISTANCE, junction to air Full temperature range 30 * C/W
TEMPERATURE RANGE, shutdown 150 * C
NOTES: * The specification of PA82J is identical to the specification for PA81J in applicable column to the left.
4. On the PA81J and PA82J, signal slew rates at pins 5 and 6 must be limited to less than 1V/ns to avoid damage. When faster
waveforms are unavoidable, resistors in series with those pins, limiting current to 150mA will protect the amplifier from damage.
250
TYPICAL PERFORMANCE
GRAPHS PA81J PA82J
POWER DERATING CURRENT LIMIT BIAS CURRENT

12
NORMALIZED BIAS CURRENT, IB (X)

130 256

T = TC
10 120
64
110
8 16
100
6 4
90
4 1
T = TA 80
2 70 .25
0 60 .06
0 25 50 75 100 125 50 25 0 25 50 75 100 125 15 5 25 45 65 85 105
TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C)

120 0 300
PA82J
200

100 30
80 60
100 PA81J
PHASE, ()
60 90 C
60
40 120
20 150
30
0 180
20 210 15
1 10 100 1K 10K 100K 1M 10M 1 10 100 1K 10K .1M 1M 10M 25K 50K .1M .15M .25M.35M.5M
HARM0NIC DISTORTION SLEW RATE INPUT NOISE

3 20
1 1.0
NORMALIZED SLEW RATE
10
DISTORTION (%)
.3 C

0.9 +85
.1 PA81J TO 6
RL = 2K C
5 C
.03
40VRMS +2 5
0.8 2 4
PA82J
.01 RL = 10K
100VRMS
.003 0.7 2
100 300 1K 3K 10K 30K 100K 40 50 60 70 80 90 100 110 10 100 1K 10K .1M
FREQUENCY, F (Hz) POWER SUPPLY (% OF MAX) FREQUENCY, F (Hz)

COMMOM MODE REJECTION, CMR (dB)
300
140 140
PA82J
120 120 200
100 100
100 PA81J
PA 80
80 81 +VS
J/P
A8 60
60 2J 60
VS
40 40
30
20 20
0 0 15
251
OPERATING
PA81J PA82J CONSIDERATIONS
GENERAL THERMAL SHUTDOWN

Please read Application Note 1 , which covers stability, The thermal protection circuit shuts off the amplifier when
supplies, heatsinking, mounting, current limit, SOA interpreta- the substrate temperature exceeds approximately 150C. This
tion, and specification interpretation. Additional information allows heatsink selection to be based on normal operating
can be found in the application notes. For information on the conditions while protecting the amplifier against excessive
package outline, heatsinks, and mounting hardware, consult junction temperature during temporary fault conditions.
the Accessory and Package Mechanical Data section of the Thermal protection is a fairly slow-acting circuit and there-
handbook. fore does not protect the amplifier against transient SOA
violations (areas outside the TC = 25C boundary). It is de-
SAFE OPERATING AREA (SOA) signed to protect against short-term conditions that result in
high power dissipation within the amplifier. If the conditions
For the PA80J and PA81J, the combination of voltage
that cause thermal shutdown are not removed, the amplifier
capability and internal current limits mandate that the devices
will oscillate in and out of shutdown. This will result in high peak
are safe for all combinations of supply voltage and load. On the
power stresses, destroy integrity, and reduce the reliability of
PA82J, any load combination is safe up to a total supply of 250
the device.
volts. When total supply voltage equals 300 volts, the device
will be safe if the output current is limited to 10 milliamps or less.
This means that the PA82J used on supplies up to 125 volts will SINGLE SUPPLY OPERATION
sustain a short to common or either supply without danger. These amplifiers are suitable for operation from a single
When using supplies above 125 volts, a short to one of the supply voltage. The operating requirements do however, im-
supplies will be potentially destructive. When using single pose the limitation that the input voltages do not approach
supply above 250 volts, a short to common will be potentially closer than 10 volts to either supply rail. This is due to the
destructive. operating voltage requirements of the current sources, the
Safe supply voltages do not imply disregard for heatsinking. half-dynamic loads and the cascode stage. Refer to the
The thermal calculations and the use of a heatsink are required simplified schematics.Thus, single supply operation requires
in many applications to maintain the case temperature within the input signals to be biased at least 10 volts from either
the specified operating range of 0 to 70C. Exceeding this case supply rail. Figure 3 illustrates one bias technique to achieve
temperature range can result in an inoperative circuit due to this.
excessive input errors or activation of the thermal shutdown.
50K
+VS +210V
2.5K 50K
+210V +210V
50K +50/+200V
2.5/10V 2.5K PA82J
D/A
FIGURE 2. 50K
PROTECTION, FIGURE 3.
INDUCTIVE LOAD VS TRUE SINGLE
SUPPLY OPERATION
INDUCTIVE LOADS Figure 4 illustrates a very common deviation from true single
Two external diodes as shown in Figure 2, are required to supply operation. The availibility of two supplies still allows
protect these amplifiers against flyback (kickback) pulses ground (common) referenced signals, but also maximizes the
exceeding the supply voltage of the amplifier when driving high voltage capability of the unipolar output. This technique
inductive loads. For component selection, these external can utilize an existing low voltage system power supply and
diodes must be very quick, such as ultra fast recovery diodes does not place large current demands on that supply. The 12
with no more than 200 nanoseconds of reverse recovery time. volt supply in this case must supply only the quiescent current
Be sure the diode voltage rating is greater than the total of both of the PA81J, which is 8.5mA maximum. If the load is reactive
supplies. The diode will turn on to divert the flyback energy into or EMF producing, the low voltage supply must also be able to
the supply rails thus protecting the output transistors from absorb the reverse currents generated by the load.
destruction due to reverse bias. 50K
A note of caution about the supply. The energy of the flyback
pulse must be absorbed by the power supply. As a result, a +12V
transient will be superimposed on the supply voltage, the 0/5V
magnitude of the transient being a function of its transient D/A
impedance and current sinking capability. If the supply voltage 2K
PA81J
plus transient exceeds the maximum supply rating, or if the AC 0/125V
impedance of the supply is unknown, it is best to clamp the
output and the supply with a zener diode to absorb the FIGURE 4.
transient. NON-SYMMETRIC
SUPPLIES 130V
without notice.
PA81, 82U REV. F DECEMBER 1997 1997 Apex Microtechnology Corp.
252
PA83 PA83A
FEATURES
PROTECTED OUTPUT Thermal Shutoff
FULLY PROTECTED INPUT Up to 150V
APPLICATIONS
ELECTROSTATIC TRANSDUCERS & DEFLECTION 100K
PROGRAMMABLE POWER SUPPLIES UP TO 290V
ANALOG SIMULATORS +150V
GATED 3.57K
DESCRIPTION OSCILLATOR 5V A1
The PA83 is a high voltage operational amplifier designed PA83
for output voltage swings up to 145V with a dual () supply or
290V with a single supply. Its input stage is protected against
transient and steady state overvoltages up to and including the 150V
supply rails. High accuracy is achieved with a cascode input V * C
I=
circuit configuration. All internal biasing is referenced to a t C
zener diode fed by a FET constant current source. As a result, SIMPLE PIEZO ELECTRIC TRANSDUCER DRIVE
the PA83 features an unprecedented supply range and excel-
lent supply rejection. The output stage is biased in the class A/
B mode for linear operation. Internal phase compensation TYPICAL APPLICATION
assures stability at all gain settings without need for external While piezo electric transducers present a complex imped-
components. Fixed current limits protect these amplifiers ance, they are often primarily capacitive at useful frequencies.
against shorts to common at supply voltages up to 120V. For Due to this capacitance, the speed limitation for a given
operation into inductive loads, two external flyback pulse transducer/amplifier combination may well stem from limited
protection diodes are recommended. A built-in thermal shutoff current drive rather than power bandwidth restrictions. With its
circuit prevents destructive overheating. However, a heatsink drive capability of 75mA, the PA83 can drive transducers
may be necessary to maintain the proper case temperature having up to 2nF of capacitance at 40kHz at maximum output
under normal operating conditions. voltage. In the event the transducer may be subject to shock
This hybrid circuit utilizes beryllia (BeO) substrates, thick or vibration, flyback diodes, voltage clamps or other protection
(cermet) film resistors, ceramic capacitors and silicon semi- networks must be added to protect the amplifier from high
conductor chips to maximize reliability, minimize size and give voltages which may be generated.
top performance. Ultrasonically bonded aluminum wires pro-
vide reliable interconnections at all operating temperatures. EQUIVALENT SCHEMATIC
The 8-pin TO-3 package is hermetically sealed and electrically
isolated. The use of compressible thermal isolation washers 4
and/or improper mounting torque voids product warranty. 2
C1
Please see Application Note 1 General Operating Consider-
ations. D1
3 Q3
Q1 Q2
EXTERNAL CONNECTIONS Q4
Q5
C3
C2 Q6
+VS
BAL 2
3 Q8 Q9 Q7
OUTPUT C5 Q10
1 C4 Q11
BAL Q12B
4 1
5 Q12A
TOP VIEW
IN Q13
5
Q14 Q17
8 Q16
6 6 Q15
+IN 7 N.C.
NOTES:
1. Pin 8 not internally connected. VS Q18
C6 D2
2. Input offset trimpot optional. 7
Recommended value 100K .
253

POWER DISSIPATION, internal at TC = 25C1 17.5W
INPUT VOLTAGE, common mode 300V
TEMPERATURE, pin solder - 10s max (solder) 300C

2
INPUT
OFFSET VOLTAGE, initial TC = 25C 1.5 3 .5 1 mV
OFFSET VOLTAGE, vs. supply TC = 25C .5 .2 V/V
OFFSET CURRENT, vs. supply TC = 25C .01 * pA/V
INPUT CAPACITANCE Full temperature range 6 * pF
COMMON MODE REJECTION, DC Full temperature range 130 * dB
GAIN
OPEN LOOP GAIN at 10Hz TC = 25C, RL = 2K 96 116 * * dB
UNITY GAIN CROSSOVER FREQ. TC = 25C, RL = 2K 5 3 * MHz
POWER BANDWIDTH TC = 25C, RL = 10K 60 40 * kHz
OUTPUT
VOLTAGE SWING4, full load Full temp. range, IO = 75mA VS10 VS5 * * V
VOLTAGE SWING4 Full temp. range, IO = 15mA VS5 VS3 * * V
CURRENT, short circuit TC = 25C 100 * mA
SLEW RATE6 TC = 25C, RL = 2K 20 30 * * V/s
CAPACITIVE LOAD, unity gain Full temperature range 10 * nF
CAPACITIVE LOAD, gain > 4 Full temperature range SOA * F
SETTLING TIME to .1% TC = 25C, RL = 2K, 10V step 12 * s
POWER SUPPLY
VOLTAGE TC = 55C to +125C 15 150 150 * * * V
CURRENT, quiescent TC = 25C 6 8.5 * * mA
THERMAL
RESISTANCE, AC, junction to case5 F > 60Hz 3.8 * C/W
RESISTANCE, DC, junction to case F < 60Hz 6 6.5 * * C/W
RESISTANCE, case to air 30 * C/W
TEMP. RANGE, case (PA83/PA83A) Meets full range specification 25 +85 * * C
TEMP. RANGE, case (PA83J) Meets full range specification 0 70 C
2. The power supply voltage for all tests is the TYP rating, unless otherwise noted as a test condition.
6. Signal slew rates at pins 5 and 6 must be limited to less than 1V/ns to avoid damage. When faster waveforms are unavoidable,
resistors in series with those pins, limiting current to 150mA will protect the amplifier from damage.
254
TYPICAL PERFORMANCE
GRAPHS PA83 PA83A

POWER DERATING CURRENT LIMIT OUTPUT VOLTAGE SWING
30 250 8
25 200 7

C
20
6 25
150 =
C TC
5
15 5 2
=
100 TC C
10 4 85
=
PA83J TC
5 50
3
PA83/
0 PA83A 0 2
0 25 50 75 100 125 150 55 25 0 25 50 75 100 125 0 20 40 60 80 100 120
TEMPERATURE, T (C) CASE TEMPERATURE, TC (C) OUTPUT CURRENT IO (mA)
SMALL SIGNAL RESPONSE PHASE RESPONSE 300

POWER RESPONSE
120 0
RL = 2K RL = 2K | +VS | + | VS | = 300V
200

100 30
80 60 RL = 2K
100
PHASE, ()
60 90 C
60
40 120
| +VS | + | VS | = 100V
20 150
30
0 180
20 210 15
1 10 100 1K 10K 100K 1M 10M 1 10 100 1K 10K .1M 1M 10M 50K .1M .2M .3M .5M .7M 1M
PULSE RESPONSE SLEW RATE VS. SUPPLY INPUT NOISE

6 1.6 20
RL = 2K RL = 2K
OUTPUT VOLTAGE, VO (VP)
4 15
1.4
2 1.2 10
0 1.0 6
2 .8
4
4 .6
VIN = 5V, tr =100ns
6 .4 2
.5 0 .5 1 1.5 2.0 2.5 3.0 30 50 100 150 200 250 300 10 100 1K 10K .1M
TIME, t (s) TOTAL SUPPLY VOLTAGE, VS (V) FREQUENCY, F (Hz)

140 140 300

| +VS | + | VS | = 300V
120 120 200
100 100
100
80 80
+VS
60
60 60
| +VS | + | VS | = 100V
40 40
VS 30
20 20
0 0 15
255
OPERATING
GENERAL
Please read Application Note 1, which covers stability, 4. The output stage is protected against transient flyback.
supplies, heatsinking, mounting, current limit, SOA interpreta- However, for protection against sustained, high energy
tion, and specification interpretation. Additional information flyback, external fast-recovery diodes should be used.
can be found in the application notes. For information on the
package outline, heatsinks, and mounting hardware, consult
the Accessory and Package Mechanical Data section of the
handbook.
THERMAL SHUTDOWN PROTECTION
The thermal protection circuit shuts off the amplifier when
SAFE OPERATING AREA (SOA) the substrate temperature exceeds approximately 150C. This
allows heatsink selection to be based on normal operating
The bipolar output stage of this high voltage amplifier has conditions while protecting the amplifier against excessive
two distinct limitations. junction temperature during temporary fault conditions.
Thermal protection is a fairly slow-acting circuit and there-
1. The internal current limit, which limits maximum available fore does not protect the amplifier against transient SOA
output current. violations (areas outside of the TC = 25C boundary). It is
2. The second breakdown effect, which occurs whenever the designed to protect against short-term fault conditions that
simultaneous collector current and collector-emitter voltage result in high power dissipation within the amplifier. If the
exceed specified limits. conditions that cause thermal shutdown are not removed, the
200 amplifier will oscillate in and out of shutdown. This will result in
high peak power stresses, destroy signal integrity, and reduce
150 the reliability of the device.
OUTPUT CURRENT FROM +VS OR VS(mA)
INDUCTIVE LOADS
INTERNAL CURRENT LIMIT
100 Two external diodes as shown in Figure 1, are required to
protect these amplifiers against flyback (kickback) pulses
SE
t=
C
exceeding the supply voltages of the amplifier when driving

0.
O
5m
t=
N
D
70 inductive loads. For component selection, these external

s
1m
BR
diodes must be very quick, such as ultra fast recovery diodes

s
t=
EA
KD
5m with no more than 200 nanoseconds of reverse recovery time.

st
O
50 ea s
W
dy Be sure the diode voltage rating is greater than the total of both
N
st
at supplies. The diode will turn on to divert the flyback energy into
40 e the supply rails thus protecting the output transistors from
destruction due to reverse bias.
30 A note of caution about the supply. The energy of the flyback
pulse must be absorbed by the power supply. As a result, a
transient will be superimposed on the supply voltage, the
20 magnitude of the transient being a function of its transient
80 100 120 150 200 250 300 impedance and current sinking capability. If the supply voltage
INTERNAL VOLTAGE DROP, SUPPLY TO OUTPUT (V) plus transient exceeds the maximum supply rating or if the AC
The SOA curves combine the effect of these limits. For a impedance of the supply is unknown, it is best to clamp the
given application, the direction and magnitude of the output output and the supply with a zener diode to absorb the
transient.
current should be calculated or measured and checked against +VS
following guidelines may save extensive analytical efforts:
1. The following capacitive and inductive loads are safe:
VS C(MAX) L(MAX)
150V .7 F 1.5H
125V 2.0F 2.5H
100V 5.F 6.0H
75V 60F 30H VS
50V ALL ALL
FIGURE 1. PROTECTION, INDUCTIVE LOAD
2. Short circuits to ground are safe with dual supplies up to
120V or single supplies up to 120V.
3. Short circuits to the supply rails are safe with total supply
voltages up to 120V, e.g. 60V.
without notice.
PA83U REV. L DECEMBER 1997 1997 Apex Microtechnology Corp.
256
PA83M


3 Input Offset Voltage VOS 55C 150V VIN = 0, AV =100 5 mV

C



BURN IN CIRCUIT
+50V burn in board.
100K 5
* 1
power dissipation of approximately 2.1W at
** * 6
7 60
50V
however, FAXis(520)
ORDERS (520) 690-8601
257
NOTES:
258
PA84 PA84A PA84S

FEATURES
HIGH SLEW RATE 200V/s
FAST SETTLING TIME .1% in 1s (PA84S)
FULLY PROTECTED INPUT Up to 150v
APPLICATIONS
100K 50K
ELECTROSTATIC TRANSDUCERS & DEFLECTION +150V
4.7K
ANALOG SIMULATORS 10V 390pF
DAC
DESCRIPTION 10K
PA84
The PA84 is a high voltage operational amplifier designed for
output voltage swings up to 145V with a dual supply or 290V ......
INK JET ......
with a single supply. Two versions are available. The new CONTROL ......
PA84S, fast settling amplifier can absorb differential input over-
voltages up to 50V while the established PA84 and PA84A can 150V C
handle differential input overvoltages of up to 300V. Both
versions are protected against common mode transients and TYPICAL APPLICATION
overvoltages up to the supply rails. High accuracy is achieved The PA84 is ideally suited to driving ink jet control units
with a cascode input circuit configuration. All internal biasing is
(often a piezo electric device) which require precise pulse
referenced to a zener diode fed by a FET constant current
shape control to deposit crisp clear date or lot code information
source. As a result, the PA84 features an unprecedented supply
on product containers. The external compensation network
range and excellent supply rejection. The output stage is biased-
has been optimized to match the gain setting of the circuit and
on for linear operation. External phase compensation allows for
user flexibility in obtaining the maximum slew rate. Fixed current the complex impedance of the ink jet control unit. The combi-
limits protect these amplifiers against shorts to common at nation of speed and high voltage capabilities of the PA84 form
supply voltages up to 150V. For operation into inductive loads, ink droplets of uniform volume at high production rates to
two external flyback pulse protection diodes are recommended. enhance the value of the printer.
With the exception of PA84S, a built-in thermal shutoff circuit
prevents destructive overheating. However, a heatsink may be
necessary to maintain the proper case temperature under
4
normal operating conditions.
2
This hybrid integrated circuit utilizes a beryllia (BeO) sub- C1
strate, thick film resistors, ceramic capacitors and semicon-
D1
ductor chips to maximize reliability, minimize size and give top 3 Q3
performance. Ultrasonically bonded aluminum wires provide Q1 Q2
reliable interconnections at all operating temperatures. The 8- Q4
pin TO-3 package is hermetically sealed and electrically Q5
isolated. The use of compressible thermal isolation washers
8 Q6
and/or improper mounting torque will void the product war-
ranty. Please see General Operating Considerations. Q8 Q9 Q7
C5 * Q10
C4 Q11
Q12B
1
Q12A
EXTERNAL CONNECTION 5
* Q13 *
PHASE COMPENSATION
Q14 * Q17
Q16
+VS GAIN CC RC 6 *
BAL 2 Q15
3
1 OUT 1 10nF 200 Q18
C6 *
4 CC 10 500pF 2K * D2
BAL 100 50pF 20K 7

TOP VIEW 1000 none none
5 * NOTE: Not used for PA84S
RC NOTES:
IN 8 1. Phase Compensation required
6 for safe operation.
7 COMP
+IN 2. Input offset trimpot optional.
VS Recommended value 100K .
259
PA84 PA84A PA84S SPECIFICATIONS

POWER DISSIPATION, internal at TC = 25C2 17.5W
INPUT VOLTAGE, differential PA84/PA84A1 300V
INPUT VOLTAGE, differential PA84S 50V
INPUT VOLTAGE, common mode1 VS
TEMPERATURE, pins for 10s max (solder) 300C
SPECIFICATIONS PA84/PA84S PA84A
3
INPUT
OFFSET VOLTAGE, initial TC = 25C 1.5 3 .5 1 mV
OFFSET VOLTAGE, vs. temperature TC = 25 to +85C 10 25 5 10 V/C
OFFSET VOLTAGE, vs. supply TC = 25C .5 .2 V/V
OFFSET CURRENT, vs. supply TC = 25C .01 * pA/V
INPUT CAPACITANCE TC = 25 to +85C 6 * pF
COMMON MODE VOLTAGE RANGE5 TC = 25 to +85C VS10 VS8.5 * * V
COMMON MODE REJECTION, DC TC = 25 to +85C 130 * dB
GAIN
OPEN LOOP GAIN at 10Hz TC = 25C, RL = 120 * dB
OPEN LOOP GAIN at 10Hz. TC = 25C, RL = 3.5K 100 118 * * dB
GAIN BANDWIDTH PRODUCT@ 1MHz TC = 25C, RL = 3.5K, RC = 20K 75 * MHz
POWER BANDWIDTH, high gain TC = 25C, RL = 3.5K, RC = 20K 250 180 * kHz
POWER BANDWIDTH, low gain TC = 25C, RL = 3.5K, RC = 20K 120 * kHz
OUTPUT
VOLTAGE SWING5 TC = 25C, IO = 40mA VS7 VS3 * * V
VOLTAGE SWING5 TC = 25 to +85C, IO = 15mA VS5 VS2 * * V
CURRENT, short circuit TC = 25C 50 * mA
SLEW RATE, high gain TC = 25C, RL = 3.5K, RC = 20K 200 150 * V/s
SLEW RATE, low gain TC = 25C, RL = 3.5K, RC = 2K 125 * V/s
SETTLING TIME .01% at gain = 100 TC = 25C, RL = 3.5K PA84S 2 s
SETTLING TIME .1% at gain = 100 RC = 20K, VIN = 2V step ONLY 1 s
SETTLING TIME .01% at gain = 100 TC = 25C, RL = 3.5K PA84/84A 20 20 s
SETTLING TIME .1% at gain = 100 RC = 20K, VIN = 2V step 12 12 s
POWER SUPPLY
VOLTAGE TC = 55C to +125C 15 150 * * V
CURRENT, quiescent TC = 25C 5.5 7.5 * * mA
THERMAL
RESISTANCE, AC, junction to case6 TC = 55C to +125C, F > 60Hz 3.8 * C/W
RESISTANCE, DC, junction to case TC = 55C to +125C, F < 60Hz 6 6.5 * * C/W
RESISTANCE, case to air TC = 55C to +125C 30 * C/W
NOTES: * The specification of PA84A is identical to the specification for PA84/PA84S in applicable column to the left.
1. Signal slew rates at pins 5 and 6 must be limited to less than 1V/ns to avoid damage. When faster waveforms are unavoidable,
resistors in series with those pins, limiting current to 150mA will protect the amplifier from damage.
3. The power supply voltage for all tests is 150V, unless otherwise noted as a test condition.
5. +VS and VS denote the positive and negative power supply rail respectively.
260
TYPICAL PERFORMANCE
GRAPHS PA84 PA84A PA84S
POWER DERATING CURRENT LIMIT OPEN LOOP GAIN

RELATIVE OPEN LOOP GAIN, A(dB)

30 80 4
TC = 85C
25 70 2
CURRENT LIMIT, ILIM (mA)

RL = 3.5K
20 60 0
TC = 25C
15 50 2
10 40 4
TC = 25C
5 30 6
0 20 8
0 25 50 75 100 125 150 55 25 0 25 50 75 100 125 0 50 100 150 200 250 300
TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C) TOTAL SUPPLY VOLTAGE, VS (V)

120 5.0 300
VOLTAGE DROP SUPPLY, VSVO(V)
RC /
R C
RC
RC
200 C =

C /C
100 4.5 2
/C C
/C C
C =
150
0K
=2
RC
=2
80 4.0
2K

/C C
K 0
/50

0K
100
C
C
/5
RC
=
pF
25
/50 /10
60 3.5
00
20
/C C
=
pF
0p nF
50
TC 60
F
=
pF
40 3.0
20
C
5
0
2
=
/1
20 2.5 TC
0n
C 30
RL = 3.5K 5
F
0 2.0 =8
TC VS = 150V
20 1.5 15
1 10 100 1K 10K .1M 1M 10M 0 10 20 30 40 50 60 70 50K .1M .2M .3M .5M .7M 1M
FREQUENCY, F (Hz) OUTPUT CURRENT, IO (mA) FREQUENCY, F (Hz)
SLEW RATE VS. COMP SLEW RATE VS. SUPPLY INPUT NOISE
200 1.6 20
150 1.4 15
SLEW RATE (V/S)
100 1.2 10
70 7
1.0
50 5
.8
30 .6 3
RL = 3.5K RL = 3.5K
20 .4 2
200 500 1K 2K 5K 10K 20K 30 50 100 150 200 250 300 10 100 1K 10K .1M
EXT. COMPENSATION RESISTANCE, RC ( ) TOTAL SUPPLY VOLTAGE, VS (V) FREQUENCY, F (Hz)

140 140 300
120 120 200

150
100 100 100
80 80
50
60 60
30
40 40
VS = 150V
20 20 15
261
OPERATING
PA84 PA84A PA84S CONSIDERATIONS
GENERAL Thermal protection is a fairly slow-acting circuit and there-

fore does not protect the amplifier against transient SOA
Please read the General Operating Considerations sec- violations (areas outside of the TC = 25C boundary). It is
tion, which covers stability, supplies, heatsinking, mounting, designed to protect against short-term fault conditions that
current limit, SOA interpretation, and specification interpreta- result in high power dissipation within the amplifier. If the
tion. Additional information can be found in the application conditions that cause thermal shutdown are not removed, the
notes. For information on the package outline, heatsinks, and amplifier will oscillate in and out of shutdown. This will result in
mounting hardware, consult the Accessory and Package high peak power stresses, will destroy signal integrity, and
Mechanical Data section of the handbook. reduce the reliability of the device.
SAFE OPERATING AREA (SOA) OUTPUT PROTECTION

The bipolar output stage of this high voltage operational Two external diodes as shown in Figure 2, are required to
amplifier has two output limitations: protect these amplifiers against flyback (kickback) pulses
1. The internal current limit which limits maximum available exceeding the supply voltages of the amplifier when driving
output current. inductive loads. For component selection, these external
2. The second breakdown effect, which occurs whenever the diodes must be very quick, such as ultra fast recovery diodes
simultaneous collector current and collector-emitter voltage with no more than 200 nanoseconds of reverse recovery time.
exceeds specified limits. Be sure the diode voltage rating is greater than the total of both
supplies. The diode will turn on to divert the flyback energy into
50 the supply rails thus protecting the output transistors from

ST t=
t= 1m destruction due to reverse bias.
EA 5m
D s
s A note of caution about the supply. The energy of the flyback
Y
40
ST pulse must be absorbed by the power supply. As a result, a
AT transient will be superimposed on the supply voltage, the
E
magnitude of the transient being a function of its transient
35
impedance and current sinking capability. If the supply voltage
plus transient exceeds the maximum supply rating or if the AC
30 impedance of the supply is unknown, it is best to clamp the
output and the supply with a zener diode to absorb the
transient.
25
FIGURE 1. PROTECTIVE, +VS
INDUCTIVE LOAD
SAFE OPERATING AREA CURVES
20
150 170 200 250 300
SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE (V)
The SOA curves combine the effect of these limits. For a

given application, the direction and magnitude of the output
current should be calculated or measured and checked against VS
the SOA curves. This is simple for resistive loads but more STABILITY
following guidelines may save extensive analytical efforts: Due to its large bandwidth the PA84 is more likely to oscillate
than lower bandwidth Power Operational Amplifiers such as
1. The following capacitive and inductive loads are safe: the PA83 or PA08. To prevent oscillations, a reasonable phase
VS C(MAX) L(MAX) margin must be maintained by:
150V 1.2F .7H
1. Selection of the proper phase compensation capacitor and
125V 6.0F 25H
resistor. Use the values given in the table under external
100V 12F 90H connections and interpolate if necessary. The phase mar-
75V ALL ALL gin can be increased by using a large capacitor and a
2. Short circuits to ground are safe with dual supplies up to smaller resistor than the slew rate optimized values listed in
150V or single supplies up to 150V. the table. The compensation capacitor may be connected to
3. Short circuits to the supply rails are safe with total supply common (in lieu of +VS) if the positive supply is properly
voltages up to 150V (i.e. 75V). bypassed to common. Because the voltage at pin 8 is only
a few volts below the positive supply, this ground connec-
THERMAL SHUTDOWN PROTECTION tion requires the use of a high voltage capacitor.
PA84S does not have this feature. 2. Keeping the external sumpoint stray capacitance to ground
The thermal protection circuit shuts off the amplifier when at a minimum and the sumpoint load resistance (input and
the substrate temperature exceeds approximately 150C. This feedback resistors in parallel) below 500. Larger sumpoint
allows heatsink selection to be based on normal operating load resistance can be used with increased phase compen-
conditions while protecting the amplifier against excessive sation (see 1 above).
junction temperatures during temporary fault conditions. 3. Connecting the amplifier case to a local AC common thus
preventing it from acting as an antenna.
without notice.
262
PA84M



C
4 Output Voltage, IO = 28.6mA VO 25C 150V RL = 5K 143 V
4 Slew Rate SR 25C 150V RL = 5K, CC = 50pF 100 600 V/s
4 Open Loop Gain AOL 25C 150V RL = 5k, F = 10Hz 100 dB
4 Common Mode Rejection CMR 25C 32.5V RL = 5k, F = DC, VCM = 22.5V 90 dB

6 Common Mode Rejection CMR -55C 32.5V RL = 5k, F = DC, VCM = 22.5V 90 dB

5 Stability/Noise EN 125C 150V RL = 5 , AV = 1, CL = 10nF 1 mV
5 Common Mode Rejection CMR 125C 32.5V RL = 5k, F = DC, VCM = 22.5V 90 dB

BURN IN CIRCUIT
+50V burn in board.
100K 5
* 1 power dissipation of approximately 2.1W at
** * 6
7 60
50V
however, FAXis(520)
ORDERS (520) 690-8601
263
NOTES:
264
PA85 PA85A
FEATURES
HIGH VOLTAGE 450V (225V)
HIGH SLEW RATE 1000V/S
HIGH OUTPUT CURRENT 200mA
APPLICATIONS
HIGH VOLTAGE INSTRUMENTATION PATENTED
PIEZO TRANSDUCER EXCITATION
ELECTROSTATIC TRANSDUCERS & DEFLECTION TYPICAL APPLICATION
Dynamic focusing is the active correction of focusing volt-
DESCRIPTION age as a beam traverses the face of a CRT. This is necessary
in high resolution flat face monitors since the distance be-
The PA85 is a high voltage, high power bandwidth MOSFET
operational amplifier designed for output currents up to 200mA. tween cathode and screen varies as the beam moves from the
center of the screen to the edges. PA85 lends itself well to this
Output voltages can swing up to 215V with a dual supply and
up to +440 volts with a single supply. The safe operating area function since it can be connected as a summing amplifier with
inputs from the nominal focus potential and the dynamic
(SOA) has no second breakdown limitations and can be
observed with all types of loads by choosing an appropriate correction. The nominal might be derived from a potentiom-
current limiting resistor. High accuracy is achieved with a
eter, or perhaps automatic focusing circuitry might be used to
generate this potential. The dynamic correction is generated
C
cascode input circuit configuration. All internal biasing is
from the sweep voltages by calculating the distance of the
referenced to a bootstrapped zener-MOSFET current source.
As a result, the PA85 features an unprecedented supply range beam from the center of the display.
and excellent supply rejection. The MOSFET output stage is
biased on for linear operation. External compensation pro- R IN1 RF
DC
vides user flexibility. FOCUS
This hybrid circuit utilizes thick film (cermet) resistors, ce- +225V
X SWEEP R CL
ramic capacitors and silicon semiconductor chips to maximize SAMPLE
R IN2
reliability, minimize size and give top performance. Ultrasoni-
z = x2 + y2
cally bonded aluminum wires provide reliable interconnec- TO
PA85 FOCUS
tions at all operating temperatures. The 8-pin TO-3 package is Y SWEEP GRID
hermetically sealed and electrically isolated. The use of com- SAMPLE
pressible isolation washers voids the warranty.
225V
3 EXTERNAL CONNECTIONS
+VS
D1
CL RCL PHASE COMPENSATION
Q1 Q2 Q4 +Vs Gain CC RC
D23 Q9 2
Q8 3 1 68pF 100
COMP CL
20 10pF 330
7 8
Q12
2
+IN 4
1 OUT 100 3.3pF 0
Q6 Q7
IN +IN CC RATED FOR FULL
Q11 TOP VIEW SUPPLY VOLTAGE
5 4 1
Q10A Q10B OUT
5 COMP
IN 8
Q17
Q18 CC
Q13 6 7
Q16 Vs
COMP
RC
D2
VS
6
265

OUTPUT CURRENT, continuous within SOA 200mA
POWER DISSIPATION, continuous @ TC = 25C2 30W
1
INPUT
OFFSET VOLTAGE, initial .5 2 .25 .5 mV
OFFSET VOLTAGE, vs. time 75 * V/kh
BIAS CURRENT, initial3 5 50 3 10 pA
OFFSET CURRENT, initial3 10 100 3 30 pA
COMMON MODE VOLTAGE RANGE4 VS12 * V
COMMON MODE REJECTION, DC VCM = 90V 90 110 * * dB
NOISE 100kHz BW, RS = 1K, CC = 10pf 1 * Vrms
GAIN
OPEN LOOP, @ 15Hz RL = 2K, CC = OPEN 96 111 * * dB
GAIN BANDWIDTH PRODUCT at 1MHz RL = 2K, CC = 3.3pf 100 * MHz
POWER BANDWIDTH CC = 10pf 300 * kHz
CC = 3.3pf 500 * kHz
OUTPUT
VOLTAGE SWING4 IO = 200mA Vs10 Vs6.5 * * V
VOLTAGE SWING4 IO = 75mA V8.5 Vs6.0 * * V
VOLTAGE SWING4 IO = 20mA V8.0 Vs5.5 * * V
CURRENT, continuous TC = 85C 200 * mA
SLEW RATE, AV = 20 CC = 10pf 400 * V/s
SLEW RATE, AV = 100 CC = OPEN 1000 700 * V/s
CAPACITIVE LOAD, AV = +1 Full temperature range 470 * * pf
SETTLING TIME to .1% CC = 10pf, 2V step 1 * s
RESISTANCE, no load RCL = 0 50 *
POWER SUPPLY
VOLTAGE6 Full temperature range 15 150 225 * * * V
CURRENT, quiescent 21 25 * * mA
THERMAL
RESISTANCE, AC, junction to case5 Full temperature range, F > 60Hz 2.5 * C/W
RESISTANCE, DC, junction to case Full temperature range, F < 60Hz 4.2 * C/W
1. Unless otherwise noted: TC = 25C, compensation = CC = 68pF, RC = 100. DC input specifications are value given. Power
supply voltage is typical rating.
to achieve high MTTF. Ratings apply only to output transistors. An additional 10W may be dissipated due to quiescent power.
6. Derate max supply rating .625 V/C below 25C case. No derating needed above 25C case.
CAUTION
266
TYPICAL PERFORMANCE
GRAPHS PA85 PA85A

POWER DERATING PHASE RESPONSE QUIESCENT CURRENT
40 0 1.20
32 45 1.15
OUTPUT STAGE
90 1.10 C
PHASE, ()
C C = 68pF
24 125
C C = 10pF TC=
135 1.05 TC = 25C
16
180 1.00
TC = 55C
8
225 .95
C C = 3.3pF
0 270 .90
0 25 50 75 100 125 150 .2M 1M 10M 40M 0 100 200 300 400 450
CASE TEMPERATURE, TC (C) FREQUENCY F (Hz) TOTAL SUPPLY VOLTAGE, VS (V)
VOLTAGE DROP FROM SUPPLY, V S VO (V)

120 10 500

100
9
C C = 3.3pF 250
CC
80
5
8
12
=3
CC
=
.3p
60
C
C
T
=1
C C = 10pF 125
f
7
CC
0p
40 100
= 25
C
f
=6
TC 75
6
8p
20
55C
TC =
f
C C = 68pF 50
0 5
R L = 2K
20 4 25
10 100 1K 10K .1M 1M 10M 20M 0 100 200 250 50K 100K 200K 500K 1M 2M 5M
FREQUENCY, F (Hz) OUTPUT CURRENT, I O (mA) FREQUENCY, F (Hz)
SLEW RATE HARMONIC DISTORTION INPUT NOISE VOLTAGE

1000 .05 20
AV = 30
.03 PO = 15W 15
CC = 10pf
SLEW RATE, (V/ S)
DISTORTION, (%)
500 RL = 1K 10
.01
7
.005 5
200 .003
3
100 .001 2
0 15 30 45 60 75 90 10 100 1K 10K 100K 10 100 1K 10K 100K
EXT. COMPENSATION CAPACITOR, C C (pF) FREQUENCY, F (Hz) FREQUENCY, F (Hz)
COMMON MODE REJECTION POWER SUPPLY REJECTION CURRENT LIMIT

140 140 500

C C = 10pF
CURRENT LIMIT, I LIM (mA)
120 120 300
200
100 100
80 80 100
60 60
50
40 40
20 20 20
1K 10K 100K 1M 10M 1 10 100 1K 10K .1M 1M 1 2 5 10 20 30
FREQUENCY, F (Hz) FREQUENCY, F (Hz) RESISTOR VALUE, R CL ( )
267
OPERATING
GENERAL
Please read the General Operating Considerations sec- power dissipation listed elsewhere in the specification since
tion, which covers stability, supplies, heatsinking, mounting, the quiescent power dissipation is significant compared to the
current limit, SOA interpretation, and specification interpreta- total.
notes. For information on the package outline, heatsinks, and INPUT PROTECTION
mounting hardware, consult the Accessory and Package Although the PA85 can withstand differential voltages up to
Mechanical Data section of the handbook. 25V, additional external protection is recommended. Since
CURRENT LIMIT the PA85 is a high speed amplifier, low leakage, low capaci-
tance JFETs connected as diodes are recommended (e.g.
For proper operation, the current limit resistor (RCL) must be 2N4416, Q1-Q4 in Figure 2). The differential input voltage will
connected as shown in the external connection diagram. The be clamped to 1.4V. This is sufficient overdrive to produce
minimum value is 1.4 ohm, however for optimum reliability the maximum power bandwidth.
resistor value should be set as high as possible. The value is
calculated as follows; with the maximum practical value of 30 POWER SUPPLY PROTECTION
ohms. Unidirectional zener diode transient suppressors are recom-
.7
RCL = mended as protection on the supply pins. The zeners clamp
ILIM - .016 transients to voltages within the power supply rating and also
clamp power supply reversals to ground. Whether the zeners
SAFE OPERATING AREA (SOA) are used or not, the system power supply should be evaluated
The MOSFET output stage of this power operational ampli- for transient performance including power-on overshoot and
fier has two distinct limitations: power-off polarity reversals as well as line regulation.
1. The current handling capability of the MOSFET geometry Conditions which can cause open circuits or polarity rever-
and the wire bonds. sals on either power supply rail should be avoided or protected
2. The junction temperature of the output MOSFETs. against. Reversals or opens on the negative supply rail is
known to induce input stage failure. Unidirectional transzorbs
NOTE: The output stage is protected against transient flyback.
prevent this, and it is desirable that they be both electrically and
However, for protection against sustained, high energy flyback,
physically as close to the amplifier as possible.
external fast-recovery diodes should be used.
STABILITY
SAFE OPERATING CURVES
The safe operating area curves define the maximum addi-
be tailored to the application. Use the graphs of small signal
tional internal power dissipation the amplifier can tolerate
response and power response as a guide. The compensation
when it produces the necessary output to drive an external
capacitor CC must be rated at 500V working voltage. An NPO
load. This is not the same as the absolute maximum internal
capacitor is recommended. The compensation network CCRC
500
must be mounted closely to the amplifier pins 7 and 8 to avoid
spurious oscillation.
300 20
0m
S 10
0m
200 S +VS
DC
,T
Z1
DC
C =
25
100 ,T C
C = IN
5 3
85
DC C
,T Q1 Q3
C = PA85
50 12
5 Q2 Q4
C
+IN 6
4
30
FIGURE 2 Z2
20
OVERVOLTAGE
PROTECTION VS

10
25 50 75 100 125 250 500
SUPPLY TO OUTPUT DIFFERENTIAL, VS VO (V)
without notice.
PA85U REV. L JANUARY 1998 1998 Apex Microtechnology Corp.
268
PA85M
SG PARAMETER*** SYMBOL TEMP. POWER TEST CONDITIONS MIN MAX UNITS
1 Quiescent current IQ 25C 150V VIN = 0, AV = 100 25 mA



150V 10
2
2
Input bias current, IN
Input offset current
IB
IOS
125C
125C 150V
VIN = 0
VIN = 0 10
nA
nA
C
4 Output voltage, IO = 70mA VO 25C 150V RL = 2K 141 V
4 Current limits ICL 25C 50V RCL = 10, RL = 200 60 112 mA
4 Stability/noise EN 25C 150V CC = 68pF, RC = 100, AV = +1, CL = 470pF 1 mV
4 Slew rate SR 25C 150V RL = 2K, AV = 100, CC = OPEN 400 V/s
4 Open loop gain AOL 25C 150V RL = 2K, F = 15Hz, CC = OPEN 96 dB
4 Common-mode rejection CMR 25C 150V F = DC, VCM = 90V 90 dB


100K
BURN IN CIRCUIT
* These components are used to stabilize device due to
+15V
2.7
100K 5 3 2 ** Input signals are calculated to result in internal power
* 1 dissipation of approximately 2.1W at case temperature
U.U.T
8 = 125C.
** * 4
6 7 20
*** An additional test is performed manually at
100 68pF TC = 25C which stresses power supply, common
15V mode range and output swing to 225V (450V total).
however, FAXis(520)
ORDERS (520) 690-8601
PA85MU REV. A FEBRUARY 1998 1998 Apex Microtechnology Corp.
269
NOTES:
270
PA88 PA88A
FEATURES
HIGH VOLTAGE 450V (225V)
LOW QUIESCENT CURRENT 2mA
HIGH OUTPUT CURRENT 100mA
APPLICATIONS PATENTED
PIEZOELECTRIC POSITIONING
ELECTROSTATIC TRANSDUCERS
PROGRAMMABLE POWER SUPPLIES UP TO 440V TYPICAL APPLICATION
RF
DESCRIPTION
+V S
The PA88 is a high voltage, low quiescent current MOSFET CC
operational amplifier designed for output currents up to 100mA.
Output voltages can swing up to 215V with a dual supply and R IN
up to +440 volts with a single supply. The safe operating area PIEZO DRIVE
(SOA) has no second breakdown limitations and can be PA88 V OUT
C
observed with all types of loads by choosing an appropriate
current limiting resistor. High accuracy is achieved with a COMPUTER
cascode input circuit configuration. All internal biasing is FOCUS
COMMAND
referenced to a bootstrapped zener-MOSFET current source. VOLTAGE
As a result, the PA88 features an unprecedented supply range V S
and excellent supply rejection. The MOSFET output stage is
biased on for linear operation. External compensation pro- LOW POWER, PIEZOELECTRIC POSITIONING
vides user flexibility. Piezo positioning may be applied to the focusing of seg-
This hybrid circuit utilizes beryllia (BeO) substrates, thick mented mirror systems. The composite mirror may be com-
film resistors, ceramic capacitors and semiconductor chips to posed of hundreds of elements, each requiring focusing under
maximize reliability, minimize size and give top performance. computer control. In such complex systems the PA88s advan-
Ultrasonically bonded aluminum wires provide reliable inter- tage of low quiescent power consumption reduces the costs of
connections at all operating temperatures. The 8-pin TO-3 power supplies and cooling, while providing the interface
package is hermetically sealed and electrically isolated. The between the computer and the high voltage drive to the piezo
use of compressible thermal isolation washers and/or im- positioners.
proper mounting torque will void the product warranty. Please
see General Operating Considerations.
3 CL R CL PHASE COMPENSATION
+VS +Vs
D1 3 2
GAIN CC RC
Q4 1 OUT 1 68pf 100

Q1 Q2 D19 Q9 +IN 4 10 33pf 100
Q8
COMP 20 15pf 100
CL
7 8 TOP VIEW 100 3.3pf
2
Q12
Q6 Q7 5 COMP
IN + IN IN 8
Q11 R CL = .7
5 4 1 ILIM
6 7 CC
OUT
Q10A Q10B Vs
COMP
Q17
CC RATED FOR FULL
RC SUPPLY VOLTAGE
Q13 Q18
Q16
D2
VS
6
271

OUTPUT CURRENT, source, sink See SOA

1
INPUT
OFFSET CURRENT, initial3 2.5 100 3 20 pA
COMMON MODE VOLTAGE RANGE4 VS12 * V
COMMON MODE REJECTION, DC VCM = 90V 90 110 * * dB
NOISE 100kHz BW, RS = 1K, CC = 15pf 2 * Vrms
GAIN
OPEN LOOP, @ 15Hz RL = 2K, CC = OPEN 96 111 * * dB
GAIN BANDWIDTH PRODUCT at 1MHz RL = 2K, CC = 15pf, RC = 100 2.1 * MHz
POWER BANDWIDTH RL = 2K, CC = 15pf, RC = 100 6 * kHz
OUTPUT
VOLTAGE SWING4 IO = 100mA VS12 VS9.8 * * V
VOLTAGE SWING4 Full temp. range, IO = 75mA VS8.5 VS7.5 * * V
VOLTAGE SWING4 Full temp. range, IO = 20mA VS8.0 VS5.2 * * V
CURRENT, continuous TC = 85C 100 * mA
SLEW RATE, AV = 20 CC = 15pf, RC = 100 8 * V/s
SLEW RATE, AV = 100 CC = OPEN 30 * V/s
CAPACITIVE LOAD, AV = +1 Full temperature range 470 * pf
SETTLING TIME to .1% CC = 15pf, RC = 100, 2V step 10 * s
RESISTANCE, no load RCL = 0 100 *
POWER SUPPLY
VOLTAGE6 See note 6 15 200 225 * * * V
CURRENT, quiescent, 1.7 2 * * mA
THERMAL
RESISTANCE, AC, junction to case5 Full temperature range, F > 60Hz 5.0 * C/W
RESISTANCE, DC, junction to case Full temperature range, F < 60Hz 8.3 * C/W
1. Unless otherwise noted: TC = 25C, compensation = CC = 68pF, RC = 100. DC input specifications are value given. Power
supply voltage is typical rating.
6. Derate max supply rating .625 V/C below 25C case. No derating needed above 25C case.
CAUTION
272
TYPICAL PERFORMANCE
GRAPHS PA88 PA88A

15 0 2.5
QUIESCENT CURRENT, I Q (mA)

12.5 30 2.25
C C = 3.3pF 5C
T = TC
60 TC = 12
10 C C = 33pF 2.0
PHASE, ()
C C = 68pF
90 C
7.5 C C = 68pF 1.75 TC = 25
120 5C
TC = -5
5 T = TA 1.5
150
2.5 C C = 33pF 1.25

180
C C = 3.3pF
0 210 1.0
0 25 50 75 100 125 150 1 10 100 1K 10K .1M 1M 10M 0 100 200 300 450
TEMPERATURE, T (C) FREQUENCY, F (Hz) TOTAL SUPPLY VOLTAGE, VS (V)

120 12 500

C
100
CC
5
C
12
10
CC
C C = 3.3pF
=
85 250
CC
=
80 =
3.3
C
CC
=
T
TC
pf
15
C C = 15pF
=
C
33
8
pf
60 C
25
68
pf
125
C C = 33pF T C=
pf
40 100
6
C C = 68pF 75
20 TC = 55C
4 50
0
20 2 25
1 10 100 1K 10K .1M 1M 10M 0 20 40 60 80 100 1K 2K 3K 5K 10K 20K 50K 100K
SLEW RATE HARMONIC DISTORTION INPUT NOISE

50 10 20
R L = 2K
30 P O = 2.5W 15
1 AV = 30
SLEW RATE, (V/ S)
20
DISTORTION, (%)
10
10 .1
7
5 .01 5
3
2 .001 3
1 .0001 2
0 10 20 30 40 50 60 70 3 30 300 3K 30K 10 100 1K 10K 1M
COMPENSATION CAPACITOR, CC (pF) FREQUENCY, F (Hz) FREQUENCY, F (Hz)

120 140 200

100 120 120

100
80 100 70
80 50
60
40 60 30
20
20 40
20 10
1 10 100 1K 10K .1M 1M 1 10 100 1K 10K .1M 1M 3 5 10 20 50 100 150
FREQUENCY, F (Hz) FREQUENCY, F (Hz) CURRENT LIMIT RESISTOR, RCL ( )
273
OPERATING
GENERAL applications 1N4148 or 1N914 signal diodes are sufficient (D1,

D2 in Figure 2a). In more demanding applications where low
tion, which covers stability, supplies, heatsinking, mounting, leakage or low capacitance are of concern 2N4416 or 2N5457-
current limit, SOA interpretation, and specification interpreta- 2N5459 JFETs connected as diodes will be required (Q1, Q2
tion. Additional information can be found in the application in Figure 2b). In either case the input differential voltage will be
notes. For information on the package outline, heatsinks, and clamped to .7V. This is sufficient overdrive to produce maxi-
mounting hardware, consult the Accessory and Package mum power bandwidth.
Mechanical Data section of the handbook.
POWER SUPPLY PROTECTION
CURRENT LIMIT
Unidirectional zener diode transient suppressors are recom-
For proper operation, the current limit resistor (RCL) must be mended as protection on the supply pins. The zeners clamp
connected as shown in the external connection diagram. The transients to voltages within the power supply rating and also
minimum value is 3.5 ohm, however for optimum reliability the clamp power supply reversals to ground. Whether the zeners
resistor value should be set as high as possible. The value is are used or not, the system power supply should be evaluated
calculated as follows; with the maximum practical value of 150 for transient performance including power-on overshoot and
ohms. power-off polarity reversal as well as line regulation.
.7
RCL = Conditions which can cause open circuits or polarity rever-
ILIM
sals on either power supply rail should be avoided or protected
against. Reversals or opens on the negative supply rail is
SAFE OPERATING AREA (SOA) known to induce input stage failure. Unidirectional transzorbs
The MOSFET output stage of this power operational ampli- prevent this, and it is desirable that they be both electrically and
fier has two distinct limitations: physically as close to the amplifier as possible.
1. The current handling capability of the MOSFET geometry
and the wire bonds. STABILITY
The PA88 has sufficient phase margin to be stable with most
NOTE: The output stage is protected against transient flyback. capacitive loads at a gain of 4 or more, using the recommended
phase compensation.
250 The PA88 is externally compensated and performance can
be tailored to the application. Use the graphs of small signal
150 10 response and power response as a guide. The compensation

0m
20 S capacitor CC must be a. +VS
100 0m rated at 500V working
S Z1
DC voltage. An NPO capaci-
,T tor is recommended. The
DC C =
50 25 compensation network 3
,T C 5
C = CCRC must be mounted IN
85
DC C closely to the amplifier D1 D2 PA88
,T pins 7 and 8 to avoid +IN
25 C = spurious oscillation. 4
12 6
5
C
15 Z2
VS
10
b. +VS
Z1
5
25 50 75 100 125 250 500
5 3
SUPPLY TO OUTPUT DIFFERENTIAL, VS VO (V) IN
Q1 Q2 PA88
However, for protection against sustained, high energy flyback,
external fast-recovery diodes should be used. +IN
4 6
INPUT PROTECTION
Although the PA88 can withstand differential input voltages Z2
up to 25V, additional external protection is recommended, VS
FIGURE 2. OVERVOLTAGE PROTECTION
and required at total supply voltages above 300 volts. In most
omissions. HOTLINE:
change 546-2739
without notice.
274
PA88M
SG PARAMETER*** SYMBOL TEMP. POWER TEST CONDITIONS MIN MAX UNITS

3 Quiescent current IQ 55C 150V VIN = 0, AV = 100 2.3 mA

2 Quiescent current IQ 125C 150V VIN = 0, AV = 100 2.3 mA

C
4 Current limits ICL 25C 50V RCL = 10, RL = 200 50 84 mA


BURN IN CIRCUIT 100K

* These components are used to stabilize device due to
+50V poor high frequency characteristics of burn in board.
100K
2.7
** Input signals are calculated to result in internal power
* 5 3 dissipation of approximately 2.1W at case temperature
2 = 125C.
** * 1
U.U.T.
4 8
*** An additional test is performed manually at
67 TC = 25C which stresses power supply, common
60
100
mode range and output swing to 225V (450V total).
68pF
50V
however, FAXis(520)
ORDERS (520) 690-8601
275
NOTES:
276
PA89 PA89A
FEATURES
1140V P-P SIGNAL OUTPUT
75 mA CONTINUOUS OUTPUT CURRENT
INPUT PROTECTION
PATENTED
APPLICATIONS
PIEZOELECTRIC POSITIONING TYPICAL APPLICATION
HIGH VOLTAGE INSTRUMENTATION Ultra-high voltage capability combined with the bridge am-
ELECTROSTATIC DEFLECTION plifier configuration makes it possible to develop +/1000 volt
SEMICONDUCTOR TESTING peak swings across a piezo element. A high gain of 50 for A1
insures stability with the capacitive load, while noise-gain
DESCRIPTION compensation Rn and Cn on A2 insure the stability of A2 by
The PA89 is an ultra high voltage, MOSFET operational operating in a noise gain of 50.
amplifier designed for output currents up to 75 mA. Output 50R 50R
voltages can swing over 1000V p-p. The safe operating area
50R
C
(SOA) has no second breakdown limitations and can be
observed with all types of loads by choosing an appropriate +600V +600V
current limiting resistor. High accuracy is achieved with a
cascode input circuit configuration and 120dB open loop gain. R R
All internal biasing is referenced to a bootstrapped zener- A1 A2
MOSFET current source, giving the PA89 a wide supply range V IN PA89 PA89 Cn
and excellent supply rejection. The MOSFET output stage is PIEZO
biased for class A/B linear operation. External compensation TRANSDUCER
provides user flexibility. The PA89 is 100% gross leak tested 600V 600V
to military standards for long term reliability.
SINGLE AXIS MICRO-POSITIONING
This hybrid integrated circuit utilizes a beryllia (BeO) sub-
strate, thick film resistors, ceramic capacitors and semicon-
ductor chips to maximize reliability, minimize size and give top
EXTERNAL CONNECTIONS*
performance. Ultrasonically bonded aluminum wires provide
reliable interconnections at all operating temperatures. The
MO-127 High Voltage, Power Dip package is hermetically IN RESERVED
sealed and electrically isolated. 1 12
+IN RESERVED
2 11
SIMPLIFIED SCHEMATIC CC
N/C 3 10 COMP
8 TOP
4 VIEW 9
+VS N/C COMP
D1 RC
5 8
Q5 VS 6 7
+VS
Q1 Q2 D57 Q19
Q20
COMP CL OUT CL
9 10
Q26 7
Q22 Q23 .7
IN +IN
R CL =
Q25A Q25B I LIM
1 2 Q29 6 R CL
Q36 OUT
PHASE COMPENSATION
D30 D34
Gain CC RC
D35 D31
Q42 1 470pF 470
Q44 10 68pF 220
Q45
D5 15 33pF 220
VS
100 15pF 220
5
Note: CC must be rated for full supply voltage Vs to +Vs.
See details under EXTERNAL COMPONENTS.
277

OUTPUT CURRENT, within SOA 100mA
POWER DISSIPATION, internal at TC = 25C 40W
VS 25V

INPUT VOLTAGE, common mode
TEMPERATURE, storage 65 to 125C
OPERATING TEMPERATURE RANGE, case 55 to 125C

1
INPUT
OFFSET VOLTAGE, vs. supply 7 * V/V
BIAS CURRENT,vs. supply .01 * pA/V
OFFSET CURRENT, initial3 5 50 3 20 pA
INPUT IMPEDANCE, DC 105 * M
VS 50

COMMON MODE VOLTAGE RANGE4 Full temperature range * V
COMMON MODE REJECTION, DC Full temperature range, VCM = 90V 96 110 * * dB
INPUT NOISE 10kHz BW, RS = 10K, CC = 15pF 4 V RMS
GAIN
OPEN LOOP GAIN at 10Hz RL = 10k, CC = 15pF 108 120 * * dB
GAIN BANDWIDTH PRODUCT RL = 10k, CC = 15pF, AV = 100 10 * MHz
POWER BANDWIDTH RL = 10k, CC = 15pF, VO = 500V p-p 5 * kHz
PHASE MARGIN Full temperature range, AV = 10 60 *
OUTPUT
VS 30 VS 15

VOLTAGE SWING4 IO = 75mA * * V
VS 20 VS 12

VOLTAGE SWING4 Full temperature range, IO = 20mA * * V
CURRENT, continuous Full temperature range 75 * mA
SLEW RATE CC = 15pF, AV = 100 12 16 * * V/s
CAPACITIVE LOAD, Av = 10 Full temperature range 1 * nF
CAPACITIVE LOAD, Av>10 Full temperature range SOA *
SETTLING TIME to .1% RL = 10K, 10V step, Av = 10 2 * s
POWER SUPPLY
VOLTAGE, VS4 Full temperature range 75 500 600 * * * V
CURRENT, quiescent 4.8 6.0 * * mA
THERMAL
RESISTANCE, AC, junction to case5 Full temperature range, F > 60Hz 2.1 2.3 * * C/W
RESISTANCE, DC, junction to case Full temperature range, F < 60Hz 3.3 3.5 * * C/W
1. Unless otherwise noted: TC = 25C, CC = 68pF, RC = 220, and VS = 500V. Input parameters for bias currents and offset
voltage are values given.
5. Rating applies only if the output current alternates between both output transistors at a rate faster than 60Hz.
CAUTION
278
TYPICAL PERFORMANCE
GRAPHS PA89 PA89A

40 0 1.10
45 33pf, 220
32
1.05
OUTPUT STAGE
90
PHASE, ()
24
135 1.00
16 68pf, 220
180
.95
8 225 15pf, 220
CC , RC
0 270 .9
0 25 50 75 100 125 150 1 10 100 1K 10K 100K 1M 10M 0 200 400 600 800 1000 1200
CASE TEMPERATURE, T (C) FREQUENCY F (Hz) TOTAL SUPPLY VOLTAGE, VS (V)

120 30 1200
15pf, 220 1000

100 800
25
33pf, 220 C C = 15pf
80 600
20 500
60
15
C
40 300
68pf, 220 10
20 C C = 33pf
0 5 C C = 68pf
CC , RC R C = 220
20 100
1 10 100 1K 10K 100K 1M 10M 0 25 50 75 100 1K 3K 10K 30K 100K
SLEW RATE VS COMP HARMONIC DISTORTION INPUT NOISE VOLTAGE

INPUT NOISE VOLTAGE, e N (nV/ Hz)
20 10 20
VS = 500V
15
C C = 15pf, R C = 220
DISTORTION, THD(%)
1 R L = 11K
SLEW RATE, (V/ S)
15 A V = 100 10
VO = 800Vpp 7
.1
VO = 600Vpp 5
10
VO = 400Vpp
.01
3
VO = 100Vpp
5 .001 2
0 25 50. 75 100 30 100 300 1K 3K 10K 30K 100K 10 100 1K 10K 100K
EXT. COMPENSATION CAPACITOR, C C (pF) FREQUENCY, F (Hz) FREQUENCY, F (Hz)

COMMON MODE REJECTION, CMR(dB)
100 100 100

80 80 80
60 60 60
40 40 40
20 20 20
0 0 0
1 10 100 1K 10K 100K 1M 10M 1 10 100 1K 10K 100K 1M 10M 0 20 40 60 80 100
FREQUENCY, F (Hz) FREQUENCY, F (Hz) RESISTOR VALUE, R CL ( )
279
OPERATING
GENERAL The compensation capacitance CC must be rated for the full

supply voltage range. For example, with supply voltages of
500V the possible voltage swing across CC is 1000V. In
tion, which covers stability, supplies, heatsinking, mounting,
addition, a voltage coefficient less than 100PPM is recom-
mended to maintain the capacitance variation to less than 5%
for this example. It is strongly recommended to use the highest
notes. For information on the package outline, heatsinks, and
quality capacitor possible rated at least twice the total supply
voltage range.
Mechanical Data section of the handbook. Of equal importance are the voltage rating and voltage
coefficient of the gain setting resistances. Typical voltage
STABILITY ratings of low wattage resistors are 150 to 250V. In the above
Although the PA89 can be operated at unity gain, maximum example 1000V could appear across the feedback resistor.
slew rate and bandwidth performance was designed to be This would require several resistors in series to obtain the
obtained at gains of 10 or more. Use the small signal response proper voltage rating. Low voltage coefficient resistors will
and phase response graphs as a guide. In applications where insure good gain linearity. The wattage rating of the feedback
gains of less than 10 are required, use noise gain compensa- resistor is also of concern. A 1 megohm feedback resistor
tion to increase the phase margin of the application circuit as could easily develop 1 watt of power dissipation.
illustrated in the typical application drawing. Though high voltage rated resistors can be obtained,
a 1 megohm feedback resistor comprised of five 200Kohm, 1/
SAFE OPERATING AREA (SOA) 4 watt metal film resistors in series will produce the proper
The MOSFET output stage of this power operational ampli- voltage rating, voltage coefficient and wattage rating.
fier has two distinct limitations:
1. The current handling capability of the MOSFET geometry CURRENT LIMIT
and the wire bonds. For proper operation the current limit resistor (RCL) must be
2. The junction temperature of the output MOSFETs. connected as shown in the external connection diagram. The
NOTE: The output stage is protected against transient flyback. minimum value is 3.5 ohm, however for optimum reliability the
However, for protection against sustained, high energy flyback, resistor value should be set as high as possible. The value is
external fast-recovery diodes should be used. calculated as follows with the maximum practical value of 150
ohms.
SAFE OPERATING CURVES RCL =
.7
The safe operating area curves define the maximum addi- I LIM
tional internal power dissipation the amplifier can tolerate when
it produces the necessary output to drive an external load. This When setting the value for RCL allow for the load current as
is not the same as the absolute maximum internal power well as the current in the feedback resistor. Also allow for the
dissipation listed elsewhere in the specification since the quies- temperature coefficient of the current limit which is approxi-
cent power dissipation is significant compared to the total. mately -0.3% /C of case temperature rise.
EXTERNAL COMPONENTS CAUTIONS

The very high operating voltages of the PA89 demand The operating voltages of the PA89 are potentially lethal.
consideration of two component specifications rarely of con- During circuit design, develop a functioning circuit at the lowest
cern in building op amp circuits: voltage rating and voltage possible voltages. Clip test leads should be used for hands
coefficient. off measurements while troubleshooting.
100
10mS POWER SUPPLY PROTECTION

25C
Unidirectional zener diode transient absorbers are recom-
50 mended as protection on the supply pins. The zeners clamp
100mS transients to voltages within the power supply rating and also
30 clamp power supply reversals to ground. Whether the zeners
are used or not, the system power supply should be evaluated
125C for transient performance including power-on overshoot and
15 85C
power-off polarity reversals as well as line regulation.
Conditions which can cause open circuits or polarity rever-
10
sals on either power supply rail should be avoided or protected
against. Reversals or opens on the negative supply rail is
5 known to induce input stage failure. Unidirectional transzorbs
prevent this, and it is desirable that they be both electrically and
T = T CASE
physically as close to the amplifier as possible.
3
100 200 300 500 800 1000 1200
SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE, VS VO (V)
without notice.
PA89U REV. F FEBRUARY 1998 1998 Apex Microtechnology Corp.
280
POWER BOOSTER AMPLIFIER
PB50
FEATURES
HIGH OUTPUT CURRENT Up to 2A Continuous
VOLTAGE AND CURRENT GAIN
HIGH SLEW RATE 50V/s Minimum
HIGH POWER BANDWIDTH 160 kHz Minimum
LOW QUIESCENT CURRENT 12mA Typical
APPLICATIONS EQUIVALENT SCHEMATIC

3
HIGH VOLTAGE INSTRUMENTATION +Vs
Electrostatic TRANSDUCERS & DEFLECTION Q2
Programmable Power Supplies Up to 180V p-p Q1
DESCRIPTION Q3
IN
The PB50 is a high voltage, high current amplifier designed 4 Q4
to provide voltage and current gain for a small signal, general
purpose op amp. Including the power booster within the GAIN 6.2K
Q6
Q5
C
feedback loop of the driver amplifier results in a composite 7 OUT
amplifier with the accuracy of the driver and the extended 1
output voltage range and current capability of the booster. The
50K 3.1K
PB50 can also be used without a driver in some applications, 2
requiring only an external current limit resistor to function COM
Q7 CL
properly. 5
The output stage utilizes complementary MOSFETs, pro-
viding symmetrical output impedance and eliminating second- COMP
ary breakdown limitations imposed by Bipolar Junction Tran- 8 Q8
sistors. Internal feedback and gainset resistors are provided
for a pin-strappable gain of 3. Additional gain can be achieved Q9 Q10
with a single external resistor. Compensation is not required
for most driver/gain configurations, but can be accomplished
with a single external capacitor. Although the booster can be
configured quite simply, enormous flexibility is provided through Vs
the choice of driver amplifier, current limit, supply voltage, 6
voltage gain, and compensation.
This hybrid circuit utilizes a beryllia (BeO) substrate, thick
film resistors, ceramic capacitors and semiconductor chips to
maximize reliability, minimize size and give top performance.
Ultrasonically bonded aluminum wires provide reliable inter- R CL
connections at all operating temperatures. The 8-pin TO-3 CL
package is electrically isolated and hermetically sealed using +Vs
3 2
one-shot resistance welding. The use of compressible isola-
tion washers voids the warranty. OUT
IN
1
4
TYPICAL APPLICATION Figure 1. Inverting TOP VIEW

composite amplifier. COM COMP CC
CF 5 8
RF Vs 6 7
+15V +Vs R CL RG
VIN RI
GAIN
OP IN
AMP OUT
COM PB50
CC
RL
15V Vs RG
281
PB50 SPECIFICATIONS

POWER DISSIPATION, internal at TC = 25C1 35W
INPUT VOLTAGE, referred to common 15V
SPECIFICATIONS
INPUT
OFFSET VOLTAGE, initial .75 1.75 V

OFFSET VOLTAGE, vs. temperature Full temperature range 4.5 7 mV/C
INPUT IMPEDANCE, DC 25 50 k
CLOSED LOOP GAIN RANGE 3 10 25 V/V
GAIN ACCURACY, internal Rg, Rf AV = 3 10 15 %
GAIN ACCURACY, external Rf AV = 10 15 25 %
PHASE SHIFT F = 10kHz, AVCL = 10, CC = 22pF 10
F = 200kHz, AVCL = 10, CC = 22pF 60
OUTPUT
VOLTAGE SWING Io = 2A VS11 VS 9 V

VOLTAGE SWING Io = 1A VS10 VS 7 V
VOLTAGE SWING Io = .1A VS8 VS 5 V
SLEW RATE Full temperature range 50 100 V/s
CAPACITIVE LOAD Full temperature range 2200 pF
SETTLING TIME to .1% RL = 100, 2V step 2 s
POWER BANDWIDTH VC = 100Vpp 160 320 kHz
SMALL SIGNAL BANDWIDTH CC = 22pF, AV = 25, Vcc = 100 100 kHz
SMALL SIGNAL BANDWIDTH CC = 22pF, AV = 3, Vcc = 30 1 MHz
POWER SUPPLY
VOLTAGE, VS3 Full temperature range 305 60 100 V

CURRENT, quiescent VS = 30 9 12 mA
VS = 60 12 18 mA
VS = 100 17 25 mA
THERMAL
RESISTANCE, AC junction to case4 Full temp. range, F > 60Hz 1.8 2.0 C/W
RESISTANCE, DC junction to case Full temp. range, F < 60Hz 3.2 3.5 C/W
TEMPERATURE RANGE, case Meets full range specifications 25 25 85 C
NOTES: 1. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation
to achieve high MTTF (Mean Time to Failure).
2. The power supply voltage specified under typical (TYP) applies, TC = 25C unless otherwise noted.
5. +VS must be at least 15V above COM, VS must be at least 30V below COM.
The PB50 is constructed from MOSFET transistors. ESD handling procedures must be observed.
CAUTION
282
TYPICAL PERFORMANCE
GRAPHS PB50

40 2 10
RC
= .33

L

30 1.5 8
R CL = .27
20 1 RC = 6
L .68 VO
R CL = 1.5
10 .5 4
VO +
0 0 2
25 0 25 50 75 100 125 25 0 25 50 75 100 125 .01 .02 .1 .2 1 2
CASE TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C) OUTPUT CURRENT, I O (A)
SMALL SIGNAL RESPONSE SMALL SIGNAL RESPONSE SMALL SIGNAL RESPONSE

80 0 30 0
AV CL = 25 AV CL = 3
CLOSED LOOP PHASE, ()

CLOSED LOOP GAIN, A (dB)
OPEN LOOP PHASE, ()
60 45 20 45 AV CL = 10
AV CL = 10
40 90 10
AV CL = 25 C
90
AV CL = 3
20 135 0 135
C C = 22pF CC = 22pF
0 180 10 180
100 1K 10K 100K 1M 10M 1K 10K 100K 1M 10M 1K 10K 100K 1M 10M
QUIESCENT CURRENT INPUT OFFSET VOLTAGE SLEW RATE VS. TEMP.

20 .5 400
INPUT OFFSET VOLTAGE, VOS (V)
QUIESCENT CURRENT, I O (mA)
Vs = 100V
SLEW RATE, SR (V/ s)
15 0 300
Vs = 60V
+SLEW
TEMP.
10 Vs = 30V .5 200
SLEW
5 -1 SUPPLY 100
0 -1.5 0
25 0 25 50 75 100 125 25 0 25 50 75 100 125 25 0 25 50 75 100 125
CASE TEMPERATURE, T C (C) CASE TEMPERATURE, TC (C) OR VS (V) CASE TEMPERATURE, T C (C)
POWER RESPONSE HARMONIC DISTORTION HARMONIC DISTORTION

360 1 .1
NO DRIVER DRIVER = TL070
VS = 60V VS = 60V R L = 25
DISTORTION, THD (%)
DISTORTION, THD (%)
180 V O = 80VPP V O = 95VPP

.3 .03
R L = 25
VQ (V), p-p
90
.1 .01
45
.03 .003
22 R L = 1K
R L = 1K
11 .01 .001
1K 3K 10K 30K 100K 300K 1M 300 1K 3K 10K 30K 300 1K 3K 10K 30K
283
OPERATING
PB50 CONSIDERATIONS
GENERAL STABILITY
Please read the General Operating Considerations sec- Stability can be maximized by observing the following guide-
tion, which covers stability, supplies, heatsinking, mounting, lines:
current limit, SOA interpretation, and specification interpreta- 1. Operate the booster in the lowest practical gain.
tion. Additional information can be found in the application 2. Operate the driver amplifier in the highest practical effec-
notes. For information on the package outline, heatsinks, and tive gain.
mounting hardware, consult the Accessory and Package 3. Keep gain-bandwidth product of the driver lower than the
Mechanical Data section of the handbook. closed loop bandwidth of the booster.
4. Minimize phase shift within the loop.
CURRENT LIMIT
For proper operation, the current limit resistor (RCL) must be A good compromise for (1) and (2) is to set booster gain from
connected as shown in the external connection diagram. The 3 to 10 with total (composite) gain at least a factor of 3 times
minimum value is 0.27 with a maximum practical value of booster gain. Guideline (3) implies compensating the driver as
47. For optimum reliability the resistor value should be set as required in low composite gain configurations. Phase shift
high as possible. The value is calculated as follows: +IL= .65/ within the loop (4) is minimized through use of booster and loop
RCL + .010, IL = .65/RCL. compensation capacitors Cc and Cf when required. Typical
values are 5pF to 33pF.
SAFE OPERATING AREA (SOA) Stability is the most difficult to achieve in a configuration
3 where driver effective gain is unity (ie; total gain = booster
gain). For this situation, Table 1 gives compensation values for
2 t=
50 optimum square wave response with the op amp drivers listed.
t= ms
ST 10
FROM +V SOR VS (A)
EA t= 0m
OUTPUT CURRENT
1 DY 20
ST
EA ST 0m s DRIVER CCH CF CC FPBW SR
DY AT s
ST ST E
T OP07 - 22p 22p 4kHz 1.5
EA AT C =2
DY E 5
741 - 18p 10p 20kHz 7
T C
ST C =
85
LF155 - 4.7p 10p 60kHz >60
AT C
E LF156 - 4.7p 10p 80kHz >60
T
12
C = TL070 22p 15p 10p 80kHz >60
5
C
.1
10 20 30 40 50 100 200 300
For: RF = 33K, RI = 3.3K, RG = 22K
SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE VS VO (V)
NOTE: The output stage is protected against transient flyback. Table 1: Typical values for case where op amp effective gain = 1.
However, for protection against sustained, high energy flyback, exter- CF
nal fast-recovery diodes should be used.
COMPOSITE AMPLIFIER CONSIDERATIONS RF

+15V
C CH +Vs R CL
Cascading two amplifiers within a feedback loop has many RI
advantages, but also requires careful consideration of several
amplifier and system parameters. The most important of these OP IN
VIN AMP
are gain, stability, slew rate, and output swing of the driver. OUT
COM PB50
Operating the booster amplifier in higher gains results in a COMP
CC RL
higher slew rate and lower output swing requirement for the
driver, but makes stability more difficult to achieve. 15V
Vs GAIN R
G
GAIN SET Figure 2. Non-inverting composite amplifier.
RG = [ (Av-1) * 3.1K] 6.2K
SLEW RATE
RG + 6.2K
Av = +1 The slew rate of the composite amplifier is equal to the slew
3.1K rate of the driver times the booster gain, with a maximum value
The boosters closed-loop gain is given by the equation equal to the booster slew rate.
above. The composite amplifiers closed loop gain is deter-
mined by the feedback network, that is: Rf/Ri (inverting) or
OUTPUT SWING
1+Rf/Ri (non-inverting). The driver amplifiers effective gain The maximum output voltage swing required from the driver
is equal to the composite gain divided by the booster gain. op amp is equal to the maximum output swing from the booster
Example: Inverting configuration (figure 1) with divided by the booster gain. The Vos of the booster must also
R i = 2K, R f = 60K, R g = 0 : be supplied by the driver, and should be subtracted from the
Av (booster) = (6.2K/3.1K) + 1 = 3 available swing range of the driver. Note also that effects of
Vos drift and booster gain accuracy should be considered
Av (composite) = 60K/2K = - 30
when calculating maximum available driver swing.
Av (driver) = - 30/3 = -10
omissions. HOTLINE:
change 546-2739
without notice.
PB50U REV. G DECEMBER 1997 1997 Apex Microtechnology Corp.
284
POWER BOOSTER EVALUATION KIT
EK50
INTRODUCTION 6"
This easy-to-use kit provides a platform for the evalua-
tion of the PB50 and PB58 high voltage power boosters.
GND
The PB50 and PB58 are designed most commonly in GND GND
GND
GND
combination with a small signal, general purpose op amp.
However, they can also be used without a driver amplifier.
+Vcc
This kit can be used to analyze a multitude of standard or
GND
proprietary circuit configurations.
OP AMP
+IN
PARTS LIST Vcc
IN
GND
GND
GND
GND
HS13 Heatsink 1
COM
EVAL01 PC Board 1
IN
GND
GND
HWRE02 Hardware Kit 1
HWRE05 8-Pin Wire Wrap Socket 1 +Vs
Vs
TW0 3 Thermal Washer 1 Box/10
PB58
PB50
8"
GND
HWRE02 contains the following:
GND
4 #8 x .375" Panhead Screws
GND
PIN1
4 #8 x .375" Hex Spacers
C
RCL
RG
GND
4 #8 x 2.00" Hex Stand Offs
CC
2 #6 x 1.25" Panhead Screws GND
2 #6 x 5/16" Hex Nuts
GND
GND
GND
OUT
EVAL01
REVB
GND
GND
GND
GND
EK 50
ASSEMBLY
8-pin wire wrap socket

#8 x .375" Panhead Screw
4 places typ Teflon Tubing
Eval01 PC Board (2 Opposite Pins
Minimum)
MS03 Mating Socket

#8 x .375"
Hex Spacer
4 places typ
Recessed Nuts PB50/PB58

#6 x 5/16" Package
#8 x 2.00" 2 PlacesTyp
Hex Standoff
4 places typ
#6 x 1.25"
Panhead Screws
2 Places Typ
HS13 Heatsink
1. Use thermal grease or Apex Thermal Washer TW03 between power booster and heatsink.
CAUTION 2. Use 18 gauge teflon sleeve on at least two opposite pins
3. Mounting torque greater than 7 inlbs on power booster mounting bolts will void warranty!
285
+ + +
VCC VS
+
8
2 4
IN RG
VCC
6 4 6
AD707 IN
VS 7 OUT
+VCC GAIN
3 5 PB50 1
+IN + 7 PB58 OUT
COMP
1 5
COM CL 8 CC
+
+VS 2
GND
3
RCL
+
+ + + +
+VCC +VS
without notice.
EK50U REV. C DECEMBER 1997 1997 Apex Microtechnology Corp.
286
POWER BOOSTER AMPLIFIERS
PB58 PB58A
FEATURES
HIGH OUTPUT CURRENT
1.5A Continuous (PB58)
2.0A Continuous (PB58A)
VOLTAGE AND CURRENT GAIN
HIGH SLEW 50V/s Minimum (PB58)
75V/s Minimum (PB58A)
HIGH POWER BANDWIDTH 320 kHz Minimum
LOW QUIESCENT CURRENT 12mA Typical EQUIVALENT SCHEMATIC
EVALUATION KIT See EK50
3
+Vs
APPLICATIONS Q2
Q1
Electrostatic TRANSDUCERS & DEFLECTION Q3
Programmable Power Supplies Up to 280V p-p IN
4 Q4
C
Q5
DESCRIPTION GAIN 6.2K
Q6
The PB58 is a high voltage, high current amplifier designed 7 OUT
to provide voltage and current gain for a small signal, general 1
purpose op amp. Including the power booster within the feed- 50K 3.1K
back loop of the driver amplifier results in a composite amplifier 2
with the accuracy of the driver and the extended output voltage COM
Q7 CL
range and current capability of the booster. The PB58 can also 5
be used without a driver in some applications, requiring only an Q11
external current limit resistor to function properly. COMP
The output stage utilizes complementary MOSFETs, provid- 8 Q8
ing symmetrical output impedance and eliminating second
breakdown limitations imposed by Bipolar Transistors. Internal Q9 Q10
feedback and gainset resistors are provided for a pin-strapable
gain of 3. Additional gain can be achieved with a single external
resistor. Compensation is not required for most driver/gain
configurations, but can be accomplished with a single external
Vs
capacitor. Enormous flexibility is provided through the choice of
6
driver amplifier, current limit, supply voltage, voltage gain, and
compensation.
This hybrid circuit utilizes a beryllia (BeO) substrate, thick film
resistors, ceramic capacitors and semiconductor chips to maxi- EXTERNAL CONNECTIONS
mize reliability, minimize size and give top performance.
Ultrasonically bonded aluminum wires provide reliable inter- R CL
connections at all operating temperatures. The 8-pin TO-3 CL
package is electrically isolated and hermetically sealed using +Vs
3 2
one-shot resistance welding. The use of compressible isolation
washers voids the warranty. OUT
IN
1
Figure 1. Inverting 4
TYPICAL APPLICATION
C
composite amplifier.
F TOP VIEW
COM COMP CC
RF
5 8
+15V +Vs R CL
VIN RI
Vs 6 7
RG
OP IN
AMP OUT GAIN
COM PB58
CC
RL
15V RG
Vs
287
PB58 PB58A SPECIFICATIONS

OUTPUT CURRENT, within SOA 2.0A
POWER DISSIPATION, internal at TC = 25C1 83W
INPUT VOLTAGE, referred to COM 15V
SPECIFICATIONS PB58 PB58A
INPUT
OFFSET VOLTAGE, initial .75 1.75 * 1.0 V

OFFSET VOLTAGE, vs. temperature Full temperature range3 4.5 7 * * mV/C
INPUT IMPEDANCE, DC 25 50 * * k
CLOSED LOOP GAIN RANGE 3 10 25 * * * V/V
GAIN ACCURACY, internal Rg, Rf AV = 3 10 15 * * %
GAIN ACCURACY, external Rf AV = 10 15 25 * * %
PHASE SHIFT f = 10kHz, AVCL = 10, CC = 22pF 10 *
f = 200kHz, AVCL = 10, CC = 22pF 60 *
OUTPUT
VOLTAGE SWING Io = 1.5A (PB58), 2A (PB58A) VS11 VS 8 VS15 VS11 V

VOLTAGE SWING Io = 1A VS10 VS 7 * * V
VOLTAGE SWING Io = .1A VS8 VS 5 * * V
CURRENT, continuous 1.5 2.0 A
SLEW RATE Full temperature range 50 100 75 * V/s
CAPACITIVE LOAD Full temperature range 2200 * pF
SETTLING TIME to .1% RL = 100, 2V step 2 * s
POWER BANDWIDTH VC = 100 Vpp 160 320 240 * kHz
SMALL SIGNAL BANDWIDTH CC = 22pF, AV = 25, Vcc = 100 100 * kHz
SMALL SIGNAL BANDWIDTH CC = 22pF, AV = 3, Vcc = 30 1 * MHz
POWER SUPPLY
VOLTAGE, VS4 Full temperature range 156 60 150 * * * V

CURRENT, quiescent VS = 15 11 * mA
VS = 60 12 * mA
VS = 150 14 18 * * mA
THERMAL
RESISTANCE, AC junction to case5 Full temp. range, f > 60Hz 1.2 1.3 * * C/W
RESISTANCE, DC junction to case Full temp. range, f < 60Hz 1.6 1.8 * * C/W
TEMPERATURE RANGE, case Meets full range specifications 25 25 85 * * * C
NOTES: * The specification of PB58A is identical to the specification for PB58 in applicable column to the left.
to achieve high MTTF (Mean Time to Failure).
2. The power supply voltage specified under typical (TYP) applies, TC = 25C unless otherwise noted.
3. Guaranteed by design but not tested.
6. +VS/VS must be at least 15V above/below COM.
The PB58 is constructed from MOSFET transistors. ESD handling procedures must be observed.
CAUTION
288
TYPICAL PERFORMANCE
GRAPHS PB58 PB58A

100 2 14

80 12
1.5 R
CL = .4
7
60 10
1 RC =
L .68 VO -
40 8
R CL = 1.5 VO +
.5 6
20
0 0 4
25 0 25 50 75 100 125 25 0 25 50 75 100 125 .01 .05 1 1.5 2
CASE TEMPERATURE, TC (C) CASE TEMPERATURE, TC (C) OUTPUT CURRENT, I O (A)
SMALL SIGNAL RESPONSE SMALL SIGNAL RESPONSE SMALL SIGNAL RESPONSE

80 0 30 0
AV CL = 25 AV CL = 3
CLOSED LOOP PHASE, ()

CLOSED LOOP GAIN, A (dB)
OPEN LOOP PHASE, ()
60 45 20 45 AV CL = 10
AV CL = 10
40 90 10 90
AV CL = 25
C
AV CL = 3
20 135 0 135
C C = 22pF C C = 22pF
0 180 10 180
100 1K 10K 100K 1M 10M 1K 10K 100K 1M 10M 1K 10K 100K 1M 10M
QUIESCENT CURRENT INPUT OFFSET VOLTAGE SLEW RATE VS. TEMP.

20 .5 400
INPUT OFFSET VOLTAGE, VOS (V)
QUIESCENT CURRENT, I Q (mA)
SLEW RATE, SR (V/ s)
15 50V 0 300
Vs = 1
+S
V LE
Vs = 1
00 W
10 -.5 200
Vs = 3
0V
-SLEW
5 -1 100
0 -1.5 0
25 0 25 50 75 100 125 25 0 25 50 75 100 125 25 0 25 50 75 100 125
CASE TEMPERATURE, T C (C) CASE TEMPERATURE, TC (C) CASE TEMPERATURE, T C (C)
POWER RESPONSE PULSE RESPONSE HARMONIC DISTORTION

300 80 .1
DRIVER = TL070
200
OUTPUT VOLTAGE, VQ (VPP )
60
VS = 60V
OUTPUT VOLTAGE, VQ (V)
5
DISTORTION, THD (%)
V O = 95VPP
=3
40 .03
100
L
R
20

1K
50 0 .01
=
L
R
40 -20
30
-40 .003
20
-60
10 -80 .001
100K 300K 1M 3M 10M 1 2 3 4 5 6 7 8 300 1K 3K 10K 30K
289
OPERATING
PB58 PB58A CONSIDERATIONS
GENERAL STABILITY
Please read the General Operating Considerations sec- Stability can be maximized by observing the following guide-
tion, which covers stability, supplies, heatsinking, mounting, lines:
current limit, SOA interpretation, and specification interpreta- 1. Operate the booster in the lowest practical gain.
tion. Additional information can be found in the application 2. Operate the driver amplifier in the highest practical effec-
notes. For information on the package outline, heatsinks, and tive gain.
mounting hardware, consult the Accessory and Package 3. Keep gain-bandwidth product of the driver lower than the
Mechanical Data section of the handbook. closed loop bandwidth of the booster.
4. Minimize phase shift within the loop.
CURRENT LIMIT
For proper operation, the current limit resistor (RCL) must be A good compromise for (1) and (2) is to set booster gain from
connected as shown in the external connection diagram. The 3 to 10 with total (composite) gain at least a factor of 3 times
minimum value is 0.33 with a maximum practical value of booster gain. Guideline (3) implies compensating the driver as
47. For optimum reliability the resistor value should be set as required in low composite gain configurations. Phase shift
high as possible. The value is calculated as follows: +IL= .65/ within the loop (4) is minimized through use of booster and loop
RCL + .010, -IL = .65/RCL. compensation capacitors Cc and Cf when required. Typical
values are 5pF to 33pF.
SAFE OPERATING AREA (SOA) Stability is the most difficult to achieve in a configuration
3 where driver effective gain is unity (ie; total gain = booster
gain). For this situation, Table 1 gives compensation values for
2 optimum square wave response with the op amp drivers listed.
FROM +Vs or Vs (A)
t=
OUTPUT CURRENT
10
1 ste ste ste 0m
ad ad ad s
ys ys ys
ta
DRIVER CCH CF CC FPBW SR
ta ta te
te te OP07 - 22p 22p 4kHz 1.5
.5 Tc Tc Tc
.4 = = =
12 85 25 741 - 18p 10p 20kHz 7
5 C C
.3 C LF155 - 4.7p 10p 60kHz >60
.2 LF156 - 4.7p 10p 80kHz >60
TL070 22p 15p 10p 80kHz >60
.1
10 20 30 40 50 100 200 300 For: RF = 33K, RI = 3.3K, RG = 22K
SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE, Vs Vo (V)
NOTE: The output stage is protected against transient flyback. Table 1: Typical values for case where op amp effective gain = 1.
However, for protection against sustained, high energy flyback, exter-
CF
nal fast-recovery diodes should be used.
COMPOSITE AMPLIFIER CONSIDERATIONS +15V RF

+Vs R CL
RI CCH
Cascading two amplifiers within a feedback loop has many
OP IN
advantages, but also requires careful consideration of several
AMP OUT
amplifier and system parameters. The most important of these VIN COM PB58
are gain, stability, slew rate, and output swing of the driver. COMP
15V CC RL
Operating the booster amplifier in higher gains results in a
higher slew rate and lower output swing requirement for the Vs GAIN R
G
driver, but makes stability more difficult to achieve.
GAIN SET Figure 2. Non-inverting composite amplifier.

RG = [ (Av-1) * 3.1K] 6.2K
RG + 6.2K SLEW RATE
Av = +1 The slew rate of the composite amplifier is equal to the slew
3.1K
rate of the driver times the booster gain, with a maximum value
The boosters closed-loop gain is given by the equation equal to the booster slew rate.
above. The composite amplifiers closed loop gain is deter-
mined by the feedback network, that is: Rf/Ri (inverting) or OUTPUT SWING
1+Rf/Ri (non-inverting). The driver amplifiers effective gain The maximum output voltage swing required from the driver
is equal to the composite gain divided by the booster gain. op amp is equal to the maximum output swing from the booster
Example: Inverting configuration (figure 1) with divided by the booster gain. The Vos of the booster must also
R i = 2K, R f = 60K, R g = 0 : be supplied by the driver, and should be subtracted from the
Av (booster) = (6.2K/3.1K) + 1 = 3 available swing range of the driver. Note also that effects of
Av (composite) = 60K/2K = 30 Vos drift and booster gain accuracy should be considered
Av (driver) = 30/3 = 10 when calculating maximum available driver swing.
without notice.
PB58U REV. H JANUARY 1998 1998 Apex Microtechnology Corp.
290
APPLICATION
NOTES
Applications Engineers Message ............................................................................ 292
Applications Note Cross Reference ......................................................................... 293
Application Note 1, General Operating Considerations ........................................... 294
Application Note 2, Optoelectronic Position Control .............................................. 303
Application Note 3, Bridge Circuit Drives ............................................................... 305
Application Note 5, Precision Magnetic Deflection ................................................ 308
Application Note 6, Applying the Super Power PA03 ............................................ 312
Application Note 7, Programmable Power Supplies .............................................. 317
Application Note 8, Optimizing Output Power ........................................................ 319
Application Note 9, Foldover Current Limiting ........................................................ 323
Application Note 10, Power Amp Output Impedance ............................................. 326
Application Note 11, Thermal Techniques ............................................................. 327
Application Note 13, Voltage to Current Conversion ............................................. 329
Application Note 14, Power Booster Applications .................................................. 332
Application Note 16, SOA Advantages of MOSFETs ............................................ 334
Application Note 17, Wideband, Low Distortion Techniques ................................. 336
Application Note 19, Stability for Power Amplifiers ................................................ 339
Application Note 20, Bridge Mode Operation of Power Amplifiers ......................... 359
Application Note 21, Single Supply Operation of Power Amplifiers ....................... 363
Application Note 22, SOA and Load Lines ............................................................. 368 D
Application Note 24, Brush Type DC Motor Drive .................................................. 372
Application Note 25, Driving Capacitive Loads ...................................................... 374
Application Note 26, Parallel Connection ............................................................. 393
Application Note 28, Proper Analog Wiring of Power Amplifiers .......................... 396
Application Note 30, PWM Basics ........................................................................ 398
Application Note 31, Basic Op Amp Theory and Practice .................................... 403
Application Note 32, PWM Low Pass Filtering ..................................................... 405
291
TECHNICAL SUPPORT TO SERVE YOU
Applications Hotline and Technical Seminars
The APEX Applications hotline is the quickest way to get answers about your specific
circuit needs. It puts you in touch with a wealth of experience. We can assist you with
product selection, design suggestions, schematic review and circuit debugging.
APEX also conducts technical seminars across the U.S. and around the free world. These
seminars are designed to provide you with extensive information on power amplifiers
and DC/DC converter applications, in addition to the hows and whys of internal circuits
and construction. Pros and cons of various approaches are presented along with poten-
tial dangers. Question and answer periods emphasize areas of special interest. These
seminars are available free to groups of 10 or more engineers interested in APEX
products. Contact your local APEX sales representative, or one of us directly about
seminar scheduling in your area.
Application notes are developed with the help of your questions, suggestions and
feedback. Please call us if you have identified and implemented a new useful applica-
tion are ready to share the information with others.
We are always open to suggestions on products youd like to see from us.
Granger Scofield Paul Kyle

Applications Engineer Applications Engineer
(520) 690-8662 (520) 690-8667
William Cullum Eugene Wong

Applications Engineer Applications Engineer
(520) 690-8660 (520) 690-8663
292
POWER AMPLIFIERS, DC/DC CONVERTERS
APPLICATION NOTES CROSS REFERENCE

GENERAL APPLICATION TOPIC RECOMMENDED

APPLICATION NOTE (A/N)
Basics of Power Amplifiers A/N 1, 31

Motor/Valve/Actuator A/N 11, 22, 24, 30
Programmable Power Supply A/N 6, 7, 22
Electromagnetic Deflection A/N 5, 22
Electrostatic Deflection A/N 22
Piezo, Electrofluorescent Display, Capacitive Load A/N 22
Audio A/N 3, 8, 11, 17, 22
Wideband A/N 17, Consult Factory
Power Delivery and Power Dissipation A/N 8, 11, 30
Power Booster or Composite Amplifier Applications A/N 14, 19
PA12 and PA10 Applications A/N 9
Safe Operating Area A/N 16, 22
Bridge Circuit Applications A/N 3, 20, 30
Stability A/N 19, 25
Basics of PWM A/N 30
PWM Low Pass Filtering A/N 32
D
For further assistance, refer to the subject index located at the back of this data book.
293
GENERAL OPERATING CONSIDERATIONS
APPLICATION NOTE 1
SAVE HOURS OF VALUABLE TIME

This applications information is intended to save you hours (maybe With low voltage applied and reduced current limits in place, the
days) of hard work and avoid many frustrating experiences with power basic function of the circuit can be verified. Once the circuit is
circuits. We highly recommend that you take the small amount of time operating as desired, raise the current limit and check worst case
required to read this section so that you can avoid the common pitfalls operating conditions, i.e. motor reversal, square wave drive of
in designing and testing power operational amplifier circuits. As a reactive loads, or driving the output to VS /2 for resistive loads. Only
minimum, you should read all oblique print and the first paragraph in then should you gradually raise the supply voltages to the maxi-
each numbered subsection. The majority of these problem areas have mum while checking worst case operation. This procedure not only
been identified from APEX Applications Hotline discussions of actual saves many failures but it also helps to pinpoint problems to specific
circuits. They range from higher than expected errors to total destruc- voltages and power levels.
tion of the amplifier. 4) Use the largest possible heatsink for your prototype work. This
precaution provides the best environment to make thermal mea-
1.0 ELECTROSTATIC DISCHARGE surements on the case of the amplifier during worst case loading
conditions without premature failures from thermal overload. Once
(ESD) PRECAUTIONS you verify your calculations, you may decide to use a smaller
All APEX amplifiers should be handled using proper ESD precau- heatsink for your final circuit. Consult Section 7, Internal Power
tions! MOSFET amplifiers are especially susceptible to ESD damage Dissipation And Heatsinking, for information on calculating
and many of our amplifiers are MOSFET designs. Most of our bipolar heatsink requirements for your application.
designs use small geometry transistor input stages, which are vulner- 5) Avoid switching while the circuit is under power. This includes
able to ESD. plugging/unplugging banana jacks, switching relays in high current
ESD damage causes a wide range of effects, from increased lines, switching within a feedback loop, etc. See Sections 9.1 and
voltage offset or bias currents to total destruction. APEX manufactures 9.3 for a further discussion of the dangers of switching.
its products in a tightly controlled, anti-static environment and ships its
products in anti-static packaging. Strict ESD precautions from receiv- 3.0 ABSOLUTE MAXIMUM
ing inspection through final assembly at your facility must be followed. SPECIFICATIONS
Some areas which will require ESD prevention measures include
personnel, tabletops, stocking containers, floors, soldering irons, and Amplifiers should always operate below their Absolute Maximum
test equipment. Ratings to prevent permanent damage. If operation results in one of
these maximums being reached, no permanent damage will result.
Simultaneous application of two or more of these maximum stress
2.0 BEFORE YOU APPLY POWER levels may result in permanent damage to the amplifier. Note that
In the design/prototype phase of an application, many dangers exist proper operation is only guaranteed over the ranges listed in the
which will be eliminated by the time the circuit is ready for production. Specifications table.
Pins may be wired in reverse order, connections may be missing, or Example: Most amplifiers have an Absolute Maximum case tem-
test probes may cause momentary shorts. Any of these can destroy perature rating of +125C. If the Specifications table gives an operating
power amplifiers or other components in short order. temperature range of up to +85C, then the parameter limits in the
Five procedures can be employed to substantially reduce these Specifications table are not valid between +85C and +125C. In
dangers: addition, the amplifier may not even be operational in this range, (for
1) Set power supplies to the minimum operating levels allowed by the example, the amplifier may latch to one of its supply rails when above
data sheet. +85C). However, the device will not sustain permanent damage
2) Set amplifier current limit to very low levels (i.e. use a current limit unless the latched condition also violates the safe operating area.
resistor of approximately 2.2 ohms for high current models and 47 The absolute maximum power dissipation rating used by APEX is
ohms for high voltage models). Consult Section 5, Current Limit, the generally accepted industry method which assumes the case
as well as the individual data sheet to determine the proper values temperature of the amplifier is held at 25C and the junctions are
for the current limit resistor(s). Do not depend on the variable current operating at the absolute maximum rating. This standardization pro-
limit feature of your lab power supply for protecting the amplifier. vides a yardstick when comparing ratings of various manufacturers.
It is much safer to install current limit resistors. Setting the current However, it is not a reasonable operating point because it requires an
limit to a low value on a commercial lab supply will not protect the ideal (infinite) heatsink. Furthermore, even with the best heatsink,
amplifier against the surge current available from the output filter sustained operation at the maximum rated junction temperature will
capacitors. Even when average power dissipation is low, SOA result in reduced product life. Refer to Section 7, Internal Power
violations can occur due to secondary breakdown of bipolar output Dissipation And Heatsinking, for information regarding operating
stages. This mode of output stage destruction results from simul- junction temperatures and relative product life. APEX generally rec-
taneous application of high current and voltage to the conducting ommends operating at a case temperature that keeps maximum
transistor. See Section 6 on SOA and the individual data sheets to junction temperatures at 150C or below.
better understand SOA limits. Absolute Maximum Common Mode Voltage is another rating that
3) Check for oscillations. With low voltage applied and reduced current illustrates the difference between the rated absolute maximum and the
limits in place, set the input signal to zero and connect a wide specified operating range. On many amplifiers, the rated absolute
bandwidth (100 MHz or greater) oscilloscope to the output of the op maximum voltage applied to both inputs simultaneously is equal to the
amp. With the time base set to the microsecond region, check for power supply voltage. However, the linear operating range is 5V to 10V
oscillations present at any amplitude settings. Next, inject a signal less than each power supply rail. This means that inputs exceeding the
into the circuit and monitor the output for oscillations. Excessive linear range specification will not damage the part but the amplifier may
ringing on small signal square wave response indicates marginal not achieve the specified rejection ratio, may start to distort the signal,
stability. or could even latch the output to one of the supply rails.
If an oscillation is found, measure the frequency and amplitude For more information on specifications and limits, see Section 9,
of oscillation. Also note whether the oscillation only shows up on the Amplifier Protection And Performance Limitations, Section 6,
positive or negative half of the output. Refer to Section 10, Stabil- SOA, Section 4, Power Supplies, and the Parameter Defini-
ity, for diagnosing and fixing the cause of instability. tions section.
294
4.0 POWER SUPPLIES 5.0 CURRENT LIMIT
4.1 VOLTAGE SPECIFICATION The primary function of current limit is to keep an amplifier within its
The specified voltage (Vs) applies for a dual supply having equal SOA. See Section 6, Safe Operating Area. Some models of Apex
voltages ( 30V). An asymmetrical (+50V/10V) or a single supply Power Op Amps have an internal current limit, while most of our models
(60V) may be used as long as the total voltage between +Vs and Vs have an adjustable limit that is set with one or two external resistors.
does not exceed the maximum rating. Never allow reverse voltage on Any attempt to limit current with a circuit external to the amplifier
a supply pin. On a dual supply circuit, do not operate with only one must be approached with extreme caution. The pitfalls are generally
supply connected. time related and are often catastrophic. Most power supply current limit
circuits are effective only AFTER stored energy in a large output filter
4.2 POWER SUPPLY BYPASSING capacitor has been depleted. This energy plus energy in local supply
Inadequate power supply can lead to power amplifier circuit oscil- bypass capacitors is often more than enough to destroy the amplifier.
lations. Each supply pin should be bypassed to common with a low Slow response time is also a problem with even the fastest fuses. A
frequency bypass capacitance of 10F per Ampere of peak output 15 second response time to a 200% over current is common. In most
current. Tantalum capacitors should be used, although computer applications the amplifier will give its life protecting the fuse. Even if the
grade aluminum electrolytics can be substituted for operating tem- fuse does blow, the amplifier may still be damaged. The blowing fuse
peratures above 0C. is a mechanical interuption in a current carrying line which can cause
In addition, a high frequency bypass, .1F to .22F ceramic voltage spikes above the supply rating of the amplifier.
capacitor, should be added in parallel with the low frequency bypass
capacitors from each supply rail to common. Refer to Figure 1. In cases 5.1 CURRENT LIMIT PRECISION
where supply line inductance is high, it may be necessary to add 1 to Standard current limit circuitry is not designed to provide a precision
current limit function. A rule of thumb is to allow 20% variation at room
C2 temperature. Furthermore, the current limit varies over temperature.
<2" This temperature dependence is generally shown in a typical perfor-
+Vs C1
mance graph in the product data sheet. Specific values of the nominal
OP current at any given temperature may be calculated by modifying the
AMP 0.65V term of the current limit equation given in Section 5.3 with
C1 2.2mV per degree (Centigrade) of case temperature rise above 25C.
Vs For example, at a case temperature of 125C, this term becomes 0.43V
C2
rather than 0.65V; (650mV(125C25C)(2.2mV)). When working
with high currents, the impedance of PCB traces, lead lengths and
solder joints must be included in the current limit calculations.
C1 = .1 to .22 F, Ceramic Disk, High Frequency Bypass
C2 = 10F/Amp out (peak), Electrolytic/Tantalum, Low Frequency Bypass 5.2 EXTERNALLY ADJUSTABLE CURRENT LIMIT
Models with provisions to adjust current limit externally must have
FIGURE 1. POWER SUPPLY BYPASSING the current limit resistors connected as shown in the external connec-
10 ohms of resistance in series with the high frequency bypass to tion diagram.
dampen the Q of the resulting LC tank circuit. Refer to Figure 1. Current limit should never be set at a value greater than the rated
maximum output current of the power op amp. This maximum is due
4.3 OVERVOLTAGE PROTECTION to the current density limitations of conductors in the package and
The amplifier should not be stressed beyond its Absolute Maximum exceeding it can destroy the amplifier. Also, using a very low resistance
supply voltage rating. The amplifier should be protected against any (such as a jumper wire) will lead to increased bias current in the output
condition that may lead to this voltage stress level. Two common stage. This raises power and temperature, while lowering resistance to
sources of overvoltage are the high energy pulses from an inductive second breakdown, thereby destroying reliability.
Operation without current limit resistors installed (current limit pins
load coupled back through flyback diodes into a high impedance
supply and AC main transients passing through a power supply to left open) can also cause failures, especially with inductive loads. This D
appear at the op amp supply pins. includes even a momentary open circuit while switching current limits
Unipolar devices also protect against reverse polarity. Note that an with mechanical contacts. For the high current series power op amps,
open supply pin can cause supply reversal and sometimes amplifier minimum programmed limits should be 20mA, while 10mA is minimum
destruction. Transient suppressors with a voltage rating greater than for the high voltage, low current series. Open circuits or limits below
the maximum power supply voltage expected but less than the these minimums can cause voltage breakdown of the current limit
breakdown voltage of the amplifier will prevent the amplifier from transistors.
damage.
Transients from the AC mains can be clamped through the use of 5.3 CALCULATING CURRENT LIMIT
MOVs (Metal Oxide Varistors) such as those made by General Power op amps with provisions to adjust current limit externally
Electric, or bipolar TransZorbs. Connect either of these devices across require one or two current limit resistors (RCL) which must be connected
the inputs to the power supply to reduce transients before they reach as shown in the applicable external connection diagram below. Since
the power supply. Low pass filtering can be done between the AC main output current flows through these resistors, wattage ratings must be
and the power supply to cut down on as much of the high frequency considered. For optimum reliability, the resistor values should be set as
energy as possible. Note that inductors used in power supply filters will high as possible. Each resistor and its power dissipation is calculated
pass all high frequency energy and capacitors used in the filter are as follows:
usually electrolytics which have high ESR. Because of this high ESR, 0.65
high frequency energy will not be attenuated fully and therefore will RCL (ohms) = 0.01 *
avoid the capacitor with little reduction. Refer to Figure 2. ILIM (A)
+Vs PRCL(watts) = 0.65 ILIM
* .01 ohms = wire bond and pin resistance
OP POWER ILIM is the value of current limit desired and should be chosen to
MOV FILTER AC provide the amount of protection required for the specific application.
AMP SUPPLY
-Vs For details on choosing safe levels of current limit and the protection/
performance trade offs involved, see Section 6.3, Fault Protection
BIPOLAR Using Current Limit.
TRANSZORB For two resistor current limit schemes, asymmetrical current limiting
VS < VZ < V MAX (OP AMP) (RCL+ RCL) is permissible. For testing without a heatsink, the resistors
should be selected to limit power dissipation in the amplifier to less than
FIGURE 2. OVERVOLTAGE PROTECTION 3W under short circuit conditions.
295
+VS 5.0
TH
t=
(+Vs) Vo
t=
t=
+IN (+15V) E
Tc RMA
5m
1m
0.5
(+15V) 10V = 5V 3.0 =2 L
s
5
m
|5V| = 5V Tc
= 8 C
s
2.0 5C SE
Vo Tc CO
1.5 =1
(+10V) 25 ND
C
I OUT BR
RL 1.0 EA
IN .7 KD
VS steady state O
.5 W
(15V) N
.3
FIGURE 3A. SOURCING CURRENT
.2
+VS 10 15 20 25 30 35 40 50 60 70 80 100
+IN
(+15V) SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE VS VO (V)
FIGURE 4. TYPICAL SOA CURVE
Vo (10V) to avoid entering the region beyond the DC second breakdown limits.
I OUT Operation outside steady state limits in transient SOA regions is
RL
difficult to analyze adequately enough to insure best possible reliabil-
IN
ity. Note that MOSFET power transistors do not have this second
VS (Vs) (Vo) breakdown limitation.
(15V) (15V) (10V) = 5V 6.2 HIGH SOA STRESS CONDITIONS
|5V| = 5V
For resistive loads tied to ground, calculating power dissipation in
FIGURE 3B. SINKING CURRENT the amplifier is reasonably simple. Refer to Section 7.1, DC Power
Dissipation, and Section 7.2, AC Power Dissipation. However,
with reactive loads, the voltage/current phase difference results in
Foldover current limit, discussed in detail in AN #9, Current Limiting, higher power being dissipated in the amplifier.
provides a lower current limit for short circuit conditions while increas- An example of an excessive transient stress condition created by a
ing current limit for load drive. APEX power amplifiers, the PA10, PA12 capacitive load is shown in Figure 5a. In this case the capacitive load
PA04 and PA05, have this feature. Foldover reduces the protection/ has been charged to VS. Now the amplifier is given a go positive
performance trade-off inherent in setting current limit. signal. Immediately the amplifier will deliver its maximum allowed
output current (ILIM) into the capacitor, which can be modeled at time
6.0 SAFE OPERATING AREA (SOA) t=0+ as a voltage source. This leads to a voltage stress across the
6.1 READING THE SOA GRAPH conducting device equal to the rail-to-rail supply voltage. Simulta-
The horizontal axis on the SOA curve, VSVO, defines the voltage neously, the amplifier will be conducting its maximum (current-limited)
stress across the output device that is conducting. It does not define value of current.
a supply voltage or total supply voltage or the output voltage. VSVO is Figure 5b shows a similar transient stress condition for an inductive
the magnitude of the differential voltage from the supply to the output load. For this situation we imagine the output is near the positive supply
across the transistor that is conducting current to the load. Put another and current through the inductor has built up to some value ILOAD. Now
way: if the amplifier is sourcing current, use (+VS)VO. If the amplifier the amplifier is given a go negative signal which causes the output
is sinking current, use (VS)VO. Refer to Figures 3a & 3b. voltage to swing down to the negative supply. However, the inductor
The vertical axis represents the current that the amplifier is sourcing at time t=0+ can be modeled as a current source that requires the
or sinking through the Output pin. amplifier to continue to source ILOAD. This leads to the same situation
The Safe Operating Area curves show the limitations on the power as before, that is, total supply voltage across a device conducting
handling capability of the amplifier. Refer to Figure 4. There are three maximum rated current.
basic limitations: Note also that reactive loads cause higher thermal stress levels than
1) Current handling capability. This horizontal line near the top of the
+Vs +Vs
SOA CURVE represents the limit on output current imposed by
current density constraints in the wire bonds, die junction area and I LIM I LOAD
thick film conductors.
2) Power dissipation capability. This is the total power dissipation Vo = Vs Vo = Vs
capability of the amplifier and includes power due to quiescent
current as well as power dissipated in the output stage. Note that
the product of output current on the vertical axis and VSVO on the
horizontal axis is constant over this line. In other words, this portion
of the SOA curve is a constant power line. For TC = 25C, this line
represents the maximum power dissipation capability of the ampli- 5a: CAPACITIVE 5b: INDUCTIVE
fier at maximum junction temperature using an infinite heatsink. As
FIGURE 5. TRANSIENT STRESS WITH REACTIVE LOADS
case temperature increases, this constant power/thermal line
moves toward the origin. The new constant power line can be resistive loads even under steady state sinusoidal conditions. For
determined from the Power Derating curves on the data sheet. The purely reactive loads, all of the power is dissipated in the amplifier,
case temperature is primarily a function of the heatsink used. For none in the load.
more details, refer to Section 7, Internal Power Dissipation And
Heatsinking. 6.3 FAULT PROTECTION USING CURRENT LIMIT
3) Second Breakdown. Second breakdown is a phenomenon exhib- With a given supply voltage, current limit can be used to keep the
ited by bipolar transistors when they are simultaneously stressed amplifier within its Safe Operating Area. This allows amplifier protec-
with high collector-emitter voltage and high collector current. Non- tion during fault conditions such as shorts to ground or shorts to either
uniform current density in the emitter results in localized heating supply. The cost of protection is lowered output current capability.
and hot spots at the junction. The temperature dependence of For short-to-ground fault protection, set current limit to the value
junction current results in increased current density at the hot spots. given by the intersection of the supply voltage and the DC SOA curve
This concentration of current tends to further increase the tempera- for the appropriate case temperature. Simply find the supply voltage
ture. The process is cumulative, leading to thermal runaway and on the horizontal axis. When the output is shorted to ground, VO = 0;
transistor failure. therefore, VSVO = VS, follow up to the SOA curve intersection and then
across to the output current. Referring to Figure 6, we see that in this
The transient second breakdown lines (t = 0.5ms, t = 1ms, and
example, a 2A current limit provides short circuit protection to ground
t = 5ms) are based on a 10% duty cycle. For instance, in Figure 4, the
at a case temperature of 25C with 30V supplies. Note that better
amplifier may deliver 1.5A at a VSVO of 60V for 5ms but then must wait
heatsinking allows higher values of current limit.
for 50ms before repeating this stress level. It is highly recommended
296
For short-to-either supply protection, set current limit to the value
given by the intersection of the rail-to-rail supply voltage (VSS) and the +Vs
DC SOA curve. This requires a significant lowering of current limit. For
this type of protection , add the magnitudes of the two supplies used, Vo
Vs2 VIN
find that value on the VSVO axis, follow up to the SOA limit for the case
temperature anticipated, then follow across to find the correct value of 4 RL
RL
current limit. Referring to Figure 6, we see that in this example, a 0.7A -Vs
current limit allows short protection to either supply.
PD OUT
It is often the case that requirements for fault protection and
maximum output current may conflict. Under these conditions there Vo
PD OUT = (Vs- Vo)
are only four options. The first is to simply go to an amplifier with a RL
higher power rating. The second is to trim some of the requirements
for fault protection. The third is to reduce the requirement for maximum
output current. The fourth option is a special type of current limit called 0 Vs Vs 3Vs Vs
foldover or foldback. This is available on some amplifiers such as
4 2 4
the PA10 and PA12. For a detailed discussion of foldover current limit
and SOA fault protection refer to AN#9, Foldover Current Limiting. V OUT (relative to Vs)
For an explanation of how to choose current limit resistors to adjust FIGURE 7. DC POWER DISSIPATION VS. OUTPUT VOLTAGE
current limit, see Section 5.3, Calculating Current Limit.
10 ANALYTICAL APPROACH:
1 I MAX (desired)
For analysis the following equations assume the use of symmetric
2 Short to Gnd power supplies and sinusoidal signals. In single supply applications,
3.3 1
3 Short to VS simplify by using equivalent symmetric split power supplies:
2.2 2 2VS2
SOA Violation
Purely resistive loads: PDOUTmax =
1 SOA Limit 2RL
0.7 3
2VS2
Vs = 30 Volts Primarily resistive loads: PDOUTmax =
( < 40) 2ZLcos
0.1 VS2 4
30 10 60 100 Primarily reactive loads: PDOUTmax = cos
Supply to Output, VS-VO (Volts)
( > 40) 2ZL
FIGURE 6. CURRENT LIMIT FAULT PROTECTION
WHERE: VS = |VS+| or |VS| (symmetric supplies)
7.0 INTERNAL POWER DISSIPATION ZL = Magnitude of load impedance
AND HEATSINKING = Phase angle of load impedance
It is important to not confuse Internal Power Dissipation with power Refer to Figure 8 for the relationship between power dissipation and
delivered to the load. Internal dissipation is not equal to load dissipa- peak output voltage.
tion except when the output voltage is 1/2 the supply voltage and the
load is resistive. In this case the power dissipations are equal and
internal power dissipation is at its maximum.
There are two main steps in the heatsink selection process. First, +Vs
the maximum internal power dissipation must be calculated. Sec-
ondly, the maximum desired junction temperature must be chosen and VIN
D
the thermal model used to calculate the required thermal conductance 2(Vs) 2
of the heatsink. 2 RL -Vs RL
(both transistors)
7.1 DC POWER DISSIPATION

Average PD OUT
Calculating power dissipation in an amplifier under DC conditions

with a resistive load is very simple. The first portion of power dissipation
2
is the quiescent power, PDQ, that the amplifier dissipates due to Vs

quiescent current and supply voltage. Multiplying total supply voltage
by maximum quiescent current gives the value of this power dissipa-
tion:
PDQ = IQ (+VS (VS) ) 0 Vs Vs 3Vs Vs

The second portion of internal power dissipation is developed in the 4 2 4
VO PEAK (AC) (relative to VS)
output stage due to delivering load current. This output stage power,
PDOUT, is the output current times the voltage drop across the amplifier, FIGURE 8. AC POWER DISSIPATION VS. PEAK OUTPUT VOLTAGE
VSVO. For a resistive load, maximum power dissipation occurs at VO
= 1/2VS and has a value of: THERMAL MEASUREMENT METHOD:
1) With no power applied, measure TA, ambient temperature.
VS2 2) Using a resistive load, dissipate a known amount of power in the
PDOUT(max) = amplifier. For instance, set VSVO to a DC value and calculate
4RL PINT = ILOAD(VSVO).
Refer to Figure 7 for the relationship between PDOUT and VO. The 3) Measure T = TCTA
total internal power dissipation is simply the sum of these two compo- 4) Calculate RCA from: T
nents, or: RCA =
PDINT (max) = PDQ + PDOUT(max) PDINT
5) Connect the load that you will use in your application and drive the
7.2 AC POWER DISSIPATION amplifier with the typical signal for the application.
With an AC output and/or a reactive load, power dissipation calcu- 6) Measure the case temperature, TC.
lations get quite a bit stickier. Several simplifying assumptions keep 7) Calculate: TCTA
the problem reasonable for analysis. The actual internal dissipation PDINT =
can be determined analytically or through thermal or electrical bench RCA
measurements.
297
15
FAILURE RATE MULTIPLIER

ELECTRICAL MEASUREMENT METHOD #1:
1) Measure the power delivered TO the amplifier from the supply: Bipolar
10
2VSIPEAK 8.0 MOSFET
PIN = 6.0
5.0
2) Measure the power delivered from the amplifier to the load: 4.0 This data has been extracted
POUT = (1/2)VPEAK IPEAKcos 3.0 from the base failure rate tables
of MIL-HDBK-217F, revision of
3) Calculate power left in the amplifier: 2.0 2 December 1991.
PDINT = PIN POUT 1.5
ELECTRICAL MEASUREMENT METHOD #2: 1.0
1) Use a small value current sense resistor between the load and 25 50 75 100 125 150 175
ground to develop a voltage proportional to IL. Use this signal to JUNCTION TEMPERATURE, TJ (C)
drive one channel of the XY display of an oscilloscope.
FIGURE 11. MTTF VS. TEMPERATURE
2) Use the output voltage of the amplifier, VO, to drive the other
channel of the XY display.
possible. Note from Figure 8 that as the output swing is raised above
3) Calculate instantaneous power dissipation in the amplifier for
2VS/, power dissipation drops off significantly, approaching approxi-
several points on the ellipse using:
mately 1/2 of maximum value as the output peak voltage approaches
PDOUT = (VSVO)ILOAD
the supply voltage.
4) Plot the points on the SOA curve and check for violations. Refer to
The thermal resistance problem should be attacked on all three
Figure 9 for test set-up details.
fronts:
1) Buy an amplifier with the lowest possible RJC.
Resistive 2) Use good mounting practices. See Section 8.0, Amplifier Mount-
Load
ing And Mechanical Considerations.
1 3) Use the largest practical heatsink. See Section 7.4, Heatsink
YINPUT Selection.
IL 0
(Amps) RJC, the thermal resistance from the semiconductor junction to the
case of the amplifier, is characteristic of the amplifier itself. It is a
Purely
-1 Reactive function of the power die junction area, substrate material, attach
Load (max. method and package material. The way to obtain maximum reliability
Complex Reactive current at and cool junction temperatures is to buy an amplifier with as low a RJC
Load zero voltage)
RF as affordable. This is usually a major portion of the total thermal
-20 0 +20 resistance budget and reductions here result in significant reliability
RI +V S X INPUT VO (Volts) improvements. This parameter is also a function of frequency, with
power sharing between the two output devices resulting in lower
POWER VO resistance at higher frequency.
V IN AMP RCS is the thermal resistance from the case to a heatsink. This
LOAD Z >>.1 resistance can typically be kept down between 0.1 to 0.2C/W if good
-V S mounting techniques are used. This includes using thermally conduc-
IL CURRENT SENSE tive grease, properly torquing the package, and not using insulation
washers. See Section 8.0, Amplifier Mounting And Mechanical
0.1 V
I L = ------- Considerations, for details.
0.1
The final piece of the thermal budget is RSA, the thermal resistance
from the heatsink to ambient air. This is a very crucial element and
FIGURE 9. AC PDOUT : ELECTRICAL MEASUREMENT METHOD #2 should not be skimped on. A quick glance at an SOA curve or a power
derating curve will show the difference between power limitations of an
7.3 THERMO-ELECTRIC MODEL amplifier with an 85C case and a 125C case. Clearly this shows the
The thermo-electric model, refer to Figure 10, translates power benefit of using the maximum heatsink allowable. One word of caution:
terms into their electrical equivalent. In this model, power is modeled published heatsink specifications can be used as a guideline, but
as current, temperature as voltage, and thermal resistance as electri- actual performance depends significantly on a wide variety of vari-
cal resistance. ables. These include air flow, altitude, configuration, and mounting. It
TJ
is best to verify thermal performance through measurement under
R JC operating conditions.
TC
R CS 7.4 HEATSINK SELECTION
PD
TS Power op amps can be operated without a heatsink only if the
R SA
internal power dissipation is less than 5 watts at 25C ambient. Five
Watts times the typical RJA of 30C/W results in a junction temperature
TA
T J = PD (R JC + RCS + R SA ) + TA rise of 150C. Adding in the 25C ambient results in a junction
temperature of 175C.
The steps to selecting a heatsink are:
FIGURE 10. THERMO-ELECTRIC MODEL 1) Calculate the maximum internal power dissipation, PDINT(max).
Sections 7.1 and 7.2 cover how to calculate PDINT(max) for various
Reliability is a strong function of temperature. Figure 11, based on applications.
data from MIL-HDBK-217F, shows that a device constructed with 2) Determine the maximum junction temperature, TJ max, that will
bipolar transistors, operated at a junction temperature of 175C, will give the level of reliability required for your application. See Section
have a mean failure rate more that ten times higher than a device with 7.3 for details of junction temperature versus MTTF.
a juntion temperature of 25C. A MOSFET based device can be 3) Use the appropriate thermal resistance of the amplifier given on the
expected to fail almost nine times as often over the same temperature product data sheet (RJC(DC) or RJC(AC)) and the appropriate RCS
range. (typically 0.1 to 0.2C/W for thermal grease). See Section 8.0,
There are two approaches to lowering junction temperature. The Amplifier Mounting And Mechanical Considerations.
first is to reduce the internal power dissipation, and the second is to 4) Calculate the maximum allowable heatsink to ambient resistance,
reduce the total thermal resistance. RSA, from: TJTA
Reducing power dissipation can be accomplished by reducing the RSA RJC RCS
supply voltage to no more than what is required to obtain the voltage PDINT(max)
swing desired. This reduces theVSVO quantity to as low a value as
298
5) Choose a heatsink with a RSA lower than or equal to the calculated opposite pins if you are using a mating socket or printed circuit board.
value. Note that the calculation may give a value of RSA that is too If you are wiring directly to the pins, it is best to sleeve all pins. Refer
low to be attainable with commercially available heatsinks. It may to the Package and Accessories Information section of the Hybrid & IC
even result in a negative number! If this happens, first make sure Handbook for further details on sleeving sizes, mating sockets and
you arent excessively padding your assumption values, then cage jacks for PC board mounting of power amplifiers.
consider a higher allowable junction temperature or an amplifier Never drill out the entire area inside the pin circle, drill individual
with a lower RJC. holes for each pin. Often, heatsinking is accomplished with a custom
Example: heatsink or by directly mounting to a bulkhead. These approaches
Given: PA02 Power Op Amp require the use of heatsink thru-holes for the amplifiers pins. For the
VS = 18V 8-Pin TO-3 package, the main path for heat flow occurs inside the
RL = 4 Ohms circumference of 8 pins. Refer to Figure 13. Therefore, a single, large
TA = 25C hole, to allow the 8 pins to pass through, will remove the critical
Application frequency: DC to 5 kHz heatsinking from where it is most needed. Instead, 8 separate #46 drill
Find: APEX heatsink size holes must be drilled.
1) From Section 7.1, DC power dissipation is:
PDINT(max) = PDQ + PDOUT(max)
VS2 4-7 IN-LBS THIN FILM OF THERMAL GREASE
= IQ(VS+ VS) + TORQUE MAX OR APEX THERMAL WASHER
4RL
(18V)2
= 37mA(36V) +
4(4 ohms)
PDINT(max) = 21.6 Watts
2) For conservative design, keep TJ 125C.
3) PA02 data sheet gives RJC MAX, DC as 2.6C/W. For conservative
design, use 0.2C/W as RCS. TEFLON INDIVIDUAL HEATSINK
4) TJ TA SLEEVING PIN HOLES
RSA RJCRCS FIGURE 12. MOUNTING CONSIDERATIONS
PDINT(max)
(12525)C
2.6C/W0.2C/W
21.6W
RSA 1.8C/W
5) Select APEX HS03; RSA = 1.7C/W. Refer to Package and

Accessories Information section of APEX Amplifier Handbook.
8.0 AMPLIFIER MOUNTING AND

MECHANICAL CONSIDERATIONS FIGURE 13. MAIN HEAT FLOW PATH: 8-PIN TO-3 PACKAGE
For Power Op Amp designs, high reliability consists of mechanical
considerations as well as electrical considerations. Proper mounting 9.0 AMPLIFIER PROTECTION AND D
is very important for power amplifiers. Once the proper heatsink has PERFORMANCE LIMITATIONS
been selected as described in Section 7.4, the following mounting
9.1 OUTPUT PROTECTION
techniques should be used.
Attempting to make sudden changes in current flow in an inductive
All APEX metal can amplifiers have an electrically isolated case.
load will cause large voltage flyback spikes. These flyback spikes
This means that mica insulating washers are not necessary and
appearing on the output of the op amp can destroy the output stage of
should not be used. Mica washers are for electrical insulation and
the amplifier. Brush type DC motors can produce continuous trains of
therefore are unnecessary. In addition, they raise thermal resistance
high voltage, high frequency kickback spikes. In addition, mechanical
by as much as 1C/W, seriously degrading reliability.
shocks to a piezo-electric transducer will cause it to generate a
In addition, APEX uses a thin beryllia substrate to get the lowest
voltage. Again, this can destroy the output stage of an amplifier.
possible thermal resistance. While this leads to cool running, high
Although most power amplifiers have some kind of internal flyback
reliability amplifiers, it is important not to run the risk of cracking this
protection diodes, these internal diodes should not be counted on to
substrate. In order to prevent this, two major precautions must be
protect the amplifier against sustained high frequency, high energy
observed:
kickback pulses. Many of these diodes are intrinsic epi diodes that
1) Do not use compressible thermal washers. These are silicon
occur as a result of the manufacture of the power darlington output
rubber based pads such as Silpad. The amount of compressibility
transistor. Epi diodes generally have slow reverse recovery times and
in a washer over 2 mil thick can lead to header flexing, which can
may have large forward voltage drops. Under sustained high energy
crack the substrate. The use of these washers voids the warranty.
flyback conditions, high speed, fast reverse recovery diodes should be
Also, thermal grease has superior thermal properties.
used from the output of the op amps to the supplies to augment the
2) Do not over torque the case. Recommended mounting torque for
internal diodes. See Figure 14. These fast recovery diodes should
the TO-3 8-Pin package is 4-7 in-lbs (.45-.79 N-m) and for the
have reverse recovery times of less than 100 nanoseconds and for
MO-127 Power Dip packages (PD10 AND PD12) is 8-10 in-lbs
very high frequency energy should be under 20 nanoseconds.
(.90-1.13 N-m). Refer to Figure 12. Apply a thin, uniform film of
One other point to note is that the power supply must look like a true
thermal grease or an Apex thermal washer between the case and
low impedance source when current flows in the opposite direction
heatsink. Apply small increments of torque alternately between
from normal. Otherwise, the flyback energy, coupled back into the
each screw when mounting the amplifier.
supply pin, will merely result in a voltage spike at the supply pin of the
Due to dimensional tolerances between heatsink thru-holes and op amp. This would lead to an overvoltage condition and possible
power op amp packages, extreme care must be taken not to let the pins destruction. Refer to Section 4.3 for information on overvoltage
touch the heatsink inside the thru-holes. Do not count on the anodiza- protection.
tion for insulation as it can nick easily, exposing bare aluminum, an
excellent electrical conductor. Use teflon tubing to sleeve at least two
299
+VS 1) Fast rise-time inputs.
2) Signal input while not under power.
NOTE: 3) High impedance output states (current limit, thermal shutdown,
OP FAST Supplies must be sleep mode).
AMP RECOVERY able to absorb 4) Switching within the feedback loop.
DIODES transient enery,
i.e.: low impedance An example of condition 4 is shown in Figure 17a. This configu-
-VS
ration is often used in ATE systems for changing the gain of an op
amp. The amplifiers full scale transition time (microseconds) is
FIGURE 14. OUTPUT PROTECTION faster than the typical relay switching time (milliseconds); therefore
9.2 COMMON MODE VOLTAGE LIMITATIONS when the relay opens the feedback loop, the Aol of the amplifier will
One of the most widely misunderstood parameters on an op amp drive the output to one of the supply rails. In the example shown, the
data sheet is the Common Mode Voltage Range, which specifies output will approach 150V while the relay is still switching. Because
how close an input voltage common to both inputs may approach the 100K feedback resistor has completely discharged its associated
either supply rail. When these limits are exceeded, the amplifier is not rolloff capacitor, the relay will connect 150V directly to the input.
guaranteed to perform linearly. The Absolute Maximum Common Since the Absolute Maximum VID for the PA08 is 50V, the input
Mode Voltage specification on most data sheets refers to the voltage stage will be destroyed.
above which the inputs may not exceed or damage will result to the Effective input protection networks provide two functions:
amplifier. 1) Limit differential voltage to less than the reverse breakdown
There are two cases which clearly illustrate the constraints of voltage of the input transistors base-emitter junction, typically
common mode voltage specifications: single supply operation and ~6V.
asymmetrical supply operation. 2) Limit input transient current flow to less than 150mA.
Example:
The APEX PA82J has a Common Mode Voltage Range of Vs Figure 17b shows an example of an input VID protection network.
10. This implies that if the PA82J is to be operated from a single The diodes should be high speed devices such as 1N4148 and the
supply, both inputs must be biased at least 10 volts above ground. series impedance should limit instantaneous current to a maximum
Figure 15 illustrates an implementation of this which keeps both of 150mA.
inputs above 10 volts for the given range of input voltages. Note that
for single supply operation, the output of the amplifier is never
capable of swinging all the way down to ground. This is due to the 100K
output saturation voltage of the amplifier. K1 .001F
Figure 16 illustrates a very practical deviation from true single
supply operation. The availability of the second low voltage source +150V 500K
allows ground (common) referenced signals but also maximizes the 10K
high voltage capability of the unipolar supply. As long as the amplifier .001F
remains in the linear region of operation, the common mode voltage V IN PA08
will be zero. With the 12V supply the allowed positive common mode V OUT
voltage range is from 0 to 2V. Note the output of the PA81J can swing
all the way to zero now also. The 12V supply in this case need only
-150V
supply the quiescent current of the power op amp. If the load is
reactive or EMF generating, the low voltage supply must also be able FIGURE 17a. GAIN SWITCHING AND VID VIOLATION
to absorb the reverse currents generated by the load.
100K
+210V
2.5K 50K 50K K1 .001F
+150V 500K
+210V +210V
10K 1K
50K .001F
+2.5/10V PA82J V IN PA08

2.5K V OUT
D/A +50/+200V
50K
-150V
FIGURE 17b. GAIN SWITCHING AND VID PROTECTION

FIGURE 15. SINGLE SUPPLY OPERATION: VCM CONSIDERATIONS
50K 10.0 STABILITY

+12V The most common application problem when working with power
0/5V op amps is stability. Although most power op amps are compensated
D/A for unity gain stability, they are frequently required to drive reactive
2K loads, deliver high currents, or use high impedances due to high
PA81J
0/-125V voltage. These conditions make stability more difficult to achieve.
However, EVERY circuit can be stabilized if the guidelines given
-130V here are followed. Table 1 provides a troubleshooting guide for
stability problems. The Probable Cause / Possible Solution Key
FIGURE 16. NON-SYMMETRICAL SUPPLY OPERATION gives insight into the origin of the problem and provides guidance as
to the appropriate fix.
9.3 DIFFERENTIAL INPUT VOLTAGE LIMITATIONS
AND PROTECTION
Exceeding the Absolute Maximum Differential Input Voltage speci-
fied on the data sheet can cause permanent damage to the differen-
tial input stage. Failure modes range from increased VOS and VOS
drift, IB and IB drift, and input offset current, up to input stage
destruction. Although the differential input voltage (V ID) under nor-
mal closed loop conditions is microvolts, several conditions can
cause it to be in the Volt range. Causes of VID:
300
CONDITION AND Oscillates unloaded? RI RF
PROBABLE CAUSE Oscillates with VIN = 0?
TABLE Loop Check
fixes oscillation?
fosc Probable Cause(s) V IN +V S
Oscillation Frequency (in order of probability) Rn
CLBW fosc UGBW N Y N A, C, D, B
CLBW fosc UGBW Y Y Y K, E, F, J
VO
CLBW fosc UGBW N Y G R1
Rn
fosc CLBW N Y Y D 10 -V S
fosc = UGBW Y Y N* J, C
FIGURE 18. LOOP CHECK CIRCUIT
fosc<< UGBW Y Y N L, C
fosc > UGBW N Y N B, A
RF
fosc > UGBW N N** N A, B, I, H
CLBW = Closed Loop Bandwidth V OUT

UGBW = Unity Gain Bandwidth RL
See Figure 18 for loop check circuit. RI RB
Indeterminate; may or may not make a difference. V IN -V S
*Loop check (Figure 18) will stop oscillation if Rn << |Zcf| at UGBW. +V S
**Only oscillates over a portion of the output cycle.
KEY TO PROBABLE CAUSE / POSSIBLE SOLUTION FIGURE 19. BASIC REQUIREMENTS FOR STABILITY
A. Cause: Supply feedback loop (insufficient supply bypassing).
RF
Solution: Bypass power supplies. See Section 4.2.
B. Cause: Supply lead inductance.
Solution: Bypass power supplies. See Section 4.2. +V O
RI
C. Cause: Ground loops.
Solution: Use Star grounding. See Figure 19. Rn VO
D. Cause: Capacitive load reacting with output impedance (Aol pole). Cn
Solution: Raise gain or use input RC compensation network.
See Section 10.2.1 .
E. Cause: Inductor within the feedback loop (noise gain zero). V IN -V O
Solution: Use alternate feedback path. See AN#5, Precision
Magnetic Deflection, or AN#13, VI Conversion.
F. Cause: Input capacitance reacting with high RF (noise gain zero).
Solution: Use Cf in parallel with Rf. (Cf =~Cin). Do not use too much FIGURE 20. INPUT R-C NETWORK COMPENSATION
Cf, or you may get problem J.
G. Cause: Output to input coupling. The question is often asked about why a capacitor from output to
Solution: Run output traces away from input traces, ground the inverting input is used. This is often a result of trying that technique and
case, bypass or eliminate RB (the bias current compen- noting that oscillation stopped. Oscillation with the complementary
sation resistor from IN to ground) output power op amp is most often the result of capacitive effects in the
H. Cause: Emitter follower output reacting with capacitive load. load and the accompanying phase lag. Certain values of feedback
Solution: Use output snubber network. See Section 10.2.3 .
I. Cause: Composite PNP output stage with reactive load.
capacitance will create a phase lead in the feedback that will compen-
sate the load caused lag. Success with this method depends on
D
Solution: Use output snubber network. See Section 10.2.3 . capacitor value and therefore may not work with all amplifiers in
J. Cause: Feedback capacitance around amplifier that is not unity production. The problem is that this is a matching condition that will not
gain stable (integrator instability). always correctly match over a wide range of devices and operating
Solution: Reduce Cf and/or increase Cc for unity gain stability. conditions. This also creates an increase in high frequency feedback.
K. Cause: Insufficient compensation capacitance for closed loop This technique is most useful in high speed amplifiers to compensate
gain used. for input capacitance effects and achieve best settling time.
Solution: Increase Cc or increase gain and/or use input RC The R-C across the inputs can compensate for just about any type
compensation network. See Section 10.2.1. of condition causing loop instability, either inductive or capacitive. The
L. Cause: Servo loop stability problem. R-C network is intended to provide simple resistive attenuation of the
Solution: Compensate the front end or servo amplifier. feedback. If the wrong values are used, the R-C network could be
reactive at high frequencies and introduce additional phase lag into the
10.1 BASICS OF STABILITY feedback. This will aggravate oscillation problems. Two methods will
Some basic practices must be followed to ensure stability. Proper be shown for selecting the component values:
ground practices are mandatory and are illustrated in Figure 19.
Improper grounding can lead to oscillations near the unity gain GRAPHICAL METHOD (Refer to Figure 21)
bandwidth frequency of the amplifier. Proper bypassing of power 1) Measure or predict fOSC.
supplies is also illustrated in Figure 19. The local bypassing close to 2) Determine Aol, fOSC, Aol at fOSC (from amplifier small signal
the amplifier with a small electrolytic and ceramic capacitor insure response curve)
good high frequency grounding of the supply lines. The internal phase 3) Set ratio of RF/Rn = 10 x Aolfosc
compensation on op amps will be referred to one of the supply lines 4) From small signal response curve, find fINT at gain of RF/Rn.
and this is the reason for the importance of good local bypassing. 5) Select Cn such that: f3dB= fINT/4
4
10.2 METHODS OF CONTROLLING OSCILLATIONS Cn =
2Rn fint
10.2.1 INPUT R-C NETWORK COMPENSATION Example. (Refer to Figure 21)
The first method for stabilizing an oscillating amplifier is shown in Given: PA07 power op amp; ROUT = 2.25 ohms
Figure 20. Capacitive load CL = 700nF; RF = 10K, RI = 10K;
The basic theory of an oscillator states that there must be sufficient noninverting gain of 2 (Refer to Figure 21)
gain and sufficient feedback to sustain oscillation. This connection is
intended to attenuate feedback more than the open loop gain at the Find: Input R-C compensation network for stability.
frequency of oscillation.
301
Graphical Method: RF
ROUT and CL form an additional pole in the PA07 Aol.
1) Plot Acl on modified Aol. fOSC will occur at approximately 200kHz, +V S
using rate of closure stability criteria. RI
2) AolFOSC = 18dB = gain of 7.9 3-10H
3) RF/Rn = 10 AolFOSC V IN
10K/Rn = 10 x 7.9 = 79 = 38dB > Rn = 127 LI
4) fINT at 38dB = 11kHz CL
4 4 Rd
5) Cn = = = 456nF -V S
2Rnfint 2 (127) (11kHz)
FIGURE 22. CAPACITIVE LOAD ISOLATION
f3dB = fint/4 = 11kHz/4 = 2.75kHz
Before input R-C compensation was added bandwidth was about RI RF
200kHz, but system oscillated. After input R-C compensation was
added, bandwidth was about 11kHz and system was stable. Using the V IN
+V S
rate of closure criteria for stability, one can reiterate and trade off RF/
Rn with f3dB for improved bandwidth.
VO
SMALL SIGNAL RESPONSE
120 RS 1-100
Modified Aol CS
100 .1-1F
-V S
1 Acl with Input R-C Comp

80
2 Acl w/o Input R-C Comp FIGURE 23. OUTPUT R-C NETWORK ("SNUBBER")
60
F int
40 F3dB
10.3 COMMON SOURCES OF INSTABILITY
20 The following is a list of the most common instability situations
1
2 reported:
0 1) Ungrounded cases can cause oscillations, especially with faster
Fosc
amplifiers. The cases of most APEX metal can amplifiers are
20
1 10 100 1K 10K .1M 1M 10M electrically isolated to provide mounting flexibility. The case is in
FREQUENCY, F (Hz) close proximity to all the internal nodes of the amplifier and can act
as an antenna. Providing a connection to ground prevents noise
FIGURE 21. INPUT R-C COMPENSATION: GRAPHICAL METHOD pickup, cross-coupling or positive feedback leading to oscillations.
Some models have heatsink tabs connected to VS, serving the
EMPIRICAL OR BENCH METHOD: same purpose as long as VS is clean.
1) Use large resistance between inputs; reduce until oscillation 2) A standard inverting circuit includes an impedance matching resis-
stops. tor in series with the non-inverting input to take advantage of the
2) Introduce a capacitor in series with resistor. If oscillation resumes, improved input offset current specification. The high impedance
increase capacitor until it ceases. If oscillation doesnt occur, input becomes an antenna, receiving positive feedback, causing
decrease capacitor until it does; then increase capacitor just oscillation. Calculate the errors without using the resistor (some
enough to stop oscillation. amplifiers have equal bias and offset currents negating the effect of
Note: Input R-C Compensation network will only solve local loop the resistor). If the resistor is required, bypass it with a ceramic
stability problems and not power supply bypassing or other sources capacitor of at least .01uF.
of instability! 3) Large electrolytic or tantalum capacitors are installed close to the
amplifier pins as recommended, but small ceramic bypass capaci-
10.2.2 CAPACITIVE LOAD ISOLATION tors are omitted. The circuit may oscillate because the high fre-
The inductor in series with the output serves to isolate the amplifier quency impedance of the large capacitors is not low enough to
circuit from capacitor loading. The feedback should be taken prior to decouple the power supplies.
the inductor. Refer to Figure 22. The inductor is a small value, 4) A prototype circuit is checked out and approved. A printed circuit
generally from 5 to 10 microhenry, wound from heavy gauge wire. The board is built and all modes of operation test okay. A step and repeat
inductor may be paralleled with a resistor, from 5 to 100 ohms, to kill technique then uses this same artwork to generate a multiple
any resonance effects. amplifier board. When tested, every amplifier on the board oscil-
This technique is similar to using a resistor in small-signal op amp lates. Cross coupling through the supplies is a major problem in
designs to accomplish the same function. The inductor is used to multiple amplifier circuits. Use lots of bypass capacitors, ground the
reduce power losses to a minimum over the useful frequency band. case and include an input R-C compensation network as described
in Section 10.2.1 if possible.
10.2.3 OUTPUT SNUBBER NETWORK
Hybrid complementary output amplifiers wont usually oscillate as a 10.4 A FINAL STABILITY NOTE
result of inductive loading. This is one of the advantages of a full When youre at your wits end trying to solve an oscillation problem,
complementary output stage. Asymmetrical output stages, such as dont give up because you have it down to an acceptably low level.
those required in monolithic power amplifiers, do not have this luxury. A circuit either oscillates or it doesnt, and no amount of oscillation is
Usually oscillations due to this will occur at frequencies beyond the acceptable. Apply these techniques and ideas under your worst case
unity gain bandwidth of the amplifier. Compensation for this is a simple load conditions and you can conquer your oscillation problems.
R-C from output to ground which insures a low impedance resistive
load for the amplifier at high frequencies. Refer to Figure 23. Resis- The APEX Applications Hotline
tance will run from 10 to 100 ohms, and capacitance will generally be The APEX Applications Hotline provides technical support all the
between .1 to 1 microfarad. way through your project. In many cases, specific failure prevention
The only observed case of an APEX complementary hybrid ampli- can be suggested immediately. In some instances we will need the
fier showing instability into inductive loading is the PA02 in high speed amplifier to be sent to APEX for a free failure analysis. The results of
inductive load applications. The instability is a result of heavy local the analysis can pinpoint the area of damage which then narrows down
feedback in the output stage. the circuit problem.
omissions. HOTLINE:
without notice.
AN1U REV. B JANUARY 1998 1998 Apex Microtechnology Corp.
302
OPTOELECTRONIC POSITION CONTROL
APPLICATION NOTE 2
CL RF1 CF
+32
RL RF2 RCL+
V = 28
EMF = 14V
.68 RW = 14
PA07 MOTOR
RCL
+V
.68
LIGHT
32V
-V
PD1 PD2
FIGURE 1. SEQUENTIAL POSITION CONTROL
D
INTRODUCTION
Power Op Amps are ideally suited for position control because their must be small enough to allow drive reversal before the index point
response time is fast compared to any mechanical drive train. The passes the second photodiode or the system will continue on to the
optoelectronic technique of position control can move to and maintain next index. Very small values of CF can cause severe overshoot or
fixed index points on linear or rotary motion components while adding oscillation leading to motor burnout and/or drive train failure. RF1 and
no linkages or independently moving parts. The resulting system RF2 are required to stabilize the control loop at the unity gain point and
features high reliability, accuracy and repeatability. If the integration of to minimize overshoot. RL and CL form a lead network which may be
photodiode currents is required, select a power amplifier with an FET included to improve response time by enabling the amplifier to modify
input to maintain very low bias current levels such that the integrating the motor drive based on a change of the sensor output. In this manner,
capacitor voltage will remain constant during periods when both a braking force can be applied to the motor prior to reaching the index
photodiodes are not illuminated. Further selection criteria should be point. The motor shown in Figure 1, having EMF of 14V, will apply a
based on motor ratings and/or available power. 46V stress across the conducting output transistor when reversed.
With a duration longer than 5ms, the steady state secondary break-
SEQUENTIAL POSITION CONTROL down line of the SOA for the PA07 curves requires the current limits to
be set to 1A. See PA07 data sheet.
In the circuit shown in Figure 1, the PA07 integrates the differential
output of the pair of photodiodes and drives the motor in the proper
direction until the photodiode currents are equal. This differential SINGLE POINT POSITION CONTROL
configuration negates the well known temperature and time instabili- A variation of the above technique shown in Figure 2 can be used
ties of optoelectronic devices. To move between index points, a fixed to return a wheel to a single index point after rotating in either direction.
input current is momentarily switched to the amplifier input causing the The low inertia, fast response system will take the shorter route to the
amplifier to drive the motor in the desired direction. The charge on CF index point when switched from run to stop. The PA12A was selected
will maintain motor drive as the input current is switched off prior to for this application because it provides high power while keeping bias
reaching the index point. As the first photodiode is illuminated, its current levels low with respect to the photodiode currents. To improve
output reinforces the current direction of motion. As the second response time, the lead network compensates for motor response
photodiode is illuminated, its current will reverse the motor drive, lagging behind any change in drive voltage. A run control current of
causing the system to lock to the index point. sufficient amplitude to override the photodiode currents is fed to the
As motor response and system inertia vary widely, CF and RF must amplifier inverting input. Removal of this current restores control to the
be selected for the individual application to provide proper damping. CF photosensors.
303
CL 1F RL DIGITAL INTERFACING
For systems with digital control, Figure 5 illustrates a method not
LEAD NETWORK
requiring generation of bipolar control signals thus saving the cost of
RF1 100K RF2 47K digital to analog conversion. When logic lines are low, the signal diodes
RUN/STOP CONTROL will not conduct. This condition leaves control to the photodiodes. A
+15V high level on line 2 will cause current to flow to the summing junction
RCL+
and the amplifier will swing negative. A high level on line 1 will raise the
.06 summing junction voltage above ground, and the amplifier will swing
positive. Select a resistance value such that a high logic level will
PD1
PA12A provide at least twice the maximum current from each photodiode to
PD2 insure control override regardless of photodiode signals.
LIGHT
RCL
D1
15V .06 LINE 1
R1
MOTOR PD1 PD2 4.7K
POWER
OP AMP
FIGURE 2. SINGLE POINT POSITION CONTROL
POSITION CONTROL MASK R2 D2 R3

Figure 3 shows details of the wheel preparation and sensor place- LINE 2 4.7K
ments at the stop index. Arrows indicate direction of rotation when the 4.7K
corresponding photodiode has the higher output. While it is theoreti- FIGURE 5. DIGITAL INTERFACE
cally possible to achieve a stable position on the opposite side of the
wheel, system noise or a slight movement will imbalance the equal
photodiode currents and the higher current sensor will receive even DUAL SENSORS
more light. This causes the wheel to seek the desired index point. For applications requiring high precision, the use of a dual element
Masking of the wheel at an angle to the radial softens the control position sensing PD1(Figure 5) will allow smaller beam size, tighter
function and prevents overshoot. beam control and provide better thermal equilibrium. The specified
resolution of the detector recommended for this application is better
than .0127mm (.0005 inch). The detector is a three terminal device
requiring a current inverter as shown in Figure 6 to achieve the
differential configuration. Two equal resistors, R1 and R2, should be
scaled to the maximum photodiode current and swing capability of the
signal amplifier.
R1 CF
SIGNAL R2 POWER
OP AMP OP AMP
FIGURE 3. SINGLE INDEX POINT DISK
SPOT SIZE
FIGURE 6. CURRENT INVERSION
Optimum relationship of beam size to active areas of the photode-
tectors is shown in Figure 4. A centered beam should illuminate half the
photosensitive area of each diode. Too large a beam will produce no
change of sensor output for a range of positions, while a smaller beam
will produce a nonlinear transfer function near the center line between
the photosensitive areas. This makes selection of CF to dampen the
circuit difficult and requires a higher intensity light source.
FIGURE 4. BEAM-SENSOR ALIGNMENT
without notice.
304
BRIDGE CIRCUIT DRIVES
APPLICATION NOTE 3
.16mA 10V+
.16mA
R1 +35V
T
10K
R2 0/10V
4.99K C1 VTACH
R3
+35V +35V 150
+5V 5V R4 R5 VREF
.08 29.5 5.5 .065
PA12A PA12
A1 M A2
V = 24V R7
R6 EMF = 12V
R = 1.2 .065
.08 C2
R9
VCM 150
R11 .1 F R8
4.99K 5.9V
R10 2K
RV1 2K R12 C3
250 10K 1.0F
NOTE: VCM +VR1 +VTACH = VREF

FOR VIN = +5 : 5.9V + 1.6V + 10V = 17.5V
FIGURE 1. BI-DIRECTIONAL BRIDGE FOR A SINGLE SUPPLY

D
INTRODUCTION
Two power op amps configured in a bridge circuit can provide One sixth of any supply voltage variation will appear equally at both
substantial performance advantages: inputs of the amplifier. However, the common mode rejection (CMR)
of the op amp will reduce its response by four orders of magnitude at
1. Bi-directional output with a single supply low frequencies. The low pass function of C3 insures optimum rejec-
2. Twice the output voltage tion by keeping the common mode inputs in the low frequency
3. Twice the slew rate spectrum. The common mode voltage (CMV) range of the amplifier
4. Twice the output power sets the minimum common mode bias at the inputs of A1. The circuit
5. Half the power supply requirement shown provides a nominal 5.9V from the supply rail (ground) which
allows power supply variations to 10% below nominal.
Low current outputs can reach the kilovolt range or mulitple ampere For the actual input signal, C1, R1, R2, and A1 form an integrator
outputs of hundreds of volts can be obtained. To achieve these levels (non-inverting input is constant). With the control voltage applied
of performance, both terminals of the load must be driven and extra across R2 and the tachometer voltage applied across R1, integration
components are required. forces the motor speed to be proportional to the input voltage. The
value of C1 must be selected for proper damping of the total system
BI-DIRECTIONAL DRIVE ON A SINGLE SUPPLY which includes the mechanical characteristics of the drive train.
Resistors R4 and R6 set current limits of A1 to 7.5A. When A1
Figure 1 depicts a bi-directional motor speed control using a single current limits, A2 will reduce its output voltage equal to the voltage
supply which features ground referenced bipolar input signals. A mid- change of A1. By insuring A1 will limit prior to A2, power stress levels
supply reference created by R3 and R9 establishes the DC operating of the two amplifiers are equalized. In addition to amplifier protection,
levels for A1 and A2. Inverter A2 drives the load equally in the opposite this programmability is being utilized to limit the temperature rise in the
direction with respect to the output of input amplifier A1. This configu- motor, thereby increasing expected life of the system. Maximum
ration places both load terminals at the reference voltage with a zero continuous load rating of the motor shown is 10A and locked rotor
input condition and prevents premature saturation of either amplifier. (stall) current is 20A. Since locked rotor ratings generally refer to
To understand the operation of the circuit, consider A1 as having abnormal conditions, the motor is being used near capacity while
two sets of inputs: maintaining a comfortable safety margin for motor and drive circuit.
The key to accuracy of this circuit lies in matching the division ratios
1. Voltage dividers from the supply voltage to establish common mode from the reference voltage to ground for both the inverting and non-
bias. inverting inputs of A1. The inverting side division ratio is affected by the
2. Actual input signal and tachometer feedback. impedances of the control signal and tachometer. Normally, the
305
impedance of a voltage output DAC and the winding impedance of the +150V
tachometer are negligible. This allows use of cost effective 1% RV1
R2 GAIN
resistors and requires only trimpot RV1 to provide precision adjust- 10K
ment. Ratio match errors will appear as tachometer output errors. 20K C1
These errors will be of a size equal to the ratio of mismatch times the R3
R1 95K
reference voltage. 50pF
1/2W
The second major accuracy consideration of this circuit is the 1K A1
voltage offset of A1. As this error will appear at the tachometer at a gain PA84
of three, the PA12A was selected for its improved specification of 3mV
compared to 6mV for the regular PA12. 2.5V
p-p
R5
Changes of input voltage range, RPM range or tachometer output 100K
R4 C2 150V 1/2W
ratings are easily accommodated. Lowering the values of R1 and R12 R6
1K
(ratio match still required) will re-scale smaller tachometer voltage .47 47K
F
0/25V +150V
25 R7
T 20K C3 R8
10K 175 100K
+12V R9 50pF 1/2W
50 1K A2
C4 PA84
10K A1 RV2 .047F
10K
5V
17.5V 150V
CTR
REF
12V
10K 8.75V 10K
FIGURE 2. HIGH OUTPUT TACHOMETER FIGURE 3. ELECTROSTATIC DEFLECTION AMPLIFIER
spans or lower RPM ranges to the 5V input level. While increased
input signal levels could be re-scaled in the same manner, increasing 2. Only 15V power supplies are available in the system.
R2 and R11 provides the required re-scaling with the added benefit of
lowering control signal drive requirements. The bridge circuit can drive almost double the single power supply
Higher voltage tachometer voltage spans require a different ap- voltage, thereby eliminating the need of separate supplies solely for
proach to re-scaling due to the CMV limitations at the inputs of A1. CRT deflection. The maximum transition time between any two points
Figure 2 illustrates a technique using a 25V tachometer which will is 100s for display ratings of:
maintain adequate CMV for A1 with supply voltages down to 20V.
Calculations for the divide by five network at the tachometer includes Yoke inductance = 0.3mH
winding impedance to achieve accurate scaling to the 5 input signal. Full scale current = 3.75A
For error budgets, this factor of five must be applied to both the ratio DC coil resistance = 0.4 ohms
mismatch errors and voltage offset errors as above. Total gain for
calculating offset errors will be 10. The voltage required to change the current in an inductor is
proportional to current change and inductance, but inversely propor-
ELECTROSTATIC DEFLECTION tional to transition time.
The cathode ray tube (CRT) shown in Figure 3 requires 500Vpp V = di*L/dt
nominal drive. Allowing for a 5% gain error plus a 10% (of full scale) V = 7.5A*0.3mH/100s = 22.5V
centering voltage tolerance, brings the desired deflection voltage
swing to 575Vpp. Two PA84 high voltage power op amps provide this The Apex low voltage power op amp PA02 is an ideal choice for this
differential voltage swing. Slew rates of 400 volts per microsecond at circuit due to its high slew rate and ability to drive the load close to the
the CRT enable the beam to traverse the face plate in less than 1.5 supply rail. The average output voltage swing of the circuit during the
microseconds.
The gain of A1 is set by (R3+RV1)/R1 at 100. The circuit provides
for both gain adjustment (RV1) and beam centering (RV2). For proper
scaling, R4 and R6 reduce the centering control voltage of trimpot RV2
to 250mV. C2 provides the desired low AC impedance to ground to R1A R2 R3
enhance stability and eliminate noise pickup. A2 inverts the output of 1.5K 1.5K 1.5K
A1 at unity gain (set by R8/R5), to yield an overall gain of 200 for single +15V +15V
ended input signals measured at the differential output. R9 and C4
R4 R5
constitute a second input to A2 with an AC gain of 100 (R9/R8). Using
ground as an input has no direct signal contribution, but it does allow 2V R1B .15 .12
both amplifiers to use the phase compensation recommended at a DAC
1.5K A1 A2
gain of 100 (20K, 50pF), thereby achieving a large power bandwidth PA02 PA02
of 250kHz.
R6 R7
TRANSIMPEDANCE BRIDGE FOR .15 .12
R8
MAGNETIC DEFLECTION 15V .5 15V
The circuit shown in Figure 4 drives the electro-magnetic deflection RC1 R1D YOKE
yoke of a precision x-y display. Two factors constitute the design .3mH
1.5K 1.5K
challenge of this circuit: R9 C1
1. Greater than 15V drive levels are required to change current 3.3K 10pF
magnitude and polarity to achieve fast endpoint-to-endpoint dis-
play transition times.
FIGURE 4. ELECTROMAGNETIC DEFLECTION AMPLIFIER
306
beam transition time will be greater than 26V. The configuration CONCLUSION
shown in Figure 4 utilizes current sense resistor R8 to implement a
voltage controlled current source for A1 while A2 functions as an Bridge circuits can make the difference when performance re-
inverter to double the voltage drive to the load. quirements exceed voltage limitations of either the available power
In detail, the differential input configuration of A1, and R1A supplies or the power op amps. The input section of these circuits
through R1D, feeds back the output voltage of A1 as a common consists of a standard amplifier circuit for driving a single ended load.
mode signal. In this manner, the amplifier CMR and divider ratios The added amplifier serves merely as an inverter. It doubles drive
maintain a transimpedance function by removing the output voltage voltage by providing an equal and opposite output, thereby making
of A1 from a first order calculation of performance. Since R1A/R1B the output fully differential. The performance increases usually
and R1C/R1D must divide this output voltage equally for both outweigh the increased cost and complexity.
amplifier inputs, these resistors form a precision resistor network
with initial matching and temperature tracking of the divider ratios.
Mismatch errors can be modeled as control voltage errors equal to
the percent of mismatch times the output voltage of A1. The voltage
proportional to output current developed by R8 is fed back as a
differential signal for comparison with the input voltage.
As the current to voltage phase relationship of the inductive load
changes with frequency, the conversion function of R8 introduces
phase shift up to 90 into the feedback circuit. At high frequencies,
it is possible for the sum of the inductive phase shift, plus the
amplifier phase shift, to equal 180 while the amplifier still has a gain
of unity. The series RC damping network placed in parallel with the
inductive load reduces its phase shift and thereby eliminates the
potential for oscillations.
EFFICIENT USE OF POWER SUPPLIES

To illustrate the advantages of the bridge circuit, Figures 5 and 6
show two high performance audio amplifier designs with equal
output power, but substantially different supply requirements. In the
circuit of Figure 5, the instantaneous load current will appear on only
one supply rail. This means each supply rail must support the total
wattage requirement and utilization is only 50% at peak outputs. In
contrast, the equal and opposite drive characteristic of the bridge
circuit shown in Figure 6 loads both positive and negative supply rails
equally during each half cycle of the signal. This improved utilization
reduces size, weight and cost of the power supply for the circuit in
Figure 6 even though input and output power ratings are essentially
equal.
R1 R2
C1 8.2K 150K
1F +30V
R4
R3 .18 D
C2 1K
C3 PA10
.001F
1F R7 R5
8.2K
30V .18
PWR = 30V AT 3A = 180W
FIGURE 5. STANDARD AUDIO AMPLIFIER
R1 R2 R3 150K
18K 150K R4 150K
C1
+15V +15V
.47F
R5 R6
R7 .2 .16
C2 2.2K R8
A1 A2 2.2K
C4 1nF PA02 PA02
8 C3 1nF
.47F R9 R10
R11
18K .2 .16
15V 15V
POWER = 15V AT 3A = 90W
FIGURE 6. BRIDGE AUDIO AMPLIFIER
however, FAXis(520)
ORDERS (520) 690-8601
AN3U REV. B FEBRUARY 1998 1998 Apex Microtechnology Corp.
307
PRECISION MAGNETIC DEFLECTION
APPLICATION NOTE 5
INTRODUCTION
Closed loop power op amp circuits offer distinct advantages in Weighing these trade-offs between errors and efficiency in the
current control over open loop systems. Using a power op amp in the selection of RS value will produce the optimum choice for each
conventional voltage to current conversion circuit, the negative feed- application. The voltage drive requirements will then be defined by
back forces the coil current to stay exactly proportional to the control inductance, transition times and current. This display must operate at
voltage. The resulting accuracy makes many new applications fea- 50Hz or 60Hz with retrace times of 730s and coil currents of
sible. For example, by placing the non-linear impedance of the 2.25AP-P.
deflection yoke inside the feedback loop, steady state positioning, The drive voltage required to change the current in an inductor is
which is difficult, if not impossible, to achieve with open loop circuits, proportional to both current change and inductance, but inversely
can easily be implemented with a power op amp. In addition, sweep proportional to transition time.
systems with substantially improved linearity can be designed using
power op amps. VDRIVE = dl*L/*dt (1)
Typical applications include: heads-up displays, which require VDRIVE = 2.25AP-P*6.5mH/15ms = .98V (sweep) (2)
random beam positioning or E-beam lithography; and other complex VDRIVE = 2.25AP-P*6.5mH/730s = 20.03 (retrace) (3)
data displays which can achieve the needed accuracy with a power op
amp. Moreover, the versatility and ease of use of power op amps will To determine the power supply levels, add the supply-to-output
help speed up the design process while at the same time reducing differential rating of the power op amp (from the Amplifier Data Sheet)
development cost. The final result will be a more accurate and reliable and the voltage dropped across the combined values of the sense
display using fewer parts. resistor plus the coil resistance, to these drive requirements to arrive
at +26V and -7V as follows:
HIGH RESOLUTION AND HIGH EFFICIENCY
VDROP = 1PK* (RS + RL) (4)
+26V VDROP = 1.125APK* (.5 + 3 ) = 3.94V (5)
VS = VDRIVE + (VS - VO) + VDROP (6)
VS = .98V + 2V + 3.94V = 6.92V (sweep) (7)
VS = 20.03V + 2V = 3.94V= 25.97V (retrace) (8)
47F .1F
2 RCL+ Caution should be exercised when using asymmetric power sup-
6 .47 plies, because the inductive load has the potential to store energy from
1
.9VP-P the higher supply. This could be initiated by an abnormal condition
3 causing the high output voltage to remain on the yoke longer than the
PA02
5
8 normal retrace time. After such an occurrence, the collapsing mag-
R CL .6.5mH
CF 3 netic field would discharge the stored energy into the lower voltage
7 .47 supply via the inductive kickback protection diodes in the power op
1.8A
50pF p-p amp. This will produce a voltage transient on the supply rail with its
47F .1F RD amplitude a function of stored energy and the transient impedance of
2K the power supply. If this transient added to the supply voltage exceeds
7V the rail-to-rail voltage rating of the amplifier, the result will be destruc-
RF tive. In such cases, a zener clamp on the amplifier output should be
used.
1K A note of caution when using modular construction. Instruction
L* 1 RS
YOKE DRIVER: V = manuals always specify, power down first, then remove the
t .5
module. However, because this doesnt always happen, protective
FIGURE 1. HIGH CURRENT ASYMMETRICAL SUPPLY action should be taken. The mechanical break of the connection to any
inductance, coil or wire, causes high voltage flyback pulses. The
The vertical deflection circuit of Figure 1 was designed to drive a stored energy must be absorbed somewhere. Its much better to use
high efficiency RCA CODY ll tube. The PA02 was selected for this the zener clamp than to risk the op amp.
configuration because of its exceptional linearity and other advan-
tages such as high slew rate, fast settling time, low crossover distor-
tion, and low internal losses. All of these advantages contribute to a
STABILITY CONCERNS
superior resolution display. Since the current control capabilities of this circuit rely on feedback
The key to this circuit is the sense resistor (RS) which converts the from the current-to -voltage conversion sense resistor, phase shift due
yoke current to a voltage for op amp feedback. With the feedback to the inductance of the yoke will be evident in the feedback signal.
applied to the inverting input and the position control voltage applied Because the phase shift approaches 90 on a perfect inductor and the
to the non-inverting input, the summing junctions virtual ground phase margin of an op amp is always less than 90, design adaptations
characteristic assures the voltage across RS is equal to the input are required to prevent oscillation.
voltage. Thus, the highly linear control of the voltage across RS insures The network consisting of RD, RF and CF, serves to shift from a
accurate beam positioning. current feedback via RS to a direct voltage feedback at the upper
The value assigned to RS has significant impact on the performance frequencies. This bypasses the extra phase shift caused by the
of this circuit. All op amp input errors such as voltage offset, imperfect inductor. In selecting component values for this network, RF should be
common mode rejection, offset drift, etc., will appear across the sense much larger than RS, but should not exceed 1K for the PA02,
resistor and produce an error; therefore, the RS should be as large as because the input capacitance of the op amp would otherwise add
possible to insure that errors will be small when translated into current. phase shift. Next select RD to properly dampen the circuit at the unity
Very large values of RS will reduce these errors to a point of insignifi- gain frequency. Generally, its value is a multiple of RF, a safe starting
cance. Unfortunately, on the downside, the voltage drive capability will value is 2 * RF. Select CF for a 3dB corner frequency with RD at 1/3 the
be diminished and circuit power dissipation will increase because the unity gain frequency of the amplifier. For the PA02s bandwidth of
total coil current flows through the sense resistor. 4.5MHz, the CF should be 50pF.
308
+73V voltage required to achieve the retrace di/dt. From time A to time B, the
amplifier is running at the slew rate limit. The current in the yoke starts
to track the input voltages at time B. From time B to time C, the output
voltage produced is the sum of equation 3 plus the value of instanta-
47F .1F neous IR drops (Equation 11 indicates the final value).
RCL+
3 The abrupt slope change of the input waveform at point C, again
4 2 .2 puts the amplifier in slew rate limit until the output current is propor-
2.5VP-P tional to input voltage according to equation 9, plus IR drops. At point
1
5
PA10A D, the equation is satisfied and the amplifier will maintain the required
current for the sweep portion of the waveform.
8 RCL 7.8mH
RD 4 Time expansion has been used for Figure 3 to better illustrate the
6 .2 5Ap-p slew rate and voltage swing requirements for the amplifier. During the
2K
retrace section of the waveform, the amplifier has to slew the sum of
47F .1F drive voltage (Equations 9 and 10) twice. For the circuit of Figure 2, this
CF amounts to 112V. With the PA10s typical slew rate of 5V per
22V 50pF microsecond, the slew time is only 22.5 microseconds, an insignificant
portion of the total retrace period. However, by understanding the
RF
voltage swing requirements, it can be seen that slew rate becomes
1K important as the scan rates increase.
L* 1 RS Both the PA02 used in Figure 1, and the PA10 used in Figure 2, have
YOKE DRIVER: V =
t .5 raised accuracy levels by placing the non-linear inductive element
inside the op amp feedback loop. The very high gain of the op amp and
FIGURE 2. HIGH CURRENT ASYMMETRICAL SUPPLY
the use of negative feedback produces superior linearity.
For an even more powerful version of this circuit, the PA10 power
op amp can be used, as shown in Figure 2. With this device, a 7.8mH RAPID TRANSITION FOR HEADS-UP DISPLAY
4 coil can be driven at 5AP-P with the same timing requirements.
Calculations for this design are: Heads-up displays demand swift transition between any two points
on the screen. The waveforms of Figure 4 depict the input drive voltage
VDRIVE = 5AP-P* 7.8mH/15ms = 2.6V (sweep) (9) and required current to the yoke to achieve a single full-scale step in
VDRIVE = 5AP-P* 7.8mH/730s = 53.43V (retrace) (10) beam position for the circuit in Figure 5. The 3V levels sustain the
VDROP = 2.5PKA* (.5 + 4 ) = 11.25V (11) steady state current through the coil resistance and the sense resis-
VS = 2.6V + 8V + 11.25V = 21.85V (sweep) (12) tors. The 29V level corresponds to the peak output voltage required for
VS = 53.43V + 8V + 11.25V = 72.68V (retrace) (13) a position change.
Starting with amplifier slew rates and settling times from the data
Both of the circuits illustrated have a 730s retrace time require- sheet, it is determined what percentage of the total transition time will
ment, met easily by the op amps slew rate and settling time which is be required for slewing and settling. A reasonable starting point would
substantially faster. be to allow 50% of the total transition time.
To better understand this and other applications, Figure 3 illustrates
the output voltage waveforms generated by the power op amp to
obtain the desired retrace output current step for Figure 2. The wave
form preceding point A is the end of the sweep wave-form with a INPUT 0
relatively slow rate of change of the current. The peak output voltage
+29V
at point A equals the sum of equations 9 and 11.
Retracing begins at time A where equation 10 dictates the drive
+1.25 D
+3V
INPUT 0 VOUT 0
-3V
+2A
1.25
IOUT
65V -2A
FIGURE 4. FULL SCALE STEP FUNCTION WAVEFORMS

VOUT
This circuit was designed for a maximum transition time of 4s when
0 delivering 2APK currents to the 13H coil. While the fundamentals of
this circuit are the same as previously detailed, there are differences
14V due to the higher speed. To achieve rapid transitions, amplifier slew
rates must be optimized. The PA09 Video Power Op Amp with external
+2.5 phase compensation allows this. However, close examination of poles
and zeros in the feedback loop is required because reactive feedback
elements force the amplifier to operate over a very wide range of gains,
I OUT very high during transition but unity at steady state.
0
(VIR ) The network of CF, RD and RF set gain to approximately 100 at high
frequencies. This allows phase compensation for a gain of 100 and
correspondingly high slew rates. The next step shown in Figure 6 is to
plot the feedback zero of the yoke inductance and the sense resistor.
2.5
A B C D Then the high frequency feedback level of the RC network, approxi-
mately 40dB, can be drawn in and CF selected to produce a pole
TIME approximately one decade below the intersection point. Figure 7
FIGURE 3. RETRACE WAVEFORMS shows the PA09 open loop bode plot and the modification due to
309
+37V di = 2A/s frequency where the roll off slope must be flattened near the unity
CC 2pF dt gain point. The value of CF was not critical; however, a compensation
3 capacitor of 2pF, as opposed to the data sheet recommendation of
4 7 i = Vi /R S 5pF, helped to increase the slew rate without significant affect on
Vi 8 stability.
1
PA09 Due to the high speed of PA09, specific precautions are recom-
5 CF 470pF LY mended to insure that optimum stability and accuracy are main-
13H tained:
1
6 RD
12K 1. To help prevent current feedback, use single point grounding for
37V RF the entire circuit or utilize a solid ground plane.
2. To insure adequate decoupling at high frequency, bypass each
100
RS power supply with a tantalum capacitor of at least 10F per
.5 ampere of load current, plus a .47F ceramic capacitor con-
nected in parallel. The ceramic capacitors should be connected
FIGURE 5. PA09 AS DEFLECTION AMPLIFIER directly between each of the two amplifier supply pins and the
feedback effects. A slope increase below 500kHz and a shallow ground plane. The larger capacitors should be situated as close
slope at the unity crossing point to insure stability. as possible.
If 50% of the total transition time is allowed for slewing and settling, 3. Use short leads to minimize trace capacitance at the input pins.
2s will remain to change the yoke current with full voltage applied Input impedances of 500 or less combined with the PA09 input
to the coil. Voltage requirements are calculated as follows: capacitance of approximately 6pF will maintain low phase shift
V = di* L/dt (14) and promote stability and accuracy.
V = 4A*13H/2s = 26V (15) 4. The output leads should also be kept as short as possible. In the
VDROP = 2A* (.5 + 1) = 3V (16) video frequency range, even a few inches of wire have significant
VDRIVE = 26V +3V = 29V (17) inductance, thereby raising the interconnection impedance and
VS = 29V +8V = 37V (18) limiting the output slew rate. Also, the skin effect increases the
resistance of heavy wires at high frequencies. Multistrand Litz
Wire is recommended to carry large video currents with low
13H/.5 losses.
0
5. The amplifier case must be connected to an AC ground (signal
common). Even though it is isolated, it can act as an antenna in
RESPONSE, (dB)
the video frequency range and cause errors or even oscillation.

20
TRANSIMPEDANCE BRIDGE FOR HIGHER DRIVE

470pF/12K 100 VOLTAGE
40
The circuit illustrated in Figure 8 drives the deflection yoke of a
precision x-y display from an available 15V supply. Only the bridge
configuration can provide the high voltage drive levels required with
the power supplies available. This enables the system to drive
60
double the single amplifier output voltage. Consequently, the need
100 1K 10K 100K 1M 10M
for separate power supplies solely for CRT deflection is eliminated.
FREQUENCY
Figure 8 shows the current sense resistor R8 utilized to implement
FIGURE 6. FEEDBACK RESPONSE
a differential voltage-controlled current source (transimpedance)
with A1, where A2 functions as an inverter to provide an equal but
Selection of the external phase compensation will also need to be opposite phase voltage drive to the load. To convert the single ended
calculated as applicable to the PA09. Component values are recom- input to the differential output, the differential feedback of R1A
through R1D makes the output voltage a common mode signal for A1
mended on the Amplifier Data Sheet according to the effective gain
negating any feedback effects. In this manner, the amplifier common
setting of the circuit (RD to RF)
mode rejection and the resistive divider ratios, maintain the
100 transimpedance function (differential feedback from R8 only). Be-
A OL cause R1A/R1B and R1C/R1D must divide the output voltage
equally for both amplifier inputs, a matched or precision resistor
80
network must be used. In addition to initial matching, temperature
= 6dB/octave tracking of the divider ratios is also critical. Mismatch errors are
GAIN, (dB)
60 FDBK
R1A R2 R3
1.5K 1.5K 1.5K

= 12dB/octave +15V +15V
40
R4 R5
20
1.875V .15 .15
R1B
6-9dB/octave DAC
1.5K PA02 PA02
0 A1 A2
100 1K 10K 100K 1M 10M
FREQUENCY
R6 R7
R8
FIGURE 7. COMPOSITE RESPONSE .5
.15 .15
With the external compensation selected, the PA09 Data Sheet 15V 15V
indicates the amplifier slew rate will be 400V per microsecond. For R1C R1D YOKE
a calculated swing of 58V, the required voltage slewing time is 145
1.5K 1.5K .3mH
nanoseconds. Adding the settling time to 0.01% of 1.2s, the total is
comfortably below the 50% allotment of 2 microseconds. R9 C1
When the circuit was tested, values were further optimized for best 3.3K 10pF
performance. The value of RD had a considerable effect on damping
FIGURE 8. CURRENT-OUT BRIDGE DRIVE
of the circuit. This could be predicted because RD affects the corner
310
equivalent to control voltages equal to the percent of mismatch
multiplied by the output voltage of A1. The series RC damping network
placed in parallel with the inductive load reduces its phase shift at high
frequencies, which effectively eliminates the possibility of oscillations.
The maximum transition time between any two points is 100s for
display ratings:
Yoke inductance = 0.3mH

Full-scale current = 3.75A
DC coil resistance= 0.4
Calculations are identical to previous examples:
V = di*L/dt (19)
V = 7.5A*0.3mH/100s = 22.5V (20)
V DROP = 3.75A* (.5 + .4) = 3.375V (21)
V DRIVE = 22.5V + 3.375V = 25.875V (22)
One-half the total drive level required for the bridge circuit is
provided by each amplifier, or approximately 13V of output swing per
amplifier.
The Apex low voltage power op amp PA02 perfectly meets the
criteria for this circuit because of its high slew rate of 20V/s and its
ability to drive the load close to the supply rail. The average output
voltage swing of the circuit during the beam transition time will be
greater than 26V as illustrated in Figure 9.
Due to the inductive nature of the load, the direction of current flow
changes only after the transition is 50% complete. This allows both
amplifiers to swing to their no load saturation levels (less than one volt
from the supply rail) for this time period. Furthermore, IR drops during
this time period generating voltages which add to the amplifier drive.
During the second half of the transition, current direction changes and
the amplifier output swing decreases; however, even at 75% comple-
tion, each amplifier will still swing in excess of 13V because the current
magnitude has not yet reached 2A (see data sheet).
+15V
A1
VOUT < 14V
VDRIVE > 31V
> 28V D
VIR = +3.375 V
OV
A2 VOUT > 14v
-15V
FIGURE 9. CURRENT PATH AND VOLTAGES DURING

THE FIRST 50% OF A FULL SCALE TRANSITION
CONCLUSION
The capabilities of the power op amp provide higher accuracy
levels, the ability to position beams in any desired position and to retain
a steady state position. Having both the power and signals stage in one
compact package offers space/weight advantages. The lower parts
count increase reliability.
Power op amps are comparatively inexpensive and easy to use.
They represent the most efficient solution to reducing development
costs and decreasing design time.
however, FAXis(520)
ORDERS (520) 690-8601
311
APPLYING THE SUPER POWER PA03
APPLICATION NOTE 6
C1 1.0nF R1A R1B R2A
200K 50K 50K R2B

+88V +88V
+88V 50K
+88V C3
C2 3.3nF
R2C 3.3 A1 A2
nF R3 R4
50K 1K 1K
R2E R5 50A R6
+88V 50K .05 70V .05
50W 1.4 50W
R1C R1D 1 2
M
DRIVE NODE R7 200K 50K R10A
250K
C4 10nF 50K
R8A R8B R12 +88V R10B 200K

.05
R9 50W
200K +88V 50K R11 2.4M C6 3.3nF
REFERENCE R2F .05 A4
+88V R15
NODE(+44V) 50K 50W 1K
C5
R14 3.3 A3
R16 1K nF
250K R13A
200K R10C R10D
R8C R8D
50K 200K
200K 50K R17
R2D +15V 82K

+15V
50K R13B
1.25V
A5 50K 15V
R13C
50K
R13D 15V
200K
FIGURE 1. APPLYING THE SUPER POWER PA03
INTRODUCTION
Using the super power PA03 offers many advantages. With an
The super power PA03 is the result of a design effort to substantially internal power dissipation of up to 500W, the PA03s ratings top the
increase output power without sacrificing the high performance engi- previously most powerful op amp (Apex PA12) by a factor of four, and
neers are accustomed to when using small signal op amps. Thus, this one PA03 is more cost effective and far more reliable than four less
new building block can perform accurate and complex tasks previously powerful op amps. Its thermal tracking of internal bias components
reserved to modular and rack mount devices. makes the PA03 much safer to use under abnormal conditions than
The major applications for the PA03 will be in single ended circuits several units in parallel. Moreover, internal protection circuits insure
where up to 1,000W must be delivered to the load or in bridge motor that almost any power level not violating the 2,400W, 1ms Safe
servo systems delivering up to 2,000W peak. Linear motion control, Operating Area (SOA) is safe. The amplifier will shut down upon
magnetic deflection, programmable power supplies, and power trans- overload, avoiding self-destruction. Internal current limiting resistors
ducer drives are typical of these applications. High power sonar, such eliminate bulky, expensive milliohm external resistors which are
as phased array, is another key application made possible by the normally required for power op amps. The common collector comple-
accurate phase response and linearity of the class A/B output stage. mentary output stage allows the output to swing within 4V of the supply
Robot, motion control, and other high current applications which were rail at 12A and within 6V at 30A and has full shut-down control. This
previously impossible to implement with IC Power Op Amps because gives the designer a tool to protect sensitive loads or to minimize power
of power limits, are now possible using the PA03 as a building block. consumption under battery operation. By operating in class A/B, it
The most powerful TO-3 hybrid ICs currently available can dissi- exhibits low crossover distortion, a feature hard to implement without
pate up to 125W and drive loads up to 250W (APEX PA12), while the inherent thermal tracking of single package construction.
available monolithic ICs handle less. Where peak power require- An external balance control option allows the already low offset
ments for dynamic motor control exceed 250W, three approaches voltage to be zeroed. The PA03s high overall accuracy makes it
were commonly used to increase power output: (1) parallel or bridge suitable for interfacing directly to photo-diodes; to build long time
operation of two or more power op amps; (2) external booster transis- period integrators; or to design 12 bit and better resolution program-
tors; (3) modular or rack mount power op amps. mable power supplies.
While these options extend power capabilities, they can have major The super power PA03 is a hybrid IC housed in the innovative
drawbacks in increased cost, excessive weight and reduced reliability. Power-Dip dual in-line package. It has .060 pins on .200 centers to
Furthermore, the large size can be a cumbersome design burden. accommodate higher currents and allows layout on the standard 0.100
System designers need a small, reliable power op amp capable of grid. The Power-Dip copper header of the PA03 provides 8.5 times the
producing up to 1,000W while maintaining top notch performance. The thermal conductivity, and three times the area of the conventional steel
PA03 meets this challenge! TO-3 package.
312
A SUPER POWER TORQUE DRIVE 880A 176A 145A 145A
+88V +88V +80.25V +80.25V
The parallel bridge circuit in Figure 1 is shown to demonstrate
several possible power enhancement techniques in one application. It R10A R10C
50K 50K
operates in the transimpedance mode to drive the torque motor. This R2E R7
allows the D to A converter (DAC) to be programmed directly for 50K 250K (36.25V) (36.25V)
(44V) (44V)
delivered torque, since motor torque is directly proportional to arma-
R10B R10D
ture current. The bridge uses an economic and efficient single output 200K 200K
power supply and doubles delivered power levels again by increasing
REFERENCE
the current drive capability. Delete A3 and A4, and associated compo- NODE (44V)
nents if this option is not required.
Looking at the bridge configuration first, A2 and A4 invert the output
R2F R13A R1C R8A
of A1 and A3 with respect to the mid-supply reference node. Therefore, 50K 200K 200K 200K
A2 and A4 drive the load equal to A1 and A3 in the opposite direction (44V)
about the mid-supply reference point. The mid-supply node assures (42.75V) (35V) (35V)
that neither amplifier saturates prematurely. Figure 2 shows the actual
output voltages of A1/A3 and A2/A4 when delivering full scale output R13B R1D R8B R9
currents to the torque motor. 50K 50K 50K 2.4M
(36.25)
+80.25V +7.75V
(+7.75V) (+80.25V) 880A +1.25V +9V +9V +7.75V
171A 140 A 140A 165 A
A1 A2
FIGURE 3. CURRENT BALANCING OF THE REFERENCE NODE
.05 .05
780A 156 A 381 A

+79V 1 2 +9V +88V +88V +80.25V
(+9V) M (+79V)
R2C R16 R17
50K 250K 82K
(39V) (39V) (31.25V)
.05 .05
DRIVE
NODE (49V)
A3 A4
+80.25V +7.75V R2D R13D R1A R8C
(+7.75V) (+80.25V) 50K 200K 200K 200K
(49V) (41.25V) (41.25V)

FIGURE 2. FULL SCALE DRIVE VOLTAGES
R13C R1B R8D
A5 (Figure 1) configured as a level shifter at a gain of 4, takes the 50K 50K 50K
1.25V input from the DAC and swings the drive node to 5V with
respect to the reference node. A1 and A3 each amplify this differential
5V signal to a 25A output level driving terminal 1 of the motor. A4 is +9.44V 196A +7.75V +7.75V
a unity gain follower of the A2 output voltage. Since A2 and A4 have 791 A 165A 165 A
equal output voltages and equal current control resistors, they share
the total 50A current equally.
FIGURE 4. CURRENT BALANCING OF THE DRIVE NODE D
The very low bias current of the PA03 FET input stage makes it
possible to keep power dissipation low by using relatively large value nominal swing will be a 9.44V, correcting the overall current imbalance
precision resistors. This not only minimizes temperature variations in of 12A. Thus the overcompensation of R17 insures A5 will not be
the resistive networks, but also reduces power dissipation in A5. required to swing beyond its rated 10V due to component tolerances.
Current balancing for both the reference and drive nodes is used to There are a lot of resistor networks in the circuit, but each has a
prevent level shifting of the high impedance nodes as a function of critical task. The ratios are most important to insure gain accuracy. In
drive voltage. This is an easy task because of the symmetric drive addition, ratio matching provides common mode rejection and differ-
levels with respect to the reference node. ential voltage amplification. Specifically, the R13 quad around A5 sets
Figure 3 shows a breakdown of the currents associated with the drive node swing to +5V with respect to the reference voltage even
reference node. R2E and R2F form the basic voltage divider. At a zero though the reference changes with supply variations. Similarly, the R1
drive level, the current through R13A and R13B will match the current quad and the R8 quad set the full scale voltage across sense resistors
through R7. The voltages applied to R1, R8, R9, and R10 will all be R5 and R11 at 1.25V. The 35V output swings across the impedance
zero with respect to the 44V reference so the circuit is balanced. The of the torque motor are rejected as a common mode signal to maintain
voltages shown correspond to full scale drive level. R7 roughly the programmed voltage to current transfer function. Thus impedance
balances the current through R13A and R13B to the +1.25V DAC variations of the motor winding and the associated connections do not
input. R10A, R10B, R10C, and R10D current will nearly match the affect accuracy. R10 fixes the gain of A4 to unity while keeping its input
currents of R1C and R1D plus R8A and R8B. The differences encoun- pins about 4V closer to the reference than the amplifiers output
tered so far total 15 microamps, which is provided by R9 to insure the voltage. With the output swinging to within nearly 7V of the supply rails,
reference node remains at 44V. the common mode voltage requirement of Vs 10V is satisfied.
Figure 4 illustrates currents associated with the drive node where
R2C and R2D form the basic voltage divider. At zero drive, no voltage A PROGRAMMABLE POWER SUPPLY USING THE
is applied to R17, R1 and R8, and the output of A5 will be zero and the PA03
drive node voltage will be 44 volts. This means currents of R2C and
R2D balance. The currents in R16 balance the currents of R13C and Figure 5 shows the PA03 in a simple, reliable programmable power
R13D and the remaining resistor currents are zero. For a full scale supply which utilizes the PA03s shutdown features. It requires little
input of +1.25V, A5 will drive to approximately +10V. The currents calibration because the current to voltage conversion of the D to A
through R16, R13C and R13D are no longer balanced because the converter output is done by the power op amp itself, and the 12 bit
drive node voltage has risen to 49V. The currents through R1A and DAC80 provides accuracy levels high enough to eliminate the need for
R1B, plus R8C and R8D, make the node even less balanced. R17 was adjustments.
selected to slightly over compensate the current imbalance. Since the The programmable power supply is designed to test DC-to-DC
differential circuit of A5 (Figure 1) controls drive node voltage, its converter modules drawing up to 15A. The majority of tests are
313
18.5V
+39V 16K 15A
+39V
306
0/-2mA W
28V 32V
DAC80 15A 15A
SHTDN+ 28V 164 28V 104
+5V PA03 D.U.T.
SHTDN .05 1A W 1A W
OV
OA 20.8W 20.8W
3R 3R 9.8W
1.8nF 4.0 .5 2.0s .5s 2.5s .5s
10V R
P (W)
+15V AVG 3.92 15.3 4.16 8.2 5.2 5.15
+5V +15V
41.93W
FAULT OP07
CMOS COMP FIGURE 6. PROGRAMMABLE POWER SUPPLY INTERNAL
LATCH POWER DISSIPATION
RESET
.999
15V R For the balance of the test of 4.5s, the maximum current of 1A
ANALOG OUT
amounts to 20.8W. During the minimum removal/insertion time of 4s,
CLEAR the power dissipation is only the quiescent power of 9.8W. This
.019R
5V = 15A
means the average power dissipated is only 41.9W. With a heatsink
.333V/A .001R that has a thermal time constant of ten seconds, the highest peak
(306W for 500ms) amounts to 5% of the time constant, or 4.9% of the
rise for 306W continuously. Adding this spike equivalent of 15W to
FIGURE 5. HI-POWER PROGRAMMABLE POWER SUPPLY the 41.9W average will bring the peak short term equivalent power
APPLICATION
to 57.23W (though this peak could vary slightly depending upon the
exact timing).
performed at 28V. High and low limits of 18.5V and 32V will be If, for reliability, a peak junction temperature of 150C is selected,
applied for 500ms. The outputs must be accurate to within 0.5% and and a maximum ambient temperature of 38C is assumed, the
survive an occasional short circuit to ground. allowable temperature rise of the heatsink is 18C (150C 38C
The OP07 differential amplifier circuit senses the D.U.T. current 92C). At a peak short term equivalent of 52.2W, this requires a
on the four-terminal shunt resistor, and provides a signal of 0.333V/ heatsink rated at 0.35C/W. The Apex HS06 (0.6C/W free air) with
A to the comparator. The comparator will trip at a current of 18A, a forced air velocity of 500 ft/min can provide the required rating.
setting the latch, and the latch then shuts down the PA03 until the In this application, if abnormal situations arise due to faulty timing
fault is cleared and the latch is reset. This safety circuit limits arcing or defective test units, short term operation at the 306W level will not
hazards in the test socket. destroy the PA03 because the thermal shutdown will limit the
The feedback resistor of 16K yields the required 32V full-scale temperature rise. The worst case would be a short in the test socket
output when the DAC output is 2mA. The 0.05 current sense which could push the PA03 to a maximum current limit of 42A. At this
resistor develops a 0.75V signal at the full-scale output current of current, the sense resistor (RS) would drop 2.1V leaving 36.9V
15A. This amplitude is a compromise between monitoring the current across the PA03. These current and voltage levels (1.55KW) are well
accurately without imposing an excessively high power rating on the within the PA03s 1ms second breakdown line of the SOA curve.
sense resistor. However, the sense resistor still must be mounted on Therefore, the fast response of the PA03s thermal shutdown circuit
a heatsink due to 11.25W dissipation at 15A and the possible 88W will protect the power op amp for the time required to eliminate the
at the built-in maximum current limit of 42A. short.
To derive the power supply voltage needed, the 0.75V drop on the
sense resistor must be added to the headroom (supply-to-output REMOTE SITE MOON BOUNCE ANTENNA MOTOR
differential) required by the op amp. From the PA03 specifications (a
drop of 7V at 30A and 5V at 12A), a maximum drop of 6V at 15A can DRIVE
safely be assumed. Selecting a positive voltage of 39V leaves a Power conservation is essential for solar powered data gathering,
margin of 0.25V. Without remote sensing, such a conservative while a considerable amount of motive force is required for position-
approach is best due to potential IR drops in the high current leads. ing a 40 Ft dish antenna.
For the negative supply, a minimum operating voltage of 10V is With a 3 beam angle and a position accuracy of 0.5, the lunar
required to satisfy the input common mode voltage specifications. angular velocity of 14.4/Hr allows a position update only once per
Four power levels must be examined to determine the worst case minute. The PA03s shutdown control used for intermittent operation
maximum power dissipation of the power op amp. The first three are combined with a worm gear drive to hold position during shutdown
the output voltage levels for the devices under test at the maximum periods, facilitates an energy efficient positioning system.
current of 15A. Calculating all three shows the 18.5V output to be the The D to A Converter in Figure 7 converts position data to a voltage
worst case scenario. The 18.5V output plus the 0.75V drop across which is fed to the inverting input of the PA03 configured as an
the sense resistor leaves a voltage of 19.75V across the output stage integrator by feedback capacitor C1 and input resistor R1. The
of the PA03. At 15A, this produces an internal power dissipation precision reference and potentiometer apply a feedback voltage
(including quiescent power of 9.8W) of 306W and a junction to case equivalent to actual position to the non-inverting input. The PA03
temperature rise of 92C (PA03 =0.3C/W). drives the motor with the integrated difference between the desired
Because the worst case power demand exists only for 500ms, an and actual positions. R2 acts as a damping element limiting the
examination of average power and thermal time constants will help integration time constant to minimize overshoot.
to reduce the heatsink size. Figure 6 shows the general test plan and The shutdown control is released for six seconds after each
the specific testing sequence with the resulting power dissipation position update, which allows the PA03 sufficient time to position the
levels demanded of the PA03. The 32V output level requires 103.6W antenna and reduces the standby power to 2W for 54 seconds or
(39V supply less 32V output and 0.75V across the sense resistor 90% of the time.
times 15A plus 9.8W of quiescent power) for 500ms. The 28V level The normal current requirement of the motor is 8A, but under high
amounts to 163.6W (39V supply less 28V output and 0.75V across wind conditions, up to 17A may be drawn. In this application, the
the sense resistor times 15A plus 9.8W of quiescent power) for amplifier output will be decaying pulse; thus driving the motor to a
another 500ms. new position once a minute. Because the amplifier is at maximum
314
10V techniques and quality power supplies can easily cause substantial
REF AC ripple. Ripple must be considered as a possible source of error.
Positive feedback can also occur if the power supply also powers other
circuit elements.
+24V
WATCH THE POWER DISSIPATION
The internal power dissipation (P) in a DC circuit is:
+5V
1.8nF P = (VS VO) IO +(| + VS | + | VS |) IQ
+S where: IO: OUTPUT CURRENT

PA03A M I Q: QUIESCENT CURRENT
SHT DN S VO: OUTPUT VOLTAGE
DAC VS: SUPPLY VOLTAGE
0/10V R1
Errors often arise in the calculation if the wrong supply voltage is
C1 24V
used. The voltage (VS) must be the one at the supply pin sinking or
sourcing the current. Incorrect selection of the worst case conditions
R2
(short to ground or supplies) can also create errors.
When driving reactive loads, due to the phase shift between output
FIGURE 7. REMOTE SITE MOON BOUNCE APPLICATION voltage and current, the power dissipation may be several times higher
than the equivalent resistive loads. These have a totally different, but
output (saturated) most of the time, the power dissipation at the full equally simple approach that can be used to obtain the correct power
output voltage is the appropriate level to calculate. dissipation (P):
At 17A the PA03 will drive to within 5.5V of the supply voltage (rail)
dissipation of 93.5W. The quiescent current of 0.2A times the total P = PI PO
supply voltage of 48V adds another 9.6W for a total of 103.1W
dissipated in the amplifier. At the maximum ambient temperature of where: PI = POWER DRAWN FROM THE POWER SUPPLY
45C and a maximum junction temperature of 140C, the allowable PO = POWER DELIVERED TO THE LOAD
rise is 95, which requires a thermal resistance for the heatsink as
follows: Keep in mind that using purely reactive loads means that all power
QHS= 95/103.1 0.3 = 0.62/W. drawn from the supplies is dissipated in the amplifier.
The Apex HS06 meets this criteria.
Under normal low wind conditions, the peak battery drain will be
201.6W. However, due to the 10% maximum duty cycle and the power-
JUNCTION TEMPERATURES
saving shutdown feature of the PA03, the average power consumption The absolute maximum power dissipation of the PA03 is 500W and
will be only: was derived using the industry standard derating procedure. This
PAV = 0.1 (24*8+48*0.2) +0.9 (48 *0.040) = 22W assumes operation at maximum junction temperatures (175C) with
To further reduce standby power to 2W, the shutdown feature can the case at 25C.
be activated only when communications are required. With the power dissipation and the maximum ambient temperature
(TA) of the application known, the operating temperatures of both case
USING THE PA03 IN YOUR APPLICATION (TC) and junction (TJ) of the power transistors can be determined:
To achieve maximum efficiency, the power supply voltage should TC = TA + P * HS

be selected for the minimum voltage necessary to produce the D
required output. where: HS = THERMAL RESISTANCE FROM THE HEATSINK
For example, to obtain a 45V output at 12A, add the supply-to- MOUNTING SURFACE TO AMBIENT AIR
output differential as specified on the Data Sheet (5V) to produce
50V. JS = INTERNAL THERMAL RESISTANCE,
Dual supplies may be as high as 75V and asymmetric or single JUNCTION TO CASE
supply operation is permitted as long as the total rail-to-rail voltage
doesnt exceed 150V. Input voltages must always be at least 10V less Apply this to the PA03 by following these steps:
than the power supply voltage due to the common mode voltage
specification being supply voltage minus 10V. 1. Calculate the maximum internal power dissipation (P).
Because of the greater power levels involved, the thermal path to 2. Determine the maximum junction temperature allowable to achieve
remove the heat from the amplifier is of great importance to the the desired reliability of the PA03. This must be less than 175C.
successful application of the PA03. A 1C/W rated heatsink may be Apex recommends 150C or less.
suitable to remove 20-50W, but it is insufficient to handle 500W. For 3. Calculate TJ TA, the allowable rise of the junction temperature
the PA03, a heatsink with a thermal resistance on the order of above the maximum ambient temperature.
0.1C/W is often required such as: very large surfaces, forced air 4. Calculate the required thermal resistance of the heatsink:
cooling, or even water cooling. Fortunately, if insufficient heatsinking HS = (TJ TA)/P JC
is provided, the unique safety circuits of the PA03 will generally result
in thermal shutdown rather than destruction. Destructive power levels For example, in a circuit dissipating 300W at an ambient tempera-
are so high that in most applications they need not be of any concern. ture of 30C and the junction temperature not to exceed 150C:
As with all high current Power Op Amps, precautions must be taken HS = (150 30)/300 0.3 = 0.1C/W
to avoid current feedback due to voltage drops in the wiring of
electromagnetic radiation. This is especially true when using the PA03
because of its higher current rating. The wiring for all supply and output
HOW THE PA03 WORKS
leads must be done with wire equivalent to 12 gauge or thicker, as the The circuit diagram shown in Figure 8 shows that the input section
PA03 has a higher current capacity than most branch circuits in of the PA03 is similar to most Apex FET input hybrid power op amps.
residential wiring. Q21, D1 and D4 form voltage references to bias both input and output
To avoid feedback through the power supplies, they must be stages of the amplifier. Q31 is the current source for the input stage
bypassed with a ceramic capacitor of 0.47F or greater, in parallel with which consists of Q20A and Q20B (the FET input pair), Q17 and Q18
a 10F per ampere of peak output current (up to 300F), mounted not (the cascode transistors), and Q2 and Q3 (the half dynamic load). The
more than 1.5 inches from the supply lines. current through Q5 sets the operating voltage (source-drain) for the
Even when using excellent bypassing components, good layout FET input pair. Q12 acts as an impedance buffer between the high
315
+V
8
BAL
11 Q1 Q4
BAL
12
D1
Q2 Q3 Q6 Q7 Q9 D2
Q12
Q5 4 Q14
+SHUT 9 Q16 +
7
Q17 Q18 DOWN COMP OUT
Q21 Q19
1 Q20 Q20 10 6
Q22
A B Q24
3
SHUT
DOWN D3
+ Q30
2 Q29 Q32 Q26
Q31
Q34
D4
V
5
FIGURE 8. PA03 EQUIVALENT SCHEMATIC
output impedance of the input stage and Q6, the output driver. CONCLUSION
The collector load of output driver Q6 consists of current source,
Q29, and the output stage consisting of Q16, Q9, Q24, and Q26. The The PA03 is a versatile new building block which eases many
common collector configuration of Q9 and Q26 enable the PA03 design tasks and overcomes size and weight barriers which previ-
output to swing close to the supply rails. Inverters Q16 and Q24, form ously prevented implementation of linear power controls in limited
local feedback networks which cause the output stage to be linear like space. The giant step up in power levels, improved protection circuits
an emitter follower with very high input impedance. The VBE multiplier and high performance small signal characteristics make the PA03 a
Q19, provides DC bias for the output transistors via Q16 and Q24, and very cost effective innovation.
is thermally coupled to the power dissipating transistors in the output
stage. In addition, the VBE multiplier utilizes thermistors to fine tune the
temperature stability of the quiescent current through output transis-
tors Q9 and Q26. This class A/B stage provides low crossover
distortion, as well as stability of the quiescent current over the full
temperature range.
D2 and D3 are high speed diodes which protect the output stage
from inductive kickback by bypassing it into the supply rails. The 18.6
milliohm emitter resistors of Q9 and Q26 sense the output current of
the amplifier. Currents in excess of 35 amps will develop .65 volts,
thereby turning on Q1 or Q34. In turn, these transistors rob the base
drive from Q6 or Q29, thus limiting the output currents to 35A. Q4 and
Q32 are the sensors for the innovative SOA protection of the PA03.
These two transistors are mounted directly on top of power transistors
Q9 and Q26, eliminating thermal gradients and minimizing the re-
sponse time to temperature changes in the output transistor junctions.
The emitters of the sensors are connected to Q7 and Q30 which act
as level translators to turn on current limit transistors Q1 and Q34,
respectively. The complementary pair Q14 and Q22 activate the shut
down of the PA03. While common mode voltage is rejected, differential
voltages applied between these two transistors turn on the current limit
circuit consisting of Q1 and Q34, thereby shutting down the entire
output stage. In this mode the output pins appear as a high impedance
to the load. Figure 9 illustrates the physical arrangements to achieve
fast and reliable thermal shut down.
THERMISTOR EPOXY JUINCTIONS:

THE HEAT SOURCE
Q4,32
SOLDER
Q19 POWER TRANSISTOR Q9,26
BeO
H
W
E
O
A
L
COPPER HEADER
T
F
F
T
A
L
E
O
H HEATSINK
W
FIGURE 9. THERMO-MECHANICAL DESIGN
omissions. HOTLINE:
without notice.
AN6U REV.B FEBRUARY 1998 1998 Apex Microtechnology Corp.
316
PROGRAMMABLE POWER SUPPLIES
APPLICATION NOTE 7
INTRODUCTION
The programmable power supply (PPS) is not only a key element in
automated test equipment, but it is also used in fields as diverse as RF
industrial controls, scientific research and vehicular controls. When
V RIN
coupled to a computer, it bridges the gap from the software to the
control task at hand. This application note examines the basic opera- DAC
tion of the PPS, the multitude of possible configurations and the key
accuracy considerations.
AV = RF/RIN
VOLTAGE OUTPUT VERSIONS
The most basic and often most accurate version of the PPS requires FIGURE 2. INVERTING VOLTAGE GAIN
only a current output Digital to Analog Converter (DAC), a power op
amp and a feedback resistor as illustrated in Figure 1. According to op
amp theory, the voltage at the inverting input (summing junction) will
be zero and op amp input current will be zero. As a result, all current
from the DAC flows through the feedback resistor RF. Ohms law then
causes the circuit to provide a precise output voltage as function of RF
DAC output current. Given a perfect DAC and feedback resistor, only RIN
two op amp parameters contribute significantly to the output voltage
errors. These are voltage offset (VOS), modeled by the battery, and bias V
current (lB), represented by the current source. Due to the high output
DAC
impedance of the current output DAC in relation to RF, VOS errors
appear at the output without gain. AV = 1 + RF /RIN
FIGURE 3. NON-INVERTING VOLTAGE GAIN

RF
I
Figure 2 illustrates the basic inverting gain version and Figure 3
DAC shows a non-inverting setup. Error calculations are still simple even
V
though some new variables have been added. Voltage offset errors
appear at the output multiplied by the gain of the circuit (AV+1 for
inverting circuits). To maximize accuracy, the highest output DAC's
V = IR F should be used with minimum voltage gains in the op amp configura-
tion. When using 10V DACs, a direct Vos to LSB comparison can be
FIGURE 1. CURRENT TO VOLT CONVERSION made using the 20V FSR values listed in Table 1. Also, bias currents
For a 10V output and op amp offset of 5mV, this error contributes flow through the feedback resistor producing output voltage errors; D
only 0.05%. For a 100V output, a 0.5mV offset contributes an error of thus, values of RF and RIN are usually kept as low as possible.
only 5ppm. Clearly, the DAC can easily be the major error source.
Op amp bias currents add to the DAC output current. The majority A CASE FOR REMOTE SENSING
of available DACs have full scale currents of 1mA or 0/2mA. Most of The circuit of Figure 4 shows the wire resistance (RW) from the power
todays bipolar input power op amps feature bias currents of less than op amp to the load and back to the local ground via the power return
50nA. This results in errors of only 25 ppm maximum of the full scale line. A 5A load current across only 0.05 in each line would produce
range (FSR). FET input bias currents at 25C are seldom over 100 pA a 0.5V IR drop. Without remote sensing, this would become an error at
and are specified as low as 10pA. These errors translate to 0.05ppm the load. With the addition of the second ratio matched RF/RIN pair and
and 0.005 ppm. Since FET bias currents are generally characterized two low current sense wires, IR drops in the power return line become
as doubling every 10C, the bias current of the two examples could common mode voltages for which the op amp has a very high rejection
become 100nA and 10nA at 125C, producing errors of 50ppm and ratio. Voltage drops in the output and power return wires are inside the
5.4ppm, respectively. Again,the DAC is the critical error source. feedback loop; therefore, as long as the power op amp has the voltage
To determine the significance of the error contribution of a specific drive capability to overcome the IR losses, accuracy remains high.
power op amp to the performance of various systems, refer to Table
1, next page. The least significant bit (LSB) is the value of the smallest
step change of output. Comparing the calculated errors to the LSB
values reveals system compatibility. For current output, DACs op amp HI SENS
RF
bias currents compare directly with the DAC current LSB and VOS R IN
errors compare directly with the full scale output voltage. Thus, the DAC
importance of low bias currents is dependent solely on system OUT
resolution. However, the significance of voltage offset specifications POWER
OP AMP
varies with both resolution and full scale voltage range. R IN RW
LOAD
USING VOLTAGE OUTPUT DACs RF
LO SENS
When using a voltage output DAC, the power op amp can be added
with either inverting or non-inverting gain to form the PPS. It usually
costs more than implementation with a current output DAC, and has RW RTN
less accuracy. However, system or logistic factors may dictate the use
of the voltage output DAC. FIGURE 4. REMOTE SENSING PROGRAMMABLE POWER SUPPLY
317
VIN * R F
CURRENT OUTPUT VERSIONS IOUT =
R IN * RS
A current output PPS using a current output DAC can be imple-
mented as shown in Figure 5. Another version of the current output POWER
OP AMP
PPS is shown in Figure 6. This allows the load to be grounded, but is V R IN
more complex and has additional errors. Especially if the output DAC LOAD
currents are relatively low, the current through the lower RF/RIN pair
may become significant because it is also sensed by RS. Major errors RF RS
can be caused by ratio mismatching between the RF/RIN pairs. The
resulting voltage errors across the sense resistor equal the output
FIGURE 8. A HIGH CURRENT, CURRENT-OUT
voltage times the ratio mismatch. For example, consider a 0.2 sense PROGRAMMABLE POWER SUPPLY
resistor, a 5A output requiring a 20V drive and a ratio mismatch of only
0.1% causes an error of 2%. Even an 8-bit LSB is only 0.39%! PROGRAMMABLE ACTIVE LOADS
To obtain the V-I characteristics of a power source, it may be
I IN * RF desirable to control the output voltage and measure the output current
IOUT =
RS or visa versa. The current output circuits shown are suitable as active
current loads. The circuit of Figure 9 performs voltage loading of a solar
POWER
OP AMP cell panel. The power op amp forces the DAC voltage to appear across
1mA the panel and also performs an I to V conversion providing the data to
DAC LOAD plot V-I characteristics.
RF RS
V VOUT = (I IN * R F ) VIN
FIGURE 5. A CURRENT-IN, CURRENT-OUT DAC
POWER
OP AMP
SOLAR
VIN * RF PANEL
I OUT = RF
RIN * RS RF
V R IN
DAC FIGURE 9. SOLAR PANEL TESTER
POWER Due to its flexibility, accuracy and ease of use, the power op amp is
OP AMP
R IN the leading choice when programmable power supplies are called for.
RS They greatly simplify circuits requiring unipolar outputs and are very
cost effective when designing bipolar power supplies. The only re-
maining question is whether to buy the power op amp or to make one
RF LOAD
in discrete form. For low quantity production runs, the required design
effort renders the make option too expensive. For high volume runs,
the question is more involved. In many applications, the smaller size
FIGURE 6. CURRENT-OUT FOR A GROUNDED LOAD and lower weight plus high reliability, make the buy decision the only
reasonable choice. (See The Advantages of IC power op amps.") In
all applications, the hybrid power op amp enhances design quality,
In all of the current output circuits discussed, errors due to voltage speeds assembly and reduces overhead costs.
offset appear across the sense resistor at a gain of one or more. This
means higher sense resistor values will minimize output current errors
at the expense of increased power dissipation in RS, the power op amp FULL SCALE RANGE
and system power supplies. One other word of caution, if the load
contains inductive elements, refer to Applications Note 5 which dis- BITS PPM 2mA 20V 50V 200V
cusses maintaining stability in precision current output circuits having 8 3906 7.8A 78mV 195mV .78V
reactive loads such as deflection coils. A current output PPS using a 10 977 1.95A 19.5mV 48.8mV 195mV
voltage output DAC is shown in Figure 7. The power op amp drives 12 244 488nA 4.88mV 12.2mV 48.8mV
current through the load until voltage on the sense resistor (RS) equals 14 61 122nA 1.22mV 3.05mV 12.2mV
the input voltage. To achieve high efficiency (low voltage across RS 16 15.3 30.5nA 305V .763mV 3.05mV
compared to the load voltage), this circuit requires a low voltage DAC
TABLE 1. LSB VALUES FOR VARIOUS OUTPUT LEVELS
or a high voltage op amp. If neither is possible, the circuit of Figure 8
allows the sense resistor voltage drop to be lower than the input
voltage.
V
I = VIN /R S
DAC
POWER
OP AMP
LOAD
RS
FIGURE 7. A HIGH VOLTAGE CURRENT-OUT

PROGRAMMABLE SUPPLY
omissions. HOTLINE:
without notice.
318
OPTIMIZING OUTPUT POWER
APPLICATION NOTE 8
THE MODERN POWER OP AMP

Power op amps are attractive because they reduce circuit design unregulated supplies, line and load variations must be taken into
time enormously. Assembly costs of the power op amp design amount consideration along with the ripple content of the supply. The result is
to a fraction of the discrete counterpart due to vastly reduced parts a voltage band above the minimum operating voltage required by the
count. Careful attention to the power aspects of a circuit is required, as power op amp to produce the required output. Power in this band must
the well known op amp design rules based on low power devices. The be dissipated. Voltage above the minimum operating voltage de-
objectives are to maximize reliability plus optimize output power and creases the power handling capability of the power op amp.
system efficiency. This application note points out some optimizing The choice is whether to dissipate the power in the power op amp
techniques and some areas to be especially watchful. or in a separate regulator. As current levels increase, the dollar per
watt cost generally rises faster for the power op amp than it does for
INTERPRETING SPECIFICATIONS a DC regulator.
Usually, unregulated supplies are not economical because they
The first step in achieving high power levels is to operate within lack transient protection. Power lines are notorious for being ex-
specifications. This means check the data sheet first. Apex data tremely noisy. They have high voltage, high speed spikes riding on the
sheets are divided into product description, absolute maximum rat- sine wave which pass right through the power transformer. Further-
ings, specification table, typical performance graphs, and application more, the large electrolytic capacitors used for filtering often do not
hints. Each section should be checked for relevant information. have low equivalent series resistances at those high frequencies. A 1K
Absolute maximum ratings are stress levels which, when applied to volt spike on the incoming line can result in an excessive voltage spike
the amplifier one at a time, will not cause permanent damage. at the amplifier supply pin. Destruction of the op amp may be the result.
However, proper operation is only guaranteed over the ranges listed Therefore, line filters and zener clamps are required to eliminate the
in the specifications table. For example, most amplifiers have an voltage spikes; thus, the economy of unregulated supplies is reduced.
absolute maximum case temperature range of 55C to 125C. If the Once the minimum supply voltages above have been selected,
specified operating temperature range is less, i.e. 25C to 85C, an steps need to be taken to minimize IR losses. Some of today's modern
amplifier may latch to one of its supply rails when operating above that hybrid power op amps handle currents higher than most branch
temperature (+85C). However, the device will not sustain permanent circuits in residential wiring. Losses can be kept to a minimum,
damage unless the latched condition also violates the safe operating especially as frequencies increase, if leads are as short as possible
area. Simultaneous application of two or more of these maximum between supply and amplifier, as well as between the amplifier and the
stress levels, such as maximum power and temperature, may induce load. In the video frequency range, where even a few inches of wire
permanent damage to the amplifier. have significant inductance, and the skin effect increases the resis-
The generally accepted industry method of specifying absolute tance of heavy wires at high frequency, multi-strand litz wire is
maximum power dissipation assumes the case temperature is held at
recommended.
25C and the junctions are operating at the absolute maximum rating.
This standardization provides a yardstick to compare ratings of various
manufacturers. However, it is not a reliable operating point. An ideal
SINGLE OR ASYMMETRIC
heatsink is required, and even with the best heatsink, it would still result SUPPLY OPERATION
in reduced product life due to operation at extreme temperatures.
APEX recommends maximum junction temperature of 150 or less.
Asymmetric output swings present another opportunity to optimize
power supplies. Consider the circuit of Figure 1. If the symmetric
D
The specifications table should be the prime working document power supplies were used, power dissipation would be substantially
while designing the application. In addition to the minimum/maximum increased, a power op amp with a higher voltage rating would be
parameters (voltage offset, output capability, etc.), this table contains necessary and output power would be reduced.
the guaranteed linear operating ranges: common mode voltage,
temperature ranges, power supplies, etc. +26V
Typical performance graphs are most useful in determining perfor-
mance variation as operating conditions change. For example, all
amplifiers are specified for a minimum voltage output at maximum 47F .1F
current rating. If your application needs only 75% of this current, you
might determine from the typical graph you will gain 0.5V at this level. 2 R CL+
A safe design will assume output capability of 0.5V better than the .15
6
specification table, not the actual number on the typical graph. Bear in 1
mind, if your design is based on the typical performance graphs, it will .9VP-P PA02
statistically work 50% of the time. 5
8
R CL RD
.15 6.5mH
7 3
OPTIMIZING THE POWER SUPPLY 2K
1.8AP-P
To deliver the most output power and achieve maximum efficiency, 47F .1F
internal power dissipation must be minimized. This condition is met if
the power supply voltage is selected for the minimum voltage neces- 7V
sary to produce the required output. Internal power dissipation is the RF
sum of quiescent power plus the product of output current and the
supply to output differential. Supply voltage is the only variable for the 1K RS
designer to optimize. Refer to the product data sheets specified L* I .5
YOKE DRIVER: V =
minimum supply to output differential voltage. Each extra volt here t
dissipates one more watt for every ampere of output current. Trade-
FIGURE 1. HIGH CURRENT ASYMMETRICAL SUPPLY
offs in this area are not recommended. Deriving required outputs from
existing system supplies reduces efficiency if the difference between
supply and required output exceeds the supply to output differential of Fortunately, most power op amps are suitable for operation from a
the op amp. Also, this supply vs. efficiency trade-off must be consid- single supply voltage. The common mode operating requirements do,
ered when contemplating the use of unregulated supplies. When using however, impose the limitation that the input voltages not approach
319
closer than 5 to 10 volts to either supply rail (determined by the
common mode voltage specification). Thus, single supply operation REF
requires the input signals to be biased 5 to 10V from either supply rail. +36V
Figure 2A illustrates one bias technique to achieve this. .2
Figure 2A illustrates a very practical alternative to single supply
operation, a second low voltage supply. This allows ground referenced TEMP.
SET
input signals, but also maximizes the voltage swing of the unipolar POINT
output. The 12 volt supply in Figure 2B must usually supply only the PA73
quiescent current of the power op amp unless the load is reactive or
EMF producing. .2
50K
+210V 5V
2.5K 50K 10
TEMP.
SENSOR
+210V
+210V
50K +50/+200V
2.5/10V 2.5K PA82J
D/A MAX INTERNAL POWER MAX OUTPUT POWER
1/2 VS = 18V VOUT = 28V
50K I OUT = 1.8A IOUT = 2.8A
POUT = 32.4W POUT = 78.4W
PINT = 32.4W PINT = 22.4W
FIGURE 2A. TRUE SINGLE SUPPLY OPERATION FIGURE 3. TEMPERATURE CONTROL CIRCUIT POWER LEVEL
7.2K
+40V
1.3 +24V
50K 5V 1K
+12V
0/5V PA10
D.U.T.
D/A
2K PA81J 1.3
0/125V
40V 24V
130V ICL = .5A * 64V = 32W
FIGURE 2B. ASYMMETRIC SUPPLIES FIGURE 4. PPS POWER DISSIPATION CONSIDERATIONS
on DC thermal resistance. This means an AC only application is

KNOW YOUR POWER DISSIPATION capable of delivering more power or running cooler (more reliably).
Power requirements of the load are most often well known, but Sine wave circuits share a similarity with DC circuits. Maximum
calculating the power dissipated inside the amplifier is not always internal RMS power dissipation occurs when the peak output voltage
simple. swings to 63.7% of supply voltage. Maximum internal power may be
For purely resistive loads, maximum internal power dissipation calculated as follows:
occurs when the output voltage equals half the supply voltage. This is
the worst case to analyze if the amplifier does not have to withstand P = VSS2/(22 * RL)
short circuits. An example of DC application is the temperature
controller in Figure 3. Where: VSS = total rail-to-rail supply voltage
Programmable power supplies (PPS) for automated test equipment RL = load resistance
must often tolerate short circuits in the device under test. For the PPS
shown in Figure 4, the worst case dissipation will occur with a short to REACTIVE LOADS INCREASE DISSIPATION
one of the 24V DUT supplies if the PPS is programmed to the opposite
voltage. Assuming the current limit of the 24V supply is greater than the When driving reactive loads, more caution is required due to the
PPS limit, the PPS goes into current limit with considerably higher phase difference between VO and IO. The actual power dissipation may
power levels than encountered under normal operation. Worst case for be several times higher than the equivalent resistive loads. In such
the amplifier could be its supply voltage plus the DUT supply voltage cases, It is best to use a totally different, but equally simple, approach
times the current limit. to calculate power dissipation (P):
P = P1 PO
AC OUTPUTS ALLOW HIGH POWER LEVELS
Where: P1 = Power drawn from the power supply
If an AC drive has a frequency of 60Hz or greater, the halfwave PO = Real power delivered to the load
period of the power dissipating waveform is shorter than the thermal
time constant of the power amplifier. The resultant power averaging In calculating P1, use DC supply voltage and RMS output current.
between the output transistors results in a lower thermal resistance. For example, a 1A RMS output, with supplies of 15V, means 15W
This lower thermal resistance immediately increases the power han- plus quiescent current * 30V.
dling capability of a given amplifier. Driving purely reactive loads means that all power drawn from the
Apex data sheets provide both AC and DC ratings of thermal supplies is dissipated in the amplifier because the load power factor is
resistance. Power levels specified on both the absolute maximum reduced to zero.
rating and the power derating typical performance graphs are based
320
DEALING WITH MOTOR DRIVES CIRCUIT DESIGNS TO INCREASE
Motor control applications often place brutal requirements on the OUTPUT POWER
driving circuit. Section A of Figure 5 shows two output transistors of Two power op amps configured in a bridge circuit can double
a power amplifier and the motor with its ratings. It is important to power levels. To illustrate the advantages of the bridge circuit, Figure
recognize that the winding resistance and the voltage rating of the 6 shows a composite where alternate connections transform the
motor alone do not determine the running current. The back EMF of circuit from single ended to a bridge. A1 is a standard single ended
the motor must also be considered when calculating the running power op amp which would drive the 4 ohm speaker. If A2 is added,
current. This EMF can be modeled as a battery whose voltage is it completes a bridge circuit. The resulting doubling of the voltage
proportional to instantaneous velocity as shown in Section B of drive would be suitable for an 8 ohm speaker. With this trick, not only
Figure 5. are power levels doubled, but the same supply is capable of
When the amplifier is given a reversal command, it changes its powering either circuit. This is possible because the single ended
output very quickly while the actual speed and EMF can diminish only circuit peak current demand utilizes only 50% of the supply capabil-
as fast as mechanical system inertia is dissipated. The initial result ity. In contrast, the equal and opposite drive characteristics of the
of the vastly different response times between the electronics and bridge circuit loads both positive and negative supply rails equally
the mechanics is shown in Section C of Figure 5. The amplifier has during each half cycle of the signal.
responded to its new drive command, but the EMF has not yet had Parallel operation is often used to increase output current or
time to change. wattage. However, due to their low output impedance, power op
The model shows that if the amplifier could produce the pro- amps cannot be connected in parallel without modifying the circuits.
grammed output level of 24V, a total of 36V would be applied across Figure 7 illustrates one method of doing this. This uncommitted
the winding resistance developing a current on 9A. In this situation, master amplifier, configured as required to satisfy the circuit func-
the output voltage is determined by the current limit of the amplifier tion, has a small sense resistor inside its feedback loop. The slave
rather than the control voltage. The programmed limit of 4A through amplifier is a unity gain buffer. Thus, the output voltages of the two
the winding resistance produces 16V. Adding the initial 12V EMF amplifiers are equal. If the two sense resistors connected to the load
places the amplifier output voltage at -4V. With 24V across the are equal, the amplifiers share current equally. More slaves may be
conducting transistor, the internal power dissipation is eight times added as desired.
the level encountered in steady state operation. Failure to analyze
150K
this situation has taken the lives of many power op amps.
A useful technique to maximize available power for steady state 150K
18K 150K
running requirements is to limit the rate of change of the drive voltage
to approximately the same limitation imposed by the inertia of the +15V +15V
mechanical system. In this manner, the extremely high power levels .47F
.2 .16
described can be avoided. In other words, fast reversal times can be
traded off for high levels of running torque.
1nF 1nF
2.2K A1 A2 2.2K
8
+28V .2 4 36W RMS
18W
RMS .16
15V
15V
FIGURE 6. DOUBLING POWER WITH A BRIDGE
There are two factors to consider in the selection of the sense

resistors. First, the output current will produce a voltage drop which
D
24V @ 3A
RW = 4 adds to the supply requirements. Second, the voltage offset of the
EMF = 12V slave appears across the sum of the two sense resistors. Thus, a
small current will circulate strictly between the two amplifiers. This
wastes power. When this technique is used, it is recommended that
Section A 28V inputs be limited in such a way that they demand only 50% of the
typical slew rate of the amplifier. This prevents two amplifiers with
different slew rates from generating large currents between each
STEADY STATE other during fast transitions.
3A * 4V = 12W 12V 4
+28V RF
I OUT
R1
Section B +24V +12V
RS
MASTER
REVERSAL
4A * 24V = 96W! 12V 4
28V
RS
I LIM
SLAVE
Section C 4V 16V
I LOSS = VOS /RS
V LOSS = I OUT * R S
FIGURE 5. POWER DISSIPATION IN MOTOR DRIVES FIGURE 7. PARALLEL OPERATION
321
PROPER HEATSINKS INCREASE
OUTPUT POWER
With a given power op amp, the larger the heatsink is, the higher
attainable output power can be. Furthermore, as power levels in-
crease, it is more cost effective to use a larger heatsink.
To minimize space and weight, forced air cooling or even liquid
cooling is often used with power amplifiers. While obviously easier to
implement, forced air cooling gives a maximum improvement of only
about 2:1. At higher power levels, liquid cooling becomes a more
attractive option. Reasonable heatsink ratings, which can be achieved
given an area 6 inches square and 2 inches tall, are 0.85C per watt
for free air cooling, 0.4C per watt for forced air, and 0.05C per watt
for a liquid cooled system. See the Apex application note on heatsinking
for more information.
THERMAL SHUTDOWN CAN HELP

Internal thermal protection can increase output power under nomi-
nal operating conditions because the amplifier shuts off when the
substrate temperature exceeds safe limits. This allows the amplifier
circuit design to be based solely on normal conditions but prevents
excessive temperature during abnormally high power conditions.
The thermal shutdown feature is especially valuable in circuits such
as programmable power supplies (PPS). Here the output voltage is the
normal operating voltage of the unit under test. Occasionally the unit
under test will be defective which may short the output of the PPS to
ground; thus, power levels increase substantially. Thermal shutdown
will simply shut the device off rather than lead to destruction. Thermal
shutdown is not a panacea for all problems. It does not mean to
disregard the second breakdown curves of the safe operating area.
Assume the time constant for operation of the thermal shutdown is
250-500ms. This means the worst case power levels should not
exceed the steady state second breakdown line of the SOA curve.
OPTIMIZING IS A TEAM EFFORT

Apex power op amps employ unique thermistor circuits that provide
superior control of internal currents and offer exceptional specifica-
tions plus a superb quality record. With careful attention to design of
the application, the end result will be advanced products of greater
value.
without notice.
322
CURRENT LIMITING
APPLICATION NOTE 9
INTRODUCTION
Power op amp circuits without suitable current limiting can be load implies stress voltage is limited to single supply voltage and that
compared to putting a gun in the hands of a child you may get away maximum heat in the output transistor occurs at an output of 50% of
with it but disaster is waiting to strike. While elaborate circuits have supply. At 25V the SOA graph tells us maximum current is 2.7A. This
been used, most power op amps use a simple and cost effective circuit implies a minimum load of about 9.3 ohms will limit current to safe
which still requires engineering homework to be safe. The objective levels at any output voltage. Maximum current will be 4.75A (44V/9.3
is delivering desired power to the load without violating the SOA. ohms) and maximum output power will be 209W. Note: The voltage
swing specification of the PA10A is Vs-6V at 5A. However, if the
BASIC CURRENT LIMITING application must survive a shorted component or cable on the output,
Current limiting circuits in power op amps are local to only the output the stress voltage jumps to 50 and maximum safe current is only
stage so they can very quickly (sub microsecond) reduce output 1.05A. Once this current limit is set output power is limited to 46W peak
current to a predetermined level. There are at least four reasons to into 44 ohms. For energy storing loads, assume an initial voltage of
incorporate such a limit: nearly -50V and a positive going signal. Initial supply to output stress
is nearly 100V and maximum safe current is less than .3A.
1. The output transistors of the amplifiers are almost always capable
of delivering more current than the ABSOLUTE MAXIMUM RAT-
ING of the amplifier. Exceeding this limit can destroy metal, usually 5.0

a wire bond to the supply or the output pin fuses. A common
t=
mistake is to rely on the power supply current limit for this protec- TH
t=
3.0
t=
ER
0.
tion. Do NOT fall into this trap. Filter capacitors (both inside the MA
1m
5m
5m
Tc L
supply and local to the op amp) often store plenty of energy to =2
s
2.0 5C
vaporize a wire bond. Tc
=8
1.5 5C SE
2. Loads with variable impedance may need protection against Tc
=1 CO
possible fault conditions. A mechanical jam on a motor drive is a 25 ND
good example. 1.0 C
BR
3. Current limit can prevent overloading power supplies. This may be .7 EA
critical if other circuits share the same supply. steady state KD
.5 O
4. Observing the Safe Operating Area (SOA) of the power amplifier W
N
keeps junction temperatures to a reasonable level. Output current
is one term of the power equation. .3
A fixed current limit is usually adequate for the first three reasons. .2
A simple and cost effective approach to current limiting is shown in 10 15 20 25 30 35 40 50 60 70 80 100
Figure 1. Current through the output transistor Q1 is converted to a SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE V S VO (V)
voltage by the sense resistor Rcl. When this voltage exceeds the Vbe
of the current limit transistor Q2, drive current from the preceding stage FIGURE 2. SOA GRAPH OF PA10
is diverted to the output to shut down Q1. In addition to being an D
amplifier, Q2 serves as an imperfect voltage reference for the current
+ 50V
limit set point. At room temperature the typical value is around 0.65V.
Rb along with the capacitance of Q2 slow the circuit just enough to
prevent oscillation. In equation form:
Icl = 0.65/Rcl (1) PA10A
or
Rcl = 0.65/Icl (2)
where Icl is the current limit in amperes and Rcl is the current limit
resistor in ohms. 50V
+VS
FIGURE 3. DIFFICULT LOADS OR POSSIBLE FAULT CONDITIONS

Q1
Rb CURRENT LIMIT IS A MOVING TARGET

Q2 The largest variable of the current limit circuit is the temperature
280 coefficient of the imperfect reference voltage, the Vbe of Q2. It
Rcl decreases approximately 2.2mV for each degree C increase in case
VO temperature. Thus the 0.65 term ranges from 0.826 at -55C to 0.43
at 125C. From an steady state power dissipation point of view, this
slope is in the right direction but it is still possible to get in trouble.
FIGURE 1. CLASSIC CURRENT LIMIT CIRCUIT Comparing this slope to our initial reasons to limit current:
The fourth reason is more complex. Figures 2 and 3 illustrate the 1. The reason does not vary with temperature.
challenge of meeting SOA limitations with fixed current limit. First, note 2. The reason is load dependent.
that the X axis labeling of the PA10 SOA graph is NOT output voltage 3. The reason is supply dependent.
but the stress voltage across the conducting transistor. Assume DC 4. The reason does not vary with temperature.
signals and a case temperature of 25C for the following. The resistive
323
It is best to plot the limit on the SOA graph and compare to other +VS
requirements of the system. To this end, visit the Apex web site at
www.apexmicrotech.com or contact Apex applications engineering
for software to automate the task. Q1
Looking again at Figure 1, we can find several reasons actual
current limit varies from the equations presented. When in the limiting
mode, Q2 is shunting drive stage current away from Q1 directly to the R1
Q2
output. This means actual current limit can not be less than drive stage
280
capability. Some data sheets give a minimum practical current limit.
Operation in this region is unusual because drive stage current is so R CL
R FO
much less than output capability that being in this region implies
amplifier capability is likely an overkill for the application. VO
Now consider that when Q2 is conducting there will be base current
flowing through Rb which effectively increases the reference voltage.
On some amplifiers this effect is large enough that the specific data
sheet will give a unique value greater than 0.65 to use in the equations.
FIGURE 4. BASIC FOLDOVER CURRENT LIMIT CIRCUIT
Although it is not immediately obvious looking at figure 1, resistance
of internal wire bonds, solder joints, wiring traces and the leads of Rcl Looking again at the case of the resistive load driver which must
all add to the rated value of Rcl unless pins are provided to implement tolerate a short on the output, let us further assume the objective is to
four wire current sensing. In high current applications, measurements drive 22 ohms to 88W peak (44Wrms, 44V pk and 2A pk). Start with
of prototype circuits may be the best way to finalize the design. an Rb of 280 ohms and Rfo of 20Kohms and use Equation 4 to
We now have a very wide range of "safe" currents depending on calculate Rcl = 0.629 ohms for peak current at peak voltage. Use a
loads or fault conditions which must be tolerated. We have also seen 0.62 ohm resistor. Equation 1 now shows us current during the short
that while simple and cost effective, these limiting circuits are not fault condition is limited to 1.05A. Plotting the current limit on the SOA
reference standards; think in the area of +/-20%. The sad part is that graph as shown in Figure 5 reveals that this current limit is safe for any
the fixed current limit set to protect for worst case fault condition also output voltage from zero to supply. Using foldover instead of fixed
limits current for the non-fault condition. It is also interesting to note current limit has nearly doubled the power delivery capability.
that we assumed an unrealistic heatsink and safe currents are still only In the case of the energy storing load, Equation 3 shows us this
a fraction of the absolute maximum for the amplifier. This shows the foldover circuit current limit crosses zero and turns negative within the
importance of both heatsinking and current limiting. An ideal solution swing capability of the amplifier at all temperatures above 25C. This
for SOA protection might be the addition of a stress voltage sensor and can cause amplifier latch-up and MUST be avoided. A lower supply
multiplier for each output transistor such that limiting could be based voltage or a larger foldover resistor will solve this problem.
on watts. If all this circuitry is fast enough, SOA concerns would be no Even though we know the current limit is safe for a short to ground
more. This approach is quite rare because the cost measured in and for the full 100V stress level, Figure 5 shows that at 25C and
components, design time and space is almost always more than that colder allowable current crosses above the SOA line in between these
of using a larger amplifier. Clearly, an affordable improvement in points. Increasing Rcl will lower current limit at all output voltages and
current limit technique is called for. solve this problem.
FOLDOVER CURRENT LIMIT BASICS
Apex models PA04, PA05, PA10 and PA12 can take advantage of 10.000
foldover current limiting. Adding only one resistor to the classic current
limiting circuit (Figure 4) provides dynamic response to output voltage
swing. Realizing that Rcl is typically three orders of magnitude below SOA
CURRENT LIMIT, A
Rb, it is reasonable to ignore Rcl and say Rb and Rfo form a voltage
divider between ground and the output voltage. With Rfo typically
being a couple orders of magnitude larger than Rb, the divider adds a 55C
very small portion of the output voltage in series with the base of Q2. 1.000
With a 0V output, current limit will be the same as the classic circuit.
However, as the output goes positive, the addition of the divider
voltage effectively increases the reference voltage (Vbe of Q2) allow- 125C
ing more current to flow. For negative output voltages (Q1 is still
conducting), the very small fraction of the negative output added 85C
reduces current flow. Another way to view this would be state we have
added a term to the current limit equation based on output voltage but 0.100 25C
modifying current limit in an inversely proportional manner to voltage 15.8 25.1 39.8 63.1 100
stress on the conducting transistor. While this is still a long way from
SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE, Vs Vo (V)
the ideal of a multiplier calculating watts, and it does nothing in the case
of variable supplies, it does add a desirable slope to the current limit FIGURE 5. FOLDOVER ILIMIT VS. VOUT
function. In equation form:
Rb
TWO TYPES OF FOLDOVER
ICL =
0.65 + VO
* ( )
RFO + RB
The PA10 and PA12 have an internal Rb of 280 ohms and internal
RCL (3) Rfo of 20K for both the positive and negative current limit transistors.
The two 20K resistors tie together at pin 7 where the user may ground
the pin for maximum foldover slope or add an additional resistor in
Rb series from pin 7 to ground for less foldover action. Since both 280 ohm
RCL =
0.65 + VO
* ( )
RFO + RB
resistors tie essentially to Vo and the two series networks of 0.28K +
20K are essentially in parallel, the equations specific to the PA10 and
ICL (4) PA12 are more complex than the previous example:
where Vo is output voltage in volts and resistors are from Figure 4

and in ohms.
.
324
10.14
*( )( .28
ICL =
0.65 + VO 10.14 + RFO * 20.28 )
RCL (5)
10.14
RCL =
0.65 + VO
* ( 10.14 + RFO )(
*
.28
20.28 )
ICL (6)
where Icl is in amperes, Vo is in volts Rcl is in ohms and Rfo is the

PA10 or PA12 external foldover resistor and is in Kohms.
Foldover connections for the PA04 or PA05 are shown in Figure 6.
Use 270 ohms for Rb and use equations 3 and 4. Beware that even
momentary shorts directly at pin 10 can destroy the amplifier now that
pin 10 is isolated from the output by the 270 ohms.
10
7 Rcl
PA04/05 Vo
Rb
11
Rfo
FIGURE 6. FOLDOVER CIRCUIT FOR PA04 OR PA05
CONCLUSION
Current limit is to the power op amp as survival instinct is to an
animal; a REALLY good thing to have. While basic current limiting is D
simple, adding temperature variations and circuit options such as
foldover make the job of checking all the points of possible danger
quite a chore. First comes the math, then data plotting on the SOA
graph with those log scales we all love so well. This drudgery has
become history with the spreadsheet automation. Get your copy from
the Apex web site at www.apexmicrotech.com or call Apex applica-
tions.
however, FAXis(520)
ORDERS (520) 690-8601
325
POWER AMP OUTPUT IMPEDANCE
APPLICATION NOTE 10
INTRODUCTION ACTUAL IMPEDANCE VALUES

In the design of power amp circuits, the need often arises for a power Several Apex power amplifiers were measured using the gain
amp model with specified output impedance. Most often, this require- variation with loading method. The test circuit of Figure 2 was loaded
ment revolves around the need to accurately predict the phase with 10 ohms. To establish uniformity of measurement, the smallest
performance of power amp circuits. possible amplitude at 10Hz was used. Where a range of values is
Output impedance of any op amp is modified by the feedback shown, it represents a range observed for several devices.
network present around the device. In voltage source type circuits, the PA02: 10-15 ohms
effect of the network is to reduce the output impedance by a factor PA07: 1.5-3 ohms
equal to the ratio of open loop gain to closed loop gain. In power amps, PA08: 1500-1900 ohms (high voltage amplifier)
the net result is an effective output impedance of milliohm levels at PA09: 15-19 ohms
frequencies below 1kHz. Wiring and interconnections often create PA10: 2.5-8 ohms
larger impedances than the output impedance of the closed loop PA12: 2.5-8 ohms
power amp. Therefore, output impedance will play a minor role in the PA19: 30-40 ohms
phase performance at low frequencies. At high frequencies, reactive PA51: 1.5-8 ohms
load considerations are already addressed by capacitive load speci- PA61: 1.5-8 ohms
fications given on many power amplifiers. PA84: 1400-1800 ohms (high voltage amplifier)
Current control circuits, or current sources, include the load as a
series element in the feedback loop with a sense resistor developing VIN VOUT
a voltage proportional to load current. Figure 1 shows a generalized AO =
VIN
example of just such a circuit. The load often consists of an inductive 56.2K
element such as a deflection yoke which can have up to 90 of phase A O = IS UNLOADED
562
shift at higher frequencies. Totally accurate prediction of phase in the VOUT
A'O = IS 10 LOADED
feedback loop might at first seem to involve the series equivalent of 10
AO
output impedance and yoke impedance. In reality, its because the RO = ( 1) R L
feedback the op amp is operating as a true current source with an A'O
10
impedance approaching infinity. A realistic approach to stabilizing the RL
circuit merely involves an auxiliary feedback whose effect dominates
before the combination of yoke feedback and amplifier phase ap-
proaches 180. Output impedance is not necessary to determine
stability. FIGURE 2. OUTPUT IMPEDANCE MEASUREMENT CIRCUIT
It is also important to realize that output impedance of a power op
amp is not related in any way to power delivery capability or internal The high voltage amplifiers are much lower in current capability than
losses. A model of a power amp with the output resistance in series the high current amplifiers. As a result, the higher impedance is to be
with the output will develop inordinate losses which are not observed expected.
in real world op amps. The high impedance shown for PA19 is a result of the drain output
Output impedance is dependent on several variables such as MOSFET circuit without local feedback at the output stage. This is an
frequency, loading and output level. Often, the impedance will rise at example of how this parameter can be misleading. If 30 to 40 ohms
higher frequencies. A class C amplifier, such as PA51 or PA61, will of resistance were in series with the output, then the PA19 would never
exhibit higher impedances at lower levels due to bulk emitter resis- be capable of greater than 1 amp of output current. Under closed loop
tance effects in the emitter follower outputs. conditions, the output impedance is reduced to milliohm levels like any
other power amplifier. Keep in mind the output impedance is an
abstract term as far as output voltage and current capability are
concerned.
To demonstrate the effect of output impedance when modeling, use
LOAD the highest and lowest expected values. The results will verify that
VC output impedance plays an insignificant role in power amp perfor-
mance.
RS
FIGURE 1. GENERALIZED CURRENT CONTROL CIRCUIT
OUTPUT IMPEDANCE MEASUREMENT

Several methods are available to measure output impedance. The
simplest method is to measure open loop gain in loaded and unloaded
conditions. This method measures the dynamic impedance in series
with a perfect voltage source. Variations in output with loading are due
to this impedance.
A more direct method is to generate a signal which is impressed into
the output of an amplifier operating under open loop conditions. A
measurement of current will determine the effective impedance that
this signal is looking into.
omissions. HOTLINE:
without notice.
326
THERMAL TECHNIQUES
APPLICATION NOTE 11
THERMAL MANAGEMENT
As power op amps shrink in size and become more powerful, the (non-isolated) to the APEX PA12 rated at 125W (dissipation). For a
importance of a good thermal design is more critical than ever. Most stipulated audio application, the thermal resistance used is the typical
importantly, reliability is a direct function of internal component tem- AC rating and the power level is 100W for both devices. The table
peratures and dissipated power. Furthermore, as the amplifier case shows the 150W (output) device junction rises nearly twice as much
rises above 25C, derating factors do not just reduce the allowable resulting in questionable reliability at just 100W. An ideal ambient
power level. Voltage and current offsets drift, current limits change temperature and infinite heatsink are assumed.
and, sometimes even dynamic performance is affected. This applica-
tion note discusses thermal management starting with actual dissipa-
150W 125W
tion vs. allowable dissipation, the common cooling options, how to
Output Dissipation
achieve maximum performance with sound mounting techniques, as
JC 1.6 .8
well as the benefits of thermal capacity.
CS .375 .2
Thermal management techniques must be applied to remove as Delta TC 37.5 20
much heat as possible from the semiconductor junction, thereby Delta TJ 197.5 100
maintaining minimum operating temperatures and maximum reliabil-
ity. A further goal is to minimize the effects of the removed heat on other TABLE 1. COMPARING TEMPERATURE RISE
devices. Figure 1 shows the average of NPN and PNP power transistor
failure rates at elevated temperatures relative to operation at 25C. All SYSTEM LAYOUT
electronic components encounter similar increased failure rates. Thermal management starts with determination of actual dissipa-
tion and should result in a layout of an optimized thermal system to
10 This data was extracted from convey the heat to the ambient environment. In systems using natural
the base failure rate tables of convection, heat sources should be separated as widely as possible.
7
FAILURE RATE MULTIPLIER
MIL-HDBK-217C, revision of In contrast, systems using high velocity air or liquid cooling perform
1 May 1980. optimally when localizing these devices. Understanding convection
5
and radiation may help avoid layout related problems. Since con-
4 vected heat rises, it is best to place the heat sources near the top of
the enclosure and avoid having temperature sensitive circuits above
3 or near the heat sources. The hot air should flow in its natural vertical
direction using vertical board and fin orientation. Heatsinks should be
2 oriented so air can pass freely over all the fins.
MOUNTING THE AMPLIFIER

1 The thermal joint from the case to heat sink, HSC, is very important
175 150 125 100 75 50 25 from both design and production points of view. Extreme care must be
JUNCTION TEMPERATURE, TJ(C) taken in this small but critical area. Heat generation occurs near the top
FIGURE 1. MTTF VS. TEMPERATURE
of the silicon chip and typically spreads downward at an angle of 45 D
as it travels through the various materials to the heatsink. The 8 pins
of the package surround the heat source. Unfortunately, the glass
MAXIMUM POWER RATING seals present a high thermal resistance to heat flow toward the outer
JCis the thermal resistance from junction to case. A great deal of edges of the package. To maintain optimum heat flow, heatsink
effort has been put into minimizing this thermal resistance. It is the material should never be removed from the inside of the pin circle. For
major specification affecting power handling capability. When allowing example, drilling one large hole rather than eight small holes to mount
an amplifier will increase thermal resistance dramatically.
for a case temperature of 25C and maximum junction temperature,
Figure 2 illustrates a common mounting setup employing direct
the maximum internal dissipation rating is developed. wiring, using cage jacks and mating sockets. A consistent and stable
thermal joint vs. time, including temperature cycling, is an absolute
PMAX = (TJMAX 25C) / JC (1) must. Compression washers will help to accomplish this. The washers
have a spring-like quality that maintains a constant pressure over
This rating is consistent with rating methods of most transistor temperature. Steel screws should be torqued from 4 to 7 inch-pounds.
manufacturers and should not be confused with advertised output If the assembly process includes a flow or wave solder step after the
power which is highly application dependent. Before using this rating, device has been mounted and torqued down, re-torquing is required.
check for factors which might degrade the rating such as actual Torque control is one of the least expensive but more effective ways
ambient temperature (TR), heatsink thermal resistance (HS) mounting, to maintain the thermal resistance over time.
and in some cases, an isolation washer. There are a number of thermal compounds that have been success-
The optimum heatsink to case thermal resistance (HSC) for a TO-3, fully used for years to fill tiny gaps between cases and heatsinks. Most
using thermal grease and a mica isolation washer, is 0.375C/watt. of these products work well, but a word of caution is in order. The shelf
With thermal grease only or with the Apex TW03 washer, this is life for most thermal greases is indefinite when sealed in its container,
reduced to 0.2C/W. Several references cite 0.1C/W for a TO-3, but but the vehicle and the thermally conductive part may separate. If the
this data is for transistors with only two leads. With eight holes and separated material is used, the resultant joint will have poor thermal
insulating glass restricting heat flow outside the pin circle, design with properties. Mixing the components back into solution restores the
the higher number. Allow 0.1C/W for the MO-127 package. APEX materials thermal properties. To make the re-combination easier, it is
amplifiers have an isolated case which negates the need for isolating best to purchase the grease in a jar instead of the more common tube.
the mounting surface and the mounting screws. Some vendors require In one year, life tests at 100C with compression washers, the thermal
isolation washers. joint did not degrade. However, this vehicle evaporated leaving a dry
joint. This does not degrade the thermal resistance provided the joint
PMAX = (TJMAX TA)/(JC + HS + HSC) (2) is not loosened.
For the heatsink, a vast array of devices are available. The proper
To illustrate the importance of analyzing JC, rather than using match of heatsink to actual power dissipation, in accordance with
advertised ratings, Table 1 compares a 150W (output) rated amplifier Heatsink in General Operating Considerations section, will main-
327
tain a safe junction temperature and determine whether the circuit is R
indestructible or has unpredictable failures. Please note that altitude, I P
air pressure, flow rate, and power level all have a major influence on
heatsink efficiency. Also, a word of caution: forced air heatsink ratings C V C T
are usually functions of linear feet per minute (FPM) or air flow, while
fan ratings are usually given in cubic feet per minute (CFM). For ELECTRICAL THERMAL
example, a four inch diameter fan at 50 CFM pushes that volume
through only 0.087ft2 producing 573 FPM at the fan. Also keep in mind
that if you reduce the airflow cross section below that of the fan, you V
must consult its static pressure curves. V T
PC BOARD Heatsink Power Op Amp

Package t t
dQ = id t = C2V dq = C d( T) = Pd t
I*R=V P* = T
FIGURE 3. ELECTRICAL AND THERMAL MODELS
Cage Jacks Teflon Tubing PC Board sion factor of 10.22 cubic inches per pound, and the Apex HS05
(All Pins) heatsink weight of 1.04 pounds, results in a volume of 10.63 cubic
inches and a thermal capacity of 434 watt-second/C. The time
Power Op Amp constant for this heatsink is the thermal resistance of 1.1C/W x 434
MATING SOCKET Package watt-second/C, or approximately 346 seconds. The thermal resis-
tance rating used above is for a free air mounting only because
application of forced air reduces both thermal resistance and thermal
time constant. Thermal capacity remains constant.
If power is applied as a single pulse, the case temperature follows
the curve in Figure 4. The delta T in C for both heating and cooling
follow these equations :
Heatsink delta THEAT = W*HS (1-et/tau) (3)
delta TCOOL = delta THEAT(et/tau) (4)
Teflon Tubing Mating Socket
(2 Opposite Pins The Figure 4 curve indicates that thermal capacity plays a major
Minimum) role when the duty cycle is extremely low.
Figure 5 shows the initial response to application of repetitive
DIRECT WIRE Power Op Amp pulses. The pulse train is repetitive when the duty cycle does not allow
Package the circuit to return to its initial temperature between pulses. The
following procedure will predict operating temperatures after the
heatsink has reached equilibrium. Peak power is multiplied by duty
t
Teq
t t
Heatsink ON OFF
Teflon Tubing
(All Pins)
Wire
T
FIGURE 2. MOUNTING TECHNIQUES (CROSS SECTION VIEWS)
When utilizing structural elements to dissipate heat, it is advisable

to check the proposed mounting area. Surfaces must be flat and have
a smooth finish. The extrusion flatness of 4mils/inch and a surface FIGURE 4. SINGLE PULSE RESPONSE
finish of 63 micro inches are typical of commercial heatsinks. This is
cycle to arrive at average power. The average temperature of the case
perfectly acceptable in applications using TO-3 packages where
will be TA + (PAVERAGE * HS). To determine the peak power, the pulse
heatsink compound is used and results in a HSC of 0.2C/W as noted
duration and time constant are substituted into equation 3 above.
under power rating. For high power applications or packages larger
Then 1/2 delta heating is added to average temperature to yield the
than the TO-3, a surface flatness of 1 mil/inch is recommended.
maximum case temperature. This case temperature should be used
in conjunction with the SOA curves to determine the maximum power
THERMAL CAPACITY available from the device.
The power levels that can be achieved in the pulse mode of
operation are elevated far above those of steady state operation. This
is due to the thermal capacity of the heatsink. As heat is first applied, Teq
the rate at which the case temperature increases can be compared to t t
its electrical equivalent, the voltage build up on a capacitor of a R-C ON OFF
network. Figure 3 displays this analogy.
The thermal capacity of a mass is the product of its density, specific T
heat and volume. In most tables, the density is given in gm/cm3(multiplied
by 16.39 to yield gm/in3). The specific heat is usually in units cal/cm
C. To obtain the more familiar units of watts-sec/C, convert by FIGURE 5. REPETITIVE PULSE RESPONSE
multiplying by 4.1819. The thermal time constant (Tau) is equal to the
product of thermal resistance and the thermal capacitance. This time
constant defines the rate at which the material reaches thermal
CONCLUSION
equilibrium. The time required to achieve 95% of the equilibrium Thermal management optimizes space, cost and size for your
temperature is 3 times the thermal time constant. power levels and temperature range. When properly applied, it will get
To illustrate the principle, aluminum has a density of 2.7gm/ the heat out and keep your circuits cool; thereby, maintaining the
cm3(44.245gm/in3), and specific heat of .220cal/gmC, yielding highest possible reliability and performance.
9.734cal/C or 40.71 watt-second/C per cubic inch. Using the conver-
without notice.
328
VOLTAGE TO CURRENT CONVERSION
APPLICATION NOTE 13
VOLTAGE TO CURRENT CONVERSION inverting input; components can be included to raise the gain of the
circuit. Figure 2 shows a higher gain version with its equivalent transfer
Voltage controlled current sources (or VCCSs) can be useful for function. Higher gain circuits will lose some accuracy and bandwidth,
applications such as active loads for use in component testing or but can be easier to stabilize.
torque control for motors. Torque control is simplified since torque is RF
a direct function of current in a motor. Current drive in servo loops
reduces the phase lag due to motor inductance and simplifies stabiliz- Cf Rd
ing of the loop.
VCCSs using power op amps will assume one of two basic forms, +VS
depending on whether or not the load needs to be grounded. RI
CURRENT SOURCE: FLOATING LOAD

Figure 1A illustrates the basic circuit of a VCCS for a floating load. LOAD
IO
The load is actually in the feedback path. RS is a current sense resistor V IN RB VS
that develops a voltage proportional to load current.
Note the inclusion of resistor RB in Figure 1A and subsequent figures V IN RF RS
where non-inverting VCCSs are described. This resistor is present to IO = (1 + )
RS RI
prevent the non-inverting input from floating when the input voltage
source is disconnected or goes to high impedance during the power on FOR: R S << R F or R I
cycle. RB provides a path for input bias current of the amplifier and FIGURE 2. VCCS FOR FLOATING LOAD; INCREASED GAIN
commands the amplifier output current to zero in cases where VIN is CONFIGURATION
disconnected or goes to a high impedance. Figure 1B shows an
implementation of a VCCS for a floating load. At low frequencies the Figure 3 shows an inverting VCCS. The input voltage results in an
added components Cf, Rd, and RF have no effect and are included only opposite polarity of current output. Just as in the case of inverting
to insure stability. Considerations for these components are discussed voltage amplifiers, the advantage of not having any common mode
in the section on Stabilizing the Floating Load VCCS covered later in variation at the amplifier input is higher accuracy and lower distortion.
this application note. RF
Cf Rd
+VS
+VS
RI
V IN
V IN RB VS
LOAD
IO
LOAD D
VS
RS V IN RF RS
I O =
RS RI
FOR: R S << R F or R I
FIGURE 1A. BASIC VCCS FOR FLOATING LOAD
RF FIGURE 3. VCCS FOR FLOATING LOAD; INVERTING
CONFIGURATION
Cf Rd
Figure 4 is a current input version which is actually a CCCS, or
+VS current controlled current source. This is truly a current amplifier. This
circuit could be useful with current output Digital-to-Analog Converters
(DACs), or in any application where a current is available as an input.
RF
LOAD Cf Rd
IO
V IN RB VS
+VS
I IN
V IN RS
IO =
RS
FIGURE 1B. VCCS FOR FLOATING LOAD WITH STABILITY LOAD

IO
COMPENSATION VS
The amplifiers loop gain will force the voltage across RS to assume
I IN R F RS
a value equal to the voltage applied to the non-inverting input, resulting I O =
in a transfer function of: RS
IO=VIN/RS FOR: R S << R F
Several variations are possible for this basic circuit. It is not FIGURE 4. CCCS FOR FLOATING LOAD; INVERTING
necessary to have a direct feedback connection from RS to the CONFIGURATION
329
STABILIZING THE FLOATING LOAD VCCS RF
Because the load is in the feedback loop on all of these circuits, it 100
Cf Rd FB #2
will have a significant effect on stability. If the load was always purely
resistive, the analysis would be simple and many circuits would not +VS .047F 332
require any additional components (such as Cf and Rd) to insure
stability. In the real world however, we usually find ourselves using
these circuits to drive such complex loads as magnetic coils and
motors. PA07
Stability analysis is most easily accomplished using Rate of LL
Closure techniques where the response of the the feedback is RB FB #1 50H
V IN
plotted against the amplifier open loop gain. This technique uses 100K
information easily obtained on any amplifier data sheet. VS RL
Rate-of-closure refers to how the response of the feedback and 1.0
amplifier Aol intersect. If the slope of the combined intersection is not SMALL SIGNAL RESPONSE
over 20 dB per decade, the circuit will be stable. 120

For an example, consider the amplifier of Figure 1A. Assume a RS
100 0.5
PA07 amplifier with a 0.5 ohm current sense resistor will be used to
drive a 50 H coil with 1 ohm of series resistance. In Figure 5 we have 80
FB #1
superimposed on the Aol graph of the PA07 the response of the load 60
and sense resistor. FB #2
40
20
+VS
0 A
20
1 10 100 1K 10K .1M 1M 10M
PA07
FREQUENCY, F(Hz)
LL
RB 50H
V IN VS
FIGURE 6. COMPENSATING THE AMPLIFIER
100K
RL
1.0 CURRENT OUTPUT FOR GROUNDED LOAD
SMALL SIGNAL RESPONSE The VCCS for a grounded load is sometimes referred to as the
120 Improved Howland Current Pump. It is actually a differential
RS amplifier which senses both input signal and feedback differentially.

100 0.5
Feedback Figure 7 shows a general example for this VCCS with its associated
80 Response transfer function .
(1/)
60 RF
40dB/decade
40 rate of
closure
20 +VS
RI
0 R L+R S
Fz =
1/ DC 2L L RS
20
1 10 100 1K 10K .1M 1M 10M RI
FREQUENCY, F(Hz) IO
V IN -VS
.5 1.0 + .5 RF
DC = = .333 1/ = 9.5dB Fz = = 4.77kHz LOAD
1.5 2 50H V IN RF
IO =
RS RI
FIGURE 5. PLOTTING FEEDBACK RESPONSES
FOR: R S << R F or R I
The intersection of the responses exhibits a combined slope of 40 FIGURE 7. VCCS FOR A GROUNDED LOAD
dB per decade, leading to ringing or outright oscillation. Lets refer to
that point as the critical intersection frequency. Compensation for First among the special considerations for this circuit is that the two
this circuit is best accomplished with an alternate feedback path; the input resistors (RI), and the two feedback resistors (RF), must be
response of which will dominate at the critical intersection frequency. closely matched. Even slight mismatching will cause large errors in the
A good criteria for the response of the alternate feedback would be: transfer function and degrade the output impedance causing the circuit
1. A response which dominates by at least an order of magnitude (20
dB) at the critical intersection frequency. RF'
2. The alternate feedback response should have a corner occurring
10.0007K
at a frequency an order of magnitude less than the critical intersec-
tion frequency. +VS
RI ' IO
To provide this response, the alternate feedback components have
been selected to provide the compensating response illustrated in V IN 10K RS
Figure 6. AB in Figure 6 is the dominant feedback path the amplifier will RI PA07 Zo =
0.1 43K with
see in its closed loop configuration. RF merely acts as a ground leg
return impedance for the alternate feedback loop, and should be a low 10K R*C EXACT R F, R I
VALUES
value between 100 and 1000 ohms. Rd is then selected to provide the VS SHOWN
RF C*C
desired high frequency gain, and Cf is selected for the alternate
feedback corner. I O = -10A/Volt input 10K
Note that these are similar to techniques used to stabilize magnetic
deflection amplifiers described in Apex AN #5, Precision Magnetic * OPTIONAL COMPENSATIONSEE TEXT
Deflection. FIGURE 8. ACTUAL PA07 VCCS
330
to become less of a true current source. APPENDIX A.
As an example of the matching requirement, consider the actual
example using PA07 in Figure 8. Matching the resistors as closely as
tolerances permitted produced an output impedance of 43 K ohms.
RATE-OF-CLOSURE AND
A 1% mismatch reduced output impedance to 200 ohms and FEEDBACK RESPONSE
introduced nearly 20% error into the transfer function. Rate-of-closure stability analysis techniques are a method of
This suggests that matching to better than 0.1% is required which plotting feedback response against amplifier response to determine
is probably best accomplished with prepackaged resistor networks stability.
with excellent ratio match. The circuit of Figure 8 actually required a The closed loop gain of any feedback amplifier is given by:
slight amount of mismatch in the two (RF) resistors to compensate for Acl = Aol/(1-Aol)
mismatches elsewhere, suggesting that the inclusion of a trimpot
may be necessary to obtain maximum performance. Where: Aol IS THE OPEN-LOOP GAIN OF THE AMPLIFIER,
AND Acl IS THE RESULTANT CLOSED LOOP GAIN
STABILITY WITH THE GROUNDED is a term describing the attenuation from the output signal to the
signal fed back to the input (see Figure 10). In other words, is the
LOAD CIRCUIT ratio of voltage fed back to the amplifier over the amplifiers output
The grounded load circuit is remarkably forgiving from a stability voltage. (Vfeedback=Vout)
standpoint. Generally, no additional measures need to be taken to In the examples used in this application note, the plotting of
insure stability. versus amplifier response is facilitated by plotting an equivalent
Any stability problems that do arise are likely to be a result of the closed loop response (1/) of the amplifier circuit and superimposing
output impedance of the circuit appearing capacitive. The equivalent this response on the amplifier open loop response. This equivalent
capacitance can be expressed as follows: closed loop response is also referred to as noise gain, Av (n).
In the example in Figure 5, the curve referred to as feedback
RI + RF response is actually representative of the closed loop noise gain
Ceq = response of the amplifier due to the feedback network consisting of
2foRIRS yoke and sense resistor. In Figure 6, an additional feedback re-
Where: fo = THE GAIN-BANDWIDTH PRODUCT OF THE sponse for Cf, Rd, and RF is plotted independently of all other
AMPLIFIER responses. There are several important points to be noted in the use
of these graphs:
This capacitance can resonate with inductive loads, resulting 1. In the case of multiple feedback networks such as in Figure 6, the
most often in ringing problems with rapid transitions. The only response with the lowest noise gain at any given frequency will be
effective compensation is a simple Q-snubber technique: deter- the dominant feedback path. In Figure 6 this dominant feedback
mine the resonant frequency of the inductive load and output path is labelled A.
capacitance of the circuit. Then, select a resistor value one-tenth the 2. Whenever the noise gain and open loop gain intersect with a
reactance of the inductor at the resonant frequency. Add a series combined slope, or rate of closure, exceeding 20 dB/decade,
capacitor with a reactance at the resonant frequency equal to one- poor stability will result. 40 dB/decade will definitely oscillate
tenth of the resistor value. An alternate method would be to put a since this represents 180 degrees of phase shift. An example of
small inductor and damping resistor in series with RS. this is shown in Figure 5.
Also keep in mind that the equation favors larger values of RI and
RS, and the use of op amps with better gain-bandwidth to reduce +V S
effective capacitance. In circuits where good high frequency per-
formance is required, this will necessitate increasing either or both RI
and RS with the upper limits being established where stray capaci- V IN VO
tance and amplifier input capacitance become significant.
An infrequent second cause of instability in this circuit is due to
negative resistance in the output impedance characteristic of the ZF
D
circuit. This problem can be solved by trimming the feedback V S
resistors to improve matching. V FB
THE CURRENT MIRROR V FB ZI ZI

The current mirror circuit is a handy device for generating a = =
VO Z I +Z F
second current that is proportional to input current but opposite in
direction.
The mirror in Figure 9 must be driven from a true current source FIGURE 10. FEEDBACK FACTOR,
in order to have flexible voltage compliance at the input. Any input
current will attempt to develop a drop across R1 which will be
matched by the drop across R2 causing the current through R2 to be
ratioed to that in R1. For example, if R1 were 1.0 K ohm and R2 were
1 ohm, then 1 mA of input current will produce 1 Amp of output
current.
R1
+VS
I IN
(MUST BE R1
TRUE I O = I IN
R2
CURRENT
SOURCE)
VS
R2
IO
FIGURE 9. CURRENT MIRROR
however, FAXis(520)
ORDERS (520) 690-8601
331
POWER BOOSTER APPLICATIONS
APPLICATION NOTE 14
The Apex PB series of power booster amplifiers, PB50 and PB58, An example for determining the Aol (open loop gain) response of the
are high performance, yet economical and flexible, solutions to a wide composite amplifier is illustrated in Figure 1. At any given point on the
variety of applications. Their voltage and current ratings of up to 200 frequency response, the overall gain is the sum of the gains (in dB) of
volts at 2 amps for the PB50, and 300 volts at 1.5 amps for the PB58, the two amplifiers.
satisfy most high voltage and high current requirements. In addition,
the PB series is fast. The 100 V/s slew rate these boosters offer is 120
matched or exceeded by only a few expensive power or high voltage
Ao
lR
op amps. If accuracy, in the form of low offset, drift, and/or bias current, 100
ES
is the system requirement, the PB series, with the proper choice of
PO
driver amplifier, can deliver high voltage performance with accuracy
NS
equal to the best small-signal op amps available on the market, and do 80
Ao
E
O
lR
GAIN (dB)
it economically.
F
ES
CO
PO
60
M
DESIGNING WITH BOOSTER
PO
NS
SI
E
AMPLIFIERS: BASIC CONNECTIONS
TE
O
40
AM
TL
Power supply requirements for the PB50 dictate that the negative
07
PL
supply rail must be at least 30 Volts below the COMMON terminal (pin
IF
20
IE
5), setting the minimum supply voltage at +/-30 V. The PB58 can
R
RESPONSE OF PB58 @ AVCL = 3
operate from supplies as low as +/-15 volts.
The INPUT terminal of the PB series devices is a low impedance 0
input typically on the order of 50 K. Maximum safe input voltage 1 10 100 1K 10K 100K 1M 10M
range must be limited to less than +/-15 volts. These power boosters
will always have an offset of typically .75 volts as a result of the FIGURE 1. PLOTTING Aol FOR THE COMPOSITE AMPLIFIER
common base bipolar input stage. When used with a driver amplifier,
this offset will subtract from the swing available from the driver. For Figure 2 shows an example of such a plot for the deflection amplifier
example, a driver op amp that is required to swing 20 volts peak-to- described in this application note. As a general rule, the intersection of
peak will actually swing -10.75 and +9.25 volts. This offset has no the feedback response and open loop response should equate to a
effect on offset of the total driver and booster circuit since this offset is slope of no greater than 20 dB/decade to insure stability.
effectively reduced by the open loop gain of the driver amplifier. The particular deflection amplifier described in this application note
Remember that this offset will always be apparent when used without is a testament to the ease with which the PB series devices can be
a driver amplifier. designed into circuits where stability is usually a problem. The mag-
The COMMON terminal provides a ground reference for the internal netic deflection circuit, which is a current source with an inductive load
input and feedback circuitry. It might be noted that it is possible to use inside the feedback loop, is inherently unstable. The composite
this ground terminal as an input; however, the PB series has not been amplifier responded quite well to standard techniques used to stabilize
characterized for such usage. The ground terminal would appear as a deflection amplifiers (see AN #5, Precision Magnetic Deflection)
low impedance inverting input which must be driven from a low and presented no special stability problems.
impedance source such as an op amp output. The designer who may be apprehensive about using a booster
The GAIN terminal allows the connection of additional resistance in (buffer with gain) need have no reservations when using PB50 or
series with the built-in feedback resistor of the PB series. The compen- PB58.
sation capacitor connected to COMP, pin 8, is in parallel with the 120
feedback resistor. Designers can predict the frequency response of
the PB series amplifiers for any compensation by simply calculating
CO
100
AU
the pole frequency of the parallel connection of feedback resistor, RG,

M
XI
PO
and compensation capacitor. The pole frequency is given by:

LI
SI
AR
80
TE
Y
1
FE
Ao
GAIN (dB)
FP =
ED
2(RG+6.2K)CC
BA
60
Fp
KC
Where: RG = EXTERNAL FEEDB ACK RESISTANCE Fz (due to Cf,

CC = EXTERNAL COMPENSATION CAPACITOR 40 (due to Rd, RF //R I )
R L , L L , RS )
For example, a 22 pF compensation capacitor across the 6.2 K ohm PRIMARY
feedback resistor results in a pole frequency of 1.2 MHz. This corre- 20 FEEDBACK
sponds with the Closed Loop Small Signal Response graph on the PB50
data sheet. A gain of 10 will require placing a 22 K ohm resistor in series DOMINANT FEEDBACK PATH
0
with the built-in 6.2 K ohm internal feedback for a total feedback 1 10 100 1K 10K 100K 1M 10M
resistance of approximately 28 K ohm. In this case a 22 pF compensa-
tion capacitor produces a rolloff at 260 kHz, again corresponding to the FIGURE 2. DEFLECTION AMPLIFIER FEEDBACK (I/)
PB50 small signal response graph.
APPLICATION EXAMPLES: PROGRAMMABLE POWER
COMPOSITE AMPLIFIER STABILITY
CONSIDERATIONS SUPPLIES
The programmable power supply (PPS) application is useful to
The PB series data sheets provide 4 guidelines for insuring the
demonstrate the versatility of the PB series boosters. Along with the
stability of circuits designed with these boosters. Use of these guidelines
need to supply high voltages and currents, programmable power
can be complemented by the use of standard techniques such as
supplies often need high accuracy and low drift, while at other times
plotting the overall gain response of the driver/booster combination and
they may need to be fast-responding. The PB series allows the
superimposing the feedback network response.
332
+150V
designer to optimize the circuit for these choices. Figure 3 is an
example of a high accuracy PPS. An AD707 is selected as the driver +15V HV SWITCH
amplifier to provide the extremely low offset required to obtain best
possible performance from a high accuracy 18-bit DAC. The divider
R1 R CL
network on the output, R1 and R2, scale the output swing down to the +15V
full-scale range of the DAC. Accuracy will be affected by this divider, 1K C1 4 3 .4
necessitating the use of high quality, low temperature coefficient .001F TL071 2
V IN
(TC) resistors. If a packaged network can be used, then absolute TC 1
PB58
is not nearly as important as TC ratio between R1 and R2. The use 5 CC
7 8
of this divider is preferable to the alternative technique of using an 6 22pF
external DAC feedback resistor, since using the internal DAC feed- 15V
R G=0
back resistor insures the best possible temperature drift perfor-
mance of the DAC itself. Most DACs can exhibit up to 300 ppm/C
drift with external feedback resistors. HV SWITCH 15V
R1
Cf Rd
150V
R2 130K
+15V 10K RL
AD1139 24.3K
R FB 68pF IO .75
10K +280V R CL LL
YOKE 200H
1mA 4 3 RF
I DAC AD707 2 VO
1
18-BIT DAC PB58 3.9K
5 CC RI RS
7 8 (0-270
1K .5
6 Volts) I O = (9.8) (VIN )
15V
15V RG FIGURE 4. ELECTROMAGNETIC DEFLECTION AMPLIFIER
R FB R2 + R2 R1 + R1 R FB
V O = I DAC = I DAC (270K) amplifier enhances the driver amplifiers ability to maintain overall
R2 loop control by preventing the coupling of supply switching transients
into the input section of the amplifier.
FIGURE 3. HIGH ACCURACY PPS Figure 4 provides a general idea of the circuitry involved in switching
the supply rails. The actual implementation could take on many forms
APPLICATIONS AT LESS THAN FULL that are beyond the scope of this application note.
A final performance consideration in magnetic deflection amplifiers
VOLTAGE AND CURRENT is avoidance of slew rate overload (or any condition which could result
The PB series do not have to be used at high voltages to realize in input overload). This problem actually occurs during the rapid
all their performance benefits. Presently, only a few expensive IC retrace transition, but shows up during the trace interval. The evidence
power amplifiers can match these parts for slew rate and power of input overload is ringing during the trace interval. To eliminate this
bandwidth. Magnetic deflection applications require amplifiers with problem, reduce the transition time of the retrace portion of the input
good speed performance at current levels often within those that the waveform to a rate which is within the slew rate specification of the
PB series can supply. While these applications dont always require amplifier. Slower transition times do not necessarily reduce circuit
high supply voltages, the high voltage capability of the PB series is performance since the amplifier was overloaded to begin with, and
useful when fast transitions are required with high inductance yokes, eliminating ringing is actually an improvement on settling time when
necessitating high supply voltages as a result of the yoke energy returning to the trace interval. Controlling input slew rate can be
requirement:
accomplished in many ways. If the actual risetime of the input signal
itself cannot be controlled, a simple lowpass R-C filter at the input of
D
dI the amplifier will suffice. In the example shown in Figure 4., R1 and C1
V=L provide a filter which limits the slew rate of any input signal rise time to
dt
within the amplifiers slew rate.
The basic techniques of magnetic deflection amplifier design are
detailed in AN#5, Precision Magnetic Deflection. Figure 4 is an Selection of the correct filter time constant takes into account both
amplifier slew rate and gain of the circuit. In the case of a magnetic
example of these techniques put to use in the design of a magnetic
deflection amplifier, the appropriate value for gain would be the
deflection amplifier using the PB58. This circuit forces a yoke current
effective gain of the alternate feedback path Cf and Rd.
proportional to input voltage by including the yoke within a current
sensing feedback loop. In this example, the feedback resistors RF VIN Av
and RI are configured for a minimum gain of 5 to compensate for the t=
added booster gain, thereby easing stability considerations. The SR
auxiliary feedback network Cf and Rd act to bypass the 90 phase Where: VIN = PEAK TO PEAK INPUT VOLTAGE
shift of the yoke/sense resistor feedback at higher frequencies Av = COMPOSITE AMPLIFIER CLOSED LOOP GAIN
ensuring stability with best transition times. The fastest transition SR = RATED SLEW RATE OF THE AMPLIFIER
time in any magnetic deflection amplifier is determined by the
available voltage swing and yoke inductance. In the circuit of Figure BOOSTER WITH NO DRIVER
4, nearly 140 volts could be made available for the 200 microhenry
yoke, resulting in a minimum possible transition time of 2 microsec- It is entirely possible to use power boosters without an external
onds. The TL071 and PB58 combination can slew at 40 V/microsec- driver. This could be done for simplicity or economy. It also provides
ond which means the amplifier requires an additional 4 microsec- the best slew rate and bandwidth performance possible with the PB
onds to provide full voltage swing. The end result is a circuit that can series. All of this is made possible due to the boosters self-contained
deliver total transition times of less than 6 microseconds, equating to internal feedback loop.
sweep speeds of 83 kHz. When used without a driver, the PB50 will have an inherent offset
An important advantage of a separate booster amplifier in deflec- of typically 750 millivolts. Harmonic distortion remains under 0.5% at
tion applications is the ability to swing the output stage supply rails up to 30 kHz. Input impedance will be 25 K ohms minimum. Power
to improve efficiency. Slower sweep speeds can use lower power bandwidth will typically be the full 320 kHz at the 100 Volts P-P output
supply voltages than higher speeds. In addition, during a high speed the PB50 is capable of.
sweep the high voltage is only needed for a short period of time until The ground terminal on pin 5 of the PB50 presents possibilities as
yoke current builds and can then be switched to a lower value. Using an additional input. Some improvement in bandwidth would be noted
the lower supply voltages whenever possible improves efficiency if this terminal were used as an input with the actual input terminal
and reduces dissipation. In applications where the supply rails will be grounded. This forces the input transistor into a cascode connection.
flexed in this manner, only the rails connected to the power It is possible to utilize the booster as if it had true op amp type inverting
booster need to be flexed. The constant supply available at the driver and non-inverting inputs.
however, FAXis(520)
ORDERS (520) 690-8601
333
SOA ADVANTAGES OF MOSFETS
APPLICATION NOTE 16
40
20
NEW MOSFET POWER OP AMPS EASE
SAFE OPERATING AREA LIMITATIONS
Hybrid power op amps continue to provide higher levels of perfor-
mance and power handling than their monolithic counterparts. Power
MOSFETs promise to continue the dominance of the hybrid power op
A
SO
amp in terms of power delivery and Safe Operating Area (SOA).
Protection issues must not be neglected regardless of amplifier 3
choice, but the compromises required to protect the amplifier are
eased with MOSFET designs. Protection of an amplifier is a matter of 4 1
keeping it within its SOA under all expected conditions including faults
Amperes
2 2
such as short circuits. 0
An example of a common mistake in selecting an amplifier for a 2 2
motor drive application is to use a 5A rated amplifier to drive a 1A 4 1
motor. Specifying an amplifier for a motor drive application is not that
simple, and stall or reversal conditions could overstress the amplifier. 3
Here is an illustration using a motor with the following specifications:
A
Winding resistance: 1.24 ohms
SO
Voltage constant: 7.41V/K RPM
Torque constant: 10oz/in/A
The actual running current depends on the required torque. Of most

concern is the worst-case current requirements that occur under stall 20
50 40 0 50
and acceleration conditions. Under stall conditions, the amplifier is Volts
presented with a load equal to the winding resistance of the motor. This
condition must be within the SOA of the amplifier. FIGURE 2. PLOT OF OUTPUT VOLTAGE AND CURRENT WITH
The motors speed determines the applied voltage. If there are SOA SUPERIMPOSED
sudden reversals, the motor back EMF could theoretically reach a Proper selection of current limit will determine if an amplifier is safe
value equal to the full applied voltage or equal to the amplifiers supply under fault conditions. One way of viewing this limitation is to draw a
rails. This would be equivalent to shorting the amplifier output to one graph of output voltage and current, and superimpose SOA limits as
of its supply rails with only the motor winding resistance in series. shown in Figure 2. This graph (PA04 and 50V supplies shown)
While the MOSFET power op amps are often featured for their high illustrates how greater currents are available when the output voltage
speeds, motor drive applications can take advantage of the MOSFET swings closest to the rail supplying the current. The tradeoff occurs
SOA that is free from second breakdown. Second breakdown is a when setting current limits, usually for either of two fault conditions:
limitation of all bipolar output power op amps. Second breakdown shorts to ground or shorts to either supply rail. A stalled motor is
severely limits an op amp's current capacity under conditions of high equivalent to a short to ground through the motor winding resistance,
voltage stress. The MOSFET on the other hand is strictly limited by its while a reversal could assume the stresses of a short to either rail.
power dissipation, or thermal limits. Figure 1compares the 25C SOA
of the PA04 MOSFET amplifier with the bipolar PA03. While the PA03 +VS
is rated for higher currents and dissipation, the PA04 has greater
current capacity when there is more than 110V stress on the output 470pF
devices.
RF
40
30 PA THE Rb
03 RM
20 T AL 11
C =
25 PA04 OUTPUT
C 7
10 Rcl
Amperes
10
PA
04
5 T
BR
=2
SE AK
C
5C
E
CO DO
VS
ND WN
FIGURE 3. FOLDOVER CURRENT LIMITING CIRCUIT
From Figure 2, line 1, a limit safe for shorts to ground would be 4A

(4A*50V=200W). This is well below the amplifiers full 20A capability.
1 Even more stringent is the current limit for a short to either rail of 2A
10 20 50 60 100 200
Voltage indicated by line 2 of Figure 2. A 2A limit, combined with external
FIGURE 1. COMPARISON OF SOA FOR BIPOLAR (PA03) AND flyback diodes, would result in an amplifier tolerant of virtually any short
POWER MOSFET (PA04) POWER OP AMPS or voltage kickback stress on its output. Keep in mind that this brief
example uses as its basis, the 25C SOA limits. In reality, internal
For 25C SOA calculations with a MOSFET amplifier an SOA graph dissipation and heatsinking limitations elevate temperatures, further
is not even necessary. As long as the product of voltage and current reducing safe current levels.
stress is within the power dissipation rating, the amplifier is safe.
MOSFETs, to reiterate, are strictly power limited.
334
FOLDOVER CURRENT LIMITING saturation. Using these terminals reduces the swing-to-rail to 5.3V at
20A for 106W dissipation. At 15A it is 4.7V for 60.5W dissipation.
The PA04 features four-wire current limit to overcome sensing Several methods can be used to supply the higher voltage required
errors occurring when working with such low resistances. While this by the front-end. Additional power transformers, or additional taps on
four-wire current limit is useful in improving accuracy of current limit, existing power transformers, or additional regulated supplies are
it also facilitates implementing foldover current limiting. This limiting is obvious options. Modern voltage converter ICs make it inexpensive to
known as load line limiting. develop these voltages under almost any condition. In Figure 4, zener
Foldover current limit allows more amplifier current as the output regulated voltages are referred to each rail and provide power to
swings closer to the rail supplying the current shown by line 3 in Figure Maxim voltage converter ICs to develop the boost potentials.
2. Figure 3 shows the circuit to implement foldover current limiting. Rb
and Rf configure a voltage divider that reduces the signal to the current
limit transistors as the output swings closer to the current-supplying MOSFET ADVANTAGES AT HIGHER VOLTAGES
rail. Rf determines the slope of the foldover function. The value The PA04 is rated at 100V or 200V rail-to-rail. This is twice the
selected for Rb corresponds to the similar resistor internal to PA12 rating of any bipolar hybrid power op amp other than PA03, and 2.5
(actually 280 ohms) so that equations and methods developed for use times the rating of any monolithic power op amp.
with PA12 foldover limiting would be easily applied to PA04 external MOSFETs have made possible this increase in voltage ratings and
foldover limiting. The capacitor across Rb prevents stability problems this can be useful in motor drive applications at high voltages.
while in current limit. Surprisingly, some DC motors require voltages around 100 volts. The
The foldover slope must not be too steep, or latching may occur. PB50 power booster is a low-cost hybrid buffer with gain that gives the
This sets a limit to the value of Rf equal to VS/.0025 which results in a same 100 volt capability of PA04 with a maximum current of 2A.
foldover characteristic where current available when the voltage Because the PB50 is a MOSFET device, it can still provide 200mA at
output has swung fully to the rail opposite to the one supplying current a full 200V stress.
is zero. The current available when the output is closest to the rail An upgrade to the PB50 is the PB58 providing voltage capability up
supplying current is twice that available when the output is at zero to 150 volts. While PB58 is rated 1.5A, the premium PB58A is
volts. When using PA12 equations, substitute this value of Rf, in specified up to 2A. A key advantage of PB58, especially for motor
Kohms. drives, is its 87W dissipation. Operated at 100V, the PB58 can
A PA04 incorporating foldover limiting at 50V and requiring safety provide 435mA with complete safety. At 50V, PB58 can deliver up to
for a short to ground, would have RCL selected for a 4A limit (this 870mA. This is well over twice what could be tolerated from an
presumes the amplifier case can be maintained at 25C for the amplifier such as the PA12 under the same conditions, much less from
duration of the short, otherwise it would have to be reduced further to monolithic power op amps.
stay within temperature limitations). The foldover limiting would then Both PB50 and PB58 are power booster amplifiers, not stand alone
allow 8A at full output swing, or near zero current when delivering op amps. Refer to PB50 and PB58 data sheets for typical examples of
current from the rail opposite the output voltage polarity. A bipolar actual composite amplifier circuits. Several alternatives are given.
amplifier such as PA12 would be limited to 3.2A under the same They range from low speed, high accuracy circuits, to high speed
criteria. The most powerful monolithic would be limited to 300mA circuits.
because it is configured only for simple single resistor current limiting.
ADVANCED AMPLIFIER PROTECTION
330H
+Vboost 15
+V 10
PA
4 5 12
.1F T
5 C =2
Amperes
5C
100F
Max632 3
1 3
7
2
PB58 TC = 25C
D
1.5
BR
10F 1
SE AKD
E
CO OW
.7
ND N
.6
(a) Positive Vboost
.3
10 50 20100 200 300
Volts
7 8 1 FIGURE 5. COMPARISON OF SOA FOR PA12 AND PB58
6
The PA04s adaptability to foldover current limiting is important but
Max636 100F not the last word in protection. Prior efforts at SOA protection have
330F
been based on bipolar transistor designs sensing output transistor
10F temperature combined with current limiting. These techniques have
3 4 5
shortcomings when overstress occurs while operating in the second
breakdown region of bipolar power devices. The isolated hot spot
occurring during second breakdown can escape sensing by the
temperature sensor.
For example, PA03 senses power transistor temperature to provide
V a high degree of protection. But at total rail-to-rail voltages in excess
(b) Negative
of 60V (30V), second breakdown still makes the amplifier prone to
FIGURE 4. VOLTAGE BOOST CIRCUITS failure in extreme stresses.
In a MOSFET power output device, if a local hot spot occurs, the
local transconductance decreases along with an increase in Rds at the
SATURATION VOLTAGE AND BOOST PINS hot spot. This facilitates thermal spreading rather than concentrating
In motor drive applications at lower voltages, the saturation voltage, heat. As a result thermal sensing should prove extremely effective with
described on the data sheet as voltage swing, the PA04 could result power MOSFETs. Apex is developing such amplifiers and early
in considerable power dissipation. At 15A, the PA04 output can only testing has shown that this may be the key to ultimate amplifier
swing to within 8.8 volts of the rail resulting in 132W of dissipation. protection.
Boost pins are provided on the PA04 to power the front-end of the
amplifier on voltages higher than the output stage, thus improving
however, FAXis(520)
ORDERS (520) 690-8601
335
WIDEBAND, LOW DISTORTION TECHNIQUES
APPLICATION NOTE 17
WIDEBAND, LOW DISTORTION TECHNIQUES FOR

MOSFET POWER AMPS
Shake table systems, function generators and acoustic instruments It is obvious that open loop distortion is an important criteria in
all have requirements similar to quality audio amplifiers: wide band- amplifier selection. A high open loop gain is also desirable, but op
widths along with low distortion. In the past, industrial grade power op amps with high open loop gains most often have a severe tradeoff in
amps have traded off bandwidth to insure unity gain stability, and the gain-bandwidth.
bipolar designs have not always met the linearity requirements of The minimum useful closed loop gain is determined by the ampli-
demanding applications. The PA04 changes all this with a MOSFET tude of the drive signal available to the power op amp circuit. Most often
based architecture that sets new standards for bandwidth and linearity this drive is likely to come from a small signal op amp with the
of integrated circuit power amplifiers. customary 10 V peak drive capability. If for example a PA04 power
The development of the PA04 was driven by sonar application op amp is being designed which operates at the full 100 V supply rail
requirements for a highly linear, high power amplifier with a power limit of the PA04, this will require a minimum gain of 10.
bandwidth in excess of 100 kHz. MOSFETs are the optimum choice In the event the drive signal is not a full 10V peak, a tradeoff must
power device to provide this performance, and in the PA04 Apex goes be made as to whether the power op amp should be operated at a
several steps further in using MOSFETs in all active gain stages. higher gain, or an additional small signal op amp be included for
While this application note will focus on getting best bandwidth and additional gain. Consider that the additional small signal op amp will
linearity from the PA04, the techniques described apply to any power result in insignificant contributions to distortion as long as its gain is low
op amp. (<30). The light loading of the power amp circuit further minimizes
Op amps depend on negative feedback to improve performance in distortion from the small signal op amp. These considerations favor
all ways including accuracy, linearity and bandwidth. The ideal condi- this multiple op amp approach with a lower gain power op amp
tion is to use feedback around a design which has inherently good compared to a single high gain power op amp.
open loop characteristics. Evaluation of prospective amplifiers under Low closed loop gain in the power op amp equates to increased
open loop conditions quickly reveals linearity and bandwidth deficien- amounts of negative feedback. This condition occasionally meets with
cies. Even a simple distortion measurement under open loop condi- unfounded objections when the requirement is low distortion, espe-
tions will give rapid comparative evaluation. Alternatively, an X-Y cially under transient conditions. However, this is dealt with by slew
comparison using an oscilloscope and the circuit of Figure1, which rate limiting to be discussed later.
multiplies summing node error by 100, will give a visual display of The inverting amplifier configuration forces common mode poten-
amplifier linearity. The circuit of Figure 1 will reveal that PA04 has an tials to zero. By doing so, non-linearities due to common-mode effects
inherently linear characteristic while even the best bipolar designs are also reduced to zero. The main advantage a non-inverting configu-
such as PA07 have quite a bit of curvature in their open loop linearity. ration would have is greater freedom of design regarding input
This is traceable to the better inherent linearity of MOSFET devices in impedance of the power op amp circuit along with the obvious lack of
comparison to bipolar transistors. inversion.
Although the inverting configuration reduces input impedance, the
two amplifier approach insures that the power amp circuit is driven by
1K 10K Vertical
INPUT a source adequate to handle the resultant impedance. The cascade of
two inverting amplifiers yields a non-inverting circuit. A further possible
False summing node
10K useful feature of the inverting power amp circuit is that the summing
node can be monitored and any voltage detected used to indicate fault
Horizontal or non-linear conditions.
100
10
EXTERNAL PHASE COMPENSATION
Many power op amps are internally compensated for unity gain
stability. However, this trades off gain-bandwidth product for stability
under all operating conditions. Since distortion reduction is propor-
tional to the ratio of open loop to closed loop gain, it is desirable to have
FIGURE 1. SIMPLE TEST CIRCUIT
as high as possible open-loop gain at high frequencies. Since it is
unlikely that the power op amp will be configured for unity gain, the
CIRCUIT CONSIDERATIONS external phase compensation allows for a reduced compensation,
The design considerations desirable for wideband, low distortion yielding improved distortion and slew performance.
designs can be summed up with four guidelines: The small signal response curve for PA04 shown in Figure 2 helps
to illustrate the comparative advantage of external phase compensa-
1. Lowest possible closed loop gain. tion. The straight line at 20dB represents a gain of 10 amplifier which
2. Inverting configuration. if the PA04 were compensated for unity gain would provide a 200 kHz
3. External phase compensation. rolloff. Decompensation for a gain of 10 results in a 700 kHz rolloff. In
4. Input slew-rate limiting. addition, note that loop gain for the unity-gain compensation is only 22
Distortion reduction in an op amp circuit is proportional to the dB at 20 kHz, while it is 30 dB for the gain of 10 compensation. This
amount of feedback, and this corresponds to lower gain circuits having increase in loop gain results in 2.5 times less distortion at 20 kHz.
reduced distortion. Distortion reduction is described mathematically The large amount of feedback at low gains obviously reduces
as: distortion. Problems can occur however under transient conditions. If
Af a step function is applied to the input of the amplifier circuit, the output
Df=D ( ) can only change as fast as the amplifier slew rate allows. During this
A slew interval the input summing node will develop a large differential
Where: Df = % DISTORTION WITH FEEDBACK voltage. This nonlinear condition and input overload can cause a host
D = % DISTORTION OPEN LOOP of difficulties including a slow and poorly behaved recovery from this
A = OPEN LOOP GAIN overload.
Af = CLOSED LOOP GAIN
336
140
CC
220pF
120
100 100pF
Loop gain at 20kHz
PA04 22dB for unity gain compensation (a)
RC = 120 30dB for gain of 10 compensation
80 IOUT = 10A
VS = 50V
Gain (dB)
RL = 4
60 SR @ CC = 470pF = 9.81V/S
@ CC = 220pF = 18.75V/S
@ CC = 100pF = 45.1V/S Bandwidth for
gain of
40 470pF 10 compensation
20 LC
Bandwidth for unity gain compensation (for gain of 10 circuit)
(b)
0
0.001 0.01 0.1 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) RO
FIGURE 2. THE SMALL SIGNAL RESPONSE FOR THE PA04
Restriction of the input slew rate can avoid these transient distortion
problems. The input should never be allowed to slew faster than the
amplifier output can follow. If the actual slew rate of the source cannot
be predicted or controlled, then simple low pass filtering at the amplifier
input will prevent transient distortion.
(c)
The filter time constant is a function of amplifier slew rate. The
RC
maximum acceptable rate-of-change on the input signal is limited to a
value less than the amplifier slew rate divided by the amplifier gain.
CC
With a known maximum step function input, the maximum rate-of-
change at the low pass filters output occurs at t=0 and is determined
by:
dv/dt = (V/R)/C
The RC time constant trc required at the amplifier input is:
RC
trc = (VINAV)/SR (d)
Where: VIN = PEAK-TO-PEAK INPUT VOLTAGE CC
AV = CLOSED LOOP GAIN
SR = SPECIFIED AMPLIFIER SLEW RATE
FIGURE 4. STABILITY ENHANCING TECHNIQUES
Note that there is some reduction in bandwidth with this filter.
However, with the PA04 this still permits a 40 kHz bandwidth. This must be taken directly at output of amplifier so that inductor-resistor
limitation again favors the use of the fastest possible power amplifiers. has the effect of isolating the amplifier and feedback network from the
Keep in mind that transient behavior is actually enhanced by the
addition of the input filter.
capacitive load. (c.) Series resistor and capacitor from amplifier output D
to ground, often referred to as a snubber. Used only in situations where
amplifiers are sensitive to inductive loads. Insures a low, resistive load
STABILITY CONSIDERATIONS impedance at high frequencies. (d.) Series R-C network across op amp
When a power amplifier drives a capacitive load, the interaction inputs, often referred to as noise-gain compensation. Simply de-
between output resistance and capacitive load creates an additional scribed, this technique reduces feedback at high frequencies to the
pole and attendant phase shift in amplifier response (Figure 3). point where stability is not a problem.
Inductive loads can result in stability problems due to rising imped- Methods a and b offer the best overall bandwidth performance and
ances at high frequencies. Most follower type output stages are transient behavior. Method a has been mentioned already as having
immune to the effects of inductive loads, but collector output, drain the tradeoff of requiring a unity gain stable amplifier. However, with
output and quasi-complementary output stages with local feedback proper attention to design, it is possible to incorporate method a with
loops are susceptible to parasitic oscillations driving inductive loads. any amplifier to help control overshoot and ringing behavior.
Figure 4 shows several measures are available to improve stability, Method d, the noise gain compensation, will have the effect of
each with some advantage and disadvantage: (a.) Capacitor across reducing the closed loop bandwidth of the resultant circuit to the same
feedback resistor. This provides a compensating phase lead in the effective closed loop bandwidth corresponding to the noise gain. To
feedback path to counteract the effects of additional poles. This illustrate, consider a gain of 10 amplifier with a network across the
technique generally requires a unity-gain stable amplifier. (b.) Parallel inputs configured for a high frequency noise gain of 100. If the gain of
inductor-resistor combination in series with amplifier output. Feedback 10 amplifier had an uncompensated bandwidth of 100 kHz, with the
noise gain compensation, the bandwidth would be reduced to 10 kHz.
In addition, the response curve peaks near the high frequency limit
resulting in overshoots in the square wave response.
All amplifiers vary in their ability to tolerate capacitive loading before
VIN stability problems occur. PA04 is especially good in this regard
2-pole response
RO tolerating well over 1 uF while operating at a gain of 10. In the case of
= PA04, no additional stability enhancement measures are required and
this is the ideal case for best frequency response.
CL
TYPICAL DESIGN EXAMPLE
A design utilizing all of the guidelines described here would be
2nd pole due to RO and CL constructed around a PA04 in an inverting gain of 10 configuration as
shown in Figure 5. For additional gain the PA04 is preceded by a small
FIGURE 3. CAPACITIVE OP AMP LOADS signal op amp also operating at an inverting gain of 10. Many choices
337
are available for this op amp such as the 5534 or OP37. The PA04s a large input capacitance which is nonlinear with variations in input
tolerance of reactive loads negates the need for additional stability signal. Excessive impedances will increase distortion due to these
enhancement components. higher order capacitance effects. The 2K ohm input resistor of
With an 8 ohm load this circuit can supply over 300W at up to 150 Figure 5 is high enough to avoid excessive loading of the small signal
kHz with the input slew rate filter bypassed. With the filter in place, op amp and low enough to avoid distortion effects with the PA04.
gain begins to rolloff at 40kHz, although full output swing is available Several basic practices are important to implement when using
up to 150kHz. Distortion never exceeds 0.02% THD. Power supplies PA04. Power supply bypassing consisting of good high frequency
will need to be capable of at least 7A to support 8 ohm loads in ac capacitors, generally ceramic, must be connected from each supply
coupled applications. Regulated supplies arent necessary but are rail to ground. Unless these capacitors are physically close to the
desirable from a reliability standpoint. amplifier, parasitic oscillations may occur. Even an inch away from
When designing for low distortion with PA04, the impedance of the the socket pins is too far. Be sure to read and observe all ESD
feedback and input networks around the op amp should be kept as precautions on the PA04 data sheet, and those shipped with PA04.
low as possible. The input MOSFETs of the PA04 cause it to have
10K 100K
+80V 20K
INPUT 1K
3.9nF 8
2K 9
1
OP 37 10
SLEW-LIMITING 11 RCL
FILTER
7 0.068
PA04
4 OUTPUT
2
3 CC
RC 100pF
6
120
5 CURRENT-LIMITING
RESISTOR
FIGURE 5. A HIGH PERFORMANCE OP AMP DESIGN 80V
without notice.
338
STABILITY FOR POWER OPERATIONAL AMPLIFIERS
APPLICATION NOTE 19
RF
1.0 LOOP STABILITY Vs NON-LOOP STABILITY RI
There are two major categories for stability considerations Non- 100K 100K
Loop Stability and Loop Stability.
Non-Loop Stability covers design areas not related to feedback IBIAS VOUT
VIN IBIAS
around the op amp that can cause oscillations in power op amp circuits
such as layout, power supply bypassing, and proper grounding. CB+
Loop Stability is concerned with using negative feedback around the .1F RB+
amplifier and ensuring that the voltage fed back to the amplifier is less 49.9K
than an additional 180 phase shifted from the input voltage.
The two key factors to troubleshooting an oscillation problem are:
1) What is the frequency of oscillation? (refer to Figure 1 for definitions FIGURE 2. RB+
of UGBW (Unity Gain Bandwidth) and CLBW (Closed Loop Band- receiving unwanted positive feedback. Calculate your DC errors
width) to be used throughout this text) without the resistor. Some op amps have input bias current cancella-
2) When does the oscillation occur? tion negating the effect of RB+. Some op amps have such low input
bias currents that the error is insignificant when compared with the
220
initial input offset voltage. Leave RB+ out, grounding the + input, if
200 possible. If the resistor is required, bypass it with a .1 uF capacitor in
180 parallel with RB+ as shown in Figure 2.
160
140 2.3 POWER SUPPLY BYPASSING
GAIN (dB)
120 * fosc < UGBW

Aol
100 * oscillates unloaded?no
80 * oscillates with VIN = 0?may or may not
CLBW = 10KHz Supply loops are a common source of oscillation problems. Figure
60
AVCL 3 shows a case where the load current flows through the supply source
40
UNITY GAIN UGBW = 1MHz resistance and parasitic wiring or trace resistance. This causes a
20 modulated supply voltage to be seen at the power supply pin of the op
0 amp. This modulated signal is then coupled back into a gain stage of
.1 1 10 100 1K 10K 100K 1M 10M 100M the op amp via the compensation capacitor. The compensation
FREQUENCY, f (Hz)
FIGURE 1. DEFINITION OF CLBW & UGBW
The answers to these two questions, along with the sections that
follow, should enable you to identify and solve most power op amp
stability problems. More importantly, by applying the recommenda-
D
tions in the following sections, you can design power op amp circuits
free of oscillation.
GAIN POWER
2.0 NON-LOOP STABILITY STAGE STAGE
Cc
2.1 CASE GROUNDING RL
* fosc < UGBW
* oscillates unloaded?may or may not
IL
* oscillates with VIN = 0?may or may not
Ungrounded cases of power op amps can cause oscillations, Vs Rs
especially with faster amplifiers. The cases of all APEX amplifiers are
electrically isolated to allow for mounting flexibility. Because the case
is in close proximity to all the internal nodes of the amplifier, it can act
FIGURE 3. IL MODULATION
as an antenna. Providing a connection from case to ground forms a
Faraday shield around the power op amps internal circuitry that
prevents noise pickup and cross coupling or positive feedback. capacitor is usually referred to one of the supply lines as an AC ground.
Figure 4 shows a second case for supply loop oscillation problems.
Power supply lead inductance interacts with a capacitive load forming
2.2 RB+ BIAS RESISTOR an oscillatory LC, high Q, tank circuit.
* fosc < UGBW
Lw
* oscillates with VIN = 0?may or may not +Vs
Figure 2 is a standard inverting op amp circuit which includes an
input bias current matching resistor on the noninverting input. The OP
purpose of this resistor is to reduce input offset voltage errors due to AMP
CL
bias current drops across the equivalent impedance as seen by the
inverting and non-inverting input nodes. RB+ can form a high imped-
ance node on the noninverting input which will act as an antenna FIGURE 4. LC OSCILLATION
339
Fortunately, both of the above supply line related problems can be
eliminated through the use of proper power supply bypass techniques.
Each supply pin must be bypassed to common with a high frequency
bypass .1uF to .22uF ceramic capacitor. These capacitors must be
located directly at the power op amp supply pins. In rare cases where
power supply line inductance is high, it may be necessary to add 1 to
10 ohms of resistance in series with the high frequency bypass
capacitor to dampen the Q of the resultant LC tank circuit. This
additional resistor will probably only be necessary when using a
wideband amplifier since amplifiers of 5 MHz unity gain bandwidth or CL
less will not respond to the high frequency oscillation caused by line POWER OP AMP
inductance interacting with the high frequency bypass capacitor.
Refer to Figure 5.
C2
+
C1 FIGURE 6. EMITTER FOLLOWER WITH C LOAD

+VS < 2"
Rs
OP
AMP
Rs
VS
< 2" Q1
C1 C2 Q2 L
+ O
A
D
C1 = .1 TO .22 F, CERAMIC DISC R1 R2
C2 = 10 F/AMP OUT (PEAK), ELECTROLYTIC
Rs = 3 10 (PROVISIONAL
HIGHLY INDUCTIVE P.S. LINES)
FIGURE 5. POWER SUPPLY BYPASSING

Vs
In addition, a low frequency bypass capacitor, minimum value of
10uF per Ampere of peak output current, should be added in parallel
with the high frequency bypass capacitors from each supply rail to FIGURE 7. COMPOSITE OUTPUT STAGE
common. Tantalum capacitors should be used when possible due to
their low leakage, low ESR and good thermal characteristics. Alumi- power op amps where high current PNP transistors are not readily
num Electrolytic capacitors are acceptable for operating temperatures available. The local feedback in the Q1, Q2 loop will cause output
above 0C. These capacitors should be located within 2" of the power stage oscillations when the output swings negative under reactive
op amp supply pins. Refer to Figure 5. loading.
RI RF
2.4 MULTIPLE AMPLIFIER BOARDS
* fosc < UGBW
* oscillates unloaded?no
* oscillates with VIN =0?yes VOUT
A prototype circuit is built and bench tested to confirm desired
performance. Several channels of the same circuit are used on a 10 to 100
printed circuit board layout. Much to the dismay of the design engineer, VIN
the amplifier circuits on the printed circuit board oscillate. Cross
.1 to 1F
coupling through the power supply lines can be a major problem on
multiple amplifier printed circuit boards. Ground the case of each
amplifier and ensure each amplifier has its own power supply bypass-
ing per Section 2.3.
FIGURE 8. OUTPUT RC SNUBBER
2.5 OUTPUT STAGE OSCILLATIONS / Both of these output stage problems can be fixed by using an R-C
OUTPUT R-C SNUBBER Snubber on the output of the op amp to ground or the negative supply
rail. This is provided the negative supply rail is properly bypassed per
* fosc > UGBW
Section 2.3. The Snubber network consists of a 10 to 100 ohm resistor
* oscillates unloaded?no in series with a capacitor of .1 to 1 F (refer to Figure 8). This network
* oscillates with VIN = 0? no, only oscillates over a portion of the lowers the high frequency gain of the output stage preventing un-
output cycle wanted high frequency oscillations.
Sometimes output stages of power op amps can contain local
feedback loops that give rise to oscillations. The first type of output 2.6 GROUND LOOPS
stage instability problem arises from a tendency of emitter followers to
appear inductive when looking back into their emitter. This occurs if * fosc < UGBW
they are driven from a low impedance source and can create output * oscillates unloaded?no
stage oscillations if capacitance is present on the amplifiers output. * oscillates with VIN = 0?yes
Refer to Figure 6. This type of instability is rare and usually only shows Ground loops come about from load current flowing through para-
up when driving load capacitances within a limited range of values. sitic layout resistances and wiring. If the phase of the output signal is
The second, more common type of output stage oscillation is due to in phase with the signal at the node it is fed back to, it will result in
non-emitter follower output type stages. These stages have heavy positive feedback and oscillation. Although these parasitic resistances
local feedback paths. Refer to Figure 7 which is an example of a (RR in Figure 9) in the load current return line cannot be eliminated,
composite PNP type output stage. This stage is typical of monolithic they can be made to appear as a common mode signal to the amplifier.
340
RI RF RF
+
AOI VOUT

VIN
RI
RR
Vfb
VOUT

VIN VIN
RL
RR VOUT RI VOUT = VIN Aol Aol VOUT

Vfb =
RI + RF
VOUT + Aol VOUT = Aol
Vfb = VOUT VIN
RR RR RI VOUT Aol
= = = 1
RI + RF VIN 1+ Aol
IL
GROUND
( FOR: Aol >> 1)
PROBLEM FIGURE 10. BETA () FEEDBACK FACTOR
If Aol is large, there is a lot of feedback. If Aol is small, there is not

RI RF
much feedback.
3.2 RATE OF CLOSURE & STABILITY

VIN Refer to Figure 11. Aol is the amplifiers open loop gain curve. 1/
is the closed loop AC small signal gain in which the amplifier is
operating. The difference between the Aol curve and the 1/ curve is
STAR
GROUND RL
POINT 1/1
100
Aol
**
RR 80
SOLUTION GAIN (dB) * 1/2
60
FIGURE 9. GROUND LOOPS
**
This is done by the use of a star ground approach. Refer to Figure 9. 40
The star ground is a point that all grounds are referenced to. It is a 1/3
common point for load ground, amplifier ground, signal ground and
20 *
power supply ground.
1/4
2.7 PRINTED CIRCUIT BOARD LAYOUT 0
1 10 100 1K 10K 100K 1M
D
* fosc < UGBW
FREQUENCY, F (Hz)
* oscillates with VIN = 0?no * 20 dB/ DECADE RATE OF CLOSURE STABILITY
High current output traces routed near input traces can cause ** 40 dB/ DECADE RATE OF CLOSURE MARGINAL STABILITY
oscillations. This is especially true when the output is adjacent to the FIGURE 11. RATE OF CLOSURE & STABILITY
positive input, giving undesirable positive feedback through capacitive
coupling between the adjacent traces. Feedback, input, and bypass the loop gain. Loop gain is the amount of signal available to be used
components, along with current limit sense resistors, should be as feedback to reduce errors and non-linearities.
located in close proximity to the amplifier. A first order check for stability is to ensure when loop gain goes to
If a printed circuit board has both a high current output trace and a zero, open loop phase shift must be less than 180 degrees where the
return trace for that high current, then these traces should be routed 1/ curve intersects the Aol curve. Another way of viewing that same
adjacent to each other (on top of each other on a multi-layer printed criteria is to say at the intersection of the 1/ curve and the Aol curve
circuit board) so they form a twisted pair type of layout. This will help the difference in the slopes of the two curves, or the RATE OF
cancel EMI generated outside from feeding back into the amplifier CLOSURE, is less than or equal to 20 dB per decade. This is a powerful
circuit. first check for stability. It is, however, not a complete check. For a
complete check we will need to check the open loop phase shift of the
3.0 LOOP STABILITY amplifier throughout its loop gain bandwidth.
A 40 dB per decade RATE OF CLOSURE indicates marginal
3.1 BETA - FEEDBACK FACTOR stability with a high probability of destructive oscillations in your circuit.
Control theory is applicable to closing the loop around a power op Figure 11 contains several examples of both stable (20 dB per decade)
amp. The block diagram in Figure 10 consists of a circle with an X, and marginally stable (40 dB per decade) rates of closure.
which represents a voltage differencing circuit. The rectangle with Aol
represents the amplifier open loop gain. The rectangle with the 3.3 EXTERNAL PHASE COMPENSATION
represents the feedback network. The value of is defined as the
fraction of the output voltage that is fed back to the input; therefore, External phase compensation is often available on an op amp as a
can range from 0 (no feedback) to 1 (100% feedback). method of tailoring the op amps performance for a given application.
The term Aol that appears in the VOUT/VIN equation in Figure 10, has The lower the value of compensation capacitor used the higher the
been called loop gain because this can be thought of as a signal slew rate of the op amp. This is due to fixed current sources inside the
propagating around the loop that consists of the Aol and networks. front end stages of the op amp. Since current is fixed, we see from the
relationship of I = CdV/dt that a lower value of capacitance will yield a
faster voltage slew rate.
341
RF CF
1 STABLE FOR ANY Cc
RI
2 STABLE FOR ANY Cc = 0pF RF
Aol RI
1/ Vfb
VIN VOUT
AVCL
Cc
SMALL SIGNAL RESPONSE VNOISE 1

fp =
120 2 RF CF
RI + RF
fz =
2 RI RF CF
fp1
100
100
OPEN LOOP GAIN Aol (dB)
Cc = 33pF Cc = 0pF
Aol
80
80
fp2
60
GAIN (dB)
60
1
Aol
40
40
2
20 40 dB
DECADE
20
fcl
0 1 fp
1 10 100 1K 10K .1M 1M 10M
0
FREQUENCY, F (Hz) 1 10 100 1K 10K 100K 1M
fz
FIGURE 12. EXTERNAL PHASE COMPENSATION FREQUENCY, F (Hz)
FIGURE 13. STABILITY RATE OF CLOSURE
However, the advantage of a faster slew rate has to be weighed 3.5 STABILITY - OPEN LOOP
against AC small signal stability. In Figure 12 we see the Aol curve for
an op amp with external phase compensation. If we use no compen- Stability checks are easily performed by breaking the feedback path
sation capacitor, the Aol curve changes from a single pole response around the amplifier and plotting the open loop magnitude and phase
with Cc = 33pF, to a two pole response with Cc = 0pF. Curve 1 response. Refer to Figure 14. This open loop stability check has the
illustrates that for 1/ of 40 dB the op amp is stable for any value of first order criteria that the slope of the magnitude plot as it crosses 0
external compensation capacitor (20 dB/decade rate of closure for dB must be 20 dB per decade for guaranteed stability.
either Aol curve, Cc = 33pF or Cc = 0pF). Notice that 1/ curve The 20 dB per decade is to ensure the open loop phase does not dip
continues on past the intersection of the Aol curve. At the intersection to 180 degrees before the amplifier circuit runs out of loop gain. If the
of 1/ and Aol, the AVCL closed loop gain curve, or VOUT/VIN gain begins phase did reach -180, the output voltage would now be fed back in
to roll off and follow the Aol curve. This is because there is no loop gain phase with the input voltage (-180 degrees phase shift from negative
left to keep the closed loop gain flat at higher frequencies. feedback plus -180 degrees phase shift from feedback network
Curve 2 illustrates that for 1/ of 20 dB and Cc = 0pF, there is a 40 components would yield -360 degrees phase shift). This condition
dB/decade rate of closure or marginal stability. To have stability with would continue to feed upon itself causing the amplifier circuit to break
Cc = 0pF minimum gain must be set at 40dB. This requires a designer into uncontrollable oscillations.
to not only look at slew rate advantages of decompensating the op Notice in Figure 14 this open loop plot is really a plot of Aol . The
amp, but also at the gain necessary for stability and the resultant small slope of the open loop curve at fcl is 40 dB per decade indicating a
signal bandwidth. marginally stable circuit. As shown, the zero from the 1/ plot in Figure
13 became a pole in the open loop plot in Figure 14 and likewise the
pole from the 1/ plot in Figure 13 became a zero in the open loop plot
3.4 STABILITY - RATE OF CLOSURE of Figure 14. We will use this knowledge to plot the open loop phase
Figure 13 shows a typical single pole op amp configuration in the plot to check for stability. This plot of the open loop phase will provide
inverting gain configuration. Notice the additional VNOISE voltage source a complete stability check for the amplifier circuit. All the information
shown at the +input of the op amp. This is shown to aid in conceptually we need will be available from the 1/ curve and the Aol curve.
viewing the 1/ plot.
An inverting amplifier with its +input grounded, will always have 4.0 STABILITY & THE INPUT POLE /
potential for a noise source to be present on the +input . Therefore,
when one computes the 1/ plot, the amplifier will appear to run in a
INPUT & FEEDBACK IMPEDANCE
gain of 1 + RF/RI for small signal AC. The VOUT/VIN relationship will still * fosc < CLBW
be RF/RI. This is also why an amplifier can never run at a gain of less * oscillates unloaded?yes
than one for small signal AC stability considerations.
* oscillates with VIN = 0?yes
The plot in Figure 13 shows the open loop poles from the amplifiers
Aol curve, as well as the poles and zeroes from the 1/ curve. The All op amps have some input capacitance, typically 6-10 pF. Printed
locations of fp and fz are important to note as we will see that poles in circuit layout and component leads can introduce additional input stray
the 1/ plot will become zeroes and zeroes in the 1/ plot will become capacitances. When high values of feedback and input resistors are
poles in the open loop stability check. used, this input capacitance will contribute an additional pole to the
Notice that at fcl the RATE OF CLOSURE is 40 dB per decade loop gain response (a zero in the 1/ plot, a pole in the open loop phase
indicating a marginal stability condition. The difference between the check for stability, or a pole in the Aol , loop gain, plot).
Aol curve and 1/ curve is labelled Aol which is also known as loop
gain.
342
CF We will refer to Figure 15 for a detailed look at the input pole and
stability. Remember, our first order criteria for stability is a Rate Of
Closure of 20dB per decade or less. Curve 1 is the op amps Aol plot.
RF Curve 5 shows the effect of input capacitance with no CF feedback
capacitor. We see the rate of closure is 40 dB per decade and marginal
RI VOUT
stability exists. With just CI present, as frequency increases, the
impedance from the -input of the op amp decreases, thereby causing
VIN the 1/ plot to increase (remember XCI = 1/2fCI). If we now add some
small value of CF as in Curve 2 we see the 1/ plot flatten out to
intersect the Aol at a rate of closure 20 dB per decade implying stability.
If we further increase CF, as in Curve 3, such that both breakpoints are
1
fz = the same frequency, we will have ZF/ZI constant over frequency and
2 RF CF the 1/ plot will be flat with frequency. This yields the ever-stable 20 dB
fp = RI + RF per decade rate of closure. If we then continue to increase CF as in
2 RI RF CF Curve 4, we will see CFdominate as frequency increases and the net
result is a low pass filter frequency roll-off. For this case the op amp
100 must be unity gain stable, since the op amp operates at a gain of one
fp1 for frequencies above 10KHz.
Often you will see CF recommended to be used to decrease
80 overshoot and improve settling time for a transient input into a given
fp
(fp2 + fz) op amp circuit. In the AC small signal domain, we are merely optimizing
the circuit for stability.
GAIN (dB)
60 Minimize values of feedback and input resistor values. This will

Aol reduce the effect of the input pole as well as help reduce DC errors by
keeping voltage drops due to bias currents low. A summing node of an
40
op amp can pick up unwanted AC signals and amplify them if that node
40 dB is high impedance. Keeping the feedback and input resistance values
DECADE low will reduce the impedance at the summing nodes and minimize
20
fcl stray signal pick up. Practical values for feedback and input resistance
values are from 100 ohms to 1 megaohm.
0
1 10 100 1K 10K 100K 1M
5.0 LOOP STABILITY EXAMPLES
FREQUENCY, F (Hz)
5.1 VOLTAGE TO CURRENT CONVERSION
FIGURE 14. STABILITY OPEN LOOP FLOATING LOAD
* fosc < CLBW
CF * oscillates unloaded ? yes
* oscillates with VIN = 0 ? yes
1 Aol Figure 16 illustrates a common voltage to current conversion circuit.
RF
The input command voltage of +/-10V is scaled to control -/+1.67A of
2 CI / CF > RF / RI
output current through the load.
3 CI / CF = RF / RI
+28V
RI CI 4 CF >> CI
RCL +
5 RF / X CI D
.301
CI / CF = X CF / X CI PA07
RI
RCL RL IOUT
120 4.99K 9 1.67A
VIN .301 Rd
10V 28V FB#2 Cf
100 LL
159mH
RF FB#1
80 1
1K Rs VRs
1.2
GAIN (dB)
60
Rd Cf
2 FIRST GUESS 825K 820pF
40
5 FINAL VALUES 82.5K .068F
20 FIGURE 16. V-I CIRCUIT AND STABILITY

This V-I (Voltage to Current) topology is a floating load drive. Neither
3
end of the load, series RL and LL, is connected to ground.
0 The easiest way to view the voltage feedback for load current control
4 in this circuit is to look at the point of feedback which is the top of Rs.
20 The voltage gain VRs/Vin is simply -RF/RI which translates to (1K/
1 10 100 1K 10K 100K 1M 10M 4.99K = -.2004). The Iout/Vin relationship is then VRs/Rs or Iout = - Vin
(RF/RI)/Rs which for this circuit is (Iout = -.167 Vin). We will use our
FREQUENCY, F (Hz) knowledge of 1/, Rate of Closure, and open loop stability phase plots,
to design this V-I circuit for stable operation. There are two voltage
FIGURE 15. THE INPUT POLE feedback paths around the amplifier, FB#1 and FB#2. We will analyze
FB#1 first and then see why FB#2 is necessary for guaranteed
stability.
343
STABILITY SOLUTION FOR V-I CIRCUIT 220
STEP 1: On Figure 17 plot the op amps Aol curve as given by the 200
manufacturer. 180
160
220
GAIN (dB)
140
200 PA07 Aol
120
180 fp1 FB#1
100
160 fp
80
FB#2
GAIN (dB)
140
60 fz1
120
PA07 Aol fp1 FB#1 40
100
20
80 1/ fp2
0
60 .1 1 10 100 1K 10K 100K 1M 10M 100M
40 250
fz
20 FREQUENCY, F (Hz) 3p fp3
fp2
0
.1 1 10 100 1K 10K 100K 1M 10M 100M FIGURE 19. FIRST GUESS MAGNITUDE PLOT FOR STABILITY
FREQUENCY, F (Hz) and PA07 Aol curve to plot the open loop phase plot.
fp3 3p Remember the following rules when plotting open loop
phase plots for stability checks.
FIGURE 17. Aol AND FB # 1 MAGNITUDE PLOT FOR STABILITY RULES FOR PLOTTING OPEN LOOP PHASE PLOTS
STEP 2: On Figure 17 plot FB#1. Refer to Figure 18 for calculation of 1)

Poles in 1/ plot become zeroes in the open loop
FB#1. At DC, LL is a short and so is a voltage divider stability check.
through resistors as shown in Figure 18. As we go to higher 2) Zeroes in 1/ plot become poles in the open loop
frequencies, the reactance of LL will increase (XL = 2fL). stability check.
This will increase the net load impedance which will cause 3) Poles and zeroes in the Aol curve of the op amp remain
to decrease and 1/ to increase as frequency increases. respectively poles and zeroes in the open loop stability
Since we are working with a single reactive element the check since the op amp Aol curve is an open loop curve
increase of that gain will be 20 dB per decade. Figure 18 already.
details the breakpoint fz where this increase begins. We see 4) Phase for poles is represented by a -45 degree phase
that at the intersection of FB#1 and the PA07 Aol curves the shift at the frequency of the pole with a -45 degree per
rate of closure is 40 dB per decade indicating marginal decade slope, extending this line with 0 degree and -90
stability. degree horizontal lines.
5) Phase for zeroes is represented by a +45 degree phase
VOUT (1)
FB #1 DC ( LL = 0, Cf = ) shift at the frequency of the zero with a +45 degree per
decade slope, extending this line with 0 degree and +90
Vfb degree horizontal lines.
RL =
Vfb VOUT Figure 20 is the resultant open loop phase plot using
RF 9
(.098) the information from Figure 19. After plotting individual
1K = .098 1/ = 10.2 20dB open loop poles and zeroes, and drawing the appropri-
RI Rs ate slopes, we graphically add the slopes to yield a
4.99K 1.2 Rs + RL 1.2 + 9 resultant open loop phase as shown in Figure 20.
fz = = = 10.2Hz
2 LL 2 159mH Notice fp3 in Figure 20 is a triple pole. It is easier to plot
this as shown in Figure 20 as three poles on top of
each other. This makes it easier to add graphically for
FIGURE 18. FEEDBACK NO.1 (FB #1) a resultant open loop phase plot. As shown in Figure
STEP 3: Refer to Figure 19 which repeats PA07 Aol and FB#1. We 20, our open loop phase dips to -180 at 100Hz. Our first
will add FB #2 to force the high frequency part of the 1/ attempt at compensation was not successful since we
curve to flatten out and intersect the PA07 Aol curve at 20 desire at least 45 degrees of phase margin (open loop
dB per decade. FB #2 will dominate at frequencies above 1 phase should not dip to less than -135 degrees).
KHz. Although our V-I circuit has two feedback paths, the op STEP 5: We need to revisit FB#2 to make this V-I circuit stable.
amp will follow whichever feedback path is dominant. This Figure 21 shows a new FB#2 and the resultant 1/ plot.
means the larger is, the more voltage is fed back from the Before we look at the open loop phase plot, lets discuss
output to the -input as negative feedback (Remember = Figure 21. We see that in the PA07 Aol curve there is a pole
Vfb/VOUT). With a larger , 1/ will become smaller; there- at fp1, 10Hz, which will be a pole in our open loop phase plot.
fore, the dominant feedback path out of FB#1 and FB#2 will We also see a zero at fz, 10Hz, in the 1/ plot, which will
be the lowest gain path. become a pole in our open loop phase plot. Now we have
Plot a desired feedback path for FB#2. At high frequen- two poles at 10Hz in our open loop phase plot. To keep the
cies, FB#2 will be a flat line since Cf will be a short leaving open loop phase from reaching -180, we must add a zero at
a pure resistive divider for . At DC, FB#2 will be infinite 100Hz to get 45 degrees of phase margin. Poles and zeroes
since Cf is an open. This will be limited by the PA07 Aol a decade beyond fcl, the intersection of 1/ and PA07 Aol,
curve. Since we only have one reactive element in FB#2, we are of no concern for stability since at fcl the loop gain is
will have a 20 dB per decade slope from low to high zero. The reason we must look a decade beyond fcl on the
frequency. Set fz1 one half to one decade below the magnitude plot is that poles and zeroes have an effect on
intersection of FB#1 and FB#2. This Decade rule of thumb phase plus or minus a decade away from their physical
ensures that as component values and Aol curves vary we location on the magnitude plot.
will not get into stability troublemore about this later. Viewing the magnitude plot in this way can help us save
STEP 4: In Figure 19 the long-dashed line represents the 1/ feed- iterative steps in compensating to guarantee good stability.
back path that the PA07 operates in for small signal AC. Refer to Figure 22 (see second page following this one) for
According to our first order check for stability we see a 20 dB final open loop phase plot stability. Once the open loop
per decade rate of closure indicating a stable design. But phase plot verifies stability, it is time to compute final values
lets do our complete stability check by using the 1/ curve for FB#2 components Rd and Cf. Figure 23 details these
344
+180
+135 fp
+90
+45
fp1 fp3
0
45
fz fp2
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
PHASE SHIFT (degrees)
+90
+45
0
45
90
135
MARGIN = 0 DEGREES
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY, F (Hz)
FIGURE 20. FIRST GUESS OPEN LOOP PHASE PLOT FOR STABILITY
calculations. Notice in Figure 23 that to work with it is 220

easiest to set Vout to 1 which then allows us to easily use
voltage dividers and currents to calculate values for Rd. Cf
200
180
D
is computed as given by the formula in Figure 23.
160
OPEN LOOP PHASE PLOTS FOR STABILITY FINAL NOTE:
GAIN (dB)
This hand plotting technique is a linear graphical method. Actual 140

PA07 Aol
magnitude plots run on such analog circuit simulations as SPICE will 120
be 3 dB different and actual phase plots will be 6 degrees different. fp1 FB#1
100
80
5.2 CAPACITIVE LOADING & STABILITY 60 fp
fz1 FB#2
* fosc < CLBW 40
fz
* oscillates unloaded?no 20
* oscillates with VIN = 0?yes 1/
0
.1 1 10 100 1K 10K 100K 1M 10M 100M
31.6 250 fcl fp2
5.2.1 CAPACITIVE LOADING - GENERAL
FREQUENCY, F (Hz) 3p fp3
Refer to Figure 24 (see second page follwong this one) for discus-
sion of power op amps and capacitive loading. The output impedance FIGURE 21. FINAL VALUE MAGNITUDE PLOT FOR STABILITY
of a power op amp, Ro, can interact with capacitive loads and form an
additional high frequency pole in the op amps Aol curve. This modified
Aol curve is what we must look at for stability checks. In Figure 24, we
see a modified Aol curve whose slope changes from 20 dB per decade where K is a propagation constant that is sometimes called the velocity
to 40 dB per decade at 10 kHz. Note that the rate of closure for this factor (0.66 for coaxial cable) and c is the velocity of light (3.00 X108
circuit is 40 dB per decade indicating marginal stability. m/s).
EXAMPLE: If f = 10KHz:
5.2.2 CABLE AND CAPACITIVE LOADING
1 (0.66) (3x108)
Beware of coaxial cables which can appear capacitive. A coaxial l = 495 meters (1624 feet)
cable appears capacitive, instead of its characteristic impedance, 40 104
resistive, if the length of the cable is less than one-fortieth of the Cables less than 495 meters will appear capacitive for 10 kHz signals
wavelength in the cable at the frequency of interest, f. This length, l, is at the rate of 95 pF/meter (29 pF/foot) for RG-58A/U, a commonly used
given by: coaxial cable.
1 Kc meters
l
40 f
345
+180
+135
+90
+45
0 fz fp2 fp3
45
fp1
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
fp
+45
0
ADD ZERO FOR 45 MARGIN
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
MARGIN = 45
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY, F (Hz) fcl
FIGURE 22. FINAL VALUE OPEN LOOP PHASE PLOT FOR STABILITY
VOUT (1) FB #2 HI f ( CF = 0, LL= ) 5.2.3 AMPLIFIER OUTPUT IMPEDANCE, Ro

AND CAPACITIVE LOADING
1/ = 40dB = 100 = .01
Vfb Rd Ifb In the design of power amp circuits, the need often arises for a power
RI // RF 833
(.01) amp model with specified output impedance. Most often, this require-
Ifb = Vfb / (RI // RF) = .01/833 = .12mA ment revolves around the need to accurately predict the phase
RI RF performance of power amp circuits.
RT = VOUT / Ifb = 1/.012mA = 83.3K
4.99K 1K Output impedance of any op amp is modified by the feedback
Rd RT (RI // RF) = 83.3K 833 82.5K network present around the device. In voltage source type circuits, the
Rs USE 82.5K effect of the network is to reduce the output impedance by a factor
1.2 equal to the ratio of open loop gain to closed loop gain. In power amps,
1
fz1 = = 31.6Hz the net result is an effective output impedance of milliohm levels at
2 Rd Cf
frequencies below 1kHz. Wiring and interconnections often create
Cf = .068F larger impedances than the output impedance of the closed loop
power amp. Therefore, output impedance will play a minor role in the
phase performance at low frequencies. At high frequencies, reactive
Aol NOTE: AVOID DOUBLE POLE IN load considerations are already addressed by capacitive load speci-
1/ PLOT AT FR COMPLEX POLES IN fications given on many power amplifiers.
FB #2 FB #1 OPEN LOOP STABILITY 180
GAIN (dB)
Within the bandwidth of the amplifier the output impedance of most

PHASE SHIFT AT FR. APEX power op amps appears predominantly resistive. As an output
stage drives higher currents, its output impedance changes when
1/ compared to the low current or unloaded output impedance. In
general, this impedance reduces as current is driven through the
output stage.
When compensating circuits with capacitive loading we will use the
FR low current or unloaded output impedance for Ro. This will be the
FREQUENCY, F(Hz) highest value of Ro causing the lowest frequency additional pole which
modifies an amplifiers Aol curve when driving a capacitive load. Many
FIGURE 23. FEEDBACK NO. 2 (FB #2) FINAL VALUE CALCULATIONS designs in the past have verified that compensating for this condition
will give the best stability for all conditions when driving capacitive
loads.
346
The following is a list of output impedances for APEX power op RF
amps and boosters.
OP AMP OR BOOSTER OUTPUT IMPEDANCE
RI
PA01 ................................... 2.5-8.0 ohms Ro
PA02 ................................... 10-15 ohms
PA03 ................................... 25 ohms CL
PA04 ................................... 2.0 ohms
PA05 ................................... 5 ohms
PA07 ................................... 1.5-3.0 ohms UNITY GAIN STABLE AMPLIFIER
PA08 ................................... 1.5K-1.9K ohms BUT: UNSTABLE 40 dB/DECADE WITH CL
PA09 ................................... 15-19 ohms
PA10 ................................... 2.5-8.0 ohms
PA12 ................................... 2.5-8.0 ohms SMALL SIGNAL RESPONSE
120
PA19 ................................... 30-40 ohms
PA21, 25, 26 ....................... 10 ohms
PA41, PA42, PA43 ............. 150 ohms 100
OPEN LOOP GAIN AOL (dB)

PA45 ................................... 150 ohms
PA51 ................................... 1.5-1.8 ohms 80
PA61 ................................... 1.5-1.8 ohms
PA73 ................................... 1.5-1.8 ohms 60
PA81J ................................. 1.4K-1.8K ohms
PA82J ................................. 1.4K-1.8K ohms 40
PA83 ................................... 1.4K-1.8K ohms UNSTABLE STABLE
PA84 ................................... 1.4K-1.8K ohms 20

PA87 ................................... 50 ohms
PA85 ................................... 50 ohms 0
PA88 ................................... 100 ohms
PA89 ................................... 100 ohms 100
PB50 ................................... 35 ohms 1 10 100 1K 10K .1M 1M 10M
FREQUENCY, F (Hz)
PB58 ................................... 35 ohms
Aol 1/
Aol WITH CL AVCL
5.2.4 COMPENSATING CAPACITIVE LOADS FIGURE 24. CAPACITIVE LOADING
There are two main ways to compensate for capacitive loads or two
pole Aol curves. The Feedback Zero and Noise Gain or Input R- D
C Network compensation techniques for capacitive loads will both be
discussed.
The Feedback Zero technique uses a pole in the 1/ plot (a zero STEP 1: Modify the PA88 Aol due to CL. Here we use the output
in the open loop phase check for stability or a zero in the Aol , loop impedance number for the PA88 of Ro = 100 ohms.
gain, plot) to compensate for the additional pole due to capacitive
loading in the amplifiers modified Aol curve. Refer to Figure 25. Note 1 1
fp2 = = = 10 kHz
that in Curve 1 there is both a pole and zero in this 1/ plot. The pole 2 Ro CL 2 100 159nF
is due to the interaction of Rf and Cf. The zero can be found by
graphically extending the 1/ plot to zero dB. Remember from The higher frequency poles of the unmodified PA88 Aol
previous discussion that an op amp cannot operate at a gain of less must be added into the modified Aol as shown in Figure 26.
than 1 for small signal AC. STEP 2: Calculate DC for circuit.
The Noise Gain compensation technique raises the small signal
DC = RI/(RF + RI) = 10K/(316K+10K) = .030674846
AC gain of the amplifier to run at a gain that is high enough to ignore
DC 1/ = 20 Log (1/.030674846) = 30.26 dB
the additional high frequency pole in the Aol curve due to capacitive
loading. Refer to Figure 25. Curve 2 shows the 1/ plot for noise gain STEP 3: Plot DC 1/. Add pole in 1/ plot to compensate for fp2.
compensation. Ensure fp5 is one-half to one decade away from fcl such that
Notice in Figure 25 that both Curve 1 and Curve 2 yield a 20 dB per if the modified Aol plot in the real world moves to the left
decade rate of closure implying stability; whereas, with just resistive towards lower frequency we will not be back at a 40 dB per
feedback at the given gains the circuits would be unstable with a 40 decade rate of closure. Note in Figure 27 that the 1/ plot has
dB per decade rate of closure. fp5 and fz1. The feedback network continues to feed back
output voltage beyond fcl until we reach 0 dB. Then the 1/
5.2.4.1 FEEDBACK ZERO COMPENSATION plot flattens out at 0 dB. It is important to include fz1 since
it will be a pole in our open loop phase check and will affect
Figure 26 illustrates a circuit utilizing Feedback Zero Compensa- phase at frequencies lower than fcl. At fcl loop gain is zero
tion for stability when driving a capacitive load. Figure 27 is our
magnitude plot to work with for stability. The following procedure will
ensure a logical approach to optimize stability:
347
CF RF
316K CF
RF 47pF
RI
+225V
RCL
RI
6.5
CL 10K
PA88
VIN CL
1/ 1
159nF
FEEDBACK ZERO COMPENSATION Cc
225V 3.3pF
RI RF
FIGURE 26. FEEDBACK ZERO COMPENSATION FOR CL
Rn 220
Cn 200
CL 180
160
1/ 2
GAIN (dB)
140
120 PA88 w/Cc = 3.3pF
NOISE GAIN COMPENSATION
100 fp1
SMALL SIGNAL RESPONSE 80
120 fp2
60
1/ fcl
40 fp5
Aol fz1
100 20
VO / VIN dp
0
.1 1 10 100 1K 10K 100K 1M 10M 100M

80 FREQUENCY, F (Hz) fp4
MODIFIED Aol : RO = 100 , CL = 159nF
fdp3
60
MAGNITUDE PLOT FOR STABILITY
40 amplifier. One is VIN and the other is a noise source summed in via
ground through the series combination of Rn and Cn. Since this is a
1 2
summing amplifier, VO/VIN will be unaffected if we sum zero into the Rn-
20
Cn network. However, in the small signal AC domain, we will be
changing the 1/ plot of the feedback as when Cn becomes a short and
0 if Rn << RI the gain will be set by RF/Rn. Figure 29 shows the
equivalent circuits for AC small signal analysis at low and high
w/CL w/o CL
frequencies.
100 Notice in Figure 29 that the VO/VIN relationship is flat until the Noise
1 10 100 1K 10K .1M 1M 10M Gain forces the loop gain to zero. At that point, fcl, the VO/VIN curve
FREQUENCY, F (Hz) follows the Aol curve since loop gain is gone to zero. Since noise gain
introduces a pole and a zero in the 1/ plot, here are a few tips to keep
FIGURE 25. CAPACITIVE LOAD COMPENSATION phase under control for guaranteed stability. Keep the high frequency
flat part of the noise gain no higher in magnitude than 20 dB greater
and beyond fcl we are not concerned with phase shift to than the low frequency gain. This will force fp and fz in Figure 29 to be
guarantee stability. Note that the VO/VIN plot follows the 1/ no more than a decade apart. This will also keep the phase from
plot until at which point there is no loop gain and VO/VIN will dipping to -135 since there is usually an additional low frequency pole
follow the Aol curve on down in gain. due to the amplifiers Aol already contributing an additional -90
STEP 4: Plot open loop phase as in Figure 28. We see we have 67 degrees in the open loop phase plot. Keep fp one half to one decade
degrees of phase margin and therefore guaranteed stabil- below fcl to prevent a rate of closure of 40 dB per decade and prevent
ity. instability if the Aol curve shifts to the left which can happen in the real
STEP 5: Once you have chosen CF to get the fp5 you want you world.
automatically set fz1. fz1 can be gotten graphically from the Usually one selects the high frequency gain and sets fp. fz can be
1/ plot. For those of you who want exact breakpoints, here gotten graphically from the 1/ plot. Once again for completeness,
are the formulae for the 1/ plot in Figure 27. here are the formulae for noise gain poles and zeroes:
1
fp5 = 1 RF + RI
2 RF CF fp = fz =
2 Rn Cn (2) (Cn) (RFRI + RFRn + RIRn)
RI + RF
fz1 =
2 CF RI RF Figure 30 (see second page following this one) illustrates a circuit
utilizing noise gain compensation for stability when driving a capacitive
load. Figure 31 is our magnitude plot to work with for stability.
5.2.4.2 NOISE GAIN COMPENSATION The following procedure will ensure a logical approach to optimize
Figure 29 illustrates how Noise Gain compensation works. One way stability:
to view noise gain circuits is to treat the amplifier as a summing STEP 1: Modify the PA88 Aol due to CL. Here we use the output
amplifier. There are two input signals into this inverting summing impedance number for the PA88 of Ro = 100 ohms
348
+180
+135
+90
fp5
+45
fdp3
0
fp1 fp4
45
fp2 fz1
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
MARGIN = 67 fcl
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY, F (Hz)

OPEN LOOP PHASE PLOT FOR STABILITY
D
RF
SMALL SIGNAL RESPONSE
RI
120
Rn VOUT
Aol
VIN Cn
100
OPEN LOOP GAIN Aol (dB)
80
NOISE GAIN COMPENSATION

60
RF RF
RI 40
fp
VOUT fcl RF/Rn
VOUT Rn
Rn 20 RF/RI fz
Cn
Cn
0
1/ LOW f 1/ HIGH f (Rn < .1RI) 100

1 10 100 1K 10K .1M 1M 10M
FREQUENCY, F (Hz)
1/
VO/VIN
FIGURE 29. NOISE-GAIN COMPENSATION
349
RF The following steps will provide a simple, logical approach to
attacking composite amplifier stability problems:
274K
STEP 1: Given specifications:
+225V
VIN = 2.5 VOLTS
RCL DC fin 1.6 KHz
RI CL = .1F
6.5 VOUT = /+ 40 VOLTS
1K VO 15 Volts available in system
Rn PA88
VIN 274 Input offset voltage 100 V
CL
Cn 159nF STEP 2: From given specifications determine maximum slew rate
.56F Cc needed to track highest frequency output.
225V 3.3pF
S.R. [V/s] = 2()f Vopk (1x106)
S.R. = 2() (1.6K) 40V (1x106) = .4V/s
FIGURE 30. NOISE GAIN COMPENSATION FOR CL
STEP 3: From calculated slew rate and given CL, determine current
220 needed to drive capacitive load.
200 I = C dV/dt
180 I = .1 F (.4V/s) = 40mA
160 STEP 4: Select power op amp and host amplifier.
PA41 is the lowest cost power op amp with 60mA of
GAIN (dB)
140
PA88 Aol w/Cc = 3.3pF output capability; a slew Rate of 10V/us with Cc =18 pF, and
120
Vsat of 12 volts at 40mA out.
100 fp1 OP07 will provide 75V of input offset voltage; a slew rate
fcl
80 of .17 V/s; and an output voltage swing of +/-12V from +/
1/ fp2
60 fz fp -15V supplies. The maximum output voltage swing of the
host times the booster gain must meet the desired output
40 voltage swing. Here there is no problem since +/-12V out of
VO / VIN
20 OP07 times 11 (booster gain) will yield potential for +/-120V
dp
0 out of the composite amplifier configuration.
.1 1 10 100 1K 10K 100K 1M 10M 100M The slew rate of the host amplifier times the booster gain
FREQUENCY, F (Hz) fp4 should be less than or equal to the booster slew rate. If it is
greater than the booster slew rate, the host amplifier can
FIGURE 31. NOISE GAIN COMPENSATION fdp3 outrun the booster during high slew rate demands and
MAGNITUDE PLOT FOR STABILITY consequently the composite amplifier will be running open
loop and hence non-linearities and distortion will be uncon-
trolled.
1 1
fp2 = = = 10KHz
2 Ro CL 2 100 159nF Host S.R. x Booster Gain = .17/s x 11 = 1.87V/s
1.87V/s < 10V/s (Booster S.R.)
The higher frequency poles of the unmodified PA88 Aol
must be added into the modified Aol as shown in Figure 31. We will run the booster amplifier in a closed loop gain of
STEP 2: Calculate DC for circuit, Cn is an open for DC. 11 as shown in Figure 33 to allow more margin to work with
DC = RI/(RF+RI) = 1K/(274K+1K) = .003636363 when compensating the capacitive load. We know this from
DC 1/ = 20 Log (1/.03636363) = 48.79 dB experience in designing many power op amp circuits with
capacitive loads on the output.
STEP 3: Plot DC 1/. Add noise gain compensation using the hints STEP 5: Draw PA41 Aol curve for Cc = 18pF. The higher frequency
given above. Things look okay. We have 20 dB per decade poles can be reverse engineered from the PA41 open loop
rate of closure. fp is a decade away from fcl. High frequency phase plot. Note in Figure 34 the pole at 10MHz is labeled
1/ is less than 20 dB greater than low frequency 1/, and fdp4. This dp nomenclature will denote at this frequency
fz is less than a decade spaced from fp. there are two poles (double pole).
STEP 4: Plot open loop phase plot as in Figure 32 (see following
page) from the information given in Figure 31. We see
200
from this plot we have 45 degrees of phase margin.
180
5.3 COMPOSITE AMPLIFIER & STABILITY 160 PA41 Aol w/

140 Cc = 18pF
* fosc < CLBW Rc = 2.2K
120
GAIN (dB)
100 fp1
* oscillates with VIN = 0?yes
There are design cases where the input characteristics of a power 80
op amp may not be sufficient to meet required specifications. In 60 fp2
these cases one can still have the advantages of using the power op 40
amp for linear analog control, but can optimize the front end of the 1/ fp5 fz1
20
circuit to meet the required specifications. A composite amplifier PA41 AVCL
such as Figure 33 (see following page) will provide a highly accurate 0
75uV input offset voltage versus the 60 mV input offset voltage of the 20 fp3
fdp4
PA41. In the composite amplifier, the PA41 acts as a booster 40
running in a closed loop gain of 11. The PA41 booster and the .1 1 10 100 1K 10K 100K 1M 10M 100M
OP07 form a new composite amplifier with the feedback from output 7K 9.3K fcl
all the way back to the input of the OP07. FREQUENCY, F (Hz)
The application in Figure 33 provides an excellent opportunity for
us to utilize our knowledge of stabilizing circuits with capacitive (MODIFIED Aol WITH CL, RCL & Zo)
loads, as well as acquire new techniques for dealing with stability
and composite amplifiers. FIGURE 34. POWER OP AMP MAGNITUDE PLOT FOR STABILITY
350
+180
+135
+90
fp
+45
0
fp1 fz fp4
45
fp2 fdp3
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
fcl
135
MARGIN = 45
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY, F (Hz)
FIGURE 32. NOISE GAIN COMPENSATION

OPEN LOOP PHASE PLOT FOR STABILITY
D
RFC
340K 340K
RF CF
CFC
47pF +40V VOUT
+60V 47pF
+15V +15V RI
.1F
34k RCL 40V 1.6KHz
.1F
RIC
PA41
VIN 21k CL
OP07 .1F
2.5V 75
.1F Rc Rsn
.1F
2.2K 1OO
Rn
Csn
3.4K
330pF
Cc
Cn 15V 15V 60V 18pF
60V
4700pF
ALL DIODES 1N41481
FIGURE 33. PA41 COMPOSITE PIEZO TRANSDUCER DRIVE
351
STEP 6: Modify PA41 Aol curve for capacitive load of .1F. PA41 200
Ro =150 ohms, RCL = 75 ohms. Total output impedance, 180
Zo = 225 ohms. fp1
160
COMPOSITE Aol
1 1 140
fp2 = = = 7.07 kHz
2() Zo CL 2() 225 .1F 120
GAIN (dB)
fp3 and fdp4 in the modified PA41 Aol are contributions from 100
the original PA41 Aol curve. Refer to Figure 34. 80
200 60 fp2
fdp7
180 40 1/ fz1
160 20
PA41 Aol w/ VOUT / VIN fz2
140 Cc = 18pF 0 fp3
Rc = 2.2K 20 fp5
120
GAIN (dB)
100 fp1 40
.1 1 10 100 1K 10K 100K 1M 10M 100M
80 fp6
fcl
60 fdp4
fp2 FREQUENCY, F (Hz)
40
1/ fp5 fz1 FIGURE 37. COMPOSITE AMPLIFIER MAGNITUDE PLOT FOR STABILITY
20
PA41 AVCL
0 We will use Noise Gain to raise the 1/ curve to 40 dB and then use
20 fp3 the Feedback Zero Compensation to roll the 1/ plot off to 20 dB per
fdp4 decade slope to intersect the Composite Aol at a resultant rate of
40
.1 1 10 100 1K 10K 100K 1M 10M 100M closure that is 20 dB per decade. Refer to Figure 37. Notice that the
7K 9.3K fcl VOUT/VIN relationship is flat until the feedback zero at fdp7 (in the VOUT/
VIN relationship this is the pole at f = 1/(2 RFC CFC) begins to roll it
FREQUENCY, F (Hz) off at 20 dB per decade. When the 1/ intersects the Composite Aol,
(MODIFIED Aol WITH CL, RCL & Zo)
loop gain has gone to zero and VOUT/VIN follows the composite Aol
curve on down.
FIGURE 34. POWER OP AMP MAGNITUDE PLOT FOR STABILITY Once again our final stability check is completed by the open loop
phase plot for the composite amplifier as shown in Figure 38. (see
STEP 7: Compensate PA41 booster for stability with capacitive load. second page following this one.) The resultant 50 degrees of phase
If the booster stage is not locally stable, we have no chance margin guarantees a stable composite amplifier configuration.
at stabilizing the entire composite amplifier loop. We will add P.S. Refer to Figure 33. The 1N4148-1 diodes on the input of the
a feedback zero at 9.3 kHz. This will also add a zero in the OP07 provide differential and common mode overvoltage protection
1/ plot at fz1. Refer to Figure 34. Now plot the open loop from transients through CFC. Piezo elements being electromechanical
phase plot of the booster amplifier as shown in Figure 35 devices can generate high voltages if shocked mechanically. Output
(see following page). We see 67 degrees of phase margin diodes of the OP07 prevent overvoltage transients that occur through
for the booster amplifier loop. CF and shunted through PA41 internal input protection diodes, from
STEP 8: Create new Composite Aol from OP07 Aol and PA41 AVCL. damaging the output of the OP07 connected to +input of PA41.
Remember that if we add log functions it is the same as
multiplying gains. If we add the OP07 Aol plot to the PA41
AVCL plot from Figure 34, we obtain the Composite Aol plot
6.0 REAL WORLD STABILITY TESTS
as shown in Figure 36. We have devoted much text to discussing how to design stable
circuits. Once a circuit is designed and built it is often difficult to open
200
the feedback path in the real world and measure open loop phase
180 margin for stability.
160 The following Real World Stability Tests offer methods to verify if
COMPOSITE Aol predicted open loop phase margins actually make it to the real world
140
implementation of the design. Although the curves shown for these
120 tests are only exact for a second order system, they provide a good
GAIN (dB)
100 source of data since most power op amp circuits possess a dominant
OP07 Aol
80 pair of poles that will be the controlling factor in system response.
60
40 6.1 AVcl PEAKING TEST
PA41 AVCL
20 Figure 39 illustrates the AVcl Peaking Test for measuring open loop
0
phase margin in the real world closed loop domain. From the closed
loop Bode plot, we can measure the peaking in the region of gain roll-
20 off. This will directly correlate to open loop phase margin as shown.
40
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY, F (Hz) fdp4
6.2 SQUARE WAVE TEST
Figure 40 illustrates the Square Wave Test for measuring open loop
FIGURE 36. COMPOSITE AMPLIFIER Aol MAGNITUDE PLOT phase margin by closed loop tests. The output amplitude of the square
wave is adjusted to be 2 Vpp at a frequency of 1 kHz. The key elements
STEP 9: Compensate the composite amplifier for stability. With of this test are to use low amplitude (AC small signal) and a frequency
reference to Figure 37 we have repeated only the Compos- that will allow ease of reading when triggered on an oscilloscope.
ite Aol for clarity. We see that if we leave just a composite Amplitude adjustment on the oscilloscope wants to accentuate the top
gain of 17, 25 dB, we will have a 40 dB per decade rate of of the square wave to measure easily the overshoot and ringing. The
closure and instability. If we try to use just Feedback Zero results of the test can be compared to the graph in Figure 40 to yield
Compensation the 1/ plot will intersect the composite Aol open loop phase margin.
slope that is 60 dB per decade with a 20 dB per decade slope A complete use of this test is to run the output symmetrical about
yielding a resultant 40 dB per decade rate of closure. Our zero with +/-1V peak and then re-run the test with various DC offsets
optimum compensation will then use both Noise Gain on the output above and below zero. This will check stability at several
Compensation as well as Feedback Zero Compensation. operating points to ensure no anomalies show up in field use.
352
+180
+135
+90
fp5
+45
0
fp1 fz1 fp4
45
fp2 fp3
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
MARGIN = 67
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
FCL
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY (Hz)
FIGURE 35. POWER OP AMP OPEN LOOP PHASE PLOT FOR STABILITY
6.3 DYNAMIC STABILITY TEST 9.0 REFERENCES D

An expansion on the Square Wave Test is shown in Figure 41(see 1) Frederiksen, Thomas M. : INTUITIVE IC OP AMPS, R.R. Donnelley
second page following this one). The Dynamic Stability Test superim- & Sons, 1984.
poses a small signal AC square wave on a low frequency, large signal 2) Huelsman, Lawrence P. : BASIC CIRCUIT THEORY WITH DIGI-
AC sinewave to dynamically test the power op amp circuit under all TAL COMPUTATIONS, Prentice-Hall, Inc., Englewood Cliffs, N.J.,
operating point conditions. The resultant ringing on the square wave 1972.
can be compared to the graph in Figure 40 for relation to open loop 3) Faulkenberry, Luces M. : AN INTRODUCTION TO OPERATIONAL
phase margin. Note that R1 // R2 in Figure 41 must be much greater AMPLIFIERS WITH LINEAR IC APPLICATIONS, John Wiley &
than RIN or the input summing test impedances will affect the compen- Sons, New York, 1982.
sation of the power op amp circuit under test. 4) Dorf, Richard C. : MODERN CONTROL SYSTEMS (Third Edition),
Addison-Wesley Publishing Company, Reading, Massachusetts,
7.0 STABILITY TROUBLESHOOTING GUIDE 1980.
Figure 42 (see third page following this one) provides a trouble-
shooting guide for the most common stability problems. The Probable
Cause/Possible Solution Key gives insight into the origin of the
problem and provides guidance as to the appropriate fix.
8.0 FINAL STABILITY NOTE

When youre at your wits end trying to solve an oscillation problem,
dont give up because you have it down to an acceptably low level.
A circuit either oscillates or it doesnt, and no amount of oscillation is
acceptable. Apply the techniques and ideas in this Application Note
under your worst case load conditions and you can conquer your
oscillation problems.
If time is short or you cant see the forest from the trees, APEX would
be happy to provide Technical Support via FAX, 602-888-7003, or via
the Applications Hotline, 800-421-1865 (USA & CANADA, outside
Arizona only). Or call direct, 602-690-8600. More importantly, as we
tell all our customers, we would be happy to review your schematic for
stability considerations, etc., before you ever build a circuit or even buy
a power op amp.
353
+180
+135
+90
fdp7
+45
fz2 fp6
0
fp1 fp2 fdp4
45
fz1 fp3
90
fp5
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
MARGIN = 50
180
.1 1 10 100 1K 10K fcl 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY, F (Hz)
FIGURE 38. COMPOSITE AMPLIFIER OPEN LOOP PHASE PLOT FOR STABILITY
0
OPEN LOOP PHASE MARGIN (degrees)
10 CF
RF
PEAKING MEASURED CLOSED LOOP
20
RI
VO PEAKING
30 AVCL (dB)
LOAD
VIN
40
VO f
AVCL=
VIN
50
0 5 10 15 20 25
PEAKING (dB)
FIGURE 39. AVCL PEAKING TEST
354
1.6
1.4
13 0.2*
1.2
VO, RELATIVE OUTPUT TO A STEP FUNCTION INPUT
35 0.4*
40 0.6*
CF
1.0
RI RF
VOUT 2vpp
0.8
LOAD
52 0.8*
0.6
VIN 1KHz
64 1.0*
77 1.2*
0.4
90 1.4*
0.2
0
0 1 2 3 4 5 6 7 8 9 10
nt
* OPEN LOOP PHASE MARGIN AND DAMPING FACTOR

D
FIGURE 40. SQUARE WAVE TEST
RF
VIN CF +Vs
RI
+ VS
ADDED FOR STABILITY TESTING VO

R1 VO 0 t
LOAD
+ R2 VS
f = 10Hz Vs 100mV p-p SQUARE WAVE
DRAWN OUT OF SCALE FOR
+ CLARITY
f = 10KHz
(VIN FOR 100 mV VO)
(VIN TO SWEEP VO) R1//R2 > RIN
FIGURE 41. DYNAMIC STABILITY TEST
355
CONDITION AND PROBABLE CAUSE TABLE
Oscillates unloaded?
10.0 APPENDIX
Oscillates with VIN = 0? This appendix contains some handy tools for plotting magnitude and
Loop Check
fixes oscillation? phase plots for stability analyses. The Log Scaling Technique covers
Oscillation Probable Cause(s) an easy way to read exact frequency locations of poles and zeroes from
Frequency (in order of probability) magnitude plots for stability. Included, as well, are blank magnitude
fosc UGBW N Y N C, D and phase plots for copying and using to plot phase and magnitude
fosc CLBW Y Y Y K, E, F, J plots for stability.
One final tip. Once a magnitude plot has been plotted containing the
fosc UGBW N G, A, M, B
Aol curve and 1/, it is easy to translate the poles and zeroes to an open
fosc CLBW N Y Y D loop phase plot for stability. Simply use a light table (ours is very basic
fosc UGBW Y Y N* J, C a piece of plexiglass that fits over a 60W incandescent desk light !)
fosc CLBW Y Y N L, C
to trace the locations of poles and zeroes. Remember poles and zeroes
in the Aol curve are poles and zeroes in the open loop phase check for
fosc > UGBW N Y N B, A stability. But poles in the 1/ plot become zeroes, and zeroes in the 1/
fosc > UGBW N N** N A, B, I, H plot become poles in the open loop phase check for stability.
CLBW = Closed Loop Bandwidth
UGBW = Unity Gain Bandwidth LOG SCALING TECHNIQUE
See Figure 42A for loop check circuit.
Indeterminate; may or may not make a difference. When using rate-of-closure graphical techniques it is convenient to
*Loop check (Figure 42A) will stop oscillation if Rn << |XCF| at UGBW. measure what frequency fp or fz might be at without detailed
**Only oscillates over a portion of the output cycle. calculation. This handy reminder about log scale will give you that
power:
KEY TO PROBABLE CAUSE / POSSIBLE SOLUTION
A. Cause: Supply feedback loop (insufficient supply bypassing).
Solution: Bypass power supplies. See Section 2.3. l = LOG (fcl)
B. Cause: Supply lead inductance. d
Solution: Bypass power supplies. See Section 2.3. d
l
C. Cause: Ground loops. fcl = LOG1
d
( )
Solution: Use Star grounding. See Figure 9. l
D. Cause: Capacitive load reacting with output impedance (Aol pole). *fcl = 10(l/d)
Solution: Raise gain or use Noise Gain Compensation network.
See section 5.2.4.2. fcl = 10(1.4"/2") = 5.012Hz
E. Cause: Inductor within the feedback loop (loop gain pole).
Solution: Use alternate feedback path. See section 5.1. * This can be used between
F. Cause: Input capacitance reacting with high RF (noise gain zero). any decade of frequencies
Solution: Use CF in parallel with RF. (CF =~Cin). Do not use too by normalization of scale for
much CF, or you may get problem J. 1 to 10.
G. Cause: Output to input coupling. 1 fcl 10
Solution: Run output traces away from input traces, ground the FREQUENCY (Hz)
case, bypass or eliminate RB+ (the bias current compen-
sation resistor from +IN to ground)
H. Cause: Emitter follower output reacting with capacitive load.
Solution: Use output snubber network. See Section 2.5. Definition by example is easiest
I. Cause: Composite PNP output stage with reactive load. What frequency is fcl below?
Solution: Use output snubber network. See Section 2.5.
J. Cause: Feedback capacitance around amplifier that is not unity
gain stable (integrator instability). d
Solution: Reduce CF and/or increase Cc for unity gain stability. fcl = 10(1.4"/2") = 5.012Hz
K. Cause: Insufficient compensation capacitance for closed loop l
gain used. fcl = 501.2 KHz
Solution: Increase Cc or increase gain and/or use Noise Gain
Compensation network. See section 5.2.4.2.
L. Cause: Servo loop stability problem. Scale is normalized for
Solution: Compensate the front end or servo amplifier. 1 to 10 by dividing by
M. Cause: Unwanted signals coupling into op amp through case. 100. Answer to fcl is
Solution: Ground the case. multiplied by 100 to
yield final answer in KHz.
100K fcl 1M
FIGURE 42. STABILITY TROUBLESHOOTING GUIDE
FREQUENCY (Hz)
RI RF
V IN +V S
Rn
VO
RF
Rn
100 V S
FIGURE 42A. LOOP CHECK CIRCUIT
356
100M
10M
1M
100K
FREQUENCY (Hz)
1K 10K
D
.1 100
10
1
240
220
200
180
160
140
120
100
80
60
40
20
GAIN (dB)
357
100M
100M
100M
10M
10M
10M
1M
1M
1M
100K
100K
100K
FREQUENCY (Hz)
10K
10K
10K
1K
1K
1K
100
100
100
10
10
10
1
1
.1
.1
.1
+180
+135
+90
+45
0
45
90
135
180
+180
+135
+90
+45
0
45
90
135
180
+180
+135
+90
+45
0
45
90
135
180
without notice.
358
BRIDGE MODE OPERATION OF POWER OPERATIONAL AMPLIFIERS
APPLICATION NOTE 20
1.0 ADVANTAGES OF THE BRIDGE CONNECTION its output will clip. Since the master is driving the slave, we are
effectively clipping the drive to the slave also. Under these conditions
The bridge connection of two power op amps provides output the SOA voltage stress will be equally shared between the two
voltage swings twice that of one op amp. And it is the only way to obtain amplifiers.
bipolar DC coupled drive in single supply applications. Two possible Op amps such as the PA21, PA25, PA03, PA83, PA84, and others,
situations where this is an advantage would be in applications with low have fixed internal current limits and it is impossible to insure that the
supply voltages, or applications that operate amplifiers near their master current limits first. This is not a total disaster, it just means that
maximum voltage ratings in which a single amplifier could not provide under load fault conditions it cannot be guaranteed that the amplifiers
sufficient drive. will share the SOA voltage stress, and it must be assumed that one
There are other incidental advantages of the bridge connection. It amplifier could bear the entire stress.
effectively doubles the slew rate, and non-linearities become sym- Figure 2 is a simplification of output stages to give examples of
metrical reducing second harmonic distortion in comparison to a single amplifier stress under a difficult (low resistance such as a stalled DC
amplifier circuit. motor) load condition. The worst case stress must be used where
amplifier current limiting cannot be controlled. From this example it can
2.0 BRIDGE CONCEPTS AND TERMINOLOGY be seen that proper setting of current limiting, when possible, can halve
Figure 1 is a circuit diagram for the most common variation of a stresses under fault conditions.
bridge connection using power op amps. To clarify the discussion of Consider each amplifier individually for load analysis, SOA plotting
this circuit, well refer to the left hand amplifier A1 as the master and power dissipation calculations by halving the actual load imped-
amplifier, and A2 as the slave. The master amplifier accepts the input ance. Each individual amplifier cannot see the amplifier connected to
signal and provides the gain necessary to develop full output swing the other end of the load. The other amplifier doubles the voltage, and
from the input signal. The total gain across the load will be twice the thus the current, in the load.
gain of the master amplifier.
The master amplifier can be set up in virtually any op amp type +28
circuit: inverting or non-inverting, differential amplifier, or as a current
source such as an Improved Howland Current Pump. A2
1.24
Always configure the slave as a unity gain inverting amplifier and
drive it from the output of the master. Later discussions in connection
A1
with Safe Operating Area (SOA) and protection will show the impor-
tance of this point. ILim = 4A
4A x 1.24= 4.96V ACROSS LOAD
Rf 28-4.96 = 23.0V
23V WORST CASE STRESS
R 11.5V IF AI CURRENT LIMITS FIRST OR IF CURRENT

LIMITS MATCH PERFECTLY
+VS
RCL+ RCL+ +VS
FIGURE 2. EVALUATION AGAINST SOA
D
Ri R
4.0 STABILITY
A1 LOAD A2
VIN RCL RCL 4.1 STABILITY CONSIDERATIONS FOR THE SLAVE
Because the slave amplifier must operate as a unity gain inverter it
VS VS will be the most critical with regards to stability. Stability enhancement
VLOAD = +/2VS methods invariably involve a tradeoff of frequency response. Fortu-
PREVENT SOA VIOLATIONS
nately, in the case of the bridge, the master amplifier bandwidth is
SET I LIM (A2) > 1.2 I LIM (A1) naturally restricted by operating at higher gains (as well as easing
stability considerations for the master). Usually the slave can be
BANDWIDTH MISMATCH compensated such that the resultant circuit will have matching band-
widths on both halves.
FIGURE 1. BRIDGE MODE WITH DUAL SUPPLIES ( MASTER/SLAVE ) Noise gain compensation is the favored method of enhancing
stability. Keep in mind that noise gain compensation depends on the
3.0 PROTECTION AND SOA non-inverting input being connected to a low impedance (< 0.1Rn).
In the following discussions that all general precautions in using This is not a problem when the non-inverting input can be grounded,
power op amps, such as the need for external flyback diodes, transient as in split supply applications, but it must be considered in single
protection, input protection, etc., must be addressed. These subjects supply applications as the half supply voltage reference point must be
are dealt with in GENERAL OPERATING CONSIDERATIONS. The a good AC ground. The simplest way to insure a good AC ground is by
following discussion will concern itself only with specific protection good bypassing in the form of a tantalum or electrolytic capacitor in
issues related to bridge connections. parallel with a ceramic capacitor.
The concept of driving the slave from the output of the master power
op amp is essential for proper protection. The best illustration of the 4.2 NOISE GAIN COMPENSATION
value of that configuration is shown with an example such as Figure 1
where op amps with adjustable external current limiting have been As shown in Figure 3, a simple way of visualizing the effect of noise-
used. With externally settable current limit, set the master to current gain compensation is that it raises the apparent gain that the amplifier
limit 20% lower than the slave. If the master cannot be reduced, then sees (or in other words, reduces feedback) while not affecting the
raise the slave 20% above the master to provide better overall actual signal gain. Select Rn such that Rn > = 0.1Ri to limit the phase
protection than leaving them equal. If a fault occurs in the load such as shift added by the noise gain compensation. Note from the graph in
a short across the load, this will cause the master to current limit and Figure 3 that, in the example shown, the noise gain compensation
359
introduces a pole in the feedback path. In this case, at approximately output amplifiers such as the PA19, PA03 and especially the PA02, with
300 Hz. At 3000 Hz there is a zero in the feedback path. The region its local feedback loop in the output stage, can oscillate into inductive
between these points should be kept to less than a decade in loads. Monolithic amplifiers with quasi-complementary output stages,
frequency wide, and a maximum gain difference of 20 dB is implicit in such as the PA25 and PA41 can also be sensitive to inductive loading.
that requirement. In short, noise gain for the slave (which has an Compensate these amplifiers with a series R-C snubber from each
uncompensated noise gain of 2, or 6 dB) must be = 20, or 26 dB. amplifier output to ground (these are built into the PA21). For power
amplifiers the resistors typically run 1 to 10 ohms and capacitors 0.1 to
RI RF ZF ( = RF ) 1.0 F. For the monolithic PA41 refer to the PA41 data sheet.
5.0 SPECIAL CASES OF THE BRIDGE CONNECTION

CN ZI 5.1 CURRENT OUTPUT
RF The bridge connection can be a useful tool in a current output circuit.
RN
The maximum rate-of-change of current in an inductor, as would be
used in a deflection application, is a function of available voltage. For
ZI = RIII RN2 + XC2 that reason the bridge circuit could double the speed of a magnetic
deflection application.
In a current source configuration, the slave remains as an inverting
SMALL SIGNAL RESPONSE voltage amplifier. Only one amplifier needs to be (or should be) a current
120
source. Of the available ways of configuring an op amp for current
output, only the Improved Howland Current Pump is practical for a
Aol
100 power op amp bridge.
In Figure 4, the master amplifier is configured as the current pump.
R8 is the current sensing resistor. The Improved Howland Current
OPEN LOOP GAIN Aol (db)
80 Pump has many special considerations which will not be discussed

here, but it will suffice to say that generally the feedback and input
60 resistors should be very closely matched, usually better than 0.1%.
Regarding stability, with inductive loads a series R-C network will be
called for across the load, where in single amplifier applications it would
40 have gone to ground.
1/
Zf/Zl
20
Zf/Zl RF / RI
0 R1A R2 R3
+15V 1.5K 1.5K +15V 1.5K

100
R4 R5
1 10 100 1K 10K .1M 1M 10M
FREQUENCY, f (Hz) R1B .15 .12
DAC
FIGURE 3. NOISE-GAIN COMPENSATION +/-1.875V 1.5K .A1 .A2
PA02 PA02
Another consideration that could be given to the selection of Rn is
in regard to frequency response (gain vs. frequency). From Figure 3, R6 R8 R7
the signal gain of a circuit using noise gain compensation rolls off at the .5
point where the noise gain intersects the amplifier Aol. In the case of .15 .12
Figure 3, the normal bandwidth would be about 250 KHz, with R1C R1D YOKE 15
15
compensation about 25 KHz. Without compensation, the slave would
3MH,4OHM R9 C1
have wider bandwidth than the master which is operated at higher 1.5K 1.5K
gains. RPF
3.3K
An ideal value for Rn would be one which makes the noise gain of IOUT = +/- 1.875V
the slave match the signal gain of the master, assuming there is not MAXIMUM BEAM TRANSITION = 100US
greater than 20 dB of difference, and the noise gain limit of 26 dB in the
slave is not exceeded. In the event the master will also require noise FIGURE 4. ELECTROMAGNETIC DEFLECTION (BRIDGE AMPLIFIER)
gain compensation for stability, the same principle of matching the
noise gain will help to insure matched bandwidths.
The upper corner frequency of the noise gain compensation, or 20R 20R
R
1
VN = 20R
2 F R N
VIN +330
ONLY +15
zero, is determined by Cn such that : 2.2K 2.2K
where F= desired zero frequency. Cn should be selected so that the
10pF
zero is lower than one-tenth the frequency where the high frequency 10pF
noise gain crosses the Aol.
A1 A2
PA41 R CL R CL PA41 Rn
4.3 STABILITY CONSIDERATIONS FOR THE MASTER PIEZO
180 TRANSDUCER 180
In the case of the master, as well as the slave, capacitive loads 100 Cn
100
should also be considered. The only time the master would need noise
330pF 330pF
gain compensation would be for very low gains, capacitive loading, or
when using amplifiers with minimal phase margin such as the PA10
0 TO 636
and PA12. Methods of analysis for capacitive loads are discussed in VOLT ACROSS LOAD
detail in STABILITY FOR POWER OP AMPS, Application Note 19. 15 ONE POLARITY ONLY 330
Amplifiers with emitter follower or source follower outputs generally
do not have problems with inductive loads. However, collector or drain FIGURE 5.
360
5.2 UNIPOLAR OUTPUT +VS
A particularly powerful way of applying the bridge is in the unipolar

bridge. By unipolar, we mean that the output can only swing from 0 to RO
one polarity. Figure 5 is used to illustrate this technique. Rf
The master is a PA41 operating on supply rails of +330 and -15 volts. +VS
R2
The slave is operated at +15 and -330 volts. The lower voltage supplies
need only be large enough to respect the linear COMMON MODE VS
RCL+ RCL+ VS
voltage range requirements of whatever amplifier is used (12 volts in Ri
R1 R3
the case of the PA41).
The circuit is designed to accommodate positive going inputs only.
At full output swing the master can reach +318 volts while at the same A1 LOAD A2
time the slave is at 318 volts for a total voltage across the load of 636
volts. The full dynamic range with regard to the load is 0 to 636 volts
unipolar. RCL RCL R4
The circuit could also be designed such that it accepts negative Ri R3 = R4
going inputs and the output of the master swings negative and the +VS
RO
slave positive by reversing the supplies.
VIN
Rf
5.3 SINGLE SUPPLY APPLICATIONS
In the single supply circuit shown in Figure 6, connect the slaves
non-inverting input to a pair of equal value resistors connected FIGURE 6. BRIDGE MODE WITH SINGLE SUPPLY (OTHER THAN PA21)
between supply and ground. This provides a 1/2 supply center
operating point for the entire bridge. This point should be well by-
passed.
The simplest way to understand the configuration for the master is 1K 10K 10K +VS
to delete the resistors Ro, upon which the master becomes the
standard circuit for a differential amplifier. The two Rf resistors should
be reasonably matched to each other, and the two Ri resistors +2.2F +Vs 10K
matched to each other. An advantage of this configuration is that the A1 1.0 1.0 A1 10K
gain is simply the ratio of Rf/Ri. 1/2 PA25 1/2 PA25
Now consider the Ro resistors. Their sole purpose is to provide an
equal DC bias on each input and to get the quiescent DC level within +2.2F
10K
the amplifiers COMMON MODE voltage range requirements. This is
generally anywhere from 5 to 12 volts inside of each supply rail and is
given on all amplifier data sheets. For example, using PA05 on a 90 volt VIN
supply, the COMMON MODE VOLTAGE RANGE of the PA05 dictates +VS
that the inputs must never come closer than within 8 volts of either rail.
So the objective is to select Ro, to set the amplifier inputs to at least 8 A2 1.0 1.0 A2
but not more than 82 volts, and to stay within these limits under normal 1/2 PA25 1/2 PA25
input swings. As far as exactly what voltage? It could be argued that
half supply is the optimum common-mode point assuming this doesnt
cause excessive current to flow in the Ri resistors. In higher voltage 100K VS PO
applications the range of 5 to 15 volts is more practical though.The 8 4 10K
PA21 and PA25 are especially easy to use in single supply applica- 28V
40V
38W 55W
75W 100W
+2.2F D
tions. Since these amplifiers common-mode range includes the nega-
tive rail, or ground, their inputs can be driven directly without additional
biasing components. The slave must still have its noninverting input
biased at 1/2 supply for proper bridge operation. FIGURE 7. SINGLE SUPPLY PARALLEL BRIDGE
RFM RIS
100K RFS 100K

+12V +48V +48V +48V 100K +48V +12V
.1F 33F .1F IN6290
33F .1F .1F
+ IN5806 +
RIM
RCL RCL
10K IN5806
OP-07 .649 .511 OP-07
1W M 1W
RNM A1 PB58 PB58 A2
LOAD RNS
1K CC CC
6.34K
CNM IN5806 IN5806
VIN .1F 33PF 33PF .1F CNS
.082F IN6290 1500PF
+/5V 12V RG RG 12V
+ 9.31K 9.31K +
48V 48V
33F .1F 33F .1F
48V 48V
FIGURE 8. PB58A MOTOR DRIVE BRIDGE
361
5.4 PARALLEL CONNECTION
The bridge circuit can also be combined with the parallel connection
of power op amps. Figure 7 shows how substantial audio power
outputs can be obtained along with improved reliability since the
parallel connection spreads the load among more amplifiers.
Note that in the parallel connection, the pair of paralleled amplifiers
are labeled as master and slave also. Because the slave amplifier
operates as a unity gain buffer, an amplifier must be selected which
has a COMMON MODE voltage range that exceeds its output voltage
swing capability. If this cannot be done, configure the slave as a
differential amplifier with 4 equal valued and closely matched resistors.
Stability can also be a problem with the slave in the parallel amplifier.
A resistor may have to be inserted in the feedback to allow for the use
of noise gain compensation. (Noise gain compensation does abso-
lutely nothing when placed across the inputs of a unity gain buffer with
no series resistance in the feedback path)
5.5 BRIDGES USING POWER BOOSTERS

A bridge circuit using the PB50 or PB58 would require a composite
amplifier for both master and slave. The composite amplifier is not an
optimum configuration to operate at unity gain when stability is
considered. Use noise gain compensation to establish an adequately
high noise gain at high frequencies. Note that observing the criteria
previously discussed regarding noise gain would typically dictate that
the noise gain for the slave be 26 dB (Gain = 20). See Figure 8 for
a bridge circuit using power boosters.
without notice.
362
SINGLE SUPPLY OPERATION OF POWER OPERATIONAL AMPLIFIERS
APPLICATION NOTE 21
+VS
1.0 SINGLE SUPPLY OPERATION INTRODUCTION
Single supply operation of power op amps is most often done out of
necessity. Examples of such applications are battery powered appli-
cations or circuits operating from vehicular power systems.
Single supply operation improves the efficiency of power supply
usage. In split supply applications, current is drawn from only one LOAD
supply at a time, with the opposite supply sitting idle unless bridge
circuits are used.
This application note deals exclusively with applications operating
off of positive supplies as this occurs 95% of the time. Negative supply A. LOAD TO GROUND
R
principles are identical except for the reversal of polarity.
+VS
2.0 RESTRICTIONS OF SINGLE R
VS
SUPPLY OPERATION
2.1 COMMON-MODE RESTRICTIONS LOAD
Keeping op amp inputs biased to within their linear common-mode 1/2 VS
voltage range is the most important requirement in single supply
circuits. The actual value required varies for each amplifier model, and
is described in individual model data sheets under SPECIFICATIONS,
COMMON MODE VOLTAGE RANGE. DO NOT USE the specification B. BRIDGE
given in the ABSOLUTE MAXIMUM RATINGS block of the data sheet. +VS
2.2 LOAD CONNECTION TO GROUND

There will be several options available for load connection, as 1/2 VS
shown in Fig. 1. The first option shown in Fig. 1A, is a load connected LOAD
to ground. Obviously only positive going outputs are possible. Note
that when the output voltage the load sees is near zero, the amplifier
considers its output to be swung to its negative rail.
Note also that amplifiers have limits as to how close they can swing C.1/2 SUPPLY
to either rail. So the output for the grounded load can never actually
go to zero. It has been observed that substantial current is available +VS
under these non-zero conditions, and that the amplifier has full source
and sink capability. As an example, a PA12 in a single positive supply
will swing as low as 2.5 volts on the output. If a load is connected from
D
output to ground, even with the amplifier overdriven in a negative
direction, it will supply substantial positive current, on the order of
amps, and up to the current limit, into the load. LOAD
2.3 BRIDGE LOAD CONNECTION

The bridge load connection using two amplifiers, as shown in Fig. D. AC COUPLED SINGLE CAP
1B, permits bipolar swings across the load. For DC coupled loads this
+VS
is the only practical way to obtain bipolar swings. Note that the bridge
effectively doubles the gain of the circuit.
2.4 LOAD TO HALF SUPPLY

Bipolar drive is possible if the load can be referred to a point at half LOAD
supply, as in Fig. 1C. This is usually not practical, nor efficient, as the
half supply point must have the current capacity to support the load
requirements. It might be possible to use a second power op amp as
a high current source and sink regulator for this point, but this second
op amp would be much more efficiently utilized as the second half of E. AC COUPLED DUAL CAP
a bridge.
FIGURE 1. LOAD CONNECTION OPTIONS
2.5 CAPACITIVE COUPLED LOAD

In applications such as audio, it is possible and often desirable to AC
3.0 CIRCUIT TOPOLOGIES
couple the load with a capacitor. A simple series capacitor allows
driving a ground connected load, as in Fig. 1D. An alternative is to 3.1 UNSYMMETRICAL SUPPLY
connect the ground side of the load to two large electrolytics, as in Fig.
1E. The only possible advantage of Fig. 1E is the possible reduction Oddly enough, the first option that should be considered is to not use
of turn-on pop in circuits where this may be a problem. a single supply. Many applications such as those using high voltage
amplifiers require a single large high voltage supply and unipolar
363
output swings. This is to allow incorporation into systems which To illustrate, assume the use of a PA85 with +450 volt supplies. RO
already have lower bipolar supplies such as 15 or 12 volts present. can be selected for anything from 12 volts to 438 volts for linear
Should this be the case, then use the 15 or 12 volt supply on the operation. It could be argued that the ideal value is half supply, or 225
negative rail of the op amp (more than a few high voltage applications volts, but such a selection would require unreasonably large values for
have large negative supplies along with 12 or 15 volt bipolar supplies). RI to keep currents within reasonable values. A very large RI would
As shown in Fig. 2, as long as the small supply is large enough to require an even larger RF, and the net overall impedance would be so
accommodate the common-mode requirements of the amplifier over high that stray capacitance and amplifier input capacitance would
the range of normal inputs, then no other additional components are create enormous bandwidth and stability problems. For high voltage
required. applications, minimum values such as 12 to 15 volts of common mode
Rf
biasing are easier to accommodate.
When selecting RO, consider it part of a voltage divider where the
ground leg of the divider is the parallel resistance of RF and RI. Using
+430V
that assumption, at full negative input voltage swing in conjunction with
RI
full theoretical negative output swing of zero, you will be designing to
VIN meet common mode requirements. Dynamically, the inputs will only
VOUT
PA85 move positive from this point, simplifying worst-case analysis to
0 to 415 V
double checking the most positive excursion. RO selection can be
aided with the following equation:
-15V (VS VCM)
RO =
FIGURE 2. UNSYMMETRICAL SUPPLIES
( VCM
RI || RF )
3.2 DIFFERENTIAL CONFIGURATION
VCM is the desired common mode voltage. Once a value is
The most universally useful single supply circuit is the differential settled on for RO and the common mode bias point, it should be
configuration shown in Fig. 3. This topology makes it possible to set the rechecked over the expected range of input signal values to verify
gain simply as the ratio of RF/RI where each RF pair and RI pair are common mode restrictions are met dynamically and readjusted if
matched to each other. It is feasible to use the circuit either non- necessary. Also consider that part of the RO current flows in RI and
inverting or inverting, but keep in mind that noninverting will accommo- through the source driving the input. The source must be able to
date inputs which go positive only with respect to ground, and non- accommodate this current.
inverting negative only with respect to ground. Also note that the RO The differential configuration is so useful that in section 7.0, several
pair must be closely matched to each other. design examples will be explored. Appendix A outlines a procedure for
VS
the design of this circuit.
Rf
VS 4.0 EXPANDED TECHNIQUES

RO
4.1 BRIDGE CONNECTION

Ri
The bridge connection shown in Fig. 4 uses the differential configu-
RO Rf ration for the master, A1 amplifier, and a unity gain inverter for the
VO =
Ri slave, A2 amplifier. The slave non-inverting input is referred to a point
VCM on a divider at half supply voltage. Since this divider is referred to the
Ri
VIN 0 supply, there will be susceptibility to power supply variation. Note that
Rf the zero output point is defined as the point where both amplifier
outputs are equal, and this point is set by the non-inverting input of the
slave.
For VIN = 0:
+VS
VS (Ri//Rf)
VCM =
RO +(Ri//Rf)
RO
VIN (RO//Rf) Rf +VS
VCM = R2
Ri +(RO//Rf)
VS
Ri RCL+ RCL+ VS R3
For VIN > 0:
R1
VCM = VCM + VCM
@VIN = 0
A1 LOAD A2
FIGURE 3. SINGLE SUPPLY NON-INVERTING CONFIGURATION
The RO resistors provide the input common-mode biasing to keep RCL RCL
Ri
the amplifier linear. An advantage of this method is that (assuming +Vs R4
adequate resistor matching) the output would be unaffected by varia- RO
tions in power supply voltage. Normally this inherent supply rejection VIN
is desirable, but in the case of the bridge amplifier, this could be a Rf
problem since the slave of the bridge is referred to a voltage divider
operating from supply voltage. That divider is subject to supply
fluctuations, and if the master amplifier of the bridge was equally FIGURE 4. BRIDGE MODE WITH SINGLE SUPPLY OTHER THAN PA21
subject to such fluctuations, it would appear as a common-mode signal
across the load and be rejected. The preferred way of improving the bridge circuit tolerance to power
RO needs to be selected to satisfy common mode voltage require- supply variations would be to regulate the half supply point. In the
ments, and it turns out this encompasses a wide range of acceptable event this is not possible or desirable, Fig. 5 shows a bridge topology
values for any given circuit. The designer is confronted with the that reduces sensitivity to supply variations. The ratio of R2/R1 should
question of just exactly what common mode voltage to set the inputs be ratio matched to the ratio of R7/R8. Note that gain of A1 will be:
to. It could be set anywhere within the common mode range, but there
will be some practical limitations even within that range. AV = ((R4/R3)+1) * (R2/(R2+R1))
364
+Vs 5.0 SPECIAL OP AMP CASES
R5
Rf
5.1 PA02 SINGLE SUPPLY BEHAVIOR
R1 R6
R3 A PA02 presents a special problem in single supply application. Like
+Vs +Vs all BiFET input op amps, a negative common mode violation on either
Ri or both inputs causes the output to go full positive. Common mode
violations are inherent in power up conditions in all op amp circuits
A1 LOAD A2 since common mode is measured with respect to the supply rail.
In the case of a PA02, when the inputs are closer than 6 volts to
either supply rail there is a common mode violation. It is implicit in this
requirement that until total rail-to-rail supply voltage has reached at
least 12 volts, the amplifier will not be linear. With a PA02 in particular,
until the negative supply rail is at least 5 to 6 volts more negative than
R2
R1 = R 2 R3 = R4 R 5 = R6 BOTH inputs, the output will be hard positive. This causes PA02
R4 output to go full positive during power up in single supply applications.
VIN V When used as an audio amplifier, this results in a loud pop from the
Since IN by R1, R2, and A2 doubles gain
2 Rf speaker during power up.
then AV(LOAD) = +1
Ri There is no elegant solution to this problem. If the speaker is AC
coupled and returned to positive supply rather than ground, this may
FIGURE 5. MODIFIED SINGLE-SUPPLY BRIDGE FOR IMPROVED help some. But most applications have shown the only dependable
SUPPLY REJECTION
solution would be a relay that closes the circuit to the speaker once full
Or, consider that while R1/R2 attenuate the input signal by half, and supply voltage has been reached.
the bridge circuit effectively doubles circuit gain with respect to the
load, then AV is equal to the non-inverting gain of A1, or RF/RI+1. 5.2 PA21 SINGLE SUPPLY CONSIDERATIONS
The AC coupled bridge is a special case of the single supply bridge
amplifier circuit, and is especially useful for audio where a stable DC A PA21 is without a doubt the easiest power op amp to use on single
operating point is desirable. Fig. 6 depicts such a circuit. Note that both supplies since the input common mode range can actually go more
non-inverting inputs use the half supply point as a bias reference. C1 negative than the negative rail. Inputs can be applied to a PA21 in
AC couples the input signal. C2 blocks the DC ground path in the single supply applications without the need for additional biasing
feedback loop insuring a unity gain for A1 at DC. circuitry. The circuit shown on the front of the PA21 data sheet
illustrates just how easy it is to apply for unipolar inputs in a DC motor
R3
drive application.
RF +12V
10K 10K
RI 5.3 COMMON MODE BEHAVIOR IN GENERAL
10K
1K +12 1K It is helpful if the designer has some idea of which amplifiers are
R4 R5 subject to unusual behavior during common mode violations. Like the
20F PO = 8W BiFET PA02 described above, any FET input power op amp can
C2
1/2 1/2 exhibit polarity reversals during common mode violations. The polarity
PA21 PA21 of most FET input stages, such as a PA07, all high voltage op amps,
RL = 4 and Burr-Browns OPA541, are such that a positive common mode
C1 A1 A2 violation will cause a reversal of output polarity. This occurs since gate
2F to drain of input FETs becomes forward biased under these conditions
and the signal effectively bypasses the FET and its normal inversion.
VIN R1
R2 1K D
100K
10K 0.1F R6 5.4 AMPLIFIERS WHERE SINGLE SUPPLY
C3
OPERATION IS NOT RECOMMENDED
FIGURE 6. AC COUPLED BRIDGE The use of a PA89 in single supply circuits is discouraged. The input
common mode voltage range dictates the inputs must always operate
at least 50 volts inside of either supply rail, an impractical value to
4.2 CURRENT OUTPUT CONFIGURATION establish bias in the differential configuration. Unsymmetrical supply
Any voltage to current configuration is possible in the single supply techniques are more applicable for getting large unipolar swings out of
environment, as long as common mode restrictions are met. The PA89 circuits. In the case of a PA89, the smaller supply needs to be
floating load current source will be restricted to unipolar outputs at least 50 volts.
although the output cannot swing to zero current. Of course a bridge The power boosters PB50 and PB58 also present unique problems.
topology has many benefits including bipolar output, the ability to For example, the ground pin of these parts must see a clean analog
deliver zero current, and more voltage available to the load. In ground with low impedance over a wide bandwidth. This can be difficult
magnetic deflection applications, the higher voltages make for faster to insure in a single supply environment. A PB50 must operate with its
current transitions. ground pin 30 volts more positive than the negative rail, while a PB58
Since the Improved Howland Current Pump resembles a differential must operate at least 15 volts, and preferably 20 volts more positive
amplifier, it easily lends itself to single supply applications. The only than the negative rail. While it is possible to use these parts in a single
modification will be the addition of the RO common mode biasing supply environment, it is far preferable to use them with split or
resistors. The Howland is subject to wide dynamic range variations on unsymmetrical supplies.
both input and amplifier output with an infinite number of possibilities
when various gains are factored in. Suffice to say the designer must 6.0 TURN ON POPS
analyze input common mode values at the four extremes of dynamic
range: Regardless of amplifier choice, audio applications where the load is
1. Most positive input, most positive output AC coupled and connected to ground will always be susceptible to turn
2. Most positive input, most negative output on pops. The two main reasons this occurs are: the amplifier is not
3. Most negative input, most negative output linear until supply voltage is high enough; and the amplifier output
4. Most negative input, most positive input. inherently must go from zero to about half supply.
A bridge configuration will often improve (reduce) the likelihood of
pops. Or as mentioned above, a relay which closes the circuit to the
load once full supply voltage has been reached can help; although,
with an AC coupled grounded load the output capacitor must still be
365
charged. see if currents through the input resistors and input terminals remains
Controlling power supply rise time to be sufficiently slow can also reasonable. From the equation in 3.2 above, this would result in an RO
alleviate this problem. It may require slowing it such that it even takes value of approximately 8.48K ohms, nearest standard value 8.2K
seconds. Even this technique will add a relay or some type of solid ohms. This would result in 1.65mA flowing to the input terminals and
state switch. The easiest way to implement a slow rise supply is with no inordinate power dissipation in any of the input circuit resistors.
a sufficiently large resistor in series with a filter capacitor. Since the process used to select RO is based on worst case negative
voltage input/output relationships, the common mode should be re-
7.0 DESIGN EXAMPLES checked for full positive inputs and outputs. Assuming +5 volts at the
input and a theoretical +28 volts at the amplifier output, the circuit
simplifies to RO and RF being in parallel to +28 volts and forming a
7.1 DESIGN SPECIFICATIONS: voltage divider with RI as the ground leg. This results in a voltage at the
Supply voltage = 28 volts. Input signal range = 0 to 5 volts. Unipolar amplifier input of 16.32V, that is within the maximum positive common
output, single ended. mode restriction of 23 volts.
A PA12 has been selected for a unipolar voltage output motor drive.
Differential configuration is selected, see Fig. 7. (Note that many 7.2 DESIGN SPECIFICATIONS:
details will not be discussed here, but are covered in other app notes,
such as current limit resistors, flyback diodes, and power supply Supply voltage = 28 volts. Input voltage -2.5 to +2.5 volts. Voltage
bypassing.) in, current output (will require Improved Howland Current Pump).
Select RF/RI: This requires arbitrarily fixing one of these resistor Output range 2A.
A PA02 is selected for this application along with a bridge circuit.
+28 Referring to Fig. 8, the R1, R2 and R4, R3 ratios were selected to
RO provide the required transfer function based on a 0.301 ohm current
+28 sense resistor, RS. Note that over the expected normal range of input
8.2K RF signals and output voltages that common mode requirements are met.
RI
56K R
While true for this application, each one should be checked to verify the
CL + voltages are within acceptable limits. Note that even on this circuit that
10K exceeding the 2.5 volt dynamic range on the inputs will cause
common mode violations to occur.
PA12
RO RCL
+28 7.3 DESIGN SPECIFICATIONS:
8.2K
RCL Supply voltage = 450 volts. Input voltage 0 to 10 volts. High voltage
RI
VIN bridge for piezo drive. Low power consumption.
0 to 5V 10K A PA88 is selected to meet low consumption requirements, the
RF
56K +450 +450 +450 +450
FIGURE 7. UNIPOLAR MOTOR DRIVE EXAMPLE RO

300K RF R1
values. In general, the best practice is to fix RI at about 10K ohms, as RI R2
510K 510K
this is an impedance that most any small signal source will drive with
11K RCL 510K R3
no problem.
+450 200K
dVIN has been established at 5 volts. While it is true that an op amp RCL
RF dVOUT RO
= PA88 LOAD PA88
RI dVIN VIN 300K
0 to 10V RI
output cannot actually swing exactly to each rail, the circuit scaling CC CC
RC RC R4
should be selected as if it could; therefore, on a 28 volt supply, 11K RF
C.1
dVOUT=28 volts. This results in a value for RF of 56K ohm. 510K 200K
0.1
Now RO must be selected to respect PA12 common mode require-
ments which dictate that the inputs must be kept 5 volts inside of either
supply rail. So the inputs could be set anywhere from 5 to 23 volts. An FIGURE 9. PA88 H.V. BRIDGE
ideal value would be 14 volts. Lets try an RO value based on that and
circuit is shown in Fig. 9. RF and RI must provide a gain on the master
R1 amplifier of 45. In the process of minimizing power
consumption and maintaining a reasonable physical
2.1K size for components, consider there can be as much as
+28V VA1 VA2 +28 +28 450 volts across RF. In order to use a half watt resistor,
RF would need to be 510K ohms. For a gain of 45, RI
RCL1+ RCL2+ would then be 11K ohms.
R7 In this high voltage application, it is wise to design for
.258 .205 4.99K
R2 the minimum acceptable common mode voltage which
8.66K RS is 12 volts for a PA88. 15 volts will be used to provide a
R8 C1 little margin. 300K ohms will be required for RO. 510K
PA02 PA02 4.99K .1F
.301 ohms will also be required for both gain setting resistors
VIN RW = 6.5 on the slave.
RCL1 RCL2
The half supply reference point resistors will each
.258 .205 have 225 volts across them. The minimum acceptable
R3 R4 R5 R6
value for half watt resistors would be 101K ohms each,
but to minimize consumption, 200K ohms each is used.
8.66K 2.1K 4.99K 4.99K These must be bypassed.
VCM With the large value feedback components around
VIN VCM VA1 VA2 IOUT the slave, amplifier problems can result from feedback
+2.5V 6.0V 7.2V 20.8V 2A poles being created by amplifier input capacitance and
2.5V 16.5V 20.8V 7.2V +2A stray capacitance. This may require a small compensa-
tion capacitor from 2 to 20 pF across the feedback
FIGURE 8. LIMITED ANGLE TORQUE CONTROL (SINGLE SUPPLY) resistor.
366
7.4 DESIGN SPECIFICATIONS: common mode bias under all conditions if for no other reason than
it is the only hope the op amp has to recover from the following
Supply voltage = 450 volts. Input voltage 0 to 10 volts. Wide band conditions:
high voltage driver. Single ended. a. Full negative input (usually 0), full negative output (theoretical 0).
The circuit in Fig. 10 contrasts with the previous example in that it This condition is accounted for in the equation to select RO.
is a wideband circuit and requires the lowest possible impedances at b. Full negative input, full positive output (assume theoretical maxi-
all modes. The standard differential configuration will be used. This is mum equal to supply voltage).
an example where minimum common mode bias will have to be set to c. Full positive input (dont forget that most small signal op amps could
avoid excessive current and dissipation problems in resistors. swing beyond their 10 volt linear limit, often up to a full 15 volts), full
+450 negative output.
d. Full positive input, full positive output.
RO RF
68K 91K If any of these four conditions do not meet common mode restric-
+450 tions, adjust RO accordingly. For instance, if a violation is more
RI RCL negative than minimum allowable common mode bias, reduce RO
2K (most common likely problem). If the violation is positive, which is
VO unlikely with most realistic bias levels, then RO should be increased.
RO PA85
68K 5. If being used in a bridge, it is recommended that the slave amplifier
+450 CC noninverting half supply bias point be regulated, either with a zener
VIN RC diode or derived from some regulated voltage.
0 to 10V RI RF
2K 91K
(FOR RC, CC SEE PA85 DATA SHEET)
FIGURE 10. PA85 H.V. DRIVE

Gain for this circuit will be 45. In order to use the lowest possible
value for RF to insure good bandwidth, a 5 watt resistor will be used.
Assuming worst case voltage stress across RF to be 450 volts, the
lowest permissible standard value is 43K ohms. For a gain of 45 volts,
RI must be (nearest standard value) 910 ohms. Because of such low
impedances, a minimum common mode bias (from the PA85 data
sheet) of 12 volts must be set.
Solving for RO, assuming 12 volts of common mode bias, with an
input of 0 volts and theoretical 0 volt output, the value is (nearest next
lowest standard value) 30K ohms. This resistor will have 438 volts
across it and will dissipate 6.4 watts.In addition, 15mA will flow through
the input terminal. These values will be difficult, if not impossible, to
work with. It may be possible to scale up by a factor of two and have
sufficient bandwidth.
Re-calculating using 91K ohms RF, and 2K ohms RI, RO solves to
68K ohms, the nearest standard value. Dissipation in RO is now 2.8
watts and 6.3mA flows to the input resistor. While these numbers are
better, they could still be a problem. Further scaling up of impedances
will aggravate bandwidth problems as the effects of parasitic and
amplifier input capacitance become significant. D
This design example has been shown to be feasible in the design
of a single supply circuit. But use of a 15 volt supply for the negative
rail will eliminate the impedance constraints and permit the circuit to be
designed for maximum possible bandwidth with a conventional circuit.
APPENDIX A: PROCEDURE FOR DESIGN OF

DIFFERENTIAL CONFIGURATION
1. Select RF and Ri:
RF dVO
GAIN = =
RI dVI
In general, RI should be the resistor value on which all

others pivot. This is because RI essentially represents the load
presented to the input signal. Most small signal op amps work best
if RI is 10K ohms or larger, but many would permit RI to drop as low
as 1K or 2K ohms if necessary.
2. Select RO:
VS VCM (MIN, from amplifier data sheet)
RO
( VCM
RI || RF )
3. Check dissipation in Ro. If too high, all resistor values need to be
re-scaled upward.
4. Re-check VCM at all four possible extremes of both input signal and
amplifier output voltage. Although some of these operating condi-
tions may not actually occur, it is wise to have a circuit that has linear
however, FAXis(520)
ORDERS (520) 690-8601
367
SOA AND LOAD LINES
APPLICATION NOTE 22
1.0 MEANING OF SOA GRAPH +50 VO VSVO IO

SOA (Safe-Operating-Area) graphs define the acceptable limits of 0 50 0
stresses to which power op amps can be subjected. Figure 1 depicts 5 45 .556
a typical SOA graph. 10 40 1.11
PA12 15 35 1.67
20 30 2.22
OUTPUT CURRENT (AMPS) 9 25 25 2.78
10.0 30 20 3.33
35 15 3.89
50 40 10 4.44
MAXIMUM CURRENT 45 5 5.00
5.0
THERMAL t = 0.5ms
15
t=
TC = 25C 10
0.5
3.0 TH
t=
ER
ms
t = 1ms MA TC
t=
1m
L =2
5.0 5C
5m
s
2.0
TC = 85C
s
TC
=8
5C
AMPS
1.0 3.0
TC = 125C
t = 5ms 2.0 TC
.7 =1
1.5 25
ste
C
ad
.5
1.0
ys
STEADY STATE
tat
.7
e
.3
SECOND .5
BREAKDOWN SECOND BREAKDOWN
.3
.2 10 15 20 25 30 35 40 50 60 70 80 100
10 15 20 25 30 35 40 50 60 70 80 100 FIGURE 2. PLOTTING RESISTIVE LOAD LINE

SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE, VsVo (V)
line. It is interesting to note that this is a safe load which can require a
FIGURE 1. TYPICAL SOA PLOT 5 amp peak capability. If the output of the PA12 is unintentionally
shorted to ground the voltage stress on the output will be 50 volts,
Every amplifier has a maximum voltage limitation which will always which is not safe at the 5 amp current limit required to drive the load.
be defined by the right edge of the graph. Maximum current capability In applications where the amplifier output would not be subject to
is subject to more variables than voltage, so the continuous maximum abuse these operating conditions are acceptable. Foldback current
current value is well within the boundaries of the graph. Transient limiting can be used to improve on the safety of this situation.
currents are allowed in excess of the continuous limits. More on these
transient limits shortly. Besides voltage and current limits, SOA is a 2.2 PLOTTING REACTIVE LOAD LINES
function of power and this sets the sloping limits labeled for different
Reactive load lines of any phase angle can be plotted with the
temperatures. In the case of bipolar output amplifiers only, there is yet
methods shown here. A completely reactive load line almost looks like
another region called second breakdown. On the SOA graph in Figure
an ellipse on the SOA graph since current stresses will occur at two
1 for the PA10, note that the slope increases at about 33 volts as a
different levels of voltage stress.
result of second breakdown.
The voltage output waveform will define the reference phase angles
Transient SOA limits shown on data sheets are based on a 10% duty
for all point-by-point stress calculations. The waveform shown in
cycle pulse starting with junctions at 25C. The repetition rate then
Figure 3, starts at 90, since current in capacitive loads will lead in
would logically be defined by the time required for the junction to return
phase. The waveform ends at 270 since that corresponds to the
to 25C between pulses. Some amplifiers such as PA85 allow tran-
maximum phase lag of the current in an inductive load. All calculations
sient currents beyond the maximum continuous current rating. Most
will be within the limits of these angles.
often though, the transient ratings are based on power or second
Calculations proceed according to the steps in Figure 4. Currents
breakdown restrictions.
will only need to be calculated over 180 since the load line for each
half of the amplifier is a mirror image. Capacitive loads will start at 90
2.0 ANALYTICAL METHODS and progress through +90. Inductive load calculations will start at
+90 and progress to +270. Step 2 in the procedure defines the
2.1 PLOTTING RESISTIVE LOAD LINES starting angle for calculations based on the load phase angle. For
Resistive load lines can be plotted quite easily. Keep in mind that example, a 45 load would start at 45 and continue to +135. A 45
since SOA graphs are log-log graphs, the resistive load line will have load will start at 45 and continue to 225
a curvature, so several points should be calculated and plotted. Example of a typical load calculation:
Output voltage and current will always have the same polarity with In the resistive load example the load line of a 9 ohm resistive load
a resistive load, so calculations can be performed at all times from 0 was plotted and was quite safe. For this example lets use the same
to 90 of the output cycle. Figure 2 depicts an example of resistive load impedance but with a 60 phase angle.
368
VOLTAGE WAVE FORM ESTABLISHES REFERENCE PHASE ANGLE
V I Vd (VS VO)
FOR ALL LOAD LINE CALCULATIONS. SHADED AREA REPRESENTS
CALCULATION REGIONS 9 <+60 60 0 11
(INDUCTIVE) LOAD 75 1.29 6.53
90 0 90 180 270 +VS 90 2.5 5
(+50V) 45VP 105 3.54 6.53
= 5APK 120 4.33 11
9 135 4.83 18.2
150 5A 27.5
VO 45V 165 4.83 38.4
PA12 180 4.33 50
195 3.54 61.6
LOAD 210 2.5 72.5
225 1.29 81.8
VS 240 0 89
IO (50V)
RESISTOR 15
t=
10 TC
TH
0.5
ER =2
t=
t=
MA 5C
ms
IO L
5m
1m
CAPACITOR 5.0
s
(90) TC
=8
3.0 5C
IO
2.0 TC
INDUCTOR =1
1.5 25
ste
(+90) C
a
dy
1.0
sta
te
.7
(45) .5
.3
10 15 20 25 30 35 40 50 60 70 80 100
(+45) Vs2 4
(NOTE THAT Pd max = Cos L = 107 w
2Z L
FIGURE 5. TYPICAL LOAD LINE CALCULATIONS
FIGURE 3. TYPICAL WAVEFORMS ASSOCIATED WITH average power dissipation using the formula shown in Fig 5 (refer to
REACTIVE LOAD LINE ANALYSIS General Operating Considerations for background on this calculation)
shows the amplifier dissipating 107 watts.
1. KNOWN: Vp , Z L, L
2. BEGIN POINT CALCULATIONS WITH L AT 0 + L AND PLOT
The 107 watt dissipation will certainly cause the amplifier to operate
at significantly elevated temperatures, even with a generous heatsink.
D
FOR NEXT 180 IN WHATEVER INCREMENTS NEEDED FOR Realistically the SOA limits are being reduced by the heating. We can
DESIRED ACCURACY (15 OR 30 INCREMENTS RECOMMENDED.) even define exactly how badly. Assume a 25C ambient (thats pretty
optimistic). Using an HS05 heatsink rated 0.85C/watt results in an
3. Ipk = amplifier case temperature 91C. It is evident that the PA12 is not well
Vp
CALCULATE ONLY ONCE suited for this application. The alternatives include either paralleling
ZL PA12s or upgrading to a PA05.
4. CALCULATE EACH INCREMENT:
I = Ipk (sin ( V L)) 2.3 SPECIAL CASES OF LOAD LINE PLOTTING
5. CALCULATE EACH INCREMENT: AND OTHER GENERALIZATIONS
Vd = Vs Vp (sin V)
For parallel connected amplifiers, assume each amplifier drives a
FIGURE 4. REACTIVE LOAD CALCULATIONS load rated at half the current of the total load. In essence, double the
Figure 5 shows a PA12 driving an inductive load of 9 ohm at 60. load impedance. Do just the opposite for a bridge circuit.
From step 2 of our procedure we know we begin calculating current at Some simple relationships to keep in mind: for totally reactive loads
60 and continue to 60+180 or 240. For this example we will use 15 maximum current occurs at a voltage stress corresponding to Vs and
increments. Actually, it is only necessary to perform the step-by-step maximum dissipation occurs at a voltage stress of Vs+(0.707Vs),
calculations for current up to the point where peak current occurs, in where current is also 0.707*Ipeak. In a resistive load, stresses are
this case 150. The increments back down to 240 will be a mirror much less with maximum current occurring at maximum output voltage
image of what was just calculated. However, dont get this lazy with the swing. This generally corresponds to the maximum swing specification
voltage calculations we have yet to do. given in every amplifier data sheet.
Even though the point of maximum voltage stress occurring at full Also keep in mind that there are many load lines which will fit well
negative output swings is not evident in the voltage stress calculations, within an amplifier SOA and be quite safe to drive. Yet these same
it is inconsequential since we have established that no current flows loads can demand current capability that requires current limits be set
through the output device at that time. As long as the amplifier itself is so high the amplifier output will not be able to tolerate inadvertent
within its voltage ratings, all will be well. shorts on its output. This is usually acceptable in applications with
After all points are calculated, they may be plotted on the SOA committed loads; however, applications where the amplifier output
graph. In this particular case note there are significant excursions terminals are accessible to poorly defined loads or fault conditions
beyond the steady state 25C SOA limit. Is this acceptable? Consider demand fault tolerance on the part of the amplifier. A good example is
the following factors to help make the decision: 1. The area beyond the a set of screw terminals like those found as the output connectors of
continuous SOA is quite sizeable. 2. A calculation of maximum an audio amplifier.
369
The methods shown here calculate load lines for reactive loads at 15

only one frequency. For inductive loads worst case stresses will occur
t=
at the lowest frequency of interest with the opposite true for capacitive 10
TH TC
0.5
loads. ER =2
t=
t=
MA 5C
ms
MOSFET amplifiers have an important difference from bipolar L
5m
1m
amplifiers regarding SOA limits: MOSFETs are only limited by power 5.0
s
dissipation, or the product of V*I stress. Bipolar amplifiers are power TC
=8
limited up to certain voltages indicated on the SOA graphs, where 3.0 5C
second breakdown imposes even lower limits on safe current than TC
=1
power dissipation would allow. 25
2.0 C
1.5
ste
2.4 PLOTTING AMPLIFIER CURRENT LIMITS CURRENT LINE
ady
1.0
Additional information which can be plotted on the SOA graph to
sta
help assess amplifier safety is the current limit of the amplifier. Simple
te
.7
fixed current limiting is simply plotted along the current corresponding
to that limit. Any load line excursions beyond that level can be .5
disregarded. They are simply not possible.
.3
Figure 6A depicts the SOA graph from Figure 5 with a fixed current 10 15 20 25 30 35 40 50 60 70 80 100
limit drawn in. The fixed limit is set to 1.5 amps to provide short circuit
safety at up to 85C case temperature. It is obvious the load line is SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE VS VO (V)
totally outside this current limit. The maximum available output will be A FIXED 15A CURRENT LIMIT
set by the 1.5 amp current limit and impedance of the load. Or in the Max VO(PEAK) REACTIVE = ILIM x ZL
case of a resistive load, the lowest load impedance is a function of
VO (pK) 45
maximum output voltage and current limit. LOWEST POSSIBLE RL = = = 30
Foldover current limiting can also be plotted on an SOA graph. This ILIM 1.5
is important with inductive loads since foldover limiting in conjunction 15

with inductive loads can cause more problems than it solves unless
applied carefully. When foldover current limiting occurs with an induc-
t=
10 TC
tive load, a violent flyback spike occurs that transitions all the way up TH
0.5
ER =2
t=
t=
to one of the supply rails. External ultra-fast recovery flyback diodes MA 5C
ms
L
5m
1m
are a must when combining foldover limiting and inductive loads. It is 5.0
s
also possible for relaxation oscillation to occur. This can be prevented
TC
by insuring that the normal inductive load line is well within all limiting =8
3.0 5C
values.
Figure 6B portrays foldover limiting according to formulas contained CURRENT LINE
in Application Note 9 or the PA12 data sheet. The load of Figure 5 2.0
TC
obviously cannot be driven. Note that with foldover limiting a peak 1.5 =1
25
ste
C
current of 2.8 amps is available yet short circuit current is limited to 1.5
ad
1.0
ys
amps making it possible to safely drive a 16 ohm resistive load. To
tat
determine the minimum acceptable value for a reactive load, consider .7
e
that 70.7% of peak current occurs at a voltage stress of Vs+(0.707Vs). 86 REACTIVE LOAD
A reactive load line within that operating point will likely be within all .5
operating points and representative of minimum acceptable load.
Figure 6B depicts the worst case acceptable reactive load. It really .3
doesnt fill up much of the permissible operating region, but such are 10 15 20 25 30 35 40 50 60 70 80 100
the trade-offs involved in driving difficult loads. SUPPLY TO OUTPUT DIFFERENTIAL VOLTAGE VS VO (V)
B FOLDOVER CURRENT LIMIT

3.0 BENCH TESTING SOA RCL= 0.433 PIN 7 OF PA12 GROUNDED
An oscilloscope can be used to do real world plotting of load lines
on actual working circuits. The SOA limits can be drawn in on the scope .65 + VO .28
( )
screen if necessary. First, the SOA limits should be redrawn on linear- IO = 20
linear graph paper. This results in an SOA graph as shown in Figure RCL
7A. The graph shown is for a PA12 bipolar amplifier, and second 45
LOWEST POSSIBLE RL = = 16
breakdown causes the break in the shape at 55 volts. MOSFET 2.8
amplifiers will have a continuous curve representative of power REACTIVE LOAD
dissipation. This can then be transferred to a transparency sized to
properly fit on a scope screen. 0.707 IPK @ VS + 0.707 (VS) = 50 + 35 = 85V
The easiest method of connecting a scope to plot actual output ILIM@ 85v = 370 mA
device stresses will be to refer the scope ground to the negative supply 0.707 VO 0.707 x 45
of the circuit as shown in Figure 7B. This connection results in the = = 86
proper phases for easy viewing on the oscilloscope. Since the oscillo- 0.37A 0.37
scope ground is connected to the negative supply line, be certain there FIGURE 6. PLOTTING CURRENT LIMITS
is ground isolation either in the amplifier power supply or the oscillo-
scope is connected to an isolation transformer.
Rs is a current sensing resistor. When possible, use of a 1 ohm 4.0 SOA MEASUREMENT CIRCUITS
resistor provides a direct scale factor on the vertical input of volts = Another means of analyzing SOA stresses in operating circuits uses
amps. If other values must be used consider scaling accordingly. The an analog multiplier to calculate real time instantaneous power dissi-
current sense resistor must be right at the amplifier power pin. This is pation. This method is especially applicable where second breakdown
one of those rare cases where it is temporarily necessary to violate the is not encountered. For example, working with MOSFET amplifiers
rules of proper power supply bypassing. Any capacitance present at under any condition or most bipolar amplifiers at total rail-to-rail supply
the node, where the resistor meets the amplifier will interfere with high voltages of less than 30 volts.
frequency measurements. If an oscilloscope current probe is available The circuit shown in Figure 8 senses output device current and
it is certainly preferable to the current sensing resistor since it provides voltage stress as is done with an oscilloscope. Differential amplifiers
accuracy and speed without having to disrupt the circuit. with wide common-mode ranges are used for sensing these values
370
and levels, translating them to be applied to an analog multiplier. The ZL = |ZL|
output of the multiplier will be the product of the voltage and current
stress on the output device. The Rs current sense resistor must be in PD (OUT)MAX = 2Vs2 , < 40
the supply line so current is measured in only the output device 2 ZL Cos
corresponding to the voltage stress measurement. 2
This circuit provides a signal indicating instantaneous power dissi- PD (OUT)MAX = Vs
2ZL
[ 4 Cos ] > 40
pation. When working with a MOSFET amplifier such as the PA04, the
designer should be concerned that this output be within the 200 watt PTOTAL= PD(OUT)MAX +PD(IQ)
dissipation of the PA04, or less if elevated temperatures are consid-
ered. Once worst case dissipation is known, use the heat sink thermal
resistance and ambient temperature to calculate amplifier case tem-
perature since SOA temperature limits are based on case tempera-
15
ture.
14 Effects of current limiting with reactive loads can also be evaluated
13 when plotting load lines. Current limit lines can be drawn on the SOA
12 representing current limit values. If reactive loads exceed these limits,
15 distortion will occur. Often an inductive load causes what appears at
14 first to be crossover distortion when viewing an amplifier output. In fact,
13 what is actually occurring is that the current peaks when voltage
12
transitions through zero and a light excursion into current limit looks
much like crossover distortion.
11
Foldover current limits can be plotted on SOA graphs point by point
10 as is done with load lines. Again, reactive loads must fit well within
A 9 current limits. This is especially important when relaxation oscillation
8 can occur if current limits are exceeded. In such cases the foldover
7 effect must be reduced or even eliminated.
6
5
4 AV = 0.053
+15
3
7
2 1 15
1 VSENSE BURR 6
BROWN
0 INA 117
10 20 30 40 50 60 70 80 90 100
4 X1
5 X2 X
15 ANALOG
DEVICES OUT
PAI2 PLOT OF 25C STEADY STATE SOA ON LINEAR GRAPH +15 AD534 Z1 VO
Y1
7 Y2 Z2
+VS
1
ISENSE
BYPASS BURR 6
(from RS) BROWN
INA 117
+15
4
5
15 Av = 1
D
B +VS
VO
PD = 1 8 9
O'SCOPE RS
RS (SEE TEXT)
OP AMP
V H UNDER +
BYPASS TEST V

VO PD
VS +
I

RS
FIGURE 7. OSCILLOSCOPE TESTING OF SOA 1
VS
5.0 OTHER FACTORS FOR DETERMINING SOA FIT FIGURE 8. INSTANTANEOUS POWER DISSIPATION TESTER
Since different SOA limits are shown for different temperatures, it is
helpful to be able to predict the amplifier temperature. One factor that
only the designer can define is ambient temperature. In particular,
maximum ambient temperature.
Amplifier power dissipation will also be a factor in determining case
temperature. Equations for predicting power dissipation maximums
are discussed in the Apex Handbook, General Operating Consider-
ations, section 7.0, and the equations are shown here for conve-
nience:
however, FAXis(520)
ORDERS (520) 690-8601
371
BRUSH TYPE DC MOTOR DRIVE WITH POWER OPERATIONAL AMPLIFIERS
APPLICATION NOTE 24
1.0 AMPLIFIER SELECTION Alternatively, stall resistance can be plotted as a load line on the
SOA graph. On the SOA graph, current limit should also be plotted.
One of the most entertaining moments as a power op amp applica- This is useful for conditions where the amplifier output will be attempt-
tions engineer is when a customer calls up asking for an op amp to ing to go to some other value than full output voltage under stall
drive a 24V, 2A motor and has already settled on a 5 amp amplifier. Its conditions. Remember, maximum dissipation occurs at an output
just not that simple. This current rating could have many meanings, voltage one half way between zero and the supply rail.
and actually there are two current rating conditions to be considered Figure 1 shows just such an example of a calculation. This example
when designing a reliable application: stall current and reversal uses a PA12A along with a motor which has a 3.2 ohm stall resistance
current. and bipolar 50V power supplies. If we simply plot the condition where
Reversing a motor is about the most stressful application to which the amplifier is against the rail, we have approximately 44V at the
power op amps are subjected. Its important to establish from the output and 13.8A of current flow. The supply to output differential and
outset if it will be necessary to sustain reversals. Some applications current result is a dissipation of 6 * 13.8, or 82.5W, which is within the
can disregard this; a good example being a simple speed control for amplifier SOA. If the amplifier output voltage were commanded to one
a motor always rotating the same direction. half supply rail or 25V under a stalled condition, the power dissipation
would be 195W, which is beyond the continuous SOA.
+50 This illustrates the value in plotting the stall resistance load line.
Both the low output and full output conditions are within the SOA, but
intermediate values create excessive dissipation and this is immedi-
ately apparent by plotting the load line. The point where the load line
D1 exceeds the 25C continuous SOA is a good value for maximum
acceptable current limit.
PA12 In summary, design for stalled conditions should at least plot the
resistive load line to determine proper setting of current limits. If the
D2 load line completely falls within the SOA, then other fault conditions of
3.2 STALL shorts from output to ground or output to either rail will take precedence
RESISTANCE in determining current limit values in the event these faults must be
accounted for.
50
MOTOR
MODEL 1A
REVERSAL LOAD LINE +

15
STALL LOAD LINE EMF RW

t=
45V
t=
10 41.8 3.2ohms
5m
TH RW = 3.2ohms
0.5
ER
t=
s
MA
ms
L TC I = 1A
1m
=2 REVERSAL
5.0 5C
s
WITH 3A
3.2 TC LIMIT
=8
LOAD 3.0 5C STEADY STATE REVERSAL
LINE 3A I LIM
+50 +50
2.0 TC
=1
1.5 25
ste
C
ad
1.0
ys
tat
.7 +45V
e
.5 RCL+ RCL+
SECOND BREAKDOWN 1A 3A
.3
10 15 20 25 30 35 40 50 60 70 80 100
RCL 41.8 RCL 41.8
+3.2V + 32.2V 9.6V
FIGURE 1. EXAMPLE OF MOTOR DRIVE LOAD LINE ANALYSIS
50 50
1.1 STALL RESISTANCE
VS VO = 82.2V
Every motor will be stalled. This is the required state of transition to
Pd = 82.2 x 3 = 246.6W
get a motor rotating. And it is doubtful any mechanical system can be
devised which is guaranteed to never jam.
A single operating point for the stalled condition can be plotted. The
location of the point is defined by several factors: 1) If the product of FIGURE 2. MOTOR REVERSAL
current limit and stall resistance is greater than maximum output
voltage swing ((Ilim*Rs)>Vomax) the amplifier output will be at maxi-
mum swing; or 2) If the product of current limit and stall resistance is 1.2 REVERSAL
less than maximum swing, then the amplifier output voltage will be at Reversal brings the back EMF of the motor into the stress equation.
the value of Ilim*Rs. To calculate dissipation, subtract this voltage from The back EMF is equivalent to a new source of voltage with a polarity
the supply voltage and multiply by current limit: Pd = (Vs-Vo)*Ilim
372
such that it adds to the supply voltage and increases voltage stress on PA05. Reason being that foldover current limiting causes more prob-
the output devices. As in the stalled condition, motor resistance also lems than it solves when used with nonlinear loads. For instance, with
plays a part. inductive loads (and motors are very inductive), the amplifier can go
Determining back EMF may seem difficult, but most motor data into relaxation oscillation. And with an inductive load, when the
sheets shed some light on determining its value. Knowing the motor amplifier goes into current limit, it generates a violent pulse all the way
resistance and current draw permits exact calculation of back EMF: it up to the supply rail (limited only by flyback diodes, without which it
is the applied voltage, less the drop across the motor resistance. Worst would go beyond the rail).
case assumption for back EMF should assume it could be equal to If a designer insists on experimenting with foldover current limiting,
applied voltage, and this would be true for any motor drawing negligible then it would be wise to plot the current limit line on the SOA along with
current. the expected load lines. If the load lines are within the current limit
The schematic in Figure 2 shows an example of what happens to the boundaries, then youre OK. Keep in mind that foldover current limiting
circuit in Figure 1 during reversalassuming the amplifier current limit slope can be varied and sometimes a gentle foldover characteristic
is set at 3 amps. Motor operating current is a function of load. So for can provide adequate protection.
this example, lets assume the motor requires 1A under normal
running conditions. Maximum output from the PA12 could be up to 2.2 FLYBACK DIODES
45V. Subtract 3.2V for the drop across the motor resistance for a back
EMF of 41.8V. Upon command to reverse the negative half goes into Brush type DC motors generate a continuous pulse train of inductive
3A current limit. The resulting voltage drop across the motor resistance kick-back due to brush commutation. This inductive kickback must be
subtracts from the back EMF, providing the values shown during the clamped within the limits set by the power supply rails by flyback
reversal. The dissipation during this event is 246Wclearly outside diodes as shown in Fig. 1.
the PA12 SOA. Motor reversal by nature is a transient condition. If it Many amplifier schematics show these diodes internally, but this
can be assured the motor can reverse within an amount of time does not mean they can be depended upon in motor drive applications.
equivalent to transient stress limits on the SOA graph, then the In most bipolar, darlington, emitter-follower output stages, these
application could be safe. diodes are the substrate diodes of the darlington output transistors.
This causes the diodes to exhibit slow recovery, which will in turn
overheat under the stress of a continuous pulse train of inductive
1.2.1 PLOTTING REVERSAL LOAD LINE kickback.
Just as stall load lines can be plotted, so can reversal load lines. The Amplifiers with no diodes, or slow recovery diodes, internally must
process of plotting a worst-case reversal load line starts with the have external fast or ultra-fast recovery diodes added. If these are not
assumption that back EMF is equal to maximum amplifier output available, then standard recovery is better than nothing. The diodes
voltage. An even worse assumption is that it is equal to the supply must be rated for voltage well in excess of the total rail-to-rail voltage.
voltage of one of the rails. Current requirements are not demanding. One amp types will suffice.
Plot the load line by: All APEX amplifiers require external flyback diodes except the
1. Calculate the drop across the motor resistance at various currents MOSFET output amplifiers PA04, PA05, PA09, PA19; and the PA02
within the SOA. and PA03 which are bipolar amplifiers with built-in high speed flyback
2. Subtract that voltage from the back EMF to result in the amplifier diodes. In general, on any APEX data sheet schematic or in the Apex
output voltage. data book, if the flyback diodes have a different part numeral than the
3. Take the resulting difference between supply rail and output as the output transistor, then they are separate fast recovery diodes. Diodes
stress point. with the same part number as the output transistor are slow recovery
Figure 1 also shows its reversal load line. This load line indicates diodes and external additions will be needed. For example in the
that it is not within the continuous SOA unless current is limited to PA12, the upper output transistor is Q2A and Q2B and the flyback
approximately less than 400mA. If this application were required to diode is D2. If youre not sure, there is no harm in adding them even
tolerate reversal, an amplifier with better SOA should probably be if they are not needed.
used.
Load lines that exceed the continuous SOA, but are within transient 3.0 AMPLIFIER PERFORMANCE
SOA, may be safe if the time conditions are met with certainty. This is D
difficult to assess, and usually requires a judgement call when any
signal other than pulse is present. In general, as in any case, life is 3.1 VOLTAGE VS CURRENT
simpler and more reliable if we at least make the effort to keep within OUTPUT BEHAVIOR
continuous SOA limits.
Voltage output configurations are generally used for speed control.
Although a voltage output configuration can be incorporated within a
1.3 NOMINAL OPERATING CONDITIONS larger current control loop. The importance of voltage output in the
Nominal operating conditions can only be determined on a by amplifier itself relates to output impedance, which will be very low. As
application basis. All motor data sheets shows torque and RPM such, the output voltage as seen on a scope will generally be quiet and
constants allowing the engineer to determine required voltage and steady under steady state conditions.
current once the load is known. The worst case normal operating point Current output can be implemented as mentioned above with a
will be when the amplifier output is halfway between zero and the larger current sense loop that incorporates a voltage output power
supply rail. amp. Alternatively, current output circuits can be implemented within
the feedback loop around the op amp alone. When this is done, the
amplifier apparently exhibits a very high output impedance. A current
2.0 AMPLIFIER PROTECTION source should do this by definition. This is mentioned because if the
AND HEATSINKING output of such a circuit is scoped, the flyback pulses will be exagger-
As has already been shown, the load lines must be within the ated by this high impedance a perfectly normal behavior for current
amplifiers capabilities or current limit must be configured to restrict output.
operation to within the SOA. However, the SOA shrinks with increasing There is no performance advantage in selecting voltage or current
temperature. Therefore, either adequate (read: generous) heatsinking output, at least not due to power op amp circuit choice alone. Many
must be provided for, or SOA analysis should consider limits of higher other factors will play a part in which choice provides the best
case temperature curves. Using standard heatsink formulae the exact performance. In general, without using larger control loops, the
amplifier case temperature can be determined under any operating voltage output configuration is preferred for speed control, and the
condition (as well as junction temperature). current output for torque control.
2.1 FOLDBACK CURRENT LIMITING

Current limit, as demonstrated, is truly a good thing and necessary.
But designers must not be lured into the attraction of using foldback
current limiting as available on PA10, PA12 and can be used on PA04,
however, FAXis(520)
ORDERS (520) 690-8601
373
DRIVING CAPACITIVE LOADS
APPLICATION NOTE 25
1.0 INTRODUCTION For capacitive load applications this formula reduces to:
High voltage power op amps are often selected to drive capacitive 4 Vs2 4 (200)2
PDOUT max = = = 17W
loads, such as PIEZO TRANSDUCERS, CAPACITORS, ELECTRO- 2 Xc 2 1.5K
LUMINESCENT DISPLAYS, ELECTROFLUORESCENT LIGHTING, STEP 5: Summarize what we know and pick power op amp.
ELECTROSTATIC DEFLECTION, etc. There are some special consid- +/-Vs = +/-200Vdc
erations when designing circuits to meet your high voltage needs. S.R. = 11.3V/s
We will look in detail at the selection of the power op amp, stability Iop = 120mAp
considerations, power dissipation in the op amp and heatsink selec- Vop = 180Vp
tion, support components for the circuit, and power supplies and their PDOUT MAX = 17W
effect on circuit performance. When we complete these areas of In viewing the APEX High Voltage Selector Guide there is
investigation we will look at some alternative power op amp circuits for only one likely candidate for this designPA85.
attaining high voltage control across capacitive loads. STEP 6: Review the chosen amplifiers data sheets for details.
The format of our information will be definition by example along Figure 1: Contains relevant excerpts from the PA85 data
with generic formulae for your specific design. sheet.
Figure 1A: From the output specifications, a worst case
2.0 EXAMPLE DESIGN FOR DRIVING saturation voltage of 10V at 200mA is identified. Therefore
A CAPACITIVE LOAD we can meet 180Vp out at 120mAp without a problem.
GIVEN: +/-Vs= +/-200Vdc Figure 1B: From the power response curve we see 360Vpp
frequency = DC to 10KHz (sinewave) at 10KHz is within the power response curve for any value
VIN = +/-10V of Cc (PA85 compensation capacitor).
piezo load with CL = 10.6nF Figure 1C: Since we want 180Vp out for 10Vp in we will be
VOUT = 360Vpp operating at a gain of 18. This is close enough to 20 to
Tambient = 25C, free air convection cooling only choose Cc = 10pF and Rc = 330. This will maximize small
Inverting gain okay signal bandwidth as well as slew rate should a last minute
decision require more performance out of the design.
FIND: Power op amp, heatsink and recommended schematic Figure 1D: At Cc =10pF the slew rate is about 400V/s, so
for piezo drive. there is no question about meeting the requirement for an
SOLUTION: Sections 2.1 thru 2.6 will provide a detailed, logical 11.3V/s slew rate.
approach to designing a solution for this capacitive Figure 1E: At a closed loop gain of 18, (25 dB), it can be
load drive problem. determined that for Cc =10pF the closed loop bandwidth of
this circuit (fcl) is about 2MHz. This first check says not only
can a 10KHz sinewave be tracked in the large signal
2.1 POWER OP AMP SELECTION domain, but the PA85 will also have enough bandwidth to
STEP 1: Define capacitive load. Here we are given CL = 10.6nF have a flat response at 10KHz in the small signal domain.
STEP 2: Calculate large signal response (slew rate) using highest Figure 1F: From our previous calculation PDOUT MAX = 17W.
frequency and largest voltage swing. The required slew rate An Applications Engineers rule of thumb for power derating
to track a sinewave at a given frequency for a given output curves works as follows:
amplitude is as follows: For a 25C ambient temperature you can find a heatsink
S.R. = 2 f Vop (1 X 106) that will allow you to keep the case temperature at 85C
Slew Rate [V/s] = 2 X X frequency X VOUT peak X (1 X 106) using free air convection cooling.
S.R. = 2 10KHz 180 (1 X 106) = 11.3V/s Therefore, 17W output power dissipation almost intersects
STEP 3: Calculate maximum current requirements. This will occur at with the Tc = 85C line on the power derating curve. This
highest frequency with capacitive loads. means our first look says we should be able to heatsink the
PA85 for this design.
METHOD 1: Calculate Xc @ highest frequency. Now it would seem the work is done and you can proceed to build
1 a breadboard or commit to printed circuit board layout. But first you
Xc =
2 f CL must proceed to look at other key issues for driving capacitive loads
1 with power op amps such as stability.
Xc = = 1.5K
2 10 KHz 10.6nF
Vop 180V
2.2 SMALL SIGNAL STABILITY
Iop = = = 120mAp Figure 2 (see second page following this one) is a complete
Xc 1.5K
schematic of our PA85 drive circuit. The gain of -18 will give us 360Vpp
METHOD 2: Use highest slew rate and largest voltage swing. out for 20Vpp in. We will now look at the details for selecting stability
dV components Rn, Cn, and CF.
Iop = CL
dt
11.3V 2.2.1 MODIFIED Aol FOR CAPACITIVE LOADS
Iop = 10.6nF = 120mAp Figure 3 (see second page following this one) illustrates how the
s
amplifiers Aol curve gets modified by Ro, the amplifiers unloaded
STEP 4: Do a first pass worst case power dissipation calculation. For output impedance, and CL, the capacitive load. Output impedance,
details on derivation of this formula see General Operating Ro, of the amplifier, is flat within the bandwidth of the amplifier and
Considerations. predominantly resistive. Refer to Apex Application Note 19 for a
detailed discussion of this issue.
Vs2
PDOUT max =
2 ZL
[ 4 cos ] Figure 4 (see second page following this one) lists high voltage Apex
amplifiers and boosters most commonly used to drive capacitive loads
and their corresponding output impedance.
374
FIGURE 1A OUTPUT MIN TYP MAX
VOLTAGE SWING IO = 200mA Vs 10 Vs 6.5 V
VOLTAGE SWING IO = 75mA Vs 8.5 Vs 6.0 V
VOLTAGE SWING IO= 20mA Vs 7.5 Vs 5.5 V
CURRENT, continuous TC= 85C 200 mA
SLEW RATE, AV = 20 CC= 10pf 400 V/s
SLEW RATE, AV = 100 CC= OPEN 1000 V/s
CAPACITIVE LOAD, AV = +1 Full Temperature Range 470 pf
SETTLING TIME to .1% CC= 10pf, 2V step 1 s
RESISTANCE, no load RCL= 0 50
FIGURE 1B FIGURE 1E
POWER RESPONSE SMALL SIGNAL RESPONSE

500 120
100
CC= 3.3pf

250
CC
80
=3
.3 p
CC
60
=1
125
0p
100 CC= 10pf

CC
40
=6
75 AVCL
8p
fcl
20
f
50
CC= 68pf
0
R L = 2K
25 20
50K 100K 200K 500K 1M 2M 5M 10 100 1K 10K .1M 1M 10M 100M
FREQUENCY, F (Hz) FREQUENCY, F (Hz)
FIGURE 1C RCL
+Vs CL
3 2 PHASE COMPENSATION
+IN 4 1 OUT Gain CC RC
EXTERNAL TOP VIEW 1 68pf 100
CONNECTIONS COMP 20 10pf 330
IN
5 8 100 3.3pf 0 D
6 7 CC
Vs COMP CC RATED FOR FULL SUPPLY VOLTAGE
RC
FIGURE 1D FIGURE 1F
SLEW RATE POWER DERATING
1000 40
32
SLEW RATE, (V/S)
500
OUTPUT STAGE
24
16
200
8
100 0
0 15 30 45 60 75 90 0 25 50 75 100 125 150
EXT. COMPENSATION CAPACITOR, C C (pf) CASE TEMPERATURE, TC (C)
FIGURE 1. PA85 DATA SHEET EXCERPTS
375
RF OP AMP OR BOOSTER OUTPUT IMPEDANCE
PA41 150 ohms
CF 90K, 1/2W PA81J 1.4K-1.8K ohms
PA82J 1.4K-1.8K ohms
18pF +200V +200V PA83 1.4K-1.8Kohms
.1F 4.7F PA84 1.4K-1.8K ohms
P6KE250
+ PA85 50 ohms
PA88 100 ohms
RCL PA89 100 ohms
RI * PB50 35 ohms
5K 4.64 VOUT PB58 35 ohms
PA85
1N4148's
VIN DC to FIGURE 4. OUTPUT IMPEDANCE
10V 10KHz
4.7F HIGH VOLTAGE OP AMPS AND BOOSTERS
Cc Rc * CL
+ 10pF 330 10.6nF
Rn 2.2.2 STABILITY PLOTS
900
Figure 5 illustrates the magnitude plot for stability needed to analyze
Cn .1F
.018F and check for good stability on our PA85 drive circuit. The low
P6KE250 frequency pole for the Aol curve can be determined from the Small
200V
200V Signal Response curve, and the high frequency pole can be extrapo-
*INTERNAL TO PA85
lated from the Phase Response curve in the APEX data sheet for the
PA85.
FIGURE 2. PA85 PIEZO TRANSDUCER DRIVE
220
RF 200
180
160
RI
GAIN (dB)
140
Ro 120 PA85 Aol w/Cc = 10pF, Rc = 330
100 fp1
CL 80
1/ RF/Rn
60
1/ RF/RI fp5 fp6 fp2
40 fz1
UNITY GAIN STABLE AMPLIFIER 25.6 fp3
20 VO / VIN
UNSTABLE 40 dB/DECADE WITH CL fz2
0
.1 1 10 100 1K10K 100K 1M 10M 100M
275K fcl fp4
SMALL SIGNAL RESPONSE FREQUENCY, F (Hz)
120 MODIFIED Aol DUE TO CL = 10.6nF & Ro = 50
FIGURE 5. MAGNITUDE PLOT FOR STABILITY
100 (PA85 PIEZO TRANSDUCER DRIVE)
STEP 1: Modify Aol due to capacitive load and amplifiers output

80 impedance:
1 1
fp2 = = = 275 KHz
60 2 (Ro + RCL) CL 2 (50+ 4.64) 10.6nF
fp4 = 10MHz pole from amplifier's original Aol plot (fp3)

40
UNSTABLE STABLE
STEP 2: Check 1/ for resistive feedback alone:
1/ [1/(beta)] is the small signal AC gain at which the op amp
20
runs. Refer to Apex Application Note 19 for details. First
order stability criteria for magnitude plots states that the
0 Rate-of-Closure (difference between the slopes of Modified
Aol and the 1/ plot) be 20dB per decade at fcl. Refer to Apex
Application Note 19 for details on Rate-of-Closure. With AC
100 small signal gain set only by RF and RI the 1/ plot will be
1 10 100 1K 10K .1M 1M 10M a flat line at 25.6dB. At the intersection of modified Aol and
FREQUENCY, F (Hz) 25.6dB the Rate-of-Closure will be 40 dB per decade
indicating marginal stability and potentially destructive os-
Aol 1/ cillations.
Aol w/CL AVCL STEP 3: Add Noise Gain Compensation as a first step towards good
stability:
FIGURE 3. CAPACITIVE LOADING Rn and Cn will form a noise gain compensation network
which will raise the gain of the 1/ plot without directly
affecting the VOUT/VIN relationship. Refer to Apex Application
Note 19 for details.
Noise Gain equations:
High frequency gain = RF/Rn = 90K/900 = 100 ==> 40dB
1 1
fp5 = = = 9.8 KHz
2 Rn Cn 2 900 .018F
376
fz1 ==> Can be obtained graphically using +20dB per decade slope, extending this line with 0 degree and 90
decade slope starting at the intersection of fp5 and the high degree horizontal lines. Refer to Apex Application Note
frequency gain of the noise gain compensation and pro- 19 for further details.
ceeding towards the DC gain. STEP 6: Plot open loop phase using information from magnitude plot:
Even though we have raised the higher frequency portion Figure 6 is the open loop phase plot for our PA85 drive
of the 1/ curve to 40dB, it will still intersect the modified Aol circuit.
at 40dB per decade Rate-of-Closure. Notice in Figure 5 that the 1/ plot continues beyond fcl all the way
STEP 4: Add feedback zero (1/ pole) to 1/ plot to gain best AC until it intersects at 0dB forming fz2 in the 1/ plot. An amplifier will not
small signal stability (Refer to Apex Application Note 19 for run in an AC small signal gain of less than 0dB. You must account for
details): an additional high frequency pole in the open loop phase check. This
pole is easily read graphically from Figure 5 rather than calculating it
1 1 from lengthy derivations.
fp6 = = = 98 KHz
2 RF CF 2 90k 18pF A review of Figure 6 shows graphical addition of the contributions
from all poles and zeros to yield a net open loop phase plot. The phase
Now at fcl, you have the desired 20dB per decade Rate-of- margin from DC to fcl is never less than 45 degrees which implies good
Closure and good stability according to our first order criteria stability for this circuit.
for magnitude plots. You will now need to plot the open loop
phase plot for a complete stability check. 2.2.2.1 RULES OF THUMB FOR STABILITY PLOTS
STEP 5: Review of rules for open loop phase plots:
1) Poles in the 1/ plot become zeros in the open loop Now that we know we have good stability, lets return to the
stability check. magnitude plot in Figure 5 for a few handy rules of thumb:
2) Zeros in the 1/ plot become poles in the open loop 1) Think of open loop phase when you play with the 1/ plot: Notice
stability check. that fp1 (pole in open loop) is spaced about a decade away from
3) Poles and zeros in the Aol curve or modified Aol curve fz1 (pole in open loop). If you dont add fp5 (zero in open loop)
of the op amp remain respectively poles and zeros in the within a decade of fz1, (pole in open loop) the open loop phase
open loop stability check since the op amp Aol curve is margin will dip to less than 45 degrees.
an open loop curve already. 2) As you run out of loop gain (difference between Aol curve and 1/
4) Phase for zeros is represented by a +45 degree phase plot), keep poles and zeros one-half to one decade away from
shift at the frequency of the zero with +45 degree per zero loop gain. Notice that fp6 is about one-half decade away
decade slope, extending this line with 0 degree and +90 from the modified Aol curve near fp2. This allows Real World Aol
degree horizontal lines. curves and component tolerances to stack against you without
5) Phase for poles is represented by a 45 degree phase creating stability nightmares.
shift at the frequency of the pole with a 45 degree per
+180
+135
+90
fp5 fp6
+45
0
fz1 fp2 fz2
45
fp1 fp4
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
D
+180
+135
+90
+45
0
45
90
135
MARGIN = 45 fcl
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY, F (Hz)
FIGURE 6. OPEN LOOP PHASE CHECK FOR STABILITY

(PA85 PIEZO TRANSDUCER DRIVE)
377
3) Always design your circuits, using these stability techniques, for Figure 7 details the Square Wave Test for measuring open loop
45 degrees of phase margin in the open loop phase check for phase margin by closed loop testing. The output amplitude of the
stability. This is because the first order linear approximations for square wave is adjusted to be 2Vpp at a frequency of 1 KHz. The key
phase have a six degree error. As well, there is no guarantee you elements of this test are to use low amplitude (AC small signal) and a
will consistently receive op amps with the typical Aol graph. frequency that will allow ease of reading when triggered on an
In a typical design procedure, you will plot magnitude plots for oscilloscope. Amplitude adjustment on the oscilloscope wants to
stability first, do an open loop phase plot, and then return to calculate accentuate the top of the square wave to measure easily the overshoot
final component values to create the desired magnitude plot that yields and ringing. The results of the test can then be compared to the graph
45 degrees open loop phase margin for stability. in Figure 7 to yield a reading for open loop phase margin.
Refer to Apex Application Note 19 for handy tips and short cuts for A complete use of this test is to run the output symmetrical about
plotting magnitude and phase plots. zero with +/-1V peak and then re-run the test with various DC offsets
on the output above and below zero. This will check stability at several
2.2.3 REAL WORLD STABILITY TEST operating points to ensure no anomalies show up in field use.
Refer to Apex Application Note 19 for more involved closed loop
Once a circuit is built, there is a relatively easy test you can run to tests for measuring open loop phase margin and checking real world
verify if the predicted open loop phase margin made it from design to stability.
the real world.
2.3 CLOSED LOOP RESPONSE
CF From Figure 5 the VOUT/VIN relationship for our PA85 circuit is seen
as flat from DC to 100 KHz, where it begins to roll at 20dB per decade.
It continues until we reach 1.33 MHz where it rolls off at 40dB per
RI
decade until reaching 10MHz, where our slope changes to 60dB per
RF
decade.
VOUT
The VOUT/VIN phase shift for any given frequency is given by the
2vpp following:
f f f
LOAD Phase Shift = Tan1 Tan1 Tan1
fp6 fcl fp4
where f = frequency of interest for phase shift
For our upper frequency of interest of 10 KHz lets see what the VOUT/
VIN 1KHz VIN phase shift is:
10 KHz 10 KHz
1.6 Phase Shift = Tan1 Tan1
100 KHz 1.33MHz
10 KHz
Tan1 = 6.2 degrees
10MHz
1.4
13 0.2* The formula above can be expanded to include any number of
poles. If the VOUT/VIN relationship has zeros simply add the following for
each zero:
f
1.2 +Tan 1 ; where fz is the frequency of the zero
fz
35 0.4*
VO, RELATIVE OUTPUT TO A STEP FUNCTION INPUT
40 0.6* 2.4 POWER DISSIPATION AND HEATSINKING

1.0 Power dissipation inside the amplifier consists of two components,
PDQ, quiescent power dissipation, and PDOUT, output stage power
dissipation. Simply compute PDQ = Iq[+Vs - (-Vs)] and add the worst
case power dissipation for the output stage to this to form PDINT, total
internal power dissipation. Figure 8 shows the Thermo-Electric Model
0.8 that is applicable for this situation.
TJ
52 0.8* RJC
0.6 PDINT TC
TJ = PDINT(RJC + RCS + RSA) +TA
RCS
64 1.0* TS
77 1.2* RSA
0.4 TA
90 1.4*
FIGURE 8. THERMOELECTRIC MODEL

0.2
In our PA85 design case we have AC power dissipation in the output
stage. From Section 2.1, Step 4, that power dissipation is:
0 4 Vs2 4 (200)2
0 1 2 3 4 5 6 7 8 9 10 PDOUT max = = = 17W
nt
2 Xc 2 1.5K
Quiescent power is:
* OPEN LOOP PHASE MARGIN AND DAMPING FACTOR
PDQ = Iq [+Vs (Vs)] = 25mA [+200 (200)] = 10W
FIGURE 7. SQUARE WAVE TEST
378
There are two thermal requirements we must meet in this applica- 2.5 HIGH VOLTAGE AMPLIFIER
tion. First, the case temperature must be kept below 85C. Second, the
junction temperature must be kept below 150C. We know the appli- SUPPORT COMPONENTS
cation is dissipating a total of 27W, but the data sheet contains three High voltage op amps require some special considerations when
different thermal resistance ratings which vary substantially. The first selecting support components for completion of your circuit design.
is an AC rating where the two output transistors share the heat load at The following list covers these critical areas of concern:
a frequency of 60Hz or greater. When the power is dissipated in mainly
one output transistor, use the DC thermal resistance. The last rating RFeq
is applied only if no heatsink is used.
This is a rare practice with power op amps. Let us briefly pursue the RF1 RF2 RF3
possibility we might be able to not heatsink the amplifier in this
application. Figure 9 models this case. TO-3 packages are rated at CF
30C/W. When the case of the amplifier must be kept below 85C, this +600V
imposes a maximum power dissipation of 2W even with an ideal
RI CBP +600V
ambient temperature of 25C. At 27W our PA85 would burn up very
quickly without a heatsink.
VIN VTR
RCL
Dp Dp DFB
1N4148
or
1N914 Dp Dp PA89 VO
R JA
OR DFB
Rc Cc
CBP
2N4416 600V
or VTR
2N5457
600V
FIGURE 9. THERMOELECTRIC MODEL (NO HEATSINK) FIGURE 10. HIGH VOLTAGE SUPPORT COMPONENTS
1) ESD Handling Precautions:

All APEX high voltage amplifiers are rated Class 1 for ESD
The PA85 data sheet tells us the AC thermal resistance is 2.5C/W. sensitivity, as defined in MIL-H-38534. This requires that proper
We will allow 0.2C/W for RCS and use the following to determine a ESD handling precautions be observed from receiving through
maximum heatsink rating. manufacturing until the device is installed in a properly designed
circuit. Areas which will require strict ESD control include, but are
TJ TA not limited to, personnel, tabletops, stocking containers, floors,
RSA RJCRCS soldering irons, and test equipment.
PDINT(max) 2) Input Protection (Refer to Figure 10):
Most high voltage amplifiers have a differential input voltage
(15025)C rating of +/-25V. It is easier on high voltage amplifiers to cause
2.5C/W0.2C/W differential input overvoltages than on lower voltage op amps.
27W These overvoltages on the input can occur during power cycling or
can be transients fed back through CF from the output to the input. D
RSA 1.9C/W The input diodes, Dp, clamp the maximum input differential
voltage to +/-1.4V while allowing sufficient differential voltage for
Select APEX HS03; RSA = 1.7C/W with forced air flow at 100 ft/min. overdrive when demanding maximum slew rate from the amplifier.
The diodes shown are low capacitance fast signal diodes. If lower
As a last check, multiply the total power times the sum of the thermal leakage and lower capacitance diodes are desired, J-FETs may be
resistance of the heatsink and the mounting interface and add to connected as diodes as shown.
ambient temperature to verify the case temperature does not exceed 3) Output Diodes (Refer to Figure 10):
85C. MOSFET high voltage amplifiers have internal, intrinsic diodes
27W * (1.7C/W + 0.2C/W) + 25C = 76.3C that are connected from the output to each supply rail. High voltage
Bipolar amplifiers do not have these diodes and must be added
externally as shown. The MOSFET amplifiers internal diodes are
Refer to Package and Accessories Information section of sufficient for an occasional transient that may be created in a piezo
APEX Amplifier Handbook.See APEX catalog GENERAL OPERAT- drive situation where the piezo element is stressed mechanically,
ING CONSIDERATIONS for details on heatsinking and mounting the thereby creating an electrical voltage. For applications where there
amplifier. is potential for sustained high energy flyback, in ATE applications,
where everything that is not supposed to happen usually can and
does, or in applications where Kilovolt flashovers can occur and be
inmpressed onto the amplifiers output, it is recommended to use
fast (500nS or less depending upon the anticipated flyback energy
frequency) reverse recovery diodes, DFB, external to the amplifier.
Remember to size the diodes for a Peak Reverse Voltage rating of
at least the rail to rail supplies the amplifier is operating at (for Vs=+/
200V ==> 400V Peak Reverse Voltage rated diode).
4) Transient Voltage Suppressors (See Figure 10):
Transient Voltage Suppressors, VTR, can be added to the supply
lines to provide protection from undesired transients on the power
supply line. The first is power supply overvoltage on power cycling.
Secondly, when energy is dumped into the supplies from DFB, if the
power supply terminals at the amplifier do not look like a low
impedance for the frequency of that energy, the amplifier could
379
become overvoltaged. Transient suppressors, such as planes and other conductive layers. Mil-Std-275 provides some
TRANSZORBS, manufactured by General Semiconductor Indus- guidelines in these areas.
tries, Inc, will provide a low impedance path for this energy. If you 10) Probing, Plugging and Powering:
use unipolar transient suppressors, they will prevent polarity rever- Be extremely careful when probing a high voltage amplifier with
sal across the amplifier since they will become a forward biased the power on. An inadvertent slip of a probe can destroy a high
diode if supplies are reversed. voltage amplifier. There are often compensation pins adjacent to
Selection of the transient suppressors may require a series string power supply pins. Those compensation pins are often connected
of devices to reach the desired reverse stand-off voltage rating for to the gates of MOSFETs which do not take kindly to the full power
higher voltage op amps. Choose the transient suppressor for a supply being impressed upon them.
reverse stand-off voltage slightly greater than the maximum DC or Do not plug or unplug an amplifier into a live, powered socket.
continuous peak operating voltage level. This selected device will The transients generated can destroy the high voltage amplifier.
then have an actual breakdown voltage that is typically 1.1 to 1.36 Do not use fuses in the power supply lines of high voltage
times higher. For example, a P6KE250 has a reverse stand-off amplifiers or ever power them with one supply disconnected and no
voltage of 202V with a breakdown voltage of 225V to 275V. Herein path to ground for that disconnected power supply. This can lead
lies the trade-offs of transient suppressors. They are excellent to a sneak path for permanent destruction on several of the high
devices with a sharp breakdown curve and can dissipate large voltage amplifiers.
amounts of power for short periods of time. The problem is the exact
breakdown voltage is not a tightly controlled parameter for any
given model. PA85
A typical design dilemma is the case where an engineer desires POWER SUPPLY REJECTION
to use a part at its full power supply rating and still provide transient 140
voltage protection on the supply lines. Now you ask, how high is
APEXs Absolute Maximum Rating for Supply Voltage, REALLY?
Well, the guaranteed Absolute Maximum Rating for Supply Voltage 120

is exactly what our vendors guarantee to us. Lawyers aside, it is
known in the electronics industry that a 400V transistor may
actually breakdown at 500V from a given lot. In a nutshell, you are
in no-mans land above the Absolute Maximum Rating; however, it 100
is much better to limit the transient voltages to as low as possible 94.5
than to not limit at all!
5) Power Supply Bypassing (See Figure 10):
The rule of thumb is .1F ceramics directly at the op amp with 80
10F/Ampere of peak output current in parallel within 2 inches or
so of each amplifier. Many of the high voltage amplifiers are less
than 200mA and the .1F ceramic is all that will be needed. In cases 60
of PA89, +/600V supplies, .01F seems to be more readily avail-
able and this is adequate for high frequency bypassing on the
power supply line. Watch the voltage ratings for these capacitors!
6) Compensation Capacitor and Resistor (See Figure 10): 40
Cc must be rated for the rail-to-rail supply voltage at which the
amplifier is operating. In this case a 1200V rating. It is recom-
mended that the compensation capacitor be a temperature stable
20
capacitor for reliable performance over temperature. Mepco / 1 10 100 120 1K 10K .1M 1M
Centralab, Inc, series D and S type capacitors are available in
FREQUENCY, F (Hz)
50Vdc through 6KVdc ratings in various temperature characteris-
tics. FIGURE 11. PA85 PSR
Rc will normally see little or no voltage since most of the voltage
stresses will be across Cc. Rc then can be a standard 1/8W metal
film resistor. 2.6 POWER SUPPLIES
7) Feedback and Input Components (See Figure 10):
RI will generally have little voltage stress or power dissipation 2.6.1 POWER SUPPLY REJECTION
since most input signals are less than 10 volts peak. Standard metal
film resistors will work fine. Often times high voltage amplifiers require the use of either a
CF can have up to one supply impressed across it. In this case switching power supply or a simple AC full-wave bridge rectified supply
it would need to be a 600Vdc minimum rated capacitor. (make real sure you use transient suppressors if you use this type of
RF1, RF2, and RF3 will need some special considerations. supply). The question then is asked what will be the effect on the output
Power dissipation will become of prime importance since up to one of the amplifier due to the ripple of the power supply?
of the supply rails can be impressed across these resistors at a Figure 11 is the Power Supply Rejection curve for the PA85. We will
given time. This could yield power dissipations of: PD = Vs2 / RFeq. use this and our familiar circuit of Figure 2 to understand power supply
The second consideration is voltage coefficient of resistance. This ripple effect on amplifier output. Figure 11 is a referred-to-input
is a parameter that defines how a resistor changes its resistance specification. Lets assume there is a 1Vpp, 120Hz ripple on the power
with applied voltage. At low voltages this characteristic is not a supply line. From Figure 11 this implies PSR of 94.5dB. Since this is
dominant factor. At higher voltages it can become a more signifi- a rejection curve, the gain is actually -94.5dB which is a gain of
cant factor causing reductions in gain for a given resistor ratio or .000018836. This gain times 1Vpp on the power supply line means you
increased distortion. Dale RNX, ROX, FHV, MVW, and HVX series will see .018836mVpp appear as an input offset voltage in the circuit.
resistors are well characterized for high voltage use. The power At a gain of 19 this means our output will see .358mVpp ripple at 120Hz
dissipation factors and voltage coefficient of resistance may re- due to power supply fluctuations.
quire several resistors to be used in series in the feedback path of
the op amp. 2.6.2 HIGH VOLTAGELOW COST
8) Current Limit Resistor (See Figure 10):
Remember that all the load current flows through the current limit POWER SUPPLIES
resistor, RCL, and therefore size it according to the value of current APEX is often asked about low cost high voltage supplies for high
limit, Ilim, by PD = (Ilim2)(RCL). Maximum voltage stress across RCL voltage amplifiers. One manufacturer of such supplies is International
will be about +/-.7V for most amplifiers. Check the Current Limit Power. These supplies are AC line input voltages, programmable for
section of the applicable data sheet for exceptions to this. 120Vrms or 240Vrms, 50Hz or 60Hz. They are single output, isolated
9) PWB Layout: linear supplies. Since they are isolated, two separate supplies can be
Higher voltages will require wider spacings between traces on a
printed circuit board layout as well as spacings between ground
380
wired to yield +/-Vs for high voltage amplifiers. For higher voltages from 40 dB/decade to 20 dB/decade for at least a decade
such as 400V, two IHB200-0.12 can be wired in series. These supplies above AVCL and within a decade of fp1.
sell for around $50 U.S. in small quantities. The following is a list of the STEP 3: Calculate final value for RISO: Calculate from formula for fz
available models and vendor information. There are also other ven- in Figure 12A the value for RISO from fz location in Figure 13.
dors in the industry with similar models. Recalculate final value for fp and plot final modified Aol
ensuring final location of fz meets criteria in STEP 2.
VENDOR: International Power Phone: 805-987-7900 One disadvantage with the use of RISO is that the point of
360 Bernoulli Circle FAX: 805-981-1184 feedback is not directly at the capacitive load. This means
Oxnard, Ca 93030-5167 that accurate control of the voltage at CL is not obtained.
Model Voltage Current This is usually not a problem since most piezo drives are
IHB155-0.12 135V-170V 0.12A used inside of an outer control loop such as position
IHB200-0.12 175V-210V 0.12A feedback into a microprocessor which will then generate an
IHB250-0.1 215V-265V 0.1A error command to the input of the PB58 piezo drive circuit.
The major advantage of RISO is that a wide range of capaci-
CAUTION: Before powering APEX high voltage amplifiers with these
supplies contact APEX Applications Engineering for power supply set- 240
up to prevent overvoltages during power cycling!
220
200
3.0 HIGH VOLTAGE AMPLIFIER VARIATIONS 1 MODIFIED Aol w/CL = 26f, RO = 35
180 2 MODIFIED Aol w/CL = 26f, RISO = 5, RO = 35
3.1 RESISTOR ISOLATION FOR CAPACITIVE LOADS 160
GAIN (dB)
In Section 2.2.2 one method for stabilizing capacitive loads was 140
120
100
PB58 Aol fp
80
75
RISO 60 fp1
RO fz
40
VO fcl2
RG 20
CL PB58 AVCL fcl1 1 2
0
.1 1 10 100 1K 10K
100K 1M 10M 100M
153 fp2
FREQUENCY, F (Hz) fp3
1 1
fp = fz =
2 CL (RO + RISO) 2 RISO CL FIGURE 13. RISO & CAPACITIVE LOAD EFFECTS
FIGURE 12A: RISO & CL tive loads can now be driven with good stability.
discussed. There is another common way to isolate capacitive loads
and thereby acquire good stability. 3.1.1 PB58 PIEZO DRIVE WITH RISO
Figure 12A illustrates a technique for isolating the capacitive load
through the use of RISO. This isolates the point of feedback, where RG Figure 16 (see next page) is a piezo drive amplifier using the PB58
is connected, from the capacitive load. The addition of RISO adds a zero and our RISO technique for capacitive load stability.
in the modified Aol plot to counteract the pole formed by Ro and CL. The design goal for this amplifier was to have an adjustable DC
offset and still allow an AC input signal to swing about the DC offset.
+130V
240
D
220
RCL 200
.3 2W RISO 180
PB58
5 160
GAIN (dB)
RG CL 140
COMPOSITE Aol
21.5K 26F
120
100 LF355 Aol
30V Cc 80
5pF
60
FIGURE 12B: PB58 w/ RISO & CL 40 PB58 AVCL
20
Figure 12A also contains the equations for the modified Aol curve
defining fp and fz. 0
.1 1 10 100 1K 10K 100K 1M 10M 100M
Figure 12B will be part of a real world design for a PIEZO DRIVE
FREQUENCY, F (Hz)
CIRCUIT. Here a PB58 will be required to drive a 26F capacitive load.
Figure 13 illustrates the modified Aol curve with and without the use of FIGURE 17. CREATION OF COMPOSITE Aol
Riso. From Figure 14 (see next page) we see 28 degrees of phase
margin without RISO. However, in Figure 15 (see second page following Amplifier A1 AC couples VIN and offsets it around the selected DC
this one) we have 90 degrees of phase margin through the use of RISO. offset set by RADJ.
The stability of the PB58 composite amplifier begins with first
STEPS FOR CALCULATING RISO (refer to Figure 13): ensuring the PB58 itself is stable. This is accomplished with the use of
RISO in Section 3.1 and Figure 13. Figure 17 creates the composite Aol
STEP 1: Calculate initial fp: Use Ro and CL which are given by virtue
by adding the closed loop voltage gain of the PB58 to the open loop
of the load for the application and the choice of power op
gain of the LF355 front end amplifier. For details on stabilizing
amp. Plot location of fp.
STEP 2: Graphically choose fz: From plot of fp and fp1 you can see
a 40 dB/decade slope heading towards 0 dB gain. Choose
fz at a location such that it will change slope of modified Aol
381
+180
+135
+90
+45
0
fp1 fp3
45
fp fp2
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135 fcl1 MARGIN = 0
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY, F (Hz)
FIGURE 14. OPEN LOOP PHASE PLOT FOR STABILITY

CURVE 1 (w/o RISO)
100K 100K
+15V +15V +130V 1/4W

22F .1F
.1F .1F
1N4148's 56pF
+
1N6301
15F 7
100K
7 MUR120
2 6 10K RCL
LF355
3 A1 2 3
LF355 4 VOUT RISO
VIN 10K 1K 3 A2 2 .3 2W 5
4 .1F PB58
A3 20W
4 .1F 7 21.5k
5 8
6 MUR120 CL
5600pF RG 1/2W
26F
CC 5pF
OFFSET 15V 1N6286
15V 15V 22F .1F
100K
RADJ
.1F +
30V
FIGURE 16. PB58 PIEZO DRIVE w/RISO
382
+180
+135
+90
fz1
+45
0
fp1 fp3
45
fp fp2
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135 MARGIN = 90
fcl
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY, F (Hz)
FIGURE 15. OPEN LOOP PHASE PLOT FOR STABILITY

CURVE 2 (w/RISO)
240
220 D
240 200
180
220
160
200 VOUT/VIN FOR CL = 26f
GAIN (dB)
1
140
180 2 VOUT/VIN FOR CL = 10f
120 3 VOUT/VIN FOR CL = 3f
160
GAIN (dB)
100
140
COMPOSITE Aol 80
120
60
100
40
80 1 2 3 VOUT/VIN
20
60
0
40 .1 1 10 100 1K 10K 100K 1M 10M 100M
fcl
20 1.22K 3.I8K
VOUT /VIN 1/
0 FREQUENCY, F (Hz)
.1 1 10 100 1K 10K 100K 1M 10M 100M
29.4K FIGURE 20. VOUT/VIN FOR VARIOUS CL
FREQUENCY, F (Hz)
loads. Figure 20 shows the VOUT/VIN which is at the output of the
FIGURE 18. COMPOSITE MAGNITUDE PLOT FOR STABILITY amplifier. Curves 1 thru 3 show the effect of the additional VOUT/VIN pole
formed by RISO and CL. As the capacitive load is decreased its possible
to gain a wider bandwidth since the additional pole due to RISO and CL
composite amplifiers, refer to APEX Application Note 19. Figure 18 is moving out higher in frequency.
(see second page following this one) illustrates the 1/ plot selected for So far the small signal response for this amplifier has been exam-
good stability. Note the VOUT/VIN relationship which will be discussed ined. The large signal response has two limitations. The first is slew
later. Figure 19 (see second page following this one) verifies good rate. The slew rate for the composite is limited to slew rate of the front
stability through the open loop phase plot. end times the booster gain. In this case S.R. = 5V/S X 10 = 50V/S.
Since output voltage across CL is not controlled directly, it is of The upper frequency of a sinewave we can track is a 120Vpp sinewave
interest to see how the VOUT/VIN relationship changes with capacitive of 133KHz from S.R.=2 f VOP. This is not a limiting factor for this circuit
383
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
MARGIN = 45
180
.1 1 10 100 1K 10K 100K fcl 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY, F (Hz)
FIGURE 19. COMPOSITE OPEN LOOP PHASE PLOT FOR STABILITY
since the small signal bandwidth begins to roll off at 28.4 KHz for 3.2 CAPACITIVE LOADS AND GAIN SWITCHING
VOUT/VIN (refer to Figure 20). The second large signal limitation is
current drive capability. As the capacitive load is increased, the Often times in an end product or test system a customer desires
impedance is lowered as the frequency increases. This translates to control over the gain setting for the amplifier. With any load this raises
higher currents. some important questions. Capacitive loads only complicate matters
The following is lab data taken on the circuit of Figure 16 for power somewhat.
response: Figure 21(see next page) shows a bridge circuit for driving piezo
POWER RESPONSE (Ilim = 1.3A) transducers. The bridge circuit allows up to twice the peak voltage
across the load than driving the load ground referenced. This is
CL = 10F f VOUT because as A1 goes towards +120V, A2 drives towards -120V yielding
400Hz 100Vpp up to twice the peak voltage across the load. Correspondingly, the
700Hz 50Vpp bridge circuit also doubles the voltage slew rate across the load for the
4KHz 10Vpp same reason. Forcing the master amplifier, A1, to current limit first,
equally distributes SOA stresses between A1 and A2 in case of a
CL = 22F f VOUT shorted load.
A range of loads was defined for this amplifier as shown in Figure
200Hz 100Vpp 21. The key to successfully changing the gains in this circuit is to
400Hz 50Vpp change the noise gain compensation components as the input resistor
2KHz 10Vpp is changed to select the desired gain setting. It is HIGHLY RECOM-
MENDED NOT to switch in different values of Cc around the PA88
Of equal interest is the power supply rejection for this composite amplifier A1 as gains are changed. There are MOSFET gates that are
since the choice of front end amplifier will change this number to some connected to the compensation pins that could be destroyed with
degree. The following lab data for the circuit of Figure 16 illustrates the compensation capacitor switching. It is also critical for stability that Cc
PSR for the positive supply. be located directly at the amplifier which does not yield itself easily to
POSITIVE POWER SUPPLY REJECTION switching. Figure 22 (see second page following this one) illustrates
(DC set for +Vs = +110V, AC set for 2Vpp Ripple) the 1/ plots for stability for all selectable gain settings. Notice that the
stability technique applied here uses both noise gain compensation on
f VOUT Ripple Attenuation Referred to input PSR the input along with the feedback zero to maximize phase margin for
stability. The modified Aol curves are shown for CL =.06F and
1KHz 30mVpp .015 .0015 56.5db CL =.03F. Output impedance for the PA88 of 100 ohms was used.
10KHz 290mVpp .145 .0145 36.8db Figures 23,(see next page) 24,(see second page following this one)
100KHz 420mVpp .210 .0210 33.6db and 25 (see third page following this one) prove through open loop
phase plots that good stability is guaranteed. Open loop phase plot for
384
RIM
4.4K 100K 100K

RFM RIS
CFM +120V +120V
10K
+120V
100K
4.22K 15pF +120V * .1F
RFS
1500pF .1F **
+ CFS
20K
4.7F 15pF
4.22K
8.66
* 6.98
1000pF
10K PA88 PA88
A1 A2 Rn
4.22K .03F 5.62K
Cc Cc
to Cn
470pF 3.3pF * .06F * 3.3pF
.1F 270pF
10K
5.62K .1F +
**
270pF 4.7F
VIN
120V 120V 120V 120V
NOTES: UNLESS OTHERWISE NOTED:

1) ALL DIODES ARE 1N4148; *DIODES = 1N5617; **TRANSZORBS = 1N6300 or 1.5KE160
2) USE HS02 HEATSINK @ 25C AMBIENT
FIGURE 21. PA88 BRIDGE PZT DRIVE WITH SELECTABLE GAIN
+180
+135
+90
+45
0
45
90
135
180
D
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90 fcl
135
MARGIN = 29
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY, F (Hz)
FIGURE 23. A1: MASTER AMPLIFIER OPEN LOOP PHASE PLOT
CL = .06f GAIN = 6dB
385
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
fcl
135
MARGIN = 45
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY, F (Hz)

CL = .06f GAIN = 20dB a low cost monolithic ASIC designed for high voltage. The limitations
of the high voltage ASIC technology do not allow for optimization of
A2 will be the same as Figure 23. input characteristics, thus the PA41 has a 60mV input offset voltage.
In high voltage applications where low drift or high accuracy are
3.3 HIGH ACCURACY, HIGH VOLTAGE, LOW COST desired this can be accomplished through the use of a composite
amplifier which uses a low cost monolithic front end amplifier to control
PZT DRIVE accuracy and drift. The PA41 now acts as a voltage and current
Figure 26 (see next page) is an example of a high accuracy (input booster.
offset = 60V), low drift high voltage amplifier. Though only used here There are three simple steps to stabilize a composite with a
at +/-60V, the PA41 can be used up to +/-175V supplies. The PA41 is capacitive load:
STEP 1: Compensate PA41 for stability first: Refer to Figure 27( see
220 second page following this one) which shows how capaci-
200 tive load modifies Aol. Figure 28 (see second page following
180 this one) confirms that the selected 1/ plot will guarantee
stability for the PA41.
160
STEP 2: Create composite Aol: Refer to Figure 29 (see second page
GAIN (dB)
140 following this one) which shows addition of closed loop gain
120 PA88 Aol w/Cc = 3.3pF of PA41 to OP07 Aol on dB plot to yield net Composite Aol.
100 STEP 3: Compensate composite op amp: Figure 30 (see third page
following this one) shows the selected 1/ plot to stabilize
80 composite amplifier. Both noise gain compensation and
60 feedback zero compensation are used to maximize stability.
1 2 3 4 5
40 Figure 31 (see third page following this one) plots the open
20 loop phase for the composite amplifier yielding 50 degrees
75K dp phase margin and good stability.
0
.1 1 10 100 1K 10K 100K 1M 10M 100M
23.7K 39.2K
CL = .03F
3.4 HIGH HIGH VOLTAGE AMPLIFIER CIRCUIT
26.5K 53K Figure 32 (see third page following this one) illustrates the current
FREQUENCY, F (Hz) CL = .06F state of the industry with regards to highest voltage available using op
amps. This bridge circuit will give us up to +/-1160V across the load.
1 A1 GAIN = 22.7 4 A1 GAIN = 2 Remember when using the PA89 to pay particular attention to input
3 A1 GAIN = 5
2 A1 GAIN = 10 5 A1 GAIN = 1 protection, heatsinking (low quiescent current times high voltage ==>
power dissipation!), components (power dissipation and voltage coef-
FIGURE 22. A1: MASTER AMPLIFIER MAGNITUDE PLOT FOR STABILITY
386
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
MARGIN = 67 fcl
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY, F (Hz)

CL = .06f GAIN = 27.5 dB
D
RFC
340K 340K
RF CF
CFC
47pF +60V 47pF
RI
+15V +15V
34k .1F +40V VOUT
RCL
.1F
RIC 75
PA41
VIN 21k CL 40V
OP07 .1F 1.6KHz
2.5V Rsn
Rc 100
.1F 2.2K
.1F
Csn
Rn 330pF
3.4K Cc
18pF
Cn 15V 15V 60V 60V
4700pF
ALL DIODES 1N4148s
FIGURE 26. PA41 COMPOSITE PIEZO TRANSDUCER DRIVE
387
ficient of resistance), and compensation capacitor (1200V rating Figure 33 (see second page following this one) is an implementation
necessary). of an 860Vpp piezo drive. There are four simple steps to setting up the
single supply scaling:
3.5 860Vpp SINGLE SUPPLY PIEZO DRIVE STEP 1: Define maximum VOP:
MAX VOP = +Vs - VsatA - VsatB
Occasionally it is desired to provide a bipolar drive to a capacitive MAX VOP = +450 - 10V -10V = 430Vp
load using only a single supply. This will reduce area and cost by only STEP 2: Calculate gain:
requiring one power supply. It will however require the use of a bridge Gain = VOPP / VINPP = (VA - VB)pp / VINPP
circuit with two high voltage amplifiers.
200 200
180 180
160 PA41 Aol w/ 160
COMPOSITE Aol
140 Cc = 18pF 140
Rc = 2.2K
120 120
GAIN (dB)
GAIN (dB)
100 fp1 100

OP07 Aol
80 80
60 fp2 60
40 40 PA41 AVCL
1/ fp5 fz1
20 20
PA41 AVCL 0
0
20 fp3 20
fdp4
40 40
.1 1 10 100 1K 10K 100K 1M 10M 100M .1 1 10 100 1K 10K 100K 1M 10M 100M
7K 9.3K fcl FREQUENCY, F (Hz) fdp4
FREQUENCY, F (Hz) FIGURE 29. COMPOSITE AMPLIFIER Aol MAGNITUDE PLOT
(MODIFIED Aol WITH CL, RCL & Ro)
FIGURE 27. POWER OP AMP MAGNITUDE PLOT FOR STABILITY
+180
+135
+90
fp5
+45
0
fp1 fz1 fp4
45
fp2 fp3
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
MARGIN = 67 fcl
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY (Hz)
FIGURE 28. POWER OP AMP OPEN LOOP PHASE PLOT FOR STABILITY
388
Gain = 860Vpp / 12Vpp = 71.67
Gain = 2 RF/RI with the bridge configuration. That is the VA VB = +Vs(2 (1+ RF/RI) ( RARB+RB ) 1) 2(RF/RI)VIN
voltage gain across the load is twice that of the master
amplifier, A, since +1V out of amplifier A yields -1V out of But when VIN = 0 then VA-VB =+430V
amplifier B, relative to the midpoint power supply reference Using RF/RI = 35.833 and solving above equation yields RA
of +225V. Therefore: RF/RI = 71.67/2 = 35.833 = 36.669RB
STEP 3: Calculate offset: Choosing RB = 12K implies RA = 440K
STEP 4: Check for common mode voltage compliance:
200 RFM RIS

180 500K,1W 500K,1W RFS
fp1
160
COMPOSITE Aol 500K,1W
140 RIM +600V +600V
120 23.2 18.7
10K
GAIN (dB)
100 Rn
RCL RCL
80 10K
VIN PA89 PA89
60 fp2 Cn
fdp7
40 560pF
1/ fz1
20
VOUT / VIN fz2
0 fp3
600V 600V
20 fp5 33pF 33pF
220 220
40 Rc Cc Cc Rc
.1 1 10 100 1K 10K 100K 1M 10M 100M
fp6
fcl ALL DIODES IN4148's
fdp4
FREQUENCY, F (Hz)
FIGURE 32. 1160V PIEZO DRIVE BRIDGE
FIGURE 30. COMPOSITE AMPLIFIER MAGNITUDE PLOT FOR STABILITY
+180
+135
+90
fdp7
+45
fz2 fp6
0
fp1 fp2 fdp4
45
fz1 fp3
90
fp5
135
180 D
.1 1 10 100 1K 10K 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
MARGIN = 50
180
.1 1 10 100 1K 10K fcl 100K 1M 10M 100M
+180
+135
+90
+45
0
45
90
135
180
.1 1 10 100 1K 10K 100K 1M 10M 100M
FREQUENCY, F (Hz)
FIGURE 31. COMPOSITE AMPLIFIER OPEN LOOP PHASE PLOT FOR STABILITY
389
500K 1/2W Trimpot
RFM
490.9K RIS
RFS 432K,1/2W
VR1 +450V
432K,1/2W
+450V
+
C4 .1F
C1 10F D1 D3
RCLA RCLB
C2 .1F +450V
RIM 4.87 3.79
1/4W 1/4W
13.7K A PA88 PA88
1/4V A1 A2 B
VA VB
VIN
Cca Ccb
Cn
10pF 10pF
D2 D4 Rn 120pF RX
Rca Rcb 12.1K 432K
VR 330 330 1/4W
(11.95V)
D1-D4 = 1N5619
All others = 1N4148s RY
RA 432K
440K RB 1/4W
+450V C3
12K VIN VA VR VA VB .1F
500K 1/4W +12V 10 440 430
1/2W Trimpot C5 +6V 225 225 0
.1F 0V 440 10 +430
FIGURE 33. 860Vpp PIEZO DRIVE

(SINGLE SUPPLY BRIDGE)
The resistor divider of RA and RB was set to yield the

desired offset. These values yield VR = 11.95V which is
greater than the minimum common mode voltage specifica-
tion of 10V for the PA85.
4.0 FINAL NOTE

You have now looked at several ways to drive capacitive loads using
high voltage amplifiers. The techniques presented here are intended
to enable you to complete your circuit designs in a short time.
If there are additional questions or concerns not covered in this
application note, please feel free to contact APEX APPLICATIONS
ENGINEERING through our TOLL FREE HOTLINE, 800-546-2739
(Canada & USA, outside Arizona), by direct telephone, 602-690-8600,
or by using the APEX APPLICATIONS FAX, 602-888-7003.
390
100M
10M
1M
100K
FREQUENCY (Hz)
1K 10K
D
.1100
10
1
240
220
200
180
160
140
120
100
80
60
40
20
GAIN (dB)
391
100M
100M
100M
10M
10M
10M
1M
1M
1M
100K
100K
100K
FREQUENCY (Hz)
10K
10K
10K
1K
1K
1K
100
100
100
10
10
10
1
1
.1
.1
.1
+180
+135
+90
+45
0
45
90
135
180
+180
+135
+90
+45
0
45
90
135
180
+180
+135
+90
+45
0
45
90
135
180

without notice.
392
PARALLEL CONNECTION
APPLICATION NOTE 26
PARALLEL CONNECTION OF POWER OP AMPS current to the load. The challenge to the designer is to find the happy
medium for Rs values. As a general rule, power amplifiers will be used
Power op amps can be paralleled to increase current, improve SOA with Rs values of from 0.1 ohm to 1.0 ohm.
(Safe-Operating-Area), or double thermal capability. While the basic
topology seems simple, there are design details which require careful
attention such as common-mode range considerations, stability, slew 3.0 CURRENT LIMITING
rate, and losses which can reduce efficiency and increase power Current limit of the master should be set 20% lower than the slaves
dissipation. if possible, and the ultimate current limit of the overall circuit will be that
limit multiplied by the total number of amplifiers. The idea here is the
1.0 BASIC PARALLEL TOPOLOGY master current limits first, and since it provides the drive for all other
amplifiers, that drive is also clipped. This insures equal sharing of all
A1 in Figure 1 referred to as the master amplifier, can be configured stresses during current limit.
in any form desired, inverting or non-inverting, and any gain desired.
Feedback for A1, and only A1, will come from the overall output of the
parallel connection. The output of each amplifier will have in series 4.0 SLEW RATE CONSIDERATIONS
equal small-value resistors to improve current sharing characteristics. Assume an initial condition where the output of the circuit in Figure
The slave amplifiers, A2 and up to An, are configured as unity gain non- 1 is resting close to the negative rail. Then apply a step function to the
inverting buffers driven from the output terminal of the master amplifier input of the master amplifier to drive the output positive. The output will
A1. Each slaves individual feedback is taken directly at its output slew as fast as the amplifiers slew rate to the positive rail. With the
terminal. slave being driven from the master, the slave doesnt get its input
The idea of this connection is since each slave is a unity gain buffer, transition until the master slews, and then the slave requires additional
the slave outputs will match as closely as possible the output of the time to slew positive.
master. Yet with the master feedback being wrapped around the entire In the interval where the master has reached positive output and the
circuit, overall accuracy is maintained. slave is trying to catch up, there is a large difference in the output
voltage of the two amplifiers developing current through the two
RF current sharing resistors. This can be a large current equivalent to the
current limit of the amplifier. Thats the bad news. The good news is
RI +VS
that it is a transient current and as such may be within transient SOA
RS limits. But this can be difficult to prove for certain.
A1 When in doubt, the best rule of thumb is to not use the parallel
VIN connection at greater than half the rated slew rate of the amplifiers.
I
VS 2I
5.0 STABILITY CONSIDERATIONS
For detailed information on stability, refer to Application Note 19,
+VS Stability For Power Operational Amplifiers. All discussion here is
RL based on the stability theory contained in Application Note 19.
RS D
A2
5.1 SLAVE STABILITY
I
The most obvious problem from a stability standpoint is the unity
VS gain buffer connection of the slaves. This configuration has the least
ability to tolerate poor phase margin. Poor phase margin usually
CONSIDERATIONS occurs as a result of excessive capacitive loading. But in the case of
ILOSS = VOS/2RS the PA12, the unity gain buffer connection should not be used without
VLOSS = IOUTRS additional compensation. Externally compensated amplifiers should
SLEW RATE MISMATCH normally be compensated for unity gain and may still require additional
WILL GIVE LARGE ICIRC compensation. Alternatively, they may be decompensated to improve
slew rate and use noise gain compensation to insure stability.
The most common way we recommend to compensate the slave is
FIGURE 1. BASIC CONNECTION.
with a noise gain compensation network across the inputs to the
amplifier. However, for noise gain compensation to work, there must
2.0 LOSSES be impedance in the feedback path. Figure 2 shows the modifications
The output of the slaves in this configuration will not exactly match necessary to incorporate noise gain compensation.
the master. Since the slaves operate at unity gain, the difference will The RFS value of Figure 2 is somewhat arbitrary, but its choice will
be equal to the worst case offset of a single amplifier for two amplifiers dictate the final values of Rn and Cn. As is the general case in any op
in parallel since only the offset of the slave causes this mismatch. With amp circuit, excessive impedance for RFs is something to be avoided.
more than one slave, each slave could have worst case offset in A realistic range of values for RFs is from 1 K to 1 M with a good
opposite directions, and in the worst case, the mismatch is twice the starting point being 10 K.
input offset voltage. Once the value of RFS is pegged, noise gain compensation should
These offset voltages produce a drop across the current sharing usually be set to give a noise gain of 10. This corresponds to Rn being
resistors and a corresponding current flow. This is current that is lost, one-tenth Rf. Cn must be found analytically according to procedures
never appearing in the load and increasing amplifier dissipation. outlined in Application Note 19 after considering the effects of amplifier
bode plot and additional poles resulting from capacitive loading. In
many cases, selecting Cn for a corner frequency of 10KHz based on
2.1 CURRENT SHARING RESISTOR CHOICE the value of Rn (Xcn = Rn@10KHz) will result in a stable circuit;
Increasing values of current sharing resistors will reduce the circu- although, analytical methods will maximize bandwidth in comparison
lating current loss. But this improvement must be weighed against to this method.
direct losses through the current sharing resistors when delivering
393
Rf RF
+VS RCL+ +VS

RI VA1 .1F
VRZ
R RS
A1
VIN RCL VIN RI VA1
I RCL RS
R A1
VS CC1 VIN R
I
RFS .1F
CC1
VRZ
Cn +VS RCL+ VS
VA2
.8R RS RFS
Rn A2 VOUT
RCL
I
+VS
.8R ZL Rn VA2
VS CC2 IOUT Cn RCL RS
2I A2 VOUT
TRADITIONAL .8R
(VSAT VCM) I
ZL
FIGURE 2. SLAVE STABILITY. VS CC2 IOUT
2I
VRZ > VCM VSAT
5.2 MASTER STABILITY
A1 is subject to all normal considerations for stability. If A1 is a gain HIGH VOLTAGE
(VSAT < VCM)
of 10 or greater, its stability will be equal to that of the slave with noise
gain compensation described above. At gains below 10, the optimum FIGURE 3A. OVERCOMING COMMON MODE RESTRICTIONS.
noise gain will be a gain of 10 to match the slaves.
RF
6.0 COMMON MODE CONSIDERATIONS
The unity gain buffer configuration must be able to accept inputs +VS
equal to the maximum output swing of the master. This will be a
problem in MOST cases. The following is a list of op amp models in
which the output voltage swing exceeds the acceptable input com- RI VA1
mon-mode range: RCL RS
A1
PA02 .................. (Special problems)
VIN R
PA03 I
PA04 .................. (Boost equipped) .1F
PA05 .................. (Boost equipped)
CC1
PA08 VS
RFS
PA21, 25, 26 ...... (Usually OK)
PA41 +VBOOST
Any PA8X Cn +VS
PA21, PA25, PA26 are listed only because, according to the product VA2
RCL RS
data sheet, it is possible to have common-mode violations in the
A2 VOUT
parallel connection. However, this is only likely when lightly loaded Rn
.8R
and the PA21, PA25, PA26 behavior is so good under common mode I
violation conditions that it is not likely to be a problem. ZL
Special problem amplifiers deserve special mention. The PA02 VBOOST CC2 IOUT
does not lend itself to parallel connection. Negative inputs which get VS 2I
within 6 volts of the negative supply rail can cause output polarity
reversals which can be catastrophic in the parallel connection. VBOOST >VS VSAT + VCM
In the PA07, PA08, PA09, all PA8X, or anything with JFET input
stages, common-mode violations can cause output reversals and HIGH POWER with VBOOST
common-mode range is restricted to no closer than 10 to 12 volts within (VSAT < VCM)
the supply rails.
FIGURE 3B. OVERCOMING COMMON MODE RESTRICTIONS.
6.1 OVERCOMING COMMON MODE
RESTRICTIONS The PA04 and PA05 present another opportunity to overcome
A method most useful with high voltage amplifiers where currents common-mode limitations by taking advantage of their boost pins.
are low, is to simply use zener diodes in series with the supply line to Originally incorporated to improve output voltage swing, we effectively
the master amplifier as shown in Figure 3A. These drop the master increase common-mode range by increasing front-end supply volt-
supply low enough to restrict its output swing to be within the common- ages. A boost of at least 5 volts will be adequate to overcome this
mode range of the slaves. Determine wattage ratings based on limitation. Figure 3B elaborates on this connection.
expected load + quiescent current flow.
394
Other methods include operating slaves on slightly higher voltages
than the master. This is what is accomplished with the zeners
described previously, but is not easily applied to high current power
amplifiers unless they have boost voltage provisions. In such cases
the zeners can be included in series with the Vboost pins of the master
amplifier.
It may seem possible to attenuate the output of the master and set
the slaves up with corresponding gain, but it will be found that unless
very strict matching requirements of the associated resistors are met,
extremely large circulating currents will flow.
7.0 BRIDGE CIRCUITS

The master-slave combination once realized and taken as a whole,
comprises one effective op amp. Treated this way, incorporation into
a bridge circuit is simply a matter of using an inverting unity gain
configuration on the slave side of the bridge (note that the slave of the
parallel combination and the slave side of a bridge are two different
things). Bridge techniques are discussed in detail in Application Note
20, Bridge Operation.
8.0 SINGLE SUPPLY

There are no unique considerations concerning single supply
except those described in Application Note 21, Single Supply Opera-
tion. Again, as in the bridge, treat the parallel combination as a single
op amp.
however, FAXis(520)
ORDERS (520) 690-8601
395
PROPER ANALOG WIRING FOR POWER OPERATIONAL AMPLIFIERS
APPLICATION NOTE 28
1.0 AVOID PREDICTABLE FAILURES

This brief application note is intended to guide you through success- ii) Insert the two mounting bolts through the mounting holes in the
ful prototyping and final construction of power op amp circuits by using flange of the amplifier and tighten them finger-nail tight. Literally
proper component location and interconnection techniques. use your fingernail as a screwdriver. This ensures no overtorque
Proper analog construction of power op amps is just as critical as and gives a starting point so that the nut fits snugly against the
choosing the proper power op amp, heatsink, or schematic design. For mating socket.
reliable success, you should treat all power op amps as high frequency iii) After using finger-nail tightening, one complete revolution on
devices. Even though you may have designed a circuit to operate at the head of each mounting bolt is 4-7in-lbs. Apply this torque one
400Hz, the amplifier will, in general, have a bandwidth capability out quarter of a turn at a time, alternating between the two mounting
to 4MHz or so and will be happy to oscillate at that frequency if not
bolts, until one complete revolution is reached.
constructed properly.
In addition to this application note, be sure to read General
Operating Considerations in the Apex handbook for details on stabil- 3.0 PROPER ANALOG CONSTRUCTION
ity, supplies, heatsinking, mounting, current limit, SOA, and specifica- Figure 2 illustrates a typical inverting power op amp circuit which will
tions interpretation. be used to discuss proper component locations and wiring. Other
power op amp circuits will use similar techniques.
2.0 PROPER MECHANICAL MOUNTING Refer to Figure 3. This Figure shows the proper routing of connec-
Refer to Figure 1. This side view of the amplifier mounted to a tions and component locations for the circuit of Figure 2.
heatsink shows optimum mounting to allow for wiring ease of the The mating socket will be facing towards you to allow for unlimited
peripheral components associated with the power op amp. Notice the height so a circuit ball or birds nest of components can be soldered
necessity of teflon sleeving to insulate the amplifier leads from the directly to the mating socket. This will result in an analog construction
heatsink; the use of a mating socket for ease of solderable component equivalent to a properly designed printed circuit board.
connections; and the use of an Apex thermal washer (or thermal Note the location of all components associated with the power op
grease) as the only approved interface between the amplifier and the amp circuit shown in Figure 2 are directly at the power op amps mating
heatsink. socket. A single point ground is illustrated by physical connection of
You also want to be sure the recommended mounting torque of the power supply ground, input signal ground, and output load ground.
4-7in-lbs (.45-.79 N-m) for the 8-pin TO-3 package and 8-10in-lbs For the single point ground wire running from the power supply to the
(.90-1.13 N-m) for the Power Dip, JEDEC MO-127, package is used. power op amp, strip back the wires insulation about 2 or 3 inches and
This torque needs to be applied in small increments alternating tin it with solder. This wire can then be bent or bussed wherever it
between the two mounting bolts, similar to tightening the lug nuts on needs to go to pick up all ground points for the power op amp and its
a car tire.
associated components.
Stand components on end, cordwood style, or leave them hanging
2.1 8-PIN TO-3 MOUNTING in mid-air, using the leads of the components themselves as intercon-
Since the 8-pin TO-3 package is more sensitive to improper mount- nection wires.
ing torque, here is a rule of thumb for those who do not have ready DO NOT RUN WIRES FROM EACH PIN OF THE POWER OP AMP
access to a torque screwdriver: OVER TO A PIECE OF VECTOR BOARD, PERF BOARD , OR
i) After an Apex thermal washer or grease is applied and the teflon PRINTED CIRCUIT BOARD WHERE THE POWER OP AMPS
sleeving installed on the leads, assemble the power op amp onto ASSOCIATED COMPONENTS ARE LOCATEDTHIS WILL BE-
the heatsink and press it firmly into the mating socket until it is COME AN OSCILLATORY, ANALOG DISASTER!
firmly seated and there is no gap in the assembly.
Heatsink
Teflon Tubing
Mating Socket (At least 4 pins) TOP
Power Op Amp
Package
APEX Thermal Washer BOTTOM
(or thermal grease)
FIGURE 1. SIDE VIEW.
396
RF
+VS
C1
10F
C3
.1F
RI RCL+
5 3
2
VIN 1 VO
4
8
6
C2 RCL
10F
VO
C4
.1F
VS
FIGURE 2. SCHEMATIC.
POWER SUPPLY SIGNAL GENERATOR
VS +VS OUTPUT
VO
VO
RCL RCL+
C2 C4 RF C3
C1
RI
FIGURE 3. TOP VIEW. BOTTOM VIEW OF AMPLIFIER.
however, FAXis(520)
ORDERS (520) 690-8601
397
PWM BASICS
APPLICATION NOTE 30
INTRODUCTION
This note is divided into three sections. The first section provides Vs
general information on Pulse Width Modulation amplifiers and exam-
ines a typical block diagram. The second section on designing with
PWM amplifiers is NOT intended for optional reading. The family of
PWM amplifiers are not all equal in protection features and some of the PWM
design errors which would cause a linear amplifier to oscillate will CONTROL
destroy some of the less protected PWM amplifiers. The final section
examines some ways to use PWM amplifiers.
PWM circuits are taking the same general course of development 95% 50% 5%
traveled by op amps and many other electronic functions. Concepts
were brought to life using discrete components and were followed by
modules, hybrids and then monolithics. The first hybrids on the scene
in PWM technology are the SA01, SA50 and SA51 from Apex. The
SA01 and SA50 contain all the functions needed to implement a wide
variety of control circuits. The SA01 features three levels of protection FIGURE 2. PWM POWER DELIVERY.
circuits and the SA50 and SA51 feature the small TO-3 package. The
SA51 will accept digital inputs as opposed to analog inputs of the other cycle for filtering. In this manner the load sees very little of the switching
two models. frequency but responds to frequencies significantly below the switch-
ing frequency. A rule of thumb is to expect a usable bandwidth one
THE WHY AND HOW OF PWMs decade below the switching frequency. Inductive loads often provide
adequate filtering without dedicated filters.
As power levels increase the task of designing variable drives With the PWM circuit, the direct (unfiltered) amplifier output is either
increases dramatically. While the array of linear components available near the supply voltage or near zero. Continuously varying filtered
with sufficient voltage and current ratings for high power drives is output levels are achieved by changing only the duty cycle. This results
impressive, a project can become unmanageable when calculation of in efficiency being quite constant as output power varies compared to
internal power dissipation reveals the extent of cooling hardware the linear circuit. Note that efficiency claims on the hybrid PWM
required. A 20A output stage often requires multiple 20A semiconduc- amplifier data sheet do not include filter losses. Typical efficiency of
tors mounted on massive heatsinks, usually employs noisy fans and filtered PWM circuits range from 80 to 95%.
sometimes liquid cooling is mandated. Almost all power amplifiers (low duty cycle sonar amplifiers are a
PASS ELEMENT notable exception) must be designed to withstand worst case internal
power dissipation for considerable lengths of time compared to the
Vs thermal time constants of the heat sinking hardware. This forces the
design to be capable of cooling itself under worst case conditions.
LOAD Conditions to be reckoned with include highest supply voltage, lowest
load impedance, maximum ambient temperature and, lowest effi-
ciency output level. In the case of reactive loads, maximum voltage-to-
DRIVER current phase angle (lowest power factor) must also be addressed.
Consider a circuit delivering a peak power of 1KW. A 90% efficient
FIGURE 1. LINEAR POWER DELIVERY. PWM circuit generates 100W of waste heat when running full output
and around 50W delivering half power. The theoretically perfect linear
Figure 1 illustrates the linear approach to delivering power to the circuit will generate 500W of waste heat while delivering 500W. Table
load. When maximum output is commanded, the driver reduces 1 shows three possible approaches to this type design. In all three
resistance of the pass element to a minimum. At this output level cases it is assumed ambient temperature is 30C and maximum case
losses in the linear circuit are relatively low. When zero output is temperature is 85C. It is also assumed power ratings of the TO-3
commanded the pass element approaches infinity and losses ap- devices is 125W each. Heatsinks for linear designs require multiple
proach zero. The disadvantage of the linear circuit appears at the sections mounted such that heat removed from one section does not
midrange output levels and is often at its worst when 50% output is flow to other sections. The linear approaches require five times the
delivered. At this level, resistance of the pass element is equal to the heatsink rating of the PWM approach. The bad news with the hybrid
load resistance which means heat generated in the amplifier is equal linear design is that the heat is concentrated in such a small area that
to the power delivered to the load! We have just found the linear circuit this design is right on the edge of requiring liquid cooling. With its high
to have a maximum efficiency of 50% when driving resistive loads to package count the discrete linear approach will likely have more than
midrange power levels. When loads appear reactive this efficiency five times the heatsink size and weight of the PWM.
drops even further.
Figure 2 illustrates the most basic pwm operation. The PWM control
Discrete Linear Hybrid Linear Hybrid PWM
block converts an analog input level into a variable duty cycle switch
drive signal. As higher outputs are commanded, the switch is held ON Waste heat 500W 500W 100W
longer portions of the period. The switch is usually both ON and OFF Pkg count 16 x TO-3 2 x PA03 1 x SA01
once during each cycle of the switching frequency but many designs
are capable of holding a 100% ON duty cycle. In this case, losses are Heat sink 0.11C/W 0.11C/W 0.55C/W
simply a factor of the ON resistance of the switch plus the inductor
resistance. As less output is commanded the duty cycle or percent of TABLE 1. CONTRASTING DISCRETE LINEAR, HYBRID LINEAR
ON time is reduced. Losses include heat generated in the flyback AND HYBRID PWM 1KW DESIGNS
diode. At most practical supply voltages this diode loss is still small
because the diode conducts only a very small portion of the time and The simple form of PWM circuit examined thus far is very similar to
this voltage drop is a small fraction of the supply voltage. a number of switching power supply circuits. If the control block is
The job of the inductor is storing energy during the ON portion of the optimized for producing a wide output range rather than a fixed output
398
level, the power supply becomes an amplifier. Carrying this one step REF OUT
Vs
further results in the PWM circuit employing four switches configured SUPPLY/
as an H-bridge providing bipolar load current from a single supply. This REFERENCE
does mandate that both load terminals are driven and zero drive
results in 50% of supply voltage on both load terminals. See Figures
3 and 4 for the basic bridge operation and typical waveforms. SHUTDOWN/
FILTER PWM
Vs Vs
THERMAL
LIMIT
Q1 Q2
CURRENT A OUT
EA OUT LIMITS
LOAD/FILTER
SHUTDOWN
B OUT
DRIVERS
IN
Q3 Q4
+IN I SENSE
ERROR
GND AMP
FIGURE 3. BIPOLAR OUTPUT OF THE BRIDGE.

FIGURE 5. SA01 BLOCK DIAGRAM.
FILTER pin. When this voltage exceeds 200mV, all switches in the H-
95% DUTY CYCLE 50% DUTY CYCLE 5% DUTY CYCLE bridge are shut off for the remainder of the switching cycle. Because
(+90% OUTPUT) (0 OUTPUT) (90% OUTPUT)
the sense voltage will have considerable spike content, the hybrid
Vs includes an internal filter stage. A second external stage of R-C
A filtering allows larger peak currents for any given value of current
0 sense resistor. The resistor in this filter is also used as a voltage
divider to shut the amplifier down on command of a logic level input
Vs voltage.
The supply/reference block provides operating voltages for the
B PWM controller and the error amplifier plus a reference quality 7.5V
0 which can be used to bias input signals to the error amplifier. This
reference voltage is also used to provide accuracy for several func-
+Vs tions in the PWM block.
A-B The error amplifier is used to integrate the difference between
Vs command signals and feekback signals. Its output voltage will go to
the exact voltage required by the PWM block to generate the proper
FIGURE 4. H-BRIDGE WAVEFORMS. duty cycle corresponding to the desired output. The first job of the
error amplifier is responding to input signal changes, but it also
D
The H-bridge switches work in pairs to reverse polarity of the drive compensates other variables inside the feedback loop. Any variation
even though only one polarity supply is used. Notice how the levels of in supply voltage will require an adjustment of duty cycle to maintain
the A-B waveform are different even though shape is identical to the a constant output. On resistance of the H-bridge, resistance of the filter
A waveform. Q1 and Q4 conduct during one portion of each cycle and inductor and sometimes load resistance temperature variations are
Q2 and Q3 are on during the remainder of the cycle. Changing duty compensated. Systems such as speed controls may place mechanical
cycle through 50% (zero output current) is a continuous function factors such as conveyer belt load weight inside the loop where the
meaning there is no inherent cause of crossover distortion as exists in error amplifier compensates the variations.
a linear circuit where different transistors conduct depending on The PWM circuit converts the error amplifier output into a variable
current polarity. duty cycle drive signal which includes 0% and 100%. A dead time (all
Figure 5 shows a block diagram of the SA01. The hybrid construc- FETs turned OFF) is inserted between each change of polarity at the
tion of the SA01 allows monitoring temperature on the top surface of output. This precludes shoot through current spikes caused by both
each power die rather than case or heatsink monitoring, the best that FETs in the same leg of the H conducting at the same time. If these
could be achieved with a discrete PWM implementation. This tech- spikes were allowed to exist they would cause high stress and possibly
nique includes thermal resistance variables in the measurement and destruction of both amplifier and power supply components.
reduces response time orders of magnitude to enhance reliability. The Refer to figures 6 & 7 for the following discussion of the PWM control
thermal limit is set for approximately 165C. Activation will cause the block. The oscillator portion of the PWM controller consists of two
PWM controller to immediately turn off all switches in the H-bridge. A comparators, two switched current sources charging the timing ca-
latch circuit will keep the SA01 shut down until power is cycled. pacitor and a flip-flop. When voltage on the timing capacitor reaches
The first of two current limits in the PWM block is the high side 7.5V, the upper comparator resets the flip-flop which opens the upper
current limit which activates only upon output shorts to ground (assum- current source and connects the lower one. When the timing capacitor
ing the programmable current has been properly configured.) This voltage reaches 2.5V, the lower comparator sets the flip-flop to start
circuit has a variable response time based on the current magnitude the next cycle.
in +Vs line. With a fault current of 35A it will require several cycles of Comparators A and B set up the duty cycle based on the voltage
the switching frequency to activate the circuit. As higher currents are relationship of the input voltage and the very linear triangle. For initial
sensed the response time decreases. Once a fault has been sensed examination of operation imagine the 500 resistors are shorted.
the amplifier will remain latched off until power is cycled. When the input voltage is midrange, there are equal portions of the
The second current limit circuit in the block diagram is program- triangle wave above and below the input, thus a 50% duty cycle is
mable and activates upon a load fault or a short to the power supply. generated at each comparator. When the input voltage moves half way
An external resistor senses current flowing between ground and the between midrange and the 7.5V peak of the triangle, 1/4 of the triangle
low side of the H-bridge. The sensed voltage is fed to the SHDN/ is above the input and 3/4 is below the input generating a 75% duty
399
Vs DETECT R The output waveform during dead time is primarily a function of load
HIGHSIDE impedance. Current flow is interrupted by the dead time and the load
CURRENT LIMIT Q or filter inductance will discharge its flyback energy at this time. While
S
13K THERMAL generally not shown in the block diagrams, each power switch has a
SHUTDOWN diode to conduct the flyback current.
The outputs of this block labeled A Drive and B Drive do not directly
represent high and low states of the two amplifier output pins. When
B the A Drive line is high it turns on the switch between the A output and
B DRIVE the power supply and also the switch between the B output and
500 ground. When the A Drive is low, both these switches are off. B Drive
4mA controls the other two switches in the bridge. The and gates generating
7.5V both A and B drives can be disabled by either of two lines. The first of
these lines represents activation of the thermal shutdown or the high
side current limit. The second line is the comparison of the SHDN/
FILTER input and a 0.2V reference.
Q R
DESIGNING WITH PWMs
1nF
Q S PWM amplifiers are high level switching devices whose voltage and
current slew rates often surpass those found in either digital or analog
circuits. Even though signal bandwidth may not top 1KHz, adopting the
500 viewpoint of an RF designer can be very wise. Here are a few useful
2.5V
things to keep in mind:
4mA
Wire inductance 20nH per inch
Inductor voltage = dI/dt * L
Capacitor current = dV/dt * C
A A good square wave = very large harmonic content
A DRIVE
SHDN/FILTER
13K POWER SUPPLY BYPASS
It is difficult to over emphasize this aspect of the PWM design. Most
.2V of us are familiar with the good design practice of including a supply
bypass capacitor at every IC in a low level logic design. If this in not
FIGURE 6. PWM CONTROL BLOCK. done, the high switching rates cause problems. Inadequate bypass
causes ripple and spikes on the supply line which make circuits
inoperative and can even destroy components. Careful attention to
location, size, ESR and ripple current capacity can result in a good
INPUT design.
VOLTAGE Power supply bypassing is a wideband job requiring at least two
components for satisfactory operation of the amplifier. Use at least
10F per ampere of load current to bypass the lower frequencies.
Some applications appear to require many times this amount of
capacitance. Capacitors with lower ESR ratings may ease the burden
INTERNAL of finding space for such large devices. Locate this capacitor within a
RAMP few inches of the amplifier. The high frequency bypass is absolutely
critical! Think of frequencies in the 1 to 10Mhz range. Remember that
INPUT
VOLTAGE many capacitors appear inductive in this range. Use ceramic
B
capacitor(s) totaling 1F to 10F. Connect these capacitors directly
between the supply and ground pins of the amplifier. To illustrate the
importance of this consider a design having 3" between the supply pin
A
and the ground plane terminated capacitor: The supply pin had spikes
equal to the supply voltage! When this happens signal integrity is in
question and peak voltages applied to components may be twice
expected values. Connect the capacitor right at the amplifier pin and
DEAD TIME dont forget that both leads of the capacitor must be counted when
FIGURE 7. PWM WAVEFORMS. figuring distance from the pin.
The function of bypass capacitors is to satisfy AC current demands
cycle at the A comparator. The B comparator looks at the input and of the amplifier which is isolated from the power supply by the very
triangle voltages in the opposite polarity, so it generates a 25% duty same line that connects them. The degree of isolation increases with
cycle. Note the circuit is arranged such that a positive going input current magnitude, frequency and distance. When this isolation pre-
voltage results in a larger percent on time for the A driver. vents current flow to the power supply, it must come from the bypass
With the 500 resistors actually in the circuit the input voltage seen capacitors. Attempting to calculate capacitor currents is a question-
directly at the comparators is modified slightly, which modifies the duty able investment but ignoring them is no solution. Keep the requirement
cycle proportionally. The A comparator sees a voltage a little more in mind when selecting components and follow up with temperature
negative than the actual input. The basic function of positive going measurements on the prototype. Run the system at maximum fre-
input creating a longer A duty cycle means this negative offset quency and power until temperatures stabilize. During this process,
produces a slightly shorter duty cycle. In the same manner the B duty keep in mind that under-rated capacitors can explode.
cycle is also shortened to produce a dead band where all switches are
off. Voltage drops across the individual 500 resistors change as the
input signal varies, but as one drop decreases, the other increases so HOW MUCH INDUCTANCE?
total dead time is constant. PWM amplifiers driving resistive loads with no filtering are unable to
It is important to note that the input voltage depicted here is a straight modulate the output voltage, they can only switch polarity. Loads with
line. While the input voltage obviously varies, this reflects the concept small amounts of inductance may over heat with high ripple current
that useful bandwidth of the PWM amplifier is significantly less than the even with a 50/50 duty cycle (zero output) drive. Other types of loads
switching frequency. If the slew rate of the input voltage were allowed may suffer performance degradation if ripple currents exceed 1% or
to approach that of the triangle wave, dead time would changed even 0.1% of their full scale current. Once a design limit on peak-to-
significantly. This can result in shoot through and amplifier shut down. peak ripple current has been set, calculate minimum total inductance.
400
It is proportional to supply voltage and inversely proportional to IP-P and if P-channel FETs are used and a third if interconnect resistance is
switching frequency: broken out separately. Sum the above calculations with standby power
to obtain total heat loading on the heatsink. If the amplifier has a
L = Vs/(2*F*I) separate low voltage supply pin, dont forget to include it in the total
where Vs is the supply voltage and F is the switching frequency. power calculation.
As an example, this means the SA01 (switching at 42Khz) on 100V With total internal power dissipation now known, it is time to
needs 300H to keep ripple current down to 4Ap-p. determine the heatsink requirement. Again, consistent with your
design standards, choose a maximum case temperature. Do not
exceed the product operating temperature range listed on the last line
GROUND CONCERNS of the specifications table. RCS is the thermal resistance of the
Remember all the high frequency currents discussed under the package to heatsink interface.
bypass heading? Youre right, all that stuff must go through ground to
TC max - TA max
return to the supply. This means a ground plane is the only way to go. RSA RCS
It provides good cross sectional area keeping resistance low plus the Total Power
aspect ratio minimizes both skin effect and inductance. Even with a
good ground plane, all local ground connections should be made as The last item to check is the junction temperature. Multiply power in
close to the PWM ground pin as possible. a single FET by the thermal resistance of the amplifier and add to the
maximum case temperature. In the case of the SA01, use the P-
IS THE SCOPE TELLING THE TRUTH? channel power level and realize the N-channel devices will run cooler.
An alternative to finding the specific junction temperature is to find the
Could be, but touching the probe tip to the ground clip may reveal appropriate fraction of total power and then use the power derating
otherwise. If the scope shows a waveform with this grounded input, graph to make sure junctions do not exceed 150C.
or all high impedance nodes appear to have spikes which they should
not, there are at least three possible sources of error. As an example consider an SA01 delivering up to 10A from a supply
The amplifier local ground may be quite different from the local of 70V in a maximum ambient of 35C. Design rules allow case and
ground seen by the scope input amplifiers and their common mode junction temperatures up to data sheet maximums.
rejection is less than perfect. First, disconnect all other signal cables
from the scope to remove interaction with any other local grounds. If Standby power = 70V * 90mA = 6.3W
a battery operated scope is available give it a try. If not, install a ground N-channel power = 10A2 * .145 = 14.5W
breaker on the scope power cord. P-channel power = 10A2 * .26 = 26W
Use only shielded probes and do not use any extenders, grabbers, Interconnect power = 10A2 * .05 = 5W
or clips which do not have nearly complete shielding. Capacitive Total power = 51.8W
coupling into high impedance nodes works best when voltage slew Maximum case rise = 85C - 35C = 50C
rate is high and these switching amplifiers have plenty to get in trouble. Allow .02C/W for RCS
That 3" to 6" ground lead may have to go. It is forming an inductive Heatsink maximum rating = 50C/51.8W - .02C/W = .95C/W
pickup loop and the PWM is moving lots of high frequency current. If Junction temperature = 85C + 26W * 1C/W = 111C
luck holds, the scope accessory kit will yield an RF adapter capable of
providing a ground lead less than 1/4" long. If not, consider buying one This example would actually run cooler than the above example
or making your own from a length of spring wire. would seem to indicate because junction tempertures are lower than
the assumed starting point and FET ON resistance is lower. An
INTERNAL POWER DISSIPATION iteration of the above based on an assumed maximum junction of
110C would yield a heatsink rating of 1.1C/W and result in maximum
PWM amplifiers share most thermal principles with their linear junction temperatures of 106C. This will still have a small safety
counterparts. margin because the N-channel junctions run cooler than the P-channel
Quiescent current and supply voltage determine standby power. junctions.
Additional heat is generated by driving the load. D
The heatsink must dissipate both the above.
The case temperature range must not be exceeded. TYPICAL APPLICATIONS
Load related power elevates power transistor junctions above The design steps of the PWM speed control employing a tachom-
case temperature. eter feedback shown in Figure 8 are as follows: The 7.5V reference
Maximum junction temperatures must be observed. output is used to bias the non-inverting input of the error amplifier to the
Lower temperatures (case and junction) increase reliability. middle of its 2V to 8V common mode voltage range. The gain adjust
potentiometer corrects initial inaccuracies stemming from error ampli-
There are two major differences in the thermal aspects of linear fier voltage offset, tolerance of the 3.83K bias resistor in the inverting
power amplifiers and PWM amplifiers. First, power in the PWM input and possibly even for offsets in the input signal. The 470
amplifier due to loading can be calculated without knowing the output
voltage or the supply voltage. The second difference is more subtle but GAIN
3.83K 32.4K 2.5K
affects the very reason a PWM amplifier is used: Efficiency drops 7.5V
rapidly as junction temperature increases. This means heatsinking the
PWM is more than a reliability issue. Thermal design of the PWM
amplifier has a first order affect on circuit performance. 470
First order calculation of power due to loading involves the output
current and the total ON resistance of the amplifier. The high speed .068 3.4K
.022 .22
waveforms present at the output pins do indicate second order
calculations could be made but this document will concentrate only on .0047 470K
the basic elements of power dissipation.
Total On resistance includes impedance of the H-bridge power 10K
switches plus resistance of the metal interconnects. Consult the 5VIN
amplifier data sheet to find the contribution of each element. If PWM M T
interconnect resistance is not specified, consider it to be insignificant. 17V
Consider interconnect resistance to be constant over temperature.
Because FET ON resistance is a function of temperature, choose a 1.47K 3.01K
maximum junction temperature consistent with your design standards 7.5V
100
(not to exceed the data sheet absolute maximum). Find FET ON OFFSET
resistance(s) at your maximum junction temperature. I2 * R now yields
power due to loading. This is a single calculation on lower current
amplifiers using all N-channel FETs, but requires another calculation FIGURE 8. PWM SPEED CONTROL.
401
resistor and the two associated capacitors form a low pass filter to rejecting 1/2 the supply voltage present on both outputs. This means
attenuate components of the switching frequency which may be resistor ratio matching becomes critical. It should also be noted that
coupled to the tachometer through the motor. The gain adjust poten- even though the signal gain is 20, the gain of offset errors is 50 because
tiometer compensates tachometer variables of accuracy and internal the effective input resistance is the parallel combination of the signal
resistance plus tolerances of other resistors in the feed back path. The input resistor and the pull-up resistor.
10K input resistor sets overall gain to 3.4. The 3.83K resistor was
selected to pull the inverting input of the error amplifier up to 5V when CONCLUSION
both the input voltage and tachometer output voltage are zero. The two
R-C networks were selected to provide circuit stability while maximiz- The switching amplifier provides solutions to high power drives
ing system response time. Specific values will depend on both motor which could otherwise require in inordinate amount of heat sinking
parameters and mechanical load characteristics. hardware. The arrival of the hybrid PWM speeds the design process
While one of the simplest forms of position sensing is shown in and in the case of the SA01 greatly enhances fault tolerance by
Figure 9, options such as optical encoders, LVDT sensors and variable offering protection circuits simply not possible in a discrete implemen-
capacitance transducers are also viable. Again, error amplifier inputs tation. These features can make an electronic motion control solution
are biased to 5V. While 20K input and feedback resistors would have feasible where a hydraulic solution may have previously been the only
set proper gain and biasing for the inverting input, they would have practical alternative.
allowed common mode violations at the error amplifier. This could
happen if the system was at one position extreme while a very quick
command came in to travel to the opposite extreme. The three 30K
resistors prevent common mode problems by increasing impedance
from summing junction to the two 10V signal levels at the output and
at the input while adding an impedance to ground.
Figure 10 shows a differential input, voltage controlled output circuit
resembling the familiar differential op amp configuration. Signal gain
is 2*RF/RI. Again, two pull-up resistors are used to bias error amplifier
inputs within the common mode range. Select this value to get 5V bias
when both inputs are zero and both outputs are 1/2 the supply voltage
(50/50 duty cycle.) At zero drive to the load, this differential stage is
30K 30K
10V
5K
7.5V
.0047 470K
+10V
30K
EA PWM M
5K
7.5V
10V
10K
FIGURE 9. PWM POSITION CONTROL.
10K
10K Rf
Ri
Cf Rf
1K Cf
10K
3 Rf
EA OUT
1
10K Ro
6
5 7.5V EA A
PWM OUT
10K Ro
2 SA01 B 10K
SHDN/ 9
Ri FILTER Rf
Cf 1K Cf
10 8
SHUT Rfilter
DOWN Rcl
Cfilter
FIGURE 10. VOLTAGE FEEDBACK.
omissions. HOTLINE:
change 546-2739
without notice.
402
OPERATIONAL AMPLIFIER BASICS
APPLICATION NOTE 31
HISTORY
The performance and shape of operational amplifiers has changed It is important to notice that the inverting input of the op amp (junction
considerably since the vacuum tube units were produced by George of Ri and Rf) is maintained very near to the potential of the non-inverting
Philbrick, and others, over three decades ago. Discrete transistor- input. This point is a summing junction and is called a virtual ground.
circuit op amps were the main catalog item for companies like Burr- The op amp output is adjusting to maintain this relationship. This fact
Brown Research Corp. and Analog Devices. The monolithic age of gives rise to two significant extensions. The input impedance is
high-production-volume op amps began with the uA709 from Fair- constant at the value of Ri and it is possible to have multiple inputs
child. Modern op amps have taken on many signal processing chal- which are summed at the output. Each input may have a different gain
lenges. The Apex family has been specialized for high power and high associated with it as shown in Figure 3.
voltage. Whatever the specialty or construction technique, the under-
lying theory remains the same.
FIGURE 1. ELEMENTARY MODEL OF FIGURE 3. SUMMING AMPLIFIER CONNECTION.

AN OPERATIONAL AMPLIFIER.
The output of this configuration is given by the expression:
IDEAL MODEL V1 V V
Vo = Rf ( + 2+ 3)
An ideal operational amplifier (modeled in Figure 1) is a voltage R1 R2 R3
controlled voltage source. The input sense pins have infinite imped-
ance to ground and to each other. The output source has a zero output
impedance and the transfer constant (Open-loop Gain, Aol) approaches
infinity. This unit, simply placed in a system, would be of little use in a
linear mode without the benefits of closed loop control in the form of
D
negative feedback.
FIGURE 4. NON-INVERTING CONFIGURATION.
Our discussion up to here has ignored the non-inverting input. Write

the current summation equations for the circuit in Figure 4 and solve
for Vo in terms of Vi as above. With Aol approaching infinity, the following
FIGURE 2. BASIC INVERTING CONFIGURATION. relationship results.
Rf
FEEDBACK CONTROL Vo = Vi ( 1 + )
Ri
Consider the circuit in Figure 2. For this first example, the op amp
is placed in an inverting configuration with input resistor Ri and This circuit has the features that the output signal is not inverted as
feedback resistor Rf. Since the op amp input impedance is infinite, all it is amplified, the input impedance approaches infinity, and the gain
current flowing through Ri must flow through Rf. If one writes the can not be less than unity.
equations for current flow from Vi to Vo and solves for the Vi to Vo ratio By combining the inverting and non-inverting circuits it is possible to
the result is: make a full, weighted sum and difference system element as shown in
Figure 5.
Vo R
= f
Vi Ri
Where: Aol approaches infinity.
The operational amplifier has now been converted into a linear
circuit element with significant possible extensions.
403
FIGURE 5. SUM AND DIFFERENCE AMPLIFIER.
Through the use of super-position the sum and difference amplifier FIGURE 6. TYPICAL BODE PLOT.
can be analyzed. The accuracy of this relationship depends on the
matching accuracy of the two resistors labeled Rf. The complete the op amp circuit deviates more from the ideal. Consider the op amp
transfer function is given by: of Figure 6 if it were used in a closed loop gain configuration of 20 dB
(X10) as shown by the dashed line. At low frequencies the excess loop
gain is 80 dB. As the frequency is increased the excess loop gain
V1 V V V
Vo = Rf ( 2+ 3+ 4) decreases until it reaches zero dB at 100 KHz. The performance of the
R1 R2 R3 R4 circuit would be very near ideal at low frequencies and deviate more
from ideal as the frequency approached 100 KHz. If the closed loop
gain was increased to 40dB(X100). The non-ideal response would
NON-IDEAL OP AMPS become apparent one frequency decade earlier.
All of the discussion to this point has assumed an ideal device. With
real world op amps there are deviations from the ideal, or errors. The CONCLUSION
magnitude of some of the possible errors for an op amp are listed in the
specification sheet for that device. A description of the circuits used to Some of the basic features of operational amplifier circuits have
measure these parameters can be found in the section titled Parame- been discussed here. The concept of negative feedback and the
ter Definitions & Test Methods. graphical representation of the Bode plot are the most common tools
When the magnitude of the error, as seen at the output, is a direct used in op amp circuit design. The application notes that follow present
function of the closed loop gain that error magnitude is specified techniques for solving many of the problems which arise in the use of
referred to the input (RTI). The maximum error to be expected at the op amps.
output is the error value times the non-inverting gain of the amplifier.
The most common of these errors is initial voltage offset.
Recall that the op amp works because the negative feedback brings
the inverting input to equal the non-inverting input. When connected as
a non-inverting amplifier both inputs will be at a potential equal to the
input signal. Since this input is common to both inputs it is called the
Common Mode Voltage. In an ideal amplifier the common mode
signal would be subtracted out and not appear at the output. Due to
limitations imposed by the real world circuits there is an error signal at
the output which is a function of the common mode voltage. A limit
exists on the range of the common mode voltage that the op amp can
withstand.
POWER SUPPLY SYMMETRY

To this point we have not considered the power supply configura-
tion. When op amps are furnished symmetric power supplies common
mode voltage limits are easy to meet. It is generally possible to operate
from a single supply if the common mode voltage limits are honored.
For further extensions on single supply operation Application Note 21
should be studied.
AC CONSIDERATIONS
All of the relationships discussed above can be extended to the AC
domain by replacing resistance with impedance and allowing for the
finite frequency response of the op amp. If a plot is made of open loop
gain vs frequency it would look similar to Figure 6. This graphic display
is used to describe the op amps open loop performance as a function
of frequency and to predict stability.
The two change of slope points in the response curve are caused
by the existence of poles in the transfer function of the op amp. Most
op amps have Bode plots very similar to that shown in Figure 6. The
slope of the trace between 10 Hz and 1 MHz is -20 dB per frequency
decade. Extensive discussions of stability are presented in Application
Note 19 and others. In the opening discussion we assumed the op amp
gain to approach infinity. The difference between the open loop gain
of the op amp and the closed loop gain, set by the feed-back network,
is referred to as excess loop gain. As the excess loop gain decreases
without notice.
404
PWM LOW PASS FILTERING
APPLICATION NOTE 32
1.0 INTRODUCTION 4.0 FILTER TABLES

Pulse width modulation (PWM) amplifiers often require lowpass Filter analysis begins by developing general mathematical equa-
filtering of the output to demodulate the PWM carrier. These filters can tions to describe the filters. Each filter equation can be reduced to a set
be as simple as a single inductor to multiple LC nodes depending on of coefficients which can completely describe the filter. Each order has
the application. In some motor and solenoid applications, the load can a different set of coefficients.
act as its own filter. Deciding on the type and size of a filter can be time Filter coefficient tables are usually in a normalized form. Normalized
consuming since the calculations can be tedious and often give coefficients are calculated at a frequency of 1 radian per second and
component values that are not easily obtainable. This application note an impedance of 1 ohm. This is done for convenience so the designer
is an effort to reduce filter calculation time. does not have to calculate coefficients for every case. The normalized
coefficients require the designer only to scale the frequencies and
2.0 FILTER TYPES impedances to fit the particular requirement.
The filters most designers are familiar with is the symmetrical load
PWM filters are normally low pass configuration. These exhibit low type. These assume equal terminations on both ends of the filter. This
attenuation to the frequency spectrum from 0 hertz to the frequency of configuration will generally not work here because the source imped-
cutoff (fc). This low attenuation region is called the pass band. Beyond ance of the H bridge is usually low and the actual load usually will be
the fc, attenuation increases at a rate determined by the filter type and much higher. Apex PWM amplifiers have output impedances from
the number of poles (order). Figure 1 indicates the general response about 0.2 ohm to about 0.5 ohm at room temperature, and are mostly
of the low pass filter. resistive. The filter tables here assume a very low impedance source
and a higher impedance load.
The coefficient table also assumes lossless components, therefore
low quality parts will compromise results.
Passband
Filter orders up to 6 are given which will be more than what is usually
needed. Beyond order 5 or 6 the point of diminishing returns begins as
losses in the filter components reduce the efficiency of the PWM
VOLTAGE OUT
FC
amplifier and detract from the expected response.
Apex PWM amplifiers have differential outputs so filters are often
used in a differential configuration. This requires the inductors to be
divided by two and capacitors to be multiplied by 2 as shown in Figure 2.
L1a Lxa
IN A
C1a Cxa
FREQUENCY
FIGURE 1. LOW PASS FILTER RESPONSE Rload D
PWM Output
Many different types of low pass filters exist. Each has favorable and
unfavorable traits and the selection usually is a compromise of
C1b Cxb
performance in one area to achieve desired performance in another
area. Some characterizations are: pass band flatness, rate of attenu- Lxb
L1b
ation, and phase shift versus frequency. Common filters include IN B
Butterworth, Chebyshev, and Bessel.
The Butterworth filter has a flat response in the pass band and good
rolloff beyond the cutoff frequency. Component variations do not FIGURE 2. FILTER CONFIGURATION
greatly affect the performance. It is considered a good general filter
that is often used and therefore will only be considered here.
ORDER L1 C1 L2 C2 L3 C3
3.0 INITIAL CONSIDERATIONS 2 1.4142 0.7071
If you are unfamiliar with PWM circuitry, please refer to Application 3 1.5000 1.3333 0.5000
Note 30. As shown in the minimum inductance equation there, filter 4 1.5307 1.5772 1.0824 0.3827
component values may have to be adjusted to limit maximum current.
Desired attenuation of the PWM must be known to establish the 5 1.5451 1.6944 1.3820 0.8944 0.3090
order of the filter. The minimum order N is approximated from the 6 1.5529 1.7593 1.5529 1.2016 0.7579 0.2588
following equation:
TABLE 1. FILTER COEFFICIENTS
A
10
N=
fx COEF R COEF
2 Log (1) L= C=
fc 2F 2FR
(2) (3)
A = 20 log (H bridge supplied voltage/desired filter output L is in henries, C is in farads, R is in ohms.
peak voltage)
Where A is dB and fx = frequency of desired attenuation,
fc = cutoff frequency. Round N up to the next higher integer.
405
5.0 REACTIVE LOADS The second inductor is calculated again using equation 2:
These filters are assumed to be terminated in purely resistive loads.
In reactive loads, if the real and reactive components are known, a 0.5000 7
L2 =
simple conjugate match can be used. Use the matching network only (2 2000)
when you are sure the reactive components will change the desired
filter response noticeably, as some power is used in the circuit. The L2 = 279 microhenries
resistor power rating can be calculated using Ohm's Law in series AC
circuits. The equations for the matching components are: To insure the filter sees a resistive load and thereby insuring the
proper response, the matching network can be calculated using
L equation 4:
C= L = C R2
OR
R2 (4) (5)
100 10-6
C=
72
C = 2 microfarads
Rm RI Rm RI
In a differential configuration, inductances are halved and capaci-
tances are doubled as shown:
L1A L2A
418H 139.5H
Cm LI Lm CI
C1A Rmatch Rload

30F 7 7
FIGURE 3. MATCHING NETWORK CONFIGURATION
PWM
OUT
6.0 FILTER COMPONENTS
C1B Cmatch Lload
Filters used in high power switching circuits often are the largest 30F 2F 100H
physical part of the circuit. Expect the filter to occupy more space than
the rest of the circuitry.
L1B L2B
Filter components should be low loss, high current devices. Use
418H 139.5H
inductors with current ratings at least as high as the maximum current
delivered to the load. Check current ratings carefully as different
manufacturers can use different rating methods. Make sure the FIGURE 4. EXAMPLE 1
inductors chosen have the required inductance at the maximum rated
current and at the switching frequency.
Polyester, polycarbonate, and polypropylene capacitors are often
used in these filters. Electrolytic capacitors may be required in low
frequency filters. The capacitors should have low loss at the operating 0
frequency and allow relatively high RMS currents. The capacitors
should remain low impedance out to the megahertz range, as switch-
ing harmonics extend well above the switching frequency. Use smaller
ceramic capacitors across the main capacitors, if needed, to insure
proper high frequency bypassing. 50
Voltage Out (dB)
7.0 EXAMPLES
A. Example 1
SA01 driving shaker table solenoid with 7 ohms resistance and 100 100
microhenries inductance to be operated with a signal up to a cutoff 2
frequency of 2 kHz. Attenuation of the switching frequency of 42 kHz
to be greater than 70 dB.
From equation 1, N = 3 required. 1.
The first inductor is calculated using equation 2: 150
100 1K 10K 100K 1M
1.5000 7
L1 = Frequency in Hz
(2 2000)
FIGURE 5. EXAMPLE 1 FREQUENCY RESPONSE
L1 = 836 microhenries
B. Example 2
The capacitor is calculated using equation 3: SA02 driving resistive load of 4 ohms, operated up to a cutoff
frequency of 7 kHz. Attenuation of switching frequency of 250 kHz to
1.3333 be greater than 50 dB.
C1 = From equation 1, N = 2.
(7 2000 2 )
From equation 2:
C1 = 15 microfarads
(1.4141 4)
L1=
(2 7000)
L1 = 129 microhenries Use 68 microhenry per side
406
From equation 3: possible, adjusting these values may allow a workable solution.
Poor circuit layout can not be remedied by good filtering. PWM
(0.7071) circuits, by their nature, have high frequency, high power transients
C1 = that are difficult to eliminate from the desired output signal. Use ground
(4 7000 2 )
planes and shielding as much as possible. Use wide traces on circuit
boards for power supply and output signals and heavy gage wire for
C1 = 4 microfarads Use 8.2 microfarad per side
interconnects. Where possible, use a star grounding technique with
the PWM amplifier ground as the center. A very small amount of
L1A inductance can cause large transients where high current is involved.
68H Space circuit board traces and wiring away from sensitive circuits to
A avoid extraneous noise pickup. Use bypass capacitors liberally.
The response curves given for a low pass filter imply that the
attenuation increases continuously with increasing frequency. Attenu-
C1A
ation values are sometimes shown to beyond 100 DB. This is for
8.2f graphical clarity rather than to imply attenuation continues to that level.
PWM Rload Losses in parts, stray capacitances and other circuit parameters that
OUT 7 are unquantified will cause the attenuation to decrease. At some
extended frequency, the attenuation will be quite different from theory
and may, in fact, approach zero.
C1B Read Application Note 1 and Application Note 30 for further guide-
L1B
8.2F lines.
68H
B
FIGURE 6. EXAMPLE 2
0
VOLTAGE OUT (dB) IN dB (VOLTS)
20
60 2
1
100
140
100 1K 10K 100K 1M
FREQUENCY IN Hz
D
FIGURE 7. FILTER 2 FREQUENCY RESPONSE
8.0 FINAL CONSIDERATIONS

Figure 5 shows the frequency response of filter 1 with, and without,
the matching network. Plot 1 is with the network and plot 2 without. At
the switching frequency, the attenuation is about 10 dB less without the
matching network and the curve has a lower slope. In cases such as
these, matching may not be required. In designs where the load is
more reactive, the response can be unpredictable and circuit analysis
should be used to define the response if the matching network is not
used.
Figure 6 shows the frequency response of filter 2. As shown in the
calculations, standard values were used here to demonstrate the filter
tolerance. Plot 1 of figure 6 shows no large response changes caused
by these component deviations. As an exercise, the filter components
had losses introduced which would make them perform similar to lower
cost components. The inductor (L1) had a 0.1 ohm resistor in series
included which simulates wire loss. The capacitor had a 0.1 ohm
resistor and a 0.1 microhenry inductor included in series which
simulates ESR and ESL, respectively. Plot 2 of Figure 6 shows the
results. There is a marked change in response when these small
components are inserted. This graphically demonstrates the need to
use the best quality components.
Some filter solutions can not be used as the values may be
impractical. As an example, the initial inductor value (L1) of the filter
may be too small to limit ripple current to the required levels, as per
Application Note 30. Minor adjustments may also be required with Fc
to achieve standard off-the-shelf component values. Inductors can
often be adjusted by adding or removing turns to get non-standard
values. Equations 2 and 3 indicate only R and Fc can be varied. If
however, FAXis(520)
ORDERS (520) 690-8601
407
NOTES:
408
PACKAGES
AND
ACCESSORIES
Package Outline Dimensions ................................................................................. 411
Accessories Information ....................................................................................... 419
Product Marking ................................................................................................... 435
409
NOTES:
410
OUTLINE DIMENSIONS
PACKAGES
8-PIN TO-3 PD10/60S

600 24
5962 - 1234567890
USA B eO
USA BeO
MB3 0 9 0 37 2 7 5 7 AZ5059013
NOTE: ESD triangle () on top of package denotes pin 1 location.
1.55" .770"
39.37mm 19.56mm NOTE: Notch on package base denotes pin 1 location.
MAX MAX
.250"
.1" 6.35mm
2.54mm MAX 1.987.005"
MAX 50.47.127mm 1.10.005"
27.94.127mm
1.25.005"
31.75.127mm
.500.002" Flatness in this area shall be

PIN CIRCLE DIA 12.7.051mm .0005" T.I.R. Max.
40
TYP
.093.003" .259/.2759"
7 2.36.076mm 6.57/6.99mm
6
8
5 1.290.010"
1.01" 80 TYP 32.8.254mm
25.7mm MAX
4
.200.002" .156.002"
3 1 3.96.051mm
.210.010" 5.08.051mm
2 Dia.
5.33.254mm
2 Holes
.156.005" 1.187.01"
3.96.127mm 30.15.254mm Bottom
DIA 2 HOLES T.I.R. between these points View
not to exceed .0015"
.043, .246
.125, .217 1.305.005"
.192, .161 33.15.127mm
.594, 0 .235, .086
.594, 0 .900.005"
CAD 22.86.127mm
Coordinates
Pin 1 I.D.
No radius and
E
0, 0
.235, .086 Notch .10" Dia.
.192, .161 (2.54mm Dia.)
.125, .217 Bottom
.043, .246 View
1.634.005"
41.50.127mm
PIN DIAMETER: .965/1.067mm or .038/.042"
PIN LENGTH: 12.19/12.70mm or .480/.500"
PIN MATERIAL, STD: Nickel plated alloy 52, solderable PIN DIAMETER: 1.47/1.57mm or .058/.062"
PIN MATERIAL, MIL: Hot solder dipped, alloy 52
PACKAGE: Hermetic, nickel plated steel PIN LENGTH: 11.43/12.70mm or .450/.500"
WEIGHT: 15 g or .53 oz PIN MATERIAL, STD: Nickel plated steel
ISOLATION: 1000VDC any pin to case PACKAGE: Hermetic, nickel plated steel
SOCKETS: APEX PN: MS03 WEIGHT: 36 g or 1.27 oz
CAGE JACKS: APEX PN: MS02 (Set of 8) ISOLATION: 500VDC any pin to case
HEATSINKS: APEX PN: HS01 thru HS05 CAGE JACKS: APEX PN: MS04 (Set of 12)
CAUTION CAUTION
Recommended mounting torque is 4-7 inlbs (.45 - .79 Nm) Recommended mounting torque is 8-10 inlbs (.90 - 1.13 Nm)
411
OUTLINE
POWER DIP PACKAGES DIMENSIONS
MO-127 HIGH VOLTAGE MO-127/40S
PA89 SA06
USA BeO USA BeO

AZ5059013 AZ5059013
NOTE: Notch on package denotes pin 1 location. NOTE: Notch on package denotes pin 1 location.
1.57/1.58" 1.57/1.58"
2.309.010" 39.9/40.1mm 2.309.010" 39.9/40.1mm
58.65.25mm 1.43/1.42" 58.65.25mm 1.43/1.42"
36.3/36.1mm 36.3/36.1mm
.275" .275"
.093.003" 6.99mm MAX .093.003" 6.99mm MAX
2.36.076mm 2.36.076mm
1.609.010" 1.609.010"
40.9.254mm .156.002" 40.9.254mm .156.002"
.320".010" 3.96.051mm .320".010" 3.96.051mm
8.13.25mm .200.002" Dia. 8.13.25mm .200.002" Dia.
5.08.051mm 2 Holes 5.08.051mm 2 Holes
1.630.010" 1.630.010"
41.4.254mm 41.4.254mm
1.200.005" 1.200.005"
30.48.127mm 30.48.127mm
Pin 1 I.D. Pin 1 I.D.

No radius and No radius and
Notch .10" Dia. Notch .10" Dia.
(2.54mm Dia.) (2.54mm Dia.)
Bottom Bottom
1.959.005" View 1.959.005" View
49.76.127mm 49.76.127mm
PIN DIAMETER: .584/.686mm or .023/.027" PIN DIAMETER: .965/1.067mm or .038/.042"

PIN LENGTH: 11.43/12.70mm or .450/.500" PIN LENGTH: 11.43/12.70mm or .450/.500"
PIN MATERIAL, STD: Nickel plated steel PIN MATERIAL, STD: Nickel plated steel
PACKAGE: Hermetic, nickel plated steel PACKAGE: Hermetic, nickel plated steel
WEIGHT: 53 g or 1.87 oz WEIGHT: 53 g or 1.87 oz
ISOLATION: 1200VDC any pin to case ISOLATION: 1200VDC any pin to case
CAGE JACKS: N/A CAGE JACKS: N/A
MATING SOCKET: MS06 MATING SOCKET: MS06
HEATSINK: HS06, HS11 HEATSINK: HS06, HS11
CAUTION CAUTION
Recommended mounting torque is 8-10 inlbs (.90 - 1.13 Nm) Recommended mounting torque is 8-10 inlbs (.90 - 1.13 Nm)
412
OUTLINE
DIMENSIONS POWER DIP PACKAGES
JEDEC MO-127 (STD) & MO-127 COPPER MO-127 HIGH PROFILE
PA04 DB2805SA
USA BeO USA BeO

AZ5059013 AZ5059013
NOTE: Notch on package denotes pin 1 location. NOTE: Notch on top of package denotes pin 1 location.
1.57/1.58"
39.9/40.1mm 1.57/1.58"
2.309.010" 2.309.010" 39.9/40.1mm
58.65.25mm 1.43/1.42" 58.65.25mm
36.32/36.1mm 1.43/1.42"
36.31/36.1mm
(See
.090/.103" Below)
2.28/2.62mm 0.495.005"
12.57.127mm
.093.003"
2.36.076mm
1.609.010" .156.002"
.320".010" 40.9.254mm
8.13.25mm 3.96.051mm
.200.002" Dia.
5.08.051mm 2 Holes 1.609.010" .156.002"
.320".010" 40.9.254mm
8.13.25mm 3.96.051mm
.200.002" Dia.
5.08.051mm 2 Holes
1.630.010"
41.4.254mm
1.200.005" 1.630.010"
30.48.127mm 41.4.25mm
1.200.005"
Pin 1 I.D. 30.48.127mm
No radius and
Notch .10" Dia.
(2.54mm Dia.) Pin 1 I.D.
1.959.005" Bottom
View No radius and
49.76.127mm Notch .10" Dia.
PIN DIAMETER: 1.47/1.57mm or .058/.062"

(2.54mm Dia.)
1.959.005" Bottom E
49.76.127mm View
PIN LENGTH: 11.43/12.7mm or .450/.500"
PIN MATERIAL, STD: Nickel plated steel
PIN DIAMETER: 1.47/1.57mm or .058/.062"
ISOLATION: STANDARD: 1000VDC any pin to case
PIN LENGTH: 11.43/12.7mm or .450/.500"
COPPER: 300VDC any pin to case
PIN MATERIAL, STD: Nickel plated steel
HEIGHT: STANDARD: 7.37mm OR .275" MAX
ISOLATION: 1000VDC any pin to case
COPPER: 8.89mm OR .350" MAX
PACKAGE: Hermetic, nickel plated steel
PACKAGE: STANDARD: Hermetic, nickel plated steel
WEIGHT: 54 g or 1.90 oz
COPPER: Base: Nickel plated copper
CAGE JACKS: APEX PN: MS04 (Set of 12)
WEIGHT: STANDARD: 53 g or 1.87 oz
MATING SOCKET: APEX PN: MS05
COPPER: 58 g or 2.05 oz
HEATSINK: APEX PN: HS06, HS11
CAGE JACKS: APEX PN: MS04 (Set of 12)
MATING SOCKET: APEX PN: MS05
HEATSINK: APEX PN: HS06, HS11 CAUTION
Recommended mounting torque is 8-10 inlbs (.90 - 1.13 Nm)
CAUTION
Recommended mounting torque is 8-10 inlbs (.90 - 1.13 Nm)
413
OUTLINE
SINGLE IN-LINE PACKAGES DIMENSIONS
SIP02
PA46
5962- XXXXX
CC2689847
USA 60024
SIP03
SA09
5962- XXXXX
CC2689847
USA 60024
414
OUTLINE
DIMENSIONS SINGLE IN-LINE PACKAGES
SIP10 PA42 SIP12

5962- XXXXX
CC2689329 PA26
USA 60024 USA
KB6739313
Hole dia .180" Max

.150 .006" 4.57mm
.175" Max 3.81 .13mm .050" .006
4.445mm 1.26" Max 1.27 .13mm
32.0mm .235"
1.020" Max
25.9mm .02" .77 .006" 5.96mm .118 018"
.51mm 19.56 .13mm 2.99 .45mm
.025" Max
.635mm
.140"
3.56mm
.520"
13.2mm .555 015"
.365" 14.1 .38mm
9.27mm
1 1
.260" .030 .290" .021 .003"

6.6mm .76 .110" Max 7.37mm .525 .065mm
2.794mm MIN.
1 2 3 4 5 6 7 8 9 10 11 12
.050 .015" .025 .005"
.010" .002 1.27 .38mm .635 .125mm
.019" .002 .254mm .051
.483mm .051 .075"
.100 .010" 1.90mm
2.54 0.25mm
.030" .100" .005
.76mm 2.54mm .127 PIN PLATING: Solder
PACKAGE: Plastic
WEIGHT: 5.6g or 0.2 oz.
PIN PLATING: Solder
PACKAGE: Hermetic, glass seal ceramic
WEIGHT: 2.8 g or 0.1 oz
MATING SOCKET: MS06 CAUTION
Recommended mounting torque is 4-8 inlbs (.45 - .909 Nm)
415
OUTLINE
SURFACE MOUNT PACKAGES DIMENSIONS
PSOP1
416
OUTLINE
DUAL IN-LINE PACKAGES DIMENSIONS
DIP5 DIP6
DIP6
DIP5
5962 - 1234567890
MB3 0 9 0 37 2 7 5 7
5962 - 1234567890
USA B eO
MB3 0 9 0 37 2 7 5 7
600 24
USA B eO
600 24
417
OUTLINE
DIMENSIONS DUAL IN-LINE PACKAGES
DIP7 DIP8
DIP8
DIP7
5962 - 1234567890
5962 - 1234567890 MB3 0 9 0 37 2 7 5 7
MB3 0 9 0 37 2 7 5 7 USA B eO
USA B eO 600 24
600 24
without notice.
418 PKGU REV. K DECEMBER 1998 1998 Apex Microtechnology Corp.

HEATSINKS, MATING SOCKETS, WASHERS, VENDORS
ACCESSORIES INFORMATION
RECOMMENDATIONS FOR THERMALLY

CONDUCTIVE WASHERS
Apex TW03, TW05, and TW10 (which are available from it is recommended to sleeve, with Teflon tubing, all pins. Table
Power Devices in a material known as Thermstrate) provide 2 lists the recommended Teflon tubing and some suggested
thermal conductivity better than thermal grease. They are manufacturers (for manufacturers phone numbers, see Ven-
electrically conductive but this is not a problem with the dors for Power Op Amp Accessories).
isolated cases of Apex amplifiers. In addition they are a non-
compressible washer of 3 mils thickness. PA26 thermal washer, TUBING DIMENSIONS
TW12, provides both thermal conductivity and electrical isola- PIN Nominal I.D. Nominal O.D. MFG.
tion.
DIAMETER Inches mm Inches mm MFG. PART NO.
In applications where electrical isolation is required the
Power Devices Isostrate or Crayotherm provides thermal .025" .028 .711 .052 1.321 TSI-S22
conductivity equal to a mica washer with grease and meets TFT-250-22
Apex requirement of being non-compressible. Apex does not .040" .042 1.067 .074 1.88 TSI-S18
supply these washers but considers them acceptable from a
warranty standpoint. TFT-250-18
Use of any other make/model of washer than these, or any .060" .066 1.676 .098 2.489 TSI-S14
compound other than thermally conductive grease will void the TFT-250-14
warranty. If you have questions or concerns regarding these
recommendations, please contact Apex Applications Engi-
neering at 1-800-546-APEX (1-800-546-2739). Table 2: Teflon tubing. SPC Technology
Alpha Wire Corp.
HEATSINK THRU-HOLES Teflon meets all known requirements but many other mate-
Custom heatsink manufacture or mounting of the Apex rials will work fine in some applications if three requirements
power amplifier to a bulkhead for heatsinking, requires the use are met. The tubing must fit the pin and the heatsink hole, it
of individual heatsink thru-holes for the external connection must be rated for the maximum voltage of the application and
pins. For the 8-pin TO-3 package the main path for heat flow it must be rated for the temperature extremes of the applica-
occurs inside the circumference of 8 pins. (Refer to Figure 1) tion. Simply stripping the insulation from #14, #18 or #22 wire
may be a viable tubing source.
Therefore, a single large
hole, (to allow the 8 pins to HEATSINKS
pass through), will remove A wide spectrum of applications can be satisfied with the
the critical heatsink material heatsinks stocked as accessories for APEX power amplifiers.
from where it is most needed. All are made of aluminum to provide high levels of conduction.
Instead, 8 separate holes HS01 clamps over the TO-3 case using virtually no additional
must be drilled. Refer to space on a printed circuit board. Some are suitable for chassis
Table 1 for recommended or printed circuit mounting. Some are designed for chassis
drill sizes for heatsink thru- mounting only. The HS09 is a second source for 0803HS from
Fig. 1: Main heat flow path,
holes for Apex power ampli-
8-pin to TO-3 package. Burr-Brown. The HS11 provides the most protection for
fier packages.
prototyping or for production of high power products. The
PIN RECOMMENDED HOLE DIAMETER HS21 can be used for the DHC line of DC-DC converters in E
DIAMETER DRILL SIZE INCHES mm conjunction with the CLAMP03 mounting clamp. All heatsinks
.025" #50 .070.002 1.781.051 are pre-drilled with hole patterns as shown. Conservative
.040" #46 .081.002 2.057.051 calculations are recommended for prototype work while per-
.060" #37 .104.002 2.642.051 formance graphs are included to enable optimization for pro-
duction runs. Due to calculation complexity of thermal circuits
Table 1: Heatsink thru-hole sizes. and of power dissipation levels where reactive loads are
driven, it is often helpful to utilize temperature measurements
TEFLON TUBING after the electrical design has been completed.
Ratings are all thermal resistances from amplifier mounting
Anodized heatsinks can be easily nicked or scratched, surface to ambient expressed as C/W. Rating 1 is for an
exposing bare aluminum, which is an excellent electrical unobstructed mounting of optimum orientation, running at high
conductor. When mounting the Apex power amplifier using a temperature. Refer to performance graphs to obtain tempera-
socket, it is recommended to sleeve, with Teflon tubing, a ture rise at lower power levels. Rating 2 pertains to forced air
minimum of two opposite pins. This centers the external
connection pins in the heatsink thru-holes and prevents elec-
trical shorts when tightening the power amplifier down on a
heatsink. When soldering directly to external connection pins Individual heatsink ratings shown on following page.
419
ACCESSORIES
HEATSINKS INFORMATION
C
L
at a velocity of 100 FPM and Rating 3 is for 200 FPM. For HS09
further details consult individual heatsink graphs.
APEX PN RATING 1 RATING 2 RATING 3
HS01 11.6 6.0 4.2
C 1.29"
HS02 4.5 3.2 2.5 TOP VIEW L 32.8mm
HS03 1.7 1.4 1.0
HS04 .95 .57 .44
HS05 .85 .7 .53
1.63"
HS06 .96 .72 .51 Material: Aluminum 41.4mm
HS09 11.7 6.6 Finish: Black Anodized
HS11* .68 Approximate Weight: .36 oz SIDE VIEW
HS13 1.48 1.1 .77

HS14/16 2.0 1.47 1.04 0.09" 0.75"
2.3mm 19.1mm
HS15 11.7 4.3
HS17 1.4
HS18 1.0
HS19 1.0 A B C D
100
DESCRIPTION
* HS11 efficiency improves for water cooling.
ABOVE AMBIENT (C)
80 FREE OF CURVES
CASE TEMP. RISE
AIR A. N.C. Horiz. & Vert

with Dissipator
60
(Free Air)
B. 200 FPM w/ Diss.
40 C. 500 FPM w/ Diss.
D. 1000 FPM with Dissipator
20
0
0 4 8 12 16 20 24 28
POWER DISSIPATED (WATTS)
1.187" .29" DIA.
HSO1 30.15mm 7.37mm
.880-.945" DIA.
22.35-24.0mm HS02 1.81" .02
45.97mm .51
.156" .017 1.5" .017
1.062" .187" 3.96mm .43 38.1mm .43
26.98mm 4.75mm
.281"
45.97mm .51
7.14mm
38.1mm .43
1.5" .017
1.81" .02
1.560" .152" DIA

39.62mm 3.86mm CL
.265 MIN.
6.73mm
1.0" 1/64"
25.4mm
.125" 1.5" CL
3.17mm .031
38.1mm .147" .005
Approximate Weight: 0.6 oz 3.73mm DIA.
Approximate Weight: 1.89 oz (4)
THERMAL RESISTANCE FROM MOUNTING

MOUNTING SURFACE TEMPERATURE
AIR VELOCITY - FEET PER MINUTE

SURFACE TO AMBIENT C/WATT

0 200 400 600 800 1000

100
RISE ABOVE AMBIENT C
20 0 200 400 600 800 1000

100
10
80 16
80 8
60 12
60 6
40 8
40 4
20 4
20 2
0 0
0 1 2 3 4 5 0 0
HEAT DISSIPATED - WATTS 0 5 10 15 20 25
HEAT DISSIPATED - WATTS
420
ACCESSORIES
INFORMATION HEATSINKS
.460" .420"
HS03 11.68mm HS04 10.67mm
.190" .010
4.83mm
1.25"
.015 .324" .012
31.75mm 8.23mm
3.00"
1.335" .050
.035 76.2mm
33.9mm
3.935 .060
99.95mm
1.335"
.035
4.75" .064 33.9mm
120.65mm
4.75" .062
120.65mm
3.0" .015 2.5" .010

76.2mm 63.5mm
3.0" .015 2.0" .010

76.2mm 50.8mm
4.36" .015
110.74mm
Mounting Holes (4):
.190" .006 DIA Slot
4.83mm 4.345" .030
110.36mm
.500"
Approximate Weight: 5.6 oz Mounting Holes (8): 12.7mm
.190" .006 DIA Slot
4.83mm

0 200 400 600 800 1000 Approximate Weight: 12 oz

100
2.0

80 1.6

60 1.2 0 200 400 600 800 1000
100
0.5
40 0.8 80 0.4
20 0.4 60 0.3
E
0 0
0 10 20 30 40 50 40 0.2
20 0.1
0 0
0 20 40 60 80 100
421
ACCESSORIES
.460"
HS05 11.68mm HS06 6.25"
158.75mm
.190" 2.312"
.010 58.72mm
4.83mm
2.63" .030
66.8mm
2.00"
50.8mm
.125"
3.18mm
1.335" 54.6 sq."/1" 3.3 lb/1' 1.3 C/W/3"

.035
33.91mm
3.94" .060
100.01mm
4.75" .060
120.65mm
4.5" .010 1.96"

114.3mm 49.78mm
5.5" .020
139.7mm
5.5" .015 5.00" .010
139.7mm 127mm
1.9"
.010
48.26mm
DEVICE PATTERN
4.36" .015 2 HOLES 12 HOLES 4 HOLES
110.74mm 0.156 DIA. 0.100 DIA. 0.190 DIA.
.250" 0.005 0.005 0.005
Mounting Holes (4): 6.35mm 3.96mm 2.54mm 4.83mm
.190" .006 DIA Slot
4.83mm
Standard Commercial
Approximate Weight: 18.3 oz Extrusion Tolerances Apply
Material: Aluminum Alloy
Finish: Black Anodize
Thermal Resistance: .96C/W


0 200 400 600 800 1000 Approximate Weight: 19.8 oz

100
1.0
THERMAL RESISTANCE
80 0.8
THERMAL RESISTANCE (C/W)
0.8
60 0.6
0.6
40 0.4
20 0.2 0.4
0 0
0 20 40 60 80 100 0.2
0
0 200 400 600 800 1000 1200
AIR FLOW (FT/MIN)
AMBIENT AIR TEMPERATURE 25C
422
ACCESSORIES
1.959"
49.76mm
HS11 1.2"
30.48mm
CL
1.5"
38.1mm
1.5"
38.1mm
6.0"
152.4mm
5.50" CL
139.7mm
1.5"
38.1mm
R
.10"
2.54mm
.2" 5.08mm
7.80"
.50" 198.12mm
12.7mm 8.0"
203.20mm
2.51"
63.75mm
2.0"
50.80mm
.125" .438"
3.18mm 11.13mm
.545" .33"
DIA. CHANNEL
13.84mm
Approximate Weight: 44.8 oz
.16 E
.15
.14 R SA = .675 C/W (Free air vertical)

R SW (C/W)**
R SW = .102 C/W (Water cooled @ 1 GPM per channel)

.13
Additional mounting loss (with Apex thermal washers):
MO-127: .05 C/W
.12 TO-3: .1 C/W
PD10: .08 C/W
.11 * BOTH CHANNELS FED IN PARALLEL USING CLEAN WATER
** R SW = THERMAL RESISTANCE FROM HEATSINK TO WATER
.10
.09
0 1 2 3 4
FLOW RATE (GPM PER CHANNEL)*
423
ACCESSORIES
HS13/HS14/HS16 HS15 FOR SIP10/SIP12 PACKAGE
1.312" .406"
33.3mm 10.3mm
1.312" .015
33.3mm .381
1.25" .400" MAX

31.75mm 10.16mm
.156" .010 .078"
.250" 3.96mm .254 1.98mm
Mounting Holes (4):
6.35mm .190" .006 DIA
4.83mm
1.70" .015
43.18mm .38
.040"
1.02mm
TO-3
.260"
6.6mm
A B .400"
10.16mm .5"
12.7mm
.097"
2.46mm 1.15" .125" Max
29.21mm 3.18mm
PD10

0 200 400 600 800 1000
CASE TO AMBIENT C/WATT

100
THERMAL RESISTANCE FROM

5
CASE TEMPERATURE
.203" 4.41" .015 80 4

5.16mm 112.01mm .381
4.81" .064 60 3
122.17mm .163
40 2
MODEL DIMENSION A DIMENSION B WEIGHT
20 1
HS13 5.50" .015 5.00" .010 13.9 oz
139.7mm .381 127mm .254 0 0
0 2 4 6 8 10
HS14 3.00" .015 2.50" .010 7.6 oz
76.2mm .381 63.5mm .254
HS16 Same as HS14 but with PD10 hole pattern.
Material: Aluminum
Finish: Black Anodize
Standard Commercial Extrusion Tolerances Apply Tabs are tinned and solderable
Material: Aluminum Alloy Finish: Black Anodize Approximate Weight: 0.3 oz
Thermal Resistance: 1.48C/W (HS13)
2C/W (HS14/16)
THERMAL RESISTANCE
THERMAL RESISTANCE (C/W)
1.6
1.4
1.2
1
0.8 HS14/16
0.6
0.4
HS13
0.2
0
0 200 400 600 800 1000 1200
AIR FLOW FT/MIN
AMBIENT AIR TEMPERATURE 25C
424
ACCESSORIES
HS17
NOTE:
Made from Aavid extrusion 61265.
Hole pattern is centered in heatsink both horizontally and vertically in each channel.
Finish: Black anodize E
Thermal resistance = 1.4C/W
Approximate weight: 9.3 oz
425
ACCESSORIES
HS18
.150 .007
.210 .007
NOTE:
Hole pattern is centered in heatsink both horizontally and vertically.
Finish: Black anodize
RSA = 1C/W
426
ACCESSORIES
HS19
NOTE:
Hole pattern is centered in heatsink both
horizontally and vertically.
Finish: Black anodize
RSA = 1C/W
427
ACCESSORIES
HS20
NOTES:
1. MADE FROM THERMALLOY EXTRUSION 15210
2. FINISH IS BLACK ANODIZE
3. RSA = 1.3 C/W
428
ACCESSORIES
HS21
429
ACCESSORIES
CAGE JACKS & MATING SOCKETS INFORMATION
REFER TO APPLICATION NOTE 11 FOR MOUNTING TECHNIQUES USING CAGE JACKS AND MATING SOCKETS
MS02/CAGE JACK MS04/CAGE JACK

(Package of 8 for PC board insertion) (Package of 12 for PC board insertion)
.040" DIA. PINS 8-PIN TO-3 PACKAGE .060" DIA. PINS POWER DIP PACKAGES
PD10/60S MO-127
.090"
2.29mm .221" .120"
5.61mm .003 .195" .018"
3.05mm 4.95mm .457mm
Knockout .073"
.002 .098"
Bottom 1.85mm .002
2.49mm
DIA
Recommended Mounting Hole: .076".002 DIA (#48 Drill) Recommended Mounting Hole: .102".002 DIA (#38 Drill)
Minimum Insertion Depth: .10 Hole Depth: .200 Minimum
MS03/MATING SOCKET
.040" DIA. PINS 8-PIN TO-3 PACKAGE
.5" .160" (4.06mm)

DIA. DIA thru
12.7mm CSK 82 x .290" (7.37mm) MS05/MATING SOCKET
40 DIA (2 holes)
TYP .060" DIA. PINS POWER DIP PACKAGES
MO-127
40
.156" (3.96mm)
DIA thru 1.96"
5/16 1.00" 49.78mm
HEX .010 CSK 82 x
TYP 25.4mm .280" (7.11mm)
DIA (2 holes) .20"
5.08mm
(TYP)
1/4
.31" DIA HEX
HOLE (TYP)
7.87mm 1.187" .005
30.15mm 1.20"
30.48mm
.75"
1.68" 1.50" 19.05mm
.010 38.1mm
42.67mm
.350
.010 1.25"
8.89mm .670" 31.75mm
.090" 17.02mm
2.36"
2.29mm 59.94mm
.120 TYP .12"
3.05mm .170" (4.32mm) Min. 3.05mm .19" (4.83mm)
Insertion Depth MAX (THROUGH CLIP)
(TYP)
.520" (13.21mm) Min.
Cavity Depth .37" .67"
Contacts: 9.4mm .52" 17.02mm
13.21mm
Resistance: .020 MAX MIN
Contact Body: Brass .02" .51mm
STANDOFF .1"
200/300 in. Tin over 100/150 in. Nickel (6 PLCS) 2.54mm
Inner Contact Clip: BeCu CONTACT
30 in. Gold over 50 in. Nickel CAVITY
DEPTH
Socket Body: Polyester, Glass Filled, 94 VORating Contacts:Resistance: .020 MAX
Color: Green Contact Body: Brass
Operating Temperature Range: 55C to +125C 200/300 in. Tin over 100/150 in. Nickel
Inner Contact Clip: BeCu
30 in. Gold over 50 in. Nickel
CAUTION Socket Body: Polyester, Glass Filled, 94 VORating
Combined heat and force during hand soldering plastic mating Color: Green
sockets can unseat pins and cause shorts to the header. Operating Temperature Range: 55C to +125C
430
ACCESSORIES
INFORMATION CAGE JACKS & MATING SOCKETS
REFER TO APPLICATION NOTE 11 FOR MOUNTING TECHNIQUES USING CAGE JACKS AND MATING SOCKETS
MS06/MATING SOCKET
.025" DIA. PINSMO-127 HIGH VOLTAGE
.118"
3.0mm
.173"
4.39mm
.120"
3.05mm
.055"
1.4mm
.020" .51mm DIA
19 EQUAL SPACES @ .100"

.100" 2.54mm 2.54mm
= 1.9" 48.26mm
2" .052"
50.8mm 1.32mm
Body: Black polyester, glass filled

Contacts: Beryllium Copper
Shell: Half Hard Brass
PCB Hole: .035" .002", .889mm .051mm
Insulation Resistance: 5000 megohms minimum
Dielectric Withstanding Voltage: 500 volts AC
Flammability: UL 94V-0
Temperature Range: -65C to +125C
S = Solder Tail
TG = 10 inch (.254m) minimum
Gold on contact area
200 inch (5.08 m) minimum Tin on terminal area
50 inch (1.27m) minimum Nickel underplate
Also suitable for SIP10 packages.
Not suitable for SIP12 packages.
431
ACCESSORIES
THERMAL WASHERS INFORMATION
Part Number TW02 TW03 TW05 TW10 TW12

Thermal Resistance .08C/W .1C/W .05C/W .08C/W .2C/W
Package Quantity 10 10 10 10 15
CAUTION
Do not store unused thermal washers above 45C. A new
washer must be used for each mounting.
TW02/THERMAL WASHER TW05/THERMAL WASHER

FOR 18-PIN DIP7 PACKAGE FOR MO-127 PACKAGE
1.609.010" .156.002"
40.9.254mm 3.96.051mm
.140" Dia. .200.002" Dia.
3.56mm 5.08.051mm 2 Places
12 Places
1.64"
41.66mm
1.200.005"
30.48.127mm
1.959"
49.76mm
2.32"
58.92mm
.480"
12.19mm
TW03/THERMAL WASHER
FOR 8-PIN T0-3 PACKAGE
40 NOTE:
TYP
1. Base material of TW12 is Kapton Type MT (over twice
6 7 the thermal conductivity of standard type HN Kapton).
8 Base material of other washers is aluminum. Total
5 thickness of all washers is .003".
1.05" 80 TYP
26.7mm 2. For optimum thermal transfer, avoid abrasive handling of
4
washers which can damage their .5 mil thick layer of dry
3 1 thermal compound with which each side is coated.
2
3. The dry thermal compund will flow filling header to
heatsink voids as soon as the material reaches 51C.
.156"
3.96mm 1.187"
DIA 2 HOLES 30.15mm
1.550"
39.37mm
PIN CIRCLE DIAMETER .500" OR 12.7mm

PIN DIAMETER .090" or 2.29mm
432
ACCESSORIES
INFORMATION THERMAL WASHERS
TW10/THERMAL WASHER
FOR PD10/60S PACKAGE
TW12/THERMAL WASHER
FOR 12-PIN SIP12 PACKAGE
.295" .77" .295"

7.49mm 19.59mm 7.49mm
.73"
18.54mm .56" .140 .002"
14.22mm 3.56 .051mm
(2)
1.36" E
35.54mm
TW12 is an electrical insulator.
433
ACCESSORIES
HARDWARE KITS INFORMATION
HK26/HARDWARE KIT HK03/HARDWARE KIT

FOR 12-PIN SIP12 PACKAGE CLAMP FOR FLANGELESS PACKAGES
F
NOTES:
G One HK03 includes two clamps.
Material: .048 thick 304 stainless
CLAMP03/HARDWARE KIT
CLAMP FOR DHC DC/DC CONVERTERS
ITEM DESCRIPTION QUANTITY
A 4-40 x 7/16" Screws 2
B PA26 (not supplied)
C TW12 Washer 1
D Heatsink (not supplied)
E Shoulder Washer* 2
F Lockwasher 2
G 4-40 Nuts 2
* Keystone Part Number 3049

Nylon 6/6 per ASTM D4066
.135"
.031"
.218" .040"
.115" DIA
434
ACCESSORIES
INFORMATION ACCESSORIES VENDORS
Semtech
VENDORS FOR POWER AMPLIFIER ACCESSORIES 652 Mitchell Road
Newbury Park, CA 91320
The following list answers the most common requests (805) 498-2111 Fax (805) 498-3804
received on the APEX Applications Hotline. It is by no means http://www.semtech.com
a complete list of sources, but can save you valuable time
locating requirements not found in the Apex data book. HEATSINKS
CAGE JACKS AAVID Engineering , Inc.
3030 Kilson Drive
Concord Electronics Corp. Santa Ana, CA 92707-4203
30 Great Jones St., New York, NY 10012 (714) 556-2665 Fax (714) 556-5140
(212) 777-6571 Fax (212) 995-0161 http://www.aavid.com
http://www.concord-elex.com
Wakefield Engineering
Mill-Max Manfacturing Corp. 60 Audubon Rd.
190 Pine Hollow Road Wakefield MA 01880
Oyster Bay, NY 11771 (617) 245-5900 Fax (617) 246-0874
(516) 922-6000 Fax (516) 922-9253 http://www.wakefield.com
http://www.mill-max.com
International Electronic Research Corp.
FAST DIODES 135 W. Magnolia Blvd.
Burbank, CA 91502-7704
Fagor Electronic Components
(818) 842-7277 Fax (818) 848-8872
18 Railroad Ave.
Andover, MA 01810 Thermalloy, Inc.
(508) 474-8765 2021 W. Valleyview Lane
Dallas TX 75234-9990
General Instrument
(888) HEATSINK Fax (214) 241-4656
10 Melville Park Road
http://www.thermalloy.com
Melville, NY 11747-3113
(516) 847-3000 Fax (516) 847-3022
http://www.gensemi.com HIGH VOLTAGE SUPPLIES
International Power
Harris Semiconductor 360 Bernoulli Circle
1301 Woody Burke Rd. Oxnard, CA 93030-5167
Melbourne, FL 32902 (805) 981-1188 Fax (805) 981-1184
(800) 4-HARRIS Fax (407) 729-5692
http://www.semi.harris.com Pacifitek
6150 Mission Gorge Road, Suite 134
MicroSemi San Diego, CA 92120
2830 Fairview St. (619) 285-5858 Fax (619) 285-5859
Santa Ana, CA 95054 http://www.pacifitek.com
(714) 979-8220 Fax (714) 557-5989
http://www.microsemi.com Piezo Systems Inc. E
186 Massachusetts Ave.
Motorola Cambridge, MA 02139
2100 East Elliot, Tempe, AZ 85284 (617) 547-1777 Fax (617) 354-2200
(800) 521-6274 http://www.piezo.com/apex
Philips Components Power-One Inc.
Discrete 740 Calle Plano
Semiconductor Group Camarillo, CA 93012
100 Providence Pike (800) 678-9445 Fax (805) 388-0476
Slatersville, RI 02876 http://www.power-one.com
(800) 234-7381 Fax (401) 767-4493
http://www.semi-conductors.philips.com UltraVolt, Inc. (DC/DC Converters)
CS 9002
Siliconix Ronkonkoma, NY 11779-9002
2201 Laurelwood Road (800) 948-POWER Fax (516) 471-4696
Santa Clara, CA 95056
(800) 554-5565 Fax (408) 567-8995
http://www.temic.com Continued on following page
435
ACCESSORIES
INFORMATION ACCESSORIES VENDORS
Continued from previous page
HIGH WATTAGE SUPPLIES TEFLON TUBING

Dynapower Corp. Alpha Wire Corp.
P.O. Box 3180, Farmington Hills, MI 48333 711 Lidgerwood Avenue
(810) 471-1800 Elizabeth, NJ 07207-0711
(800) 522-5742 Fax 1 (800) 826-6602
Pacifitek http://www.alphawire.com
6150 Mission Gorge Road, Suite 134
San Diego, CA 92120
(619) 285-5858 Fax (619) 285-5859 THERMAL GREASE
http://www.pacifitek.com Thermalloy, Inc.
2021 W. Valleyview Lane
Dynapower Corp. Dallas TX 75234-9990
P.O. Box 3180, Farmington Hills, MI 48333 (888) HEATSINK Fax (214) 241-4656
(810) 471-1800 http://www.thermalloy.com
Power Ten
120 Knowles Drive THERMALLY CONDUCTIVE WASHERS
Los Gatos, CA 95030 Power Devices, Inc.
(408) 871-1700 Fax (408) 871-1790 26941 Cabot Road
http://www.powerten.com Building 124
Laguna Hills, CA 92653
Sorensen Company (714) 582-6712 Fax (714) 582-6722
9250 Brown Deer Road http://www.powerdevices.com
San Diego, CA 92121
(800) 525-2024 Fax (619) 458-0237
http://www.sorensen.com VOLTAGE TRANSIENT SUPPRESSORS
General Instrument
LOW VALUE RESISTORS 10 Melville Park Road
Melville, NY 11747-3113
Caddock Electronics, Inc. (516) 847-3000 Fax (516) 847-3022
1717 Chicago Avenue http://www.gensemi.com
Riverside, CA 92507
(909) 788-1700 Fax (909) 369-1151 Motorola
http://www.caddock.com 2100 East Elliot
Tempe, AZ 85284
Vishay Dale Electronics (602) 244-6900 Fax (602) 897-4171
1122 23rd Street
Columbus, NE 68601-3647 MicroSemi
(402) 563-6283 Fax (402) 563-6418 2830 Fairview St.
http://www.vishay.com Santa Ana, CA 95054
(714) 979-8220 Fax (714) 557-5989
IRC Wire and Film Technologies Division http://www.microsemi.com
736 Greenway Road, P.O. Box 1860
Boone, NC 28607 Semtech
(704) 264-8861 Fax (704) 264-8865 652 Mitchell Road
Newbury Park, CA 91320
Riedon Division (805) 498-2111 Fax (805) 498-3804
M.W. Riedel & Co., 300 Cypress Ave. http://www.semtech.com
Alhambra, CA 91801-1221
(818) 284-9901 Fax (818) 282-3836 NOTE:
http://www.riedon.com Many of the above items can be purchased in small quantities
through distributors such as:
RESISTANCE WIRE
Newark Electronics
MWS Wire Industries (800) 4-NEWARK Call for local branch office.
31200 Cedar Valley Drive, Westlake Village CA 91362 http://www.newark.com
(888) 697-9473 Fax (818) 706-0911
http://www.mwswire.com
This data sheet has been carefully checked and is believed to be reliable, however, no responsibility is assumed for possible inaccuracies or omissions. All specifications are subject to change without notice.
HS01U REV. U JANUARY 1999 1999 Apex Microtechnology Corp.
POWER AMPLIFIERS/PWM AMPLIFIERS/DC-DC CONVERTERS
PRODUCT MARKING
TO-3, LINE 1
P A 1 2M / 8 8 3
MO-127 SERIES,
DIP SERIES
LINE 2
LINE 3
5962 - X X X X X XX X X X
LINE 4
MB3 0 9 Q 9 8 3 7
LINE 5
USA B eO
LINE 6
600 24
LINE 1
SMD* Parts: Apex Model Number
Standard Parts: Apex Model Number
Custom Parts: Blank
LINE 2
All Parts: APEX logo
LINE 3
SMD Parts: DSCC SMD Part Number
Standard Parts: Blank
Custom Parts: APEX Model Number
LINE 4
All Parts: Lot Code Compliance Indicator Date Code
MB309 Q 9837
Operators Lot Q = DSCC QML Compliant 1998 Work Week 37

Initials Number C = MIL-H-38534 Compliant
None = Not Compliant
E
LINE 5
All Parts: USA (or) USA BeO
ESD & Pin 1 ESD & Pin 1 BeO

Identifier Identifier Identifier
LINE 6
All Parts: 60024 = APEX CAGE Code
* SMD = Standardized Military Drawing
437
PRODUCT MARKING
SIP10 LINE 1
PACKAGE PA42
LINE 2
5962- XXXXX
LINE 3
CC2689829
USA 60024
LINE 4
ESD & Pin 1

Identifier
LINE 1 LINE 2
SMD* Parts: Apex Model Number SMD Parts: DSCC SMD Part Number
Standard Parts: Apex Model Number Standard Parts: Blank
Custom Parts: Blank Custom Parts: APEX Model Number
LINE 3
All Parts: Lot Code Compliance Indicator Date Code
CC 268 Q 9829
Operators Lot Q = DSCC QML Compliant 1998 Work Week 29

Initials Number C = MIL-H-38534 Compliant
None = Not Compliant
LINE 4
All Parts: 60024 = APEX CAGE Code
* SMD = Standardized Military Drawing
438
PRODUCT MARKING
SIP12
PACKAGE LINE 1
PA26
9829 LINE 2
Pin 1 ESD
Identifier Identifier
LINE 1 LINE 2
Apex Model Number All Parts: Date Code
9829
1998 Work Week 29
439
NOTES:
440
CUSTOMER
SERVICE
Ordering Information, Warranty, Terms & Conditions ............................................................... 442

Corporate Directory ................................................................................................................... 444
Sales Representatives .............................................................................................................. 445
Street Map Guide to Apex ......................................................................................................... 446
Subject Index ............................................................................................................................ 447
441
ORDERING INFO, LIFETIME WARRANTY, TERMS
CUSTOMER SERVICE
Evaluation Units, Small Quantity, Same

CALL THE APEX ORDER LINE 520-690-8601 Day Shipments Available From Stock
Call 7:00 a.m. to 5:00 p.m. (MST November-March and PST April-October, Monday-Friday) Technical Assistance and Support
To Place an Order Before and After the Sale
For Pricing and Delivery
For a Quote Same day shipping (On orders received
by noon MST, Monday-Friday)
24-HOUR FAX: 520-690-7749 E-MAIL: custserv@apexmicrotech.com
WEBSITE: http:// www.apexmicrotech.com
DOMESTIC ORDERS SOURCE INSPECTION AND SURVEYS

APEX MICROTECHNOLOGY ships most small orders from APEX supports Vendor Quality verification through surveys,
stock. If you need immediate delivery, call us direct before noon source inspections and audits. Source inspection must be
MST and specify EXPRESS service. We will make every effort requested at the time of order placement. Scheduling of source
to ship on the same day via air express. inspection within 5 working days is required. When product is
ready for source inspection, we will notify you by fax or tele-
EXPORT ORDERS phone. Standard charges apply if source inspection takes place
APEX F.S.C., the export arm of APEX MICROTECHNOL- within 5 working days after which extra charges will apply.
OGY, is represented worldwide by exclusive distributors who Please see Special Services on the current Apex Pricing &
offer technical assistance and/or data sheets, as well as speedy Ordering data sheet for specific charges.
delivery at competitive prices. Evaluation orders can be shipped
without delay to most countries. QUALITY
All APEX MICROTECHNOLOGY manufactured industrial
EVALUATION ORDERS grade products are functionally tested and visually inspected
EVALUATION orders are available. Please specify Evalua- (excluding high power die visual) prior to capping. After the
tion on your purchase order. Evaluation orders allow for up to package is hermetically sealed, static and dynamic final electri-
a quantity of three dc/dc converters or three amplifiers and three cal tests are performed. Final marking includes a lot code
mating sockets. If the components do not meet your needs; traceable to the flow sheets kept on record.
have not been damaged (used within specification); have not Military products are built in accordance with MIL-PRF-38534.
been soldered; and are returned to APEX within 30 days of the Quality Conformance Inspection is performed in accordance
invoice date, a credit will be issued. with MIL-PRF-38534 Option 1. Group A data is kept on file with
the production records. Generic In-line Group B, C and package
CUSTOMIZING APEX PRODUCTS evaluation data is on file. Please see Special Services on the
current Apex Pricing & Ordering data sheet for non-standard
APEX does customize standard models to meet specific cus-
data requirements charges.
tomer requirements. Available options range from custom mark-
ing through minor internal circuit changes. The following are PRODUCT WARRANTIES
examples of services performed: standard part plus burn-in, test
drift over wider temperature range, gradeout for improved voltage All hermetically packaged products manufactured by APEX
drift, customer part numbers up to 12 digits, individual test data MICROTECHNOLOGY are warranted to be free of manufactur-
and non-standard quiescent current trim. Custom orders usu- able defects when operated within the published specified oper-
ally involve a minimum quantity, a per shipment lot charge, ating conditions for the life of the equipment in which the APEX
and a per piece surcharge over the cost of the standard component is originally installed and purchased from APEX or an
model. Product ordered to a customer source control draw- authorized distributor. The warranty applies only to the original
ing (SCD), will incur additional unit and/or lot charges. customer, or the first system buyer of the original equipment from
an APEX customer. This warranty is in lieu of all other warranties,
TECHNICAL SUPPORT expressed or implied. Under no circumstances will APEX MICRO-
Technical assistance is available toll free from 6:00 a.m. to TECHNOLOGY be liable for any anticipated profits, consequen-
5:00 p.m. MST Monday-Thursday, 6:00 a.m. to 1:00 p.m. MST tial damages, loss of time or other losses incurred by the customer
Friday. APEX applications engineers are professionals with in connection with the purchase and/or use of the product. Apexs
extensive design experience. They can help you select the sole liability under this warranty is limited to, at Apexs sole
appropriate product, debug your design, and suggest design discretion, either replacing or repairing the defective product(s), or
approaches. Call toll free (800) 546-2739. refunding the original purchase price of said product(s). For
products housed in non-hermetic packages, the warranty
QML-38534 QUALIFICATION period is for one year from the date of invoice/shipment.
APEX MICROTECHNOLOGY CORP. is a DESC certified
and qualified QML-38534 facility. All qualified product is compli-
ant to MIL-STD-883, paragraph 1.2.1.c, and marked /883.
APEX is also listed on QML-38534.
MADE IN THE U.S.A.

442
ORDERING INFO, LIFETIME WARRANTY, TERMS
CUSTOMER SERVICE
FAILURE ANALYSIS
In case of failure under the warranty, PLEASE DO NOT LIFE SUPPORT POLICY. As a general policy, APEX MICRO-
RETURN the product without first calling the APEX Applications TECHNOLOGY CORP. does not recommend the use of any of
Hotline to explain the problem and receive a Return Material its products in life support applications where the failure or
Authorization number. Call toll free (800) 546-2739. malfunction of the APEX product can be reasonably expected to
The device will be tested, opened, and inspected visually to cause failure of the life support device or to significantly affect its
determine the cause of failure. A Failure Analysis will be safety or effectiveness. APEX will not knowingly sell its products
supplied free of charge. This information will help you maximize for use in such applications unless it receives written assur-
reliability and avoid a possible recurrence of the failure. ances satisfactory to APEX that the risks of injury or damage
have been minimized, the customer assumes all such risks, and
there is no product liability for APEX.
TERMS AND CONDITIONS Examples of devices considered to be life support devices are
SHIPMENTS F.O.B. is Tucson, AZ. For shipments via the neonatal oxygen analyzers, nerve stimulators (for any use), auto-
Postal Service a $6.00 surcharge will be added to the invoice. transfusion devices, blood pumps, defibrillators, arrhythmia detec-
Any delivery rescheduled with less than eight weeks notice will tors and alarms, pacemakers, hemodialysis systems, peritoneal
be charged a 2% surcharge for every month of delay. dialysis systems, ventilators of all types, and infusion pumps as
well as other devices designated as critical by the FDA. The
above are representative examples only and are not intended to be
LOST OR DAMAGED SHIPMENT. Contact the Common conclusive or exclusive of any other life support device.
Carrier and APEX at once. APEX MICROTECHNOLOGY is not
responsible for loss or damage in transit. APEX will supply proof
of shipment, thereby creating a legal obligation to pay the SPECIAL SERVICES PRICING
original invoice when due. Call the Apex Order Line at 520-690-8601 for special services
pricing: Data, Source Inspection, Special Testing, Marking and
PRODUCT RETURNS within 30 days of shipment, will be Packaging.
accepted only if prior authorization has been obtained from
APEX and the units have been used within the specified oper-
ating conditions. No solder residue should be on the pins.
Restocking charge is 25% for standard industrial products.
Custom and military products are not returnable.
PRICES are published in the current U.S. Apex Pricing &

Ordering data sheet along with custom processing charges.
Applicable state and local taxes will be added.
CANCELLATION CHARGES are 15% for standard prod-

ucts. For customized products they are:
25% if components purchase orders have been placed.
50% if parts assembly has been started.
75% if parts have been capped.
PAYMENT TERMS for approved accounts are net 30 days
from the date of shipment. C.O.D. for new accounts without
D & B rating. Past due accounts will be charged a .06% per
day late fee.
BILLING in duplicate is done on the day of shipment. Air

freight charges can be billed by the carrier directly to the
customer if requested.
443
HOURS OF OPERATION, TELEPHONE DIRECTORY
CORPORATE DIRECTORY
HOURS OF OPERATION
Mountain Standard Time (NovMarch)
Pacific Standard Time (AprilOctober) Day Greenwich Mean Time
Order Entry ............................ 7:00 a.m. to 5:00 p.m. ......................... Mon-Fri ............................... 14:00 to 24:00
Applications ........................... 6:00 a.m. to 5:00 p.m. ......................... Mon-Thur ............................ 13:00 to 24:00
6:00 a.m. to 1:00 p.m. ......................... Fri ........................................ 13:00 to 20:00
Manufacturing ....................... 6:00 a.m. to 4:30 p.m. ......................... Mon-Thur ............................ 13:00 to 23:30
All Other Departments ........... 7:00 a.m. to 4:00 p.m. ......................... Mon-Thur ............................ 14:00 to 23:00
7:00 a.m. to 1:00 p.m. ......................... Fri ........................................ 14:00 to 20:00
WEBSITE
http://www.apexmicrotech.com
MAILING AND SHIPPING ADDRESS INFORMATION FOR ALL DEPARTMENTS

APEX MICROTECHNOLOGY CORP. (Domestic)
APEX F.S.C. INC. (Export)
5980 N. Shannon Road
Tucson, AZ 85741-5230, USA
CORPORATE TELEPHONE INFORMATION

Apex Microtechnology Corp. is headquartered in Tucson, Arizona, U.S.A. All manufacturing, engineering,
sales and administrative departments can be reached at the telephone numbers listed below.
SWITCHBOARD
Connects to all departments
(520) 690-8600
E-MAIL
comments@apexmicrotech.com
GENERAL FAX, 24-HOURS
Orders/Customer Service, All Other Departments
(520) 888-3329
APPLICATIONS FAX
Applications Engineering
(520) 888-7003
APPLICATIONS ENGINEERING TOLL-FREE HOTLINE
Connects directly for calls from the U.S. & Canada
(800) 546-APEX (800-546-2739)
E-mail: support@apexmicrotech.com
PRODUCT LITERATURE TOLL-FREE HOTLINE
(800) 546-APEX (800-546-2739)
E-mail: prodlit@apexmicrotech.com
ORDER LINE, CUSTOMER SERVICE
(520) 690-8601
E-mail: custserv@apexmicrotech.com
SALES
(520) 690-8601
QUALITY
(520) 690-8623
ACCOUNTS RECEIVABLE
(520) 690-8655
444
DOMESTIC AND INTERNATIONAL
SALES REPRESENTATIVES
DOMESTIC SALES REPRESENTATIVES

To locate the Apex Sales Representative for your area, please visit our web site at http://www.apexmicrotech.com or call Apex
toll-free at 1-800-546-APEX (1-800-546-2739).
INTERNATIONAL SALES REPRESENTATIVES

International customers can obtain product literature, technical assistance, product sales and ordering support from our interna-
tional network of sales distributors. To contact the Apex Sales Distributor for one of the countires listed below, please visit our web
site at http://www.apexmicrotech.com or fax us at 520-888-3329 to request a copy of a current listing or our International Sales
Distributors.
AUSTRAILA, NEW ZEALAND

BELGIUM, LUXEMBOURG
CANADA
DAEHAN MINKUK (SOUTH KOREA)
DANMARK (DENMARK)
DEUTSCHLAND (GERMANY)
ESPAA (SPAIN)
FRANCE
HONG KONG
INDIA
ISRAEL
ITALIA (ITALY)
NEDERLAND (THE NETHERLANDS)
NIPPON (JAPAN)
NORGE (NORWAY)
STERREICH (AUSTRIA)
PEOPLE'S REPUBLIC OF CHINA
REPUBLIC OF SOUTH AFRICA
SCHWEIZ (SWITZERLAND)
SINGAPORE
SUOMI (FINLAND)
SVERIGE (SWEDEN)
TAIWAN, REPUBLIC OF CHINA (R.O.C.)
UNITED KINGDOM
445
To
Shannon Rd.
Florence
Tucson National
Resort & Spa
STREET MAP GUIDE TO APEX Club Dr.
Magee

Cortaro Farms Rd.
Magee
Approximately
110 miles to
Sky Harbor Airport
Phoenix, AZ 89
via I-10 West
I-1
0W
Ina Rd. Ina Rd.
Camino de la Tierra
ES
La Cholla Blvd.
La Caada Dr.
T
Shannon Rd.
Oracle Rd.
Mona Lisa
Thornydale
I-10
Orange Grove Rd.

Shannon
La Cholla Blvd.
Inte
rsta
te 1
0
Water
Tower
Oracle Jayn
es
Sta
I-10 .
Flowing Wells Rd.
Oracle Rd.
Riv
er R
d.
River Rd.
I-1
To
0W
Airport
ES
T
Ruthrauff
Approximately 15 miles to Orange Grove Exit Wetmore
I-10
DIRECTIONS FROM AIRPORT TO APEX

Tucson Blvd. to Interstate 10 West (follow signs).
Interstate 10 west approximately 15 miles to Orange
Follow signs to I-10 West
Grove exit. N
Orange Grove east to Shannon Road.
TUCSON BLVD.
1 Mile
Turn right (or south) on Shannon. Continue straight for
TUCSON
approximately 1/8 mile, then first available left turn INTERNATIONAL
followed by immediate right turn. AIRPORT
APEX is on the corner of Oracle Jaynes Station and

Shannon.
446
Subject Index
Absolute Maximum Specifications ................................................................................ 294, 319

AC Power Dissipation .................................................................................................... 297, 320
Accessories ......................................................................................................................... 419
Accessories Vendors .......................................................................................................... 435
Accuracy of Current Limit .............................................................................................. 295, 324
Active Loads ........................................................................................................................ 318
Advantages of Hybrids Over Discrete ................................................................................... 3
Amplifier Mounting ............................................................................................. 299, 327, 396
Amplifier Stability ............................................................................... 300, 337, 339, 359, 374
Analog Construction Techniques ...................................................................................... 396
Apex Quality .................................................................................................................. 14, 442
Application Note Subject Reference ..................................................................................... 293
Asymmetric Supply Operation ............................................................................................. 319
ATE Pin Driver .................................................................................................................. 168
Audio Amplifier ................................................................. 58, 98, 118, 124, 136, 307, 361
Bandwidth-Gain Trade-offs ................................................................................................. 336
Beat the Discrete Circuit ....................................................................................................... 3
Bias Current Matching Resistor .......................................................................................... 339
Bridge Circuit ................................................................................. 195, 277, 305, 312, 366
Bridge Circuit Basics ........................................................................................................... 359
Bridge Circuit Basics, PWM .............................................................................................. 398
Bridge Circuit with a Single Supply ................................................................... 305, 361, 364
Bridge Circuits Increase Output Power ............................................................................... 321
Bridge, Efficient use of Power Supplies .............................................................................. 307
Bridge, Transimpedance ............................................................................................. 306, 310
Business Hours ...................................................................................................................... 444
Butterworth PWM Filtering ................................................................................................ 405
Cable Capacitance .............................................................................................................. 345
CAD Coordinates of the TO-3 Package ................................................................................ 411
Cage Code .......................................................................................................................... 19
Cagejacks ........................................................................................................................... 430
Cancellation Charges ............................................................................................................. 443
Capacitive Loads ......................................................................................................... 345, 374
Common Mode Voltage Resistors .............................................................................. 300, 363
Compensating V to I Circuits ............................................................................................... 343
Composite Amplifiers .......................................................................... 225, 281, 289, 350
Converting PWM to Analog ..................................................................................... 398, 405
Corporate Directory ................................................................................................................ 444
Current Limit Accuracy .................................................................................................. 295, 324
Current Mirrors .................................................................................................................... 331
Current Output ........................................................................................ 180, 329, 360, 365
Current Output Bridge ................................................................................................. 306, 310
Current to Voltage Conversion ................................................................................ 168, 249
Customer Service ................................................................................................................... 441
Customizing of Standard Products ........................................................................................ 442
Damaged Shipments .............................................................................................................. 443
Data Sheet Explanations .............................................................................................. 22, 294
DB2800 SERIES SINGLES .................................................................................................. 30
DC Power Dissipation ................................................................................................... 297, 320
DC/DC Converter Comparisons ............................................................................................ 28
Design Aids ........................................................................................................................... 292
Design Ideas for the PA02 ................................................................................................ 141
Design Ideas for the PA21/25/26 ...................................................................................... 201
Design Ideas for the PA41/42 ........................................................................................... 215
DHC2800 SERIES SINGLES .............................................................................................. 36 F
Die Form Products ....................................................................................... 207, 214, 229
Don't Go Discrete .................................................................................................................. 3
Down Hole Amplifiers ........................................................................................................ 190
Driving Capacitive Loads .................................................................................................... 125
Dynamic Focus Drive ........................................................................................................ 265
Efficient Power Supplies with a Bridge ................................................................................ 307
447
Subject Index
EK01, Evaluation Kit for SA01 Pin-Out ............................................................................... 54

EK04, Evaluation Kit for PA04 Pin-Out ............................................................................. 152
EK10, Evaluation Kit for SA13/14 Pin-Out .......................................................................... 102
EK42, Evaluation Kit for SIP10 Pin-Out ............................................................................ 217
EK50, Evaluation Kit for Power Boosters ......................................................................... 285
EK-SA50, Evaluation Kit for SA50 ..................................................................................... 122
EK-SA51, Evaluation Kit for SA51 ..................................................................................... 129
Electromagnetic Deflection ................................................ 174, 229, 253, 306, 333, 360
Electrostatic Deflection ........................................................................................................ 306
Equivalent Second Sources .................................................................................................. 47
Evaluation Kits ........................................................ 54, 64, 72, 84, 102, 114, 122, 129
Evaluation Kits ................................................... 152, 202, 204, 217, 223, 235, 285
Evaluation Orders .................................................................................................................. 442
Export Orders ......................................................................................................................... 442
Extended Temperature Range Amplifiers ......................................................................... 190
External Phase Compensation ................................................................................... 336, 341
Failure Analysis Service ......................................................................................................... 443
Fault Latching High Power PPS .......................................................................................... 314
FAX Numbers ......................................................................................................................... 444
Feedback Zero Compensation ............................................................................................ 347
Filter Design for PWMs ..................................................................................................... 405
Flyback Diodes and Motors ................................................................................................. 373
Focus Drive, Dynamic ....................................................................................................... 265
Foldover Current Limiting ...................................................................... 183, 188, 323, 335
Four Quadrant Torque Control ............................................................................................ 121
Gain Switching ............................................................................................................ 300, 384
General Operating Considerations ........................................................................... 294
Grade Comparison and Availability ..................................................................................... 16
Ground Loops ..................................................................................................................... 340
Hardware Kit For Flangless Packages ................................................................................ 434
Hardware Kit For PA26 ....................................................................................................... 434
H-Bridge Driver ......................................................................................................... 303, 398
Heads-up-Display Deflection ............................................................................................... 310
Heatsink Holes .................................................................................................................... 419
Heatsinking Amplifiers ................................................................................................... 298, 327
Heatsinks ............................................................................................................................ 419
High Temperature Amplifiers ............................................................................................ 190
High Voltage Power Supplies ............................................................................................. 380
High Voltage Programmable Power Supply ...................................................................... 249
High Voltage Support Components .................................................................................... 379
How the PA03 Works .......................................................................................................... 315
How to Interpolate Data Sheets .................................................................................... 22, 294
Howland Current Pump ..................................................................................................... 180
Hybrid Advantages Over Discrete ......................................................................................... 3
Increasing Output Power ..................................................................................................... 321
Initial Power-up when Prototyping ........................................................................... 294
Ink Jet Control ................................................................................................................... 259
Kelvin Sensing Programmable Power Supply .......................................................... 243, 317
Liability ................................................................................................................................... 442
Life Support Policy .......................................................................................................... 7, 443
Load Lines ........................................................................................................................... 368
448
Subject Index
Loop Stability vs Non-Loop Stability ................................................................................... 339

Lost Shipments ...................................................................................................................... 443
Low Distortion Low Power Audio Amplifier ......................................................................... 136
Low Pass PWM Filtering ................................................................................................... 156
Low Quiescent Current Amplifiers ............................................. 130, 209, 237, 243, 271
Magnetic Deflection .................................................... 174, 225, 253, 306, 308, 333, 360
Magnetic Deflection, Required Voltages ............................................................................. 308
Magnetic Deflection, Typical Waveforms ............................................................................ 309
Map to Apex ........................................................................................................................... 446
Marking information ............................................................................................................. 435
Matching Networks for Reactive Loads ............................................................................. 406
Mating Sockets .................................................................................................................... 430
Maximum Power Rating ...................................................................................................... 327
Military Screening Program ................................................................................................. 18
Military/Industrial Screening Comparison ............................................................................ 16
Minimizing PA41 External Component Count ................................................................... 215
Mirror Focus Drive ............................................................................................................. 271
Model Number System ........................................................................................................ 437
Monolithic Amplifiers .................................................................................... 195, 209, 225
MOSFETs Ease SOA Limitations ....................................................................................... 334
Motor Drive ................................................... 50, 68, 76, 80, 118, 124, 130, 141, 162
Motor Drive ........................................................ 195, 237, 303, 312, 314, 366, 372, 398
Motor Drive Power Dissipation .................................................................................... 321, 372
Motor Reversal ............................................................................................................ 321, 372
Mounting Power Amplifiers ................................................................................ 299, 327, 396
Multiple Amplifier Applications ............................................................................................ 340
Noise Gain Compensation .................................................................................................. 348
Optimizing the Power Supply .............................................................................................. 319
Optoelectronic Position Control ................................................................................. 162, 303
Ordering Information .............................................................................................................. 442
Output Impedance of Power Amplifiers ....................................................................... 326, 346
Output Saturation Voltage Chart ........................................................................................... 46
Output Stage Oscillations .................................................................................................... 340
Overnight Delivery .................................................................................................................. 442
PA01, PA73 ........................................................................................................................ 130
PA02 Design Ideas ........................................................................................................... 141
PA02, PA02A ...................................................................................................................... 136
PA02M ................................................................................................................................ 140
PA03, PA03A .................................................................................................................... 144
PA03 Inside the Package ................................................................................................. 315
PA04, PA04A .................................................................................................................... 148
PA05, PA05A .................................................................................................................... 158
PA07, PA07A .................................................................................................................... 162
PA07M .............................................................................................................................. 166
PA08, PA08A .................................................................................................................... 168
PA08M .............................................................................................................................. 172
PA08V ............................................................................................................................... 173
PA09, PA09A .................................................................................................................... 174
PA09M .............................................................................................................................. 178
PA10, PA10A .................................................................................................................... 180
PA10M .............................................................................................................................. 184
PA12, PA12A .................................................................................................................... 185
PA12H ............................................................................................................................... 190
PA12M .............................................................................................................................. 189
PA19, PA19A .................................................................................................................... 191 F
PA21, PA21A, PA25, PA25A, PA26 ................................................................................. 195
PA21/25/26 Design Ideas ................................................................................................. 201
PA21M .............................................................................................................................. 200
PA25 DIE .......................................................................................................................... 207
PA26 Design Ideas ........................................................................................................... 201
449
Subject Index
PA26 Hardware Kit .............................................................................................................. 434

PA41, PA41A, PA42, PA42A ............................................................................................ 209
PA41/42 Design Ideas ...................................................................................................... 215
PA41/42 with Minimum External Components .................................................................. 215
PA41DIE ........................................................................................................................... 214
PA41M .............................................................................................................................. 213
PA44 ................................................................................................................................. 219
PA45 ................................................................................................................................. 225
PA45 DIE .......................................................................................................................... 229
PA46 ................................................................................................................................. 231
PA51, PA51A .................................................................................................................... 237
PA51M .............................................................................................................................. 241
PA61, PA61A .................................................................................................................... 243
PA61M .............................................................................................................................. 247
PA73 ................................................................................................................................... 130
PA73M ................................................................................................................................ 134
PA81J, PA82J ................................................................................................................... 249
PA83, PA83A .................................................................................................................... 253
PA83M .............................................................................................................................. 257
PA84, PA84A, PA84S ....................................................................................................... 259
PA84M .............................................................................................................................. 263
PA85, PA85A .................................................................................................................... 265
PA85M .............................................................................................................................. 269
PA88, PA88A .................................................................................................................... 271
PA88M .............................................................................................................................. 275
PA89, PA89A .................................................................................................................... 277
Packages .............................................................................................................................. 411
Parallel Operation ................................................................................... 312, 321, 361, 393
Parameter Definitions and Test Methods ............................................................................ 22
Patents .................................................................................................................................. 7
Payment Terms ...................................................................................................................... 443
PB50 ................................................................................................................................. 281
PB58, PB58A .................................................................................................................... 287
PCB Layout Considerations ................................................................................................ 341
Piezo Drive ............................................................................. 209, 360, 382, 384, 386, 388
Piezoelectric Positioning ......................................................................................... 271, 277
Piezoelectric transducer Drive ..................................................................... 148, 158, 253
Pin Driver .......................................................................................................................... 168
Plotting Load Lines ............................................................................................................. 368
Position Control ................................................................................... 144, 162, 303, 402
Power Amplifier Selector Guide ............................................................................................ 43
Power Booster Applications ............................................................................... 332, 361, 381
Power Booster Evaluation Kit ............................................................................................ 285
Power Boosters ....................................................................................................... 281, 289
Power Dissipation ................................................................................................ 297, 320, 378
Power Dissipation Driving Motors ....................................................................................... 321
Power Dissipation with PWMs .......................................................................................... 401
Power Dissipation with Reactive Loads ........................................................................ 296, 320
Power Supplies, High Voltage .................................................................................... 380, 435
Power Supply Bypassing .............................................................................................. 295, 339
Power Supply Efficiency of the Bridge ................................................................................ 307
Power Supply Optimum Voltage ......................................................................................... 319
Product Index ...................................................................................................................... 11
Product Returns ..................................................................................................................... 443
Programmable Active Loads ............................................................................................... 318
Programmable Power Supply ............................. 98, 106, 110, 243, 249, 313, 314, 332
Programmable Torque Drive ............................................................................................. 237
Protection and SOA in Bridge Circuits ................................................................................ 359
PWM Amplifiers ............................... 50, 58, 68, 76, 80, 88, 98, 106, 110, 118, 124
PWM Basics ...................................................................................................................... 398
450
Subject Index
PWM Noise Reduction ...................................................................................................... 405

QML-38534 Qualification ....................................................................................................... 442
Quality at Apex .............................................................................................................. 14, 442
Rate of Closure & Stability .................................................................................................. 341
Reactance Chart ................................................................................................................. 24
Reactive Load Lines ............................................................................................................ 368
Reactive Loads Increase Power Dissipation ....................................................................... 320
Read this Prior to Designing ....................................................................................... 294
Reducing PWM Noise ....................................................................................................... 405
Reliability and Mean-Time-to-Failure .................................................................................. 327
Remote Sensing Programmable Power Supply ........................................................ 243, 317
Resistive Load Lines ........................................................................................................... 368
Resistor Isolation for Capacitive Loads ............................................................................... 381
SA01 ..................................................................................................................................... 50
SA02 ................................................................................................................................... 58
SA03 ................................................................................................................................... 68
SA04 ................................................................................................................................... 76
SA06 ................................................................................................................................... 80
SA07 ................................................................................................................................... 88
SA13 ................................................................................................................................... 98
SA14 ................................................................................................................................... 106
SA16 ................................................................................................................................... 110
SA50 ................................................................................................................................... 118
SA50M ................................................................................................................................ 123
SA51 ................................................................................................................................... 124
SA51M ................................................................................................................................ 128
Sales Representatives ........................................................................................................... 445
Saturation Voltage and Boost Pins ................................................................ 148, 158, 335
Second Sources of Amplifiers ............................................................................................... 47
Selector Guide, Power Amplifier ........................................................................................... 44
Selector Guide, PWM Amplifier............................................................................................. 45
Shipping ................................................................................................................................. 443
Shutdown Feature on Amplifiers ........................................................... 50, 144, 148, 158
Simplify your designs ............................................................................................................ 3
Single Supply Operation ................................................................. 195, 319, 361, 363, 387
SIP Amplifiers .......................................................................................................... 195, 209
Sleeving Pins ................................................................................................................ 299, 419
SMD, Standardized Military Drawings ................................................................................. 17
SOA and MOSFETs ............................................................................................................ 334
SOA and Motors .................................................................................................................. 372
SOA Graph Meaning ..................................................................................................... 295, 368
SOA Testing and Measuring ............................................................................................... 369
Sockets ............................................................................................................................... 430
Software for Design............................................................................................................... 292
Solar Panel Tester .............................................................................................................. 318
Sonar Transducer Drive .......................................................................................... 148, 158
Source Inspections................................................................................................................. 442
Specification Definitions ...................................................................................................... 22
Speed Control with Tachometer Feedback ........................................................ 50, 306, 401
Spice Files ............................................................................................................................. 292
Stability Considerations..................................................................... 300, 337, 339, 359, 374
Stability Tests .............................................................................................................. 352, 378
Surveys of the Apex Facility ................................................................................................... 442
Switching Gain ............................................................................................................ 300, 384
Table of Contents ................................................................................................................ 11 F
Tachometer Feedback ....................................................................................... 50, 306, 401
Technical Support .................................................................................................................. 442
Telephone, Telex and Fax Numbers ...................................................................................... 444
Temperature and Current Limit ..................................................................................... 295, 324
Temperature and Reliability ................................................................................................ 327
451
Subject Index
Terms and Conditions of Sale ................................................................................................ 443

Test Methods ...................................................................................................................... 22
Thermal Capacity ................................................................................................................ 328
Thermal Management ......................................................................................................... 327
Thermal Shutdown can Help ............................................................................................... 322
Thermal Techniques ........................................................................................................... 314
Thermal Washers ........................................................................................................ 419, 432
Thermal Washers or Grease ......................................................................................... 299, 327
TO-3 Pin Coordinates ........................................................................................................... 411
Toll-free Technical Assistance ............................................................................................... 444
Torque Motor Drive ........................................................................................................... 237
Torque Specifications .................................................................................................... 299, 327
Transient Voltage Protection ....................................................................... 246, 295, 299, 379
Transimpedance Bridge .............................................................................................. 306, 310
Tutorial on Op Amp Basics ............................................................................................... 403
Tutorial on PWM Basics .................................................................................................... 398
Typical applications by industry ............................................................................................ 6
Unidirectional Optical Speed Control .................................................................................. 130
Unipolar Output Bridge ........................................................................................................ 361
Unsymmetrical Power Supplies .................................................................................. 130, 363
Vboost Improves Saturation Voltage ............................................................. 148, 158, 335
Vendors of Accessories ...................................................................................................... 435
Voltage to Current Conversion ......................................... 174, 180, 225, 253, 329, 343
Voltages Required for Magnetic Deflection ......................................................................... 308
Warranty ................................................................................................................................. 442
Washers, Thermal ....................................................................................................... 419, 432
Waveforms Typical of Magnetic Deflection ......................................................................... 309
Where to find support components ..................................................................................... 435
452
The Apex Team Vision:
Providing world leadership in innovation,
product quality and customer service
Creating our vision involves you, the customer. Your new product suggestions, your feedback
on our product quality and your evaluation of our customer service are key elements to helping
us work better for all of our customers, as well as building solid, long-term customer relation-
ships. Below are several avenues you can use to provide us your thoughts, comments and sugges-
tions. We also welcome customer visits to our Tucson, Arizona, headquarters. To arrange a visit
to Apex, please contact your local Apex sales representative or call us direct at 520-690-8601.
We look forward to hearing from you.
General Comments
E-Mail: comments@apexmicrotech.com
custserv@apexmicrotech.com
New Product Suggestions

Contact: Eric Han, Strategic Marketing Coordinator
Phone: 520-690-8630
E-Mail: ehan@apexmicrotech.com
Product Quality Feedback

Contact: John Jarvise, Quality Team Leader
Phone: 520-690-8623
E-Mail: jjarvise@apexmicrotech.com
To Arrange A Visit To Apex

Contact: Apex Team Sales
Phone: 520-690-8601
E-Mail: custserv@apexmicrotech.com
To Contact Apex President Lisa Putt

Phone: 520-690-8619
E-Mail: lputt@apexmicrotech.com

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DISCRETE OR OFF-THE-SHELF? FREE APPLICATIONS ENGINEERING

Leading edge design

Typical Power Amplifier Applications A

Computers and Optical Scanning System Galvanometer Drive High Power/PWM

Communications Telecom Test Equipment Ring Generator High Voltage

Aerospace Guidance Systems Gyro Motor Control High Power/PWM

Weapon Systems Transmitters, Seekers Motor Drive High Power/PWM

Optical Interferometer Piezo Drive High Voltage

Medical Surgical, Medical Instruments Pumps High Power/PWM

The following is a trademark of APEX MICROTECHNOLOGY CORP.

To Our Valued Customer,

In 1991, we began a change in our

To help us achieve our vision, we

A SECTION A General Info, Tab Index, Table of Contents, Quality

Simplify Your Circuit Design .......................................................................................................................... 3

B SECTION B DC/DC Converters

DC/DC Features ....................................................................................................................................... 27

C SECTION C General Operating Considerations, PWM Amplifiers,

D SECTION D Application Notes

Applications Engineer Message .................................................................................................................... 292

E SECTION E Packages and Accessories, Product Marking

Packages Outline Dimensions ...................................................................................................................... 411

Subject Index, Customer Support Request Card

Ordering Information, Product Warranty, Terms & Conditions ....................................................................... 442

A Quality Message To Our Customers ................................................................ 15

Dear Valued Customer:

In alignment with Sigma Plus, we have instituted training and development in

Clean room processing ............................................ YES .......................................... YES

SMD GRADE AVAILABILITY

DHC2803 .......................... S .......................................... S .................................. N1 ................................................ N

DESCRIPTION 1.4 PERFORMANCE SPECIFICATIONS A

* Applies to compliant (/883) product only.

Header and cap: Package evaluation to MIL-PRF-38534*

Sample nondestruct wire-pull

OPTIONAL FUNCTIONAL TEST

Sample destruct wire-pull

* Applies to compliant (/883) product only.

FINAL ELECTRICAL TEST

PRECAP VISUAL INSPECTION FINE LEAK TEST

QI SAMPLE PRECAP INSPECTION GROSS LEAK TEST

VACUUM BAKEOUT MARKING

PACKAGE SEAL EXTERNAL VISUAL

PARAMETER DEFINITIONS & TEST METHODS

ABSOLUTE MAXIMUM RATINGS COMMON MODE REJECTION: CMR

TYPICAL SUPPLY VOLTAGE FIGURE 2. INPUT BIAS CURRENT

FIGURE 4. OUTPUT VOLTAGE SWING +VS

CURRENT LIMIT: ICL VOUT

ICL = VOUT /RL PHASE MARGIN

FULL POWER RESPONSE

GAIN BANDWIDTH PRODUCT

Apex DC/DC Converter Features .......................................................................... 27

HIGH RELIABILITY BUILT IN. 1

1 Surface Mount Magnetics 5

PRODUCT DESIGN HIGHLIGHTS

DHC2800 MSA2800 ASA2800

Rugged Military Design

Welded Case STD STD STD

All Ceramic Capacitors STD N/A STD

Wave Solderable STD N/A STD

Wide Continuous Input Voltage Range STD N/A N/A

Output Voltage Adjust Standard +/10% N/A N/A