RESUME

Prajwal Hegde K
No.50 ss honnadevi nilaya Mobile number : +91-9449999230
Vidyaranyapura,Bengaluru Email-id : prajwalhegdek@gmail.com
Karnataka 560097

OBJECTIVE:
Result oriented and dynamic professional with wide exposure in ASIC verification. Sound
knowledge in verification tools and methodologies and logic design. Looking for a position as an ASIC
verification engineer in a prestigious organization.

SKILLS
HDL/HDVL : Verilog, System Verilog
Verification Methodology : UVM
Scripting Languages : PERL, SHELL
EDA Tools : Riviera Pro, Libero,Quartrus,Nios,Xilinx ISE
Operating Systems : Windows, Linux

ACADEMIC PROFILE:
BOARD/ YEAR OF % OF
COURSE INSTITUTION UNIVERSITY PASSING MARKS
Sahyadri College Of Engineering, VTU
B.E- ECE Mangalore 2015 56
PUC Vivekananda Pre University College, Karnataka PU Board
Puttur 2011 78
SSLC Rotary High School, Sullia Karnataka
2009 86

ADVANCED TRAINING: Pursuing design and verification course (QCDVE QSOCS certified design
and verification engineering)in VLSI from Qsocs Technologies, Bangalore.
PROJECTS
1. Design and Verification of UART
Platform :Windows/Linux | Language : Verilog HDL and UVM | Tools : Rivera Pro, Libero
Objective: The project focuses on design and verification of UART with AMBA 3 APB
protocol. UART is a serial communication protocol which allows the full duplex communication
in serial link, it is an essential to computers and allows them to communicate with low speed
peripheral devices, such as the keyboard, the mouse, modems etc.

Design

Analyzed the specifications of UART-APB

Prepared micro-architecture for the same
 Designed RTL of each sub modules in Verilog HDL
Direct testing of each sub modules was done.
Combined all the sub modules into a final module
Took the RTL of UART-APB and analyzed its functionality
Verification

Prepared the test plan

Prepared the test bench architecture
Created the test environment in System Verilog
Methodology used is UVM

2. Design and Verification of Asynchronous FIFO

Platform :Windows/Linux | Language : Verilog HDL | Tools : Rivera Pro, Libero

Objective: This project focuses on design and verification of Asynchronous FIFO which is used
in preventing meta-stable state when a signal crosses clock domain (Clock Domain Crossing). As
part of the project Asynchronous FIFO with Width 1 byte and Depth 16 is designed in Verilog
HDL and simulated using Rivera Pro and coverage reports are generated.

EXPERIENCE: Swave systems Pvt ltd, Bangalore(1 year).

PERSONAL PROFILE:
Fathers Name : Prakash Hegde K
Date of birth : 23.03.1993
Gender : Male
Nationality : India
Languages Known : English, Kannada,Hindi.
DECLARATION
I hereby declare that all the above details are true and correct to best of my knowledge and belief.
Place:
Date:
(Prajwal Hegde K)