MANIPAL INSTITUTE OF TECHNOLOGY

(A constituent college of Manipal University, Manipal)

Manipal Karnataka 576 104

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

COURSE PLAN

Department : Electrical and Electronics Engineering

Subject : [ELE 206] Digital Systems Design &
Computer Architecture [3 1 0 4]
Semester & branch : IV Semester BE ( E&E )
Course Coordinator : Ms. Sandhyalaxmi G Navada
NO OF CONTACT HOURS : 46 L + 05 T [4 HOURS / WEEK]

Assignment portion
Assignment no. Topics
1 L2 L13
2 L14-L22
3 L23-L32
4 L33-L42
5 L43-L46
Test portion
Test no. Topics
1 L2 L22
2 L23-L42

Submitted by: Faculty:

(Signature of the Course Coordinator) 1) Ms. Susan G Varghese A

Date: 2) Ms Shwetha V B
3) Ms Sandhyalaxmi G N C
Approved by:

(Signature of HOD)
Date:

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MIT/GEN/F-05/ELE/R0
 Prerequisite: Digital Electronic Circuits (ELE 203)
Course outcome:
CO1 Describe Top-Down design methodology, need for HDL and levels of
abstraction for modeling the system

CO2 Design combinational circuits and non-pipelined sequential circuits using

VHDL for a given set of specifications.

CO3 Implement combinational circuits and non-pipelined sequential circuits

using Programmable ASICs.

CO4 Comprehend the basics of computer architecture and its memory

organization.

CO5 Design data path and control path of a simple processor based system.

Evaluation Scheme:
Internal Assessment: 50 Marks
Two tests comprising of one word answers, multiple choice questions, short
answer questions and numericals - 20 Marks each
5 nos. of Assignments 2 Marks each
o Evaluation of assignments based on surprise tests.

End Semester Examination: 50 Marks

Questions shall cover the entire syllabus
Six questions are set, each of 10 marks
Students shall answer any five full questions

Lecture no. Topic to be covered

Review of DEC (ELE 203)
L1
Review of combinational and sequential circuit design using standard parts
Introduction to DSD & CA
Objectives of the course, relevance, course plan, evaluation plan, references
L2
Overview of lab course plan
Overview of Silicon processing, Benefits of Integration
Digital implementation options - Using standard parts; Digital System implementation using
L3 MSI/LSI circuits; ASICs Full custom & Semi custom; and Programmable ASICs. Comparison based
on performance & cost; Design flow.

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MIT/GEN/F-05/ELE/R0
 Design methodology top down, bottom up;
L4 Domains & levels of abstraction, Design hierarchy;
HDL: VHDL, Verilog, System C; Comparison.
L5-L6 VHDL: Program structure, entity, architecture, language organization
L7 L8 Data flow, structural, Algorithmic modeling in VHDL examples.
L9 L11 Data types & operators; Concurrent and sequential statements
L12-L13 Combinational circuit design examples
T1 Tutorial 1 (L6-L13)
L14-L15 Hierarchy and components, parameterized components, generate statements.
L16-L17 Sequential circuit design examples
L18-L19 Sub programs Functions & Procedures, Packages & Libraries.
T2 Tutorial 2 (L14-L19)
L20-L21 Serial Adder - a case study, RTL Approach.
L22 Verification Test bench
T3 Tutorial 3 (L20-L22)
Sessional I (L2 L22)
Introduction to Computer Architecture: components of a computer system, Instruction Set
L23
Architecture
L24 Components of a CPU - execution Units, Registers and Control Unit.
L25-L26 Instruction formats, Opcode encoding techniques, Instruction Types and Addressing modes
L27 Reduced Instruction Set Computers. Pipelining
L28 I/O interfacing, Interrupts
L29 Memory Organisation: Memory cells - SRAM, DRAM, Flash, Memory hierarchy
L30-L31 Cache memory
L32 Virtual memory, Paging, segmentation and paged segmentation
T4 Tutorial 4 (L23-L32)
Datapath design: General Register design, shifters, adders, ALU design, representation of
L33-L34
numbers
L35-L36 Multiplication of signed and unsigned integers, Booths multiplication algorithm bit pair method
L37-L38 Division of unsigned integers restoring and non-restoring methods
T5 Tutorial 5 (L33-L38)
L39-L40 Control path design: Hardwired and Micro-programmed
L41-L42 Micro-instruction formats, control unit organization, control unit optimization.
Sessional II (L23 - L42)
L43 PLD, EPROM, PAL, PLA; CPLD & FPGA Architecture, Programming technologies anti-fuse,

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 metal-metal anti-fuse, Static RAM, EPROM, EEPROM, Flash
L44 Implementation using Field programmable devices Design flow, Overview, evaluation.
Xilinx FPGAs: Spartan III Architecture, Programmable interconnects and Logic
L45 L46
implementation

References:
1. Smith M.J.S., Application Specific ICs, Pearson, 1997
2. Roth C. H., Digital System Design using VHDL, PWS, 1998
3. Brown S. & Vranesic Z., Fundamentals of Digital Logic with VHDL Design, TMH 2002
4. Wakerly J. F., Digital Design Principles & Practices, Pearson, 2001
5. David Harris and Sarah Harris, Digital Design and Computer Architecture, Elsevier, 2008
6. J. P. Hayes, Computer Architecture and Organisation, McGraw Hill, 1988.
7. M. Raffiquzzman & Rajan Chandra, Modern Computer Architecture, Galgotia Publications, 1990.
8. David Patterson and John Hennessy, Computer Organization and Design, Elsevier, 2007.

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