IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 64, NO.
4, APRIL 2017
A 32-Channel 13-b ADC for Space Applications
Florent Bouyjou, Olivier Gevin, Olivier Limousin, and Eric Delagnes
Abstract This paper presents a 13-b, 2.56-s conversion
time, 2 V input range, 32-channel single slope analog-to-digital
converter (ADC) called OWB-1 and implemented in a 0.35-m
CMOS commercial technology. It is based on an improved
Wilkinson architecture. An interpolator composed by a delay
lock loop is used to increase the time resolution of the counter
by a factor of 32, while keeping a low power consumption
and ensuring the high dynamic performance of the ADC.
Measurements performed on the ADC have shown that the
noise is better than 0.86 LSB over the full conversion range,
its differential nonlinearity is in the range of 0.28/+0.31 LSB
and its integral nonlinearity is within 1.3/+2.1 LSB. The total
power consumption of the chip is 57 mW for 32 active channels.
A new temperature compensation system based on a servo
loop has also been integrated into the chip to compensate for
temperature effects in the 40 C to +40 C range. Special
design techniques have been used to make the ASIC immune to
single event latchup. OWB-1 readout is optimized for a new low
power microgamma camera (Caliste-MC2) with digital output
based on a 32 32 CdTe or CdZnTe pixel matrix.
Index Terms Analog to digital converter (ADC), delay
lock loop (DLL), latchup, space applications, temperature
compensation system.
I. I NTRODUCTION
I N MODERN physics experiments, the sensor is the starting
point of any measurement in the acquisition channel as it
provides for the conversion of a physical quantity into a usable
electrical signal.
Generally, a front-end analog stage processes this sensor
signal and often amplifies it. This step optimizes the sig-
nal/noise ratio of this signal before it is digitized. After
digitization, it is easier to safely transmit the signal or to
apply complex online or off-line signal processing. For this
reason, the trend is generally to digitize the signal as soon as
possible in the electronics chain. However, the design of high
performance, low power analog-to-digital converters (ADCs)
remains a difficult task [1][3].
As the granularity of detectors in modern physics experi-
ments is continuously increasing [4], there is a clear need for
multichannel, low power ADCs. For example, in recent image
sensor ASICs, column-parallel ADCs are gaining prominence.
Several ADC architectures are used for these applications.
One of them is the single slope architecture, because it is
perfectly adapted to multichannel applications; it is preferred
for its simplicity, its low power consumption, and small overall
Manuscript received July 20, 2016; revised December 1, 2016; accepted
February 5, 2017. Date of publication February 22, 2017; date of current
version April 14, 2017.
The authors are with IRFU, CEA, Universit Paris-Saclay, F-91191
Gif-sur-Yvette, France (e-mail: florent.bouyjou@cea.fr; olivier.gevin@cea.fr;
olivier.limousin@cea.fr; eric.delagnes@cea.fr).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TNS.2017.2672863
0018-9499 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1071
area [2], [5]. OWB-1 is a new chip designed to address these
needs, especially for space applications. OWB-1 is expected
to be used to digitize the output signals of the IDeF-X HD
ASIC [7] and the CdTe or CdZnTe pixel matrix of a full digital
microgamma camera (new Caliste generation [8]). For this
application, the ADC must be placed as close to the detector
as possible; it must feature a resolution of at least 13 b,
a conversion time in the microseconds range, the capability
to reach an acquisition rate of about 10 s, and a power
consumption of no more than 3 mA per channel.
The space radiation environmentfor which this ASIC has
been designedcan induce many degradations (dose effects),
failures [single event upset (SEU)], or even destruction [single
event latchup (SEL)] of the CMOS integrated circuits [9], [10].
The chip uses rad-hard libraries with special layout and
registers allowing SEU error detection.
The improved single slope ADC architecture is introduced
in Section II. Section III describes the circuit implementation
of the OWB-1 chip. Section IV summarizes the results of
performance measurements. Finally, we conclude this paper
in Section V.
II. ADC W ITH S INGLE S LOPE U SING
A DLL B OOST A PPROACH
A. Benefits of the Single Slope Architecture
For multichannel digitization, the single slope ADC archi-
tecture is very attractive, because most of its building blocks,
such as the ramp generator, the master clock circuit, and the
counter, are shared by all conversion channels. This allows for
a reduction in channel power consumption when the number of
channels integrated in the chip increases. Moreover, as only
one discriminator and one register have to be integrated in
each individual channel, this architecture enables very compact
layouts for multichannel implementations. The architecture is
expected to naturally perform well with respect to differential
nonlinearity (DNL), which makes it very attractive for spec-
troscopy applications.
B. Single Slope Architecture
The principle of the single slope ADC is based on the
conversion of the input analog voltage into a time measured
by a counter. For this purpose, a discriminator compares
the input voltage VIN (to be converted) to the voltage from
the ramp generatorVRAMP. The counter starts to increment
when the ramp starts. The value of the counter is stored
when the discriminator triggers, indicating that the ramp has
reached VIN . The binary word of the counter corresponds to
the digitized value of VIN . The resolution N of this ADC is
given by
N = log2 (TC FCLK ) (1)
1072
Fig. 1. Chronogram of the single ramp with a DLL boosted ADC architecture
operation.
where TC is the conversion time and FCLK is the clock
frequency. This architecture is low power and compact but
has the major drawback of having a resolution that depends
on FCLK and T c. Consequently, increasing the number of bits
implies increasing the counter frequency or/and the conversion
time. Compared with other ADC architectures, single slope-
based ADCs are slow. We mitigate this point using a delay
lock loop (DLL)-boosted single slope.
C. DLL-Boosted Single Slope ADC Architecture
This architecture is based on the concept of the WILKY
ASIC [11], which improves the resolution of a standard ramp
ADC, without conversion time penalty. To do so, WILKY
uses a DLL-based time interpolator in addition to the standard
counter clocked by the Clk signal. As shown in Fig. 1,
the discriminator not only memorizes the value of the N-bits
counter when the ramp crosses the voltage value, but also starts
a delay line with 2 M steps. This delay is servo controlled by
the period of Clk. The state of this delay line is frozen at
the next Clk rising edge before it is encoded into a M-bit
word, providing the precise discriminator trigger time inside
the clock period. A chronogram of the single ramp with
a DLL-boosted single slope ADC architecture operation is
presented in Fig. 1.
The word sent by the Gray counter and the DLL encoder
is combined to build the final converted value of VIN . The
resolution of this ADC is now N + M and is formulated as
follows:
N+M = log2 (TC FDLL ) .
Using this method, the resolution is improved by M bits
compared with a conventional single slope ADC for the same
conversion time, the same clock frequency, and the same
counter resolution. The digital power consumption of this
architecture is negligible as the DLL is activated only during
a very small fraction of time (FCLK period).
III. OWB-1 A RCHITECTURE
A. Global Architecture
The block diagram of the OWB-1 chip is shown in Fig. 2.
The chip comprises 32 parallel converting channels.
An additional channel is used for temperature compensation.
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 64, NO. 4, APRIL 2017
Fig. 2. High-level block diagram of the OWB-1 ADC, outlining channel K.
Each ADC channel consists of an analog and a digital part.
A Gray counter is implemented to reduce the dynamic power
consumption. An input buffer is designed to shift the dc level
of the input signal (possibly inverted) and to optionally convert
it into a differential signal, which will be sent to two adjacent
ADC channels.
Compared with the WILKY ASIC, the main improvements
in OWB-1 are as follows.
1) The number of channels has been increased by a factor
of 8. OWB-1 integrates 32 channels instead of 4.
2) The ADC is optimized for 13-b resolution instead
of 12 b [11].
3) The ADC integrates an input dc shifter that allows to
match multiple input ranges.
4) The ADC integrates a temperature compensation circuit.
5) The ADC has been radiation hardened. It integrates SEL
hardened digital cells and an SEU flag signal.
6) A new 100 times multiplying PLL has also been inte-
grated to reduce constraints (jitter and frequency) on the
input clock.
The ramp generator and the counter are common to the
32 channels. This contributes to save power and silicon area.
The discriminator and the ramp generator stages have been
designed to reach the 13-b resolution over a 2 V input range.
The eight most significant bits are obtained from the 8-b Gray
counter, whereas the five less significant ones come from the
DLL (32 delays).
A PLL is integrated on the chip to generate the internal
(2) 100-MHz clock from the 1-MHz input reference Low Voltage
Differential Signaling (LVDS) signal. Consequently, the LSB
time step is 312.5 ps (corresponding to a virtual frequency
FDLL of 3.2 GHz) so that the full range conversion time TC
is 2.56 s.
When the conversion of all channels has been achieved,
their data and addresses are transferred to output shift registers
for readout. Two reading modes are then possible, a serial
mode through an LVDS output or a parallel mode using
CMOS outputs.
Slow-control programming registers are implemented in
the chip and are used to configure, through an SPI link,
the different operating modes and conversion options of the
ADC. It is possible to have the following.
BOUYJOU et al.: 32-CHANNEL 13-b ADC FOR SPACE APPLICATIONS
Fig. 3. Discriminator circuit.
1) Disable/enable each channel individually.
2) Program the ADC resolution from 11 to 14 b and adapt
the conversion time to the target application.
3) Enable the input buffers to shift the dc input range of
the ADC using a programmable 9-b DAC.
4) Enable the inversion of the input signal.
5) Use the input differential mode using two adjacent
ADC-channels for a 14-b conversion.
6) Adjust the internal ramp by a 9-b DAC.
7) Activate the temperature compensation system.
8) Choose the serial mode (LVDS) or the parallel
mode (CMOS) output.
9) Change the data readout frequency: (25, 50,
or 100 MHz).
B. Discriminator
The discriminator compares the ramp with the voltage to
convert. Its timing properties are critical as they directly
impact the performance of the overall ADC. Its jitter and
variation in response time with respect to the input signal and
other parameters must be smaller than an LSB, that is, less
than 312.5 ps.
The discriminator uses the structure described in [11].
As shown in Fig. 3, it is based on the cascade of three low
gain amplifiers followed by a digital level restorer.
The amplifiers are low gain (5)(12) in order to reach high
speed and to reduce kickback effects. For good linearity of the
ADC and its stability, the triggering delay of the discriminator
must be constant with respect to the input voltage and the
operating temperature. To keep the power consumption low,
the comparator delay is quite large. Fig. 4 shows the simu-
lations of the triggering time jitter (left) and of the average
triggering delay (right) of the discriminator for a VIN sweep
of 2 V at three different temperatures 40 C, +20 C,
and +40 C.
A flawless ramp of 781.25 kV.s1 (2 V in 2.56 s) is
injected in order to measure the variation of the triggering
delay and the jitter of the discriminator. Regarding the average
triggering delay, the largest change is observed at the lowest
temperature. A maximum variation of 220 ps is observed over
the whole input dynamic range of 2 V. This is acceptable and
will contribute to the ADC integral nonlinearity (INL) for less
than 1 LSB. The triggering time jitter remains stable with
the input range. Temperature variations have a greater impact.
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Fig. 4. Triggering time jitter (left) and average triggering delay (right) of
the discriminator over a VIN range of 2 V and for 3 temperatures 40 C,
+20 C, and +40 C. Each point corresponds to 100 simulation runs.
Fig. 5. Ramp generator circuit.
The jitter is only 60 ps rms at 40 C whereas it reaches
90 ps rms at 40 C. These values are acceptable: they are
more than 3.5 times smaller than the LSB and of the same
magnitude as the ADC quantization noise.
C. Ramp Generator
This circuit architecture is chosen for its excellent linearity
performance. A constant current IRAMP is switched at the input
of an active integrator, which is composed of an amplifier with
a feedback integrating capacitor C f , as shown in Fig. 5.
The following relationship is used to calculate the output
ramp voltage as a function of integration time:
IRAMP
VRAMP (t) = t. (3)
Cf
A reference supply source VRESET is used to discharge the
feedback integrating capacitor C f when R E S E T is activated.
The integrated current IRAMP is set by a resistor RREF placed
between the output of the current source (equal to VREF2 )
and VREF . The equation to calculate this current is, therefore,
given by
VREF V R E F 2
IRAMP = . (4)
RREF
RREF must be configurable over a wide range of values as it
allows to set the slope of the ramp and, therefore, the speed
and accuracy of the ADC. This is why RREF is implemented
1074
Fig. 6. Evolution of the simulated rms temporal noise of the ramp generator
with the integration time for temperatures of 40 C, 20 C, and 40 C with
a capacitive load of 5 pF.
as an internal resistor programmable by slow control over
a 9-b range.
An analytical study of the current source noise [12] led
us to the theoretical expression of the total transient noise at
the output of the rampgenerator as a function of the spectral
density of white and 1 f noise of the current source
t2 K 2
BRAMP (t)2 = Bfs (t)2 +BBS (t)2 = Nf+
C 2f
   
fc
K = ln 00, , 9151
fo
where NBi is the spectral white noise current density, f c is the
white noise cutoff frequency, f o is the low cutoff frequency,
and N f is the parameter of the flicker noise constant. This
expression allowed us to optimize two key parameters that
define the slope of the integrator: the value of the current
source IRAMP and the value of the capacitor C f . Using (3)(5),
a couple of value C f = 10 pF and IRAMP = 7.81 A has
been selected to make the noise compatible with the target
performance of a 13-b ADC. The evolution of the simulated
rms temporal noise of the ramp generator with the integration
time for the temperatures of 40 C, 20 C, and 40 C with
a capacitive load of 5 pF is shown in Fig. 6.
As expected, the rms noise increases with the integration
time. In addition, it increases with temperature. These simu-
lations indicate that the noise keeps lower than 131-V rms,
in the worst case, almost half of the LSB value of 244-V rms.
The power consumption of the ramp generator is 1.53 mW.
In terms of temperature dependence, using C f in this
integrator is an issue. The integration polysilicon capacitor
linearly increases with temperature with a slope of +0.3 fF per
degree. For a temperature range of 80 C, this leads to a 24-fF
shift of Cf. Using (3), a shift of 4.787 mV = 20 LSB between
40 C and +40 C is found for the maximum integration
time of 2.56 s, which corresponds to a variation of about
60 V/C or 22 ppm/C. However, an on-chip self-temperature
compensation circuit was designed to mitigate this effect as
explained in the following paragraph.
D. New Temperature Compensation System
In order to preserve the performance of the ADC in a
wide range of temperature from 40 C to +40 C, we have
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 64, NO. 4, APRIL 2017
Fig. 7. Block diagram of the on-chip self-temperature compensation system.
Fig. 8. Principle of operation of the on-chip self-temperature compensation
system.
NBi t
2C 2f
implemented a temperature compensation system based on a
(5) servo loop circuit (Fig. 7).
The main idea of this loop is to use an extra channel with a
known and constant voltage at the input to compensate for the
capacitor variation by adjusting the ramp current. The goal is
to have the same ramp slope V r amp(0 C) = 781.25 kV.s1 at
any temperature. This slope corresponds to an input voltage of
2 V for a 2.56-s integration time (213 /FDLL ). The principle
of operation of the on-chip self-temperature compensation
system is presented in Fig. 8.
During the calibration phase at the ASIC power ON,
an external voltage V i nCALIB is adjusted to have an ADC
conversion code equal to the temperature at this moment:
V i n CALIB = EncoderCALIB . For example, if we have an
ambient temperature of 25 C and we launch a conversion,
the ramp corresponds to Vramp(25 C). In the on-chip self-
temperature compensation system, a resistor network NR2
is placed in series with R2 varying with a thermometer code; it
is controlled by the result of the DLL encoder. This system can
adjust the value of the integration current of the ramp generator
function if EncoderCALIB is different from the midrange value
of the encoder (Encoder = 15 or 16) corresponding to 0 C
in each conversion phase. Then after N calibration cycles, the
slope of the ramp corresponds to V r amp(0 C). This ramp
crosses the voltage V i n CALIB and the result of this conversion
corresponds to the midrange value of the encoder (Encoder =
15 or 16). Note that these two codes cannot change the slope of
the ramp (stability zone). The ramp generator circuit with the
new temperature compensation system is presented in Fig. 9.
If there is a temperature variation, the conversion code
EncoderCALIB changes and the current is automatically
adjusted by the resistance network NR2 to calibrate the
slope of the ramp and set the ramp to V r amp(0 C).
The ramp generator slope of the temperature compensation
BOUYJOU et al.: 32-CHANNEL 13-b ADC FOR SPACE APPLICATIONS
Fig. 9. Ramp generator circuit with the new temperature compensation
system.
Fig. 10. Simulation of the evolution of the ramp generator slope as a function
of temperature with and without compensation.
can be written as
 
VRAMP (t) R1 VREF 1 being read out (pipelined). In the 13-b mode, the ADC can
= .
t R1 +R2 NR2 RREF C f
As shown in Fig. 10, the automatically adjusted value of
R2 NR2 allows to compensate for the effect of temperature
on the ramp generator slope due to C f .
An optimized temperature coefficient of the compensated
ramp generator slope of 0.32 ppm/C is extracted from
simulation.
IV. M EASUREMENT R ESULTS
OWB-1 is implemented in a 0.35-m CMOS technology.
Its dimensions are 50 m 2000 m per channel for a total
of 17.95 mm2 . The chip is packaged in a CQFP 128, as shown
in Fig. 11.
A dedicated test bench has been designed. It is based
on a ZYNQ system-on-chip FPGA, programmed in VHDL
and using Linux to exchange data through Ethernet with a
PC. A versatile Labview test program is running to acquire,
process, and visualize the measurements. In the test setup,
the signal is generated from the FPGA 1-MHz LVDS clock.
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Fig. 11. OWB-1 chip encapsulated in a CQFP 128.
Fig. 12. Single shot ADC conversion for a 100-Hz, 2 V input sine wave
input.
A. ADC Performance Measurements
First, the ADC is configured in 13-b mode with a full range
of 2 V with an LSB of 244 V. Using a 1-MHz main clock
and a 100-MHz internal clock with the PLL corresponding to
a DLL step of 312.5 ps, the conversion time required for the
13-b range is 2.56 s. For this operation, the ramp slope is
set to 781.25 kV.s1 .
After conversion, an additional 100-ns time is needed to
reset the system in order to be ready for the next conversion.
The next conversion can happen while the previous event is
(6)
operate up to 370-kHz sampling rate for 32 channels converted
simultaneously.
Presenting a low frequency sine wave to one of the inputs
of the ADC allows us to test its functionality, as shown
in Fig. 12.
The noise level appears to be smaller than 1 LSB in this
simple test. All the 32 channels have the same behavior. Table I
summarizes the measured performance of the OWB-1 chip.
The maximum static and dynamic power consumption
of 31.4 mW (common blocks) + 0.8 mW/channel = 57 mW
includes the consumption of the 32 channels and all the
different circuits: LVDS drivers, PLL, the ramp generator, and
so on.
User settings can be set to switch OFF unused channels in
order to save power. Fig. 13 shows the total typical power
consumption of one channel (W ) as a function of the number
of activated channels (X).
This plot matches the following equation of W :
9.4
W = +0.8. (7)
X
1076 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 64, NO. 4, APRIL 2017

Fig. 13. Typical power consumption/channel as a function of the number of enabled channels.

TABLE I
OWB-1 P ERFORMANCES M EASURED

Fig. 15. Measured INL: 1.3/+2.1 LSB.

Fig. 14. Measured DNL: 0.28/+0.31 LSB.

Fig. 16. ADC rms noise as a function of ADC output code (512 acquisitions
B. ADC Linearity and Noise by step).

Quasi-static measurements have been carried out using

statistical code density methods. As shown in Figs. 14 and
15, a DNL of 0.28/+0.31 LSB and a maximum INL of
1.3/+2.1 LSB have been measured.
For the whole input range, 512 acquisitions per input
voltage have been recorded and the noise extracted (standard
deviation in 512 records). This standard deviation includes
both contributions of quantization and electronic noise. The
latter is dominated by the noise of the ramp generator and
the discriminator. Fig. 16 shows the measured ADC rms noise
as a function of ADC output.
As expected theoretically [see (5)] and by simulation,
the noise increases with the integration time. The noise is
BOUYJOU et al.: 32-CHANNEL 13-b ADC FOR SPACE APPLICATIONS
TABLE II
R EADOUT M ODES AND S AMPLING R ATE
Fig. 17. Measured ADC gain dispersion of the 32 channels.
always lower than 1 LSB over the full ADC conversion range.
Note that the noise is very uniform from channel to channel.
C. Readout Modes and Sampling Rate
It is possible to reduce the sampling rate by reducing the
resolution of the ADC. The resolution can be set by slow
control to any value from 11 to 14 b. For example, for a 12-b
(respectively 11 b) resolution, the conversion time is divided
by 2 (respectively 4) to 1.28 s (respectively 780 ns).
Also, we can choose between two modes to read the data:
a serial or a parallel mode. The serial mode is carried out by
a single LVDS output and the parallel mode is carried out
by 11 CMOS outputs. The parallel mode allows for a faster
data transfer while the serial mode allows the transfer over a
single pair of wires. Details of the different sampling speeds
are shown in Table II.
D. Dispersion Between Channels
Comparisons of the dispersions of the gain and the offset in
all the conversion channels of the ASIC have been measured;
results are displayed in Figs. 17 and 18.
A gain dispersion of 0.12% is measured, corresponding
to a 98 LSB error range for the full conversion range. As the
ramp generator and counters are common to all the channels,
the source of this spread, still under investigation, is probably
related to the discriminator. For the offset dispersion, values
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Fig. 18. Measured ADC dispersion offset of the 32 channels.
Fig. 19. Evolution of the ADC output code of one channel with an input
voltage set close to the maximum voltage (1.9 V) over 14 h, without the
temperature compensation system. Each plotted dot in the solid line is the
mean value of 512 measurements. Dotted line: evolution of the ambient
temperature.
between 21 and 37 LSB have been measured. These values
correspond to an offset spread of 14-mV peak-peak longer
than the 5-mV rms offset obtained in simulation. There is
no correlation between the channel number, the gain, and the
offset dispersion. Note that these dispersions can be corrected
on digital data after calibration. There was no measurable
crosstalk between channels.
E. Endurance and Temperature Measurements
In this part, we focus on endurance and stability with
temperature measurements. Fig. 19 shows on the same plot
the ADC output code of one channel with an input voltage
close to the maximum (1.9 V, each plotted dot being the
mean value of 512 measurements) versus time and the ambient
temperature of the room versus time (14 h) without the
temperature compensation system turned ON.
This plot allows us to validate the good stability of the test
bench and the ADC measurement over a long period (14 h).
The input voltage of 1.9 V is chosen, because it is in this
configuration (end of the ramp voltage) that the largest varia-
tions in the slope versus temperature are found (worst case).
A high correlation is observed between the ADC mean output
code and the ambient temperature in Fig. 19. As shown
in Fig. 10 and (6), the output code varies linearly and in
opposite sign of the temperature. With a 7.5 C temperature
1078
Fig. 20. Evolution of the ADC output code of one channel with an input
voltage set close to the maximum voltage (0.1 V) over 14 h, without the
temperature compensation system. Each plotted dot in the solid line is the
mean value of 512 measurements. Dotted line: evolution of the ambient
temperature.
Fig. 21. Evolution of the ADC output code of one channel with an
input voltage set close to the maximum voltage (1.9 V) over 14 h, with
the temperature compensation system. Each plotted dot in the solid line is
the mean value of 512 measurements. Dotted line: evolution of the ambient
temperature.
change, an output code range of 7 LSBs is observed that
corresponds to a sensitivity of 0.93 b/C. This is much more
than the simulated value of 0.24 b/C. In order to check
whether this effect comes from the variation in the ramp
generator capacitance or is an offset of the output code,
we performed the same measurement in the beginning of the
ramp with an input voltage of 100 mV, as shown in Fig. 20.
An anticorrelation is observed between the ADC mean
output code and the ambient temperature. With a temperature
change of 4 C, an output code range of 0.7 LSB is observed
that corresponds to a sensitivity of 0.175 b/C. The sensitivity
is lower for smaller voltages. We conclude that the variation
of output codes caused by temperature evolution is mainly due
to the alteration of the ramp slope (gain) and not the outcome
of an offset.
We repeat the same measurement with the temperature
compensation system enabled. Fig. 21 shows on the same plot
the ADC output code of one channel with an input voltage
set at the top of the input range (1.9 V) versus time and the
ambient temperature of the room versus time (14 h).
The code does not depend on temperature change any
longer. With a temperature change of 4 C, an output code
range of 0.04 LSB is measured that corresponds to a sensitivity
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 64, NO. 4, APRIL 2017
Fig. 22. ADC output code as a function of the elapsed time with a fast
temperature variation of 50 C in 39 s with (solid line) and without
(dotted line) the temperature compensation system.
Fig. 23. Description of the ASIC radiation test bench.
of 0.01 b/C. This new temperature compensation system
is a great improvement for this ADC and is justified in
temperature-sensitive environments.
Submitting the chip to fast temperature change, the com-
pensation system still performs well, as shown in Fig. 22.
These tests show a large variation of 45 LSB in the output
code when the temperature compensation system is OFF.
A slow return to the ambient temperature of 26 C can be
observed. Activating the temperature compensation system,
a very small variation of the ADC output code of 2 LSB on
average can be observed. The efficiency of this on chip temper-
ature compensation system is validated. This test proves that
OWB-1 can be used in environments where the temperature
can change rapidly.
F. Latchup Tests
Radiation tests have been conducted at UCL Louvain on
September 2015. The high range (high energy) heavy ion
coktail (M/q = 3.33) of the Cyclotron Resource Center (CRC)
has been used. These measurements are performed dur-
ing 20 min to characterize two OWB-1 ASICs sensitivity
to SEL. The cocktail M/q = 3.33 achieves a Silicon LET
of 62.5 MeV/(mg/cm2) through the Xenon: 124Xe35+.
BOUYJOU et al.: 32-CHANNEL 13-b ADC FOR SPACE APPLICATIONS
The ions are aimed at the ASICs. The ASICs have been
placed in a vacuum chamber and are monitored with a
delatcher, as shown in Fig. 23.
There was no visible SEL observed for a minimum LET
of 62.5 MeV.cm2 .mg1 and for a flux of 1000 part cm2 s1
during 20 min.
V. C ONCLUSION
A 32-channel, 13-b single slope with DLLs ADC has
been presented. This special architecture improves the ADC
resolution by 5 b without additional power consumption and
time penalty. Special design techniques have been used to
increase the hardness of the ASIC to SEL and no visible
SEL for a minimum LET of 62.5 MeV cm2 mg1 has been
observed.
Measurements of noise, consumption, and linearity have
shown a very good performance. The ADC consistently main-
tains a resolution of 13 b for 32 channels converted in parallel
at a speed of 370 kHz. A new temperature compensation
system is implemented ensuring a very good stability of the
conversion over temperature changes. A built-in programmable
slow-control maximizes operational flexibility, allowing the
possibility to easily adapt this multichannel ADC to various
applications.
Considering these results, the next step will be to use this
ADC to digitize the output of a front-end chip associated to a
sensor to measure the energy spectrum of a radioactive source.
ACKNOWLEDGMENT
The authors would like to thank the CNES (French
National Space Agency) for their support for this paper. They
would also like to thank E. Vandeventer, T. Chaminade, and
H. Leprovost for their help on the ASIC test bench.
1079
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