4622 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO.

9, SEPTEMBER 2014

A New Multilevel Inverter Topology With

Self-Balancing Level Doubling Network
Sumit K. Chattopadhyay, Student Member, IEEE, and Chandan Chakraborty, Senior Member, IEEE

AbstractA new multilevel inverter (MLI) topology is proposed
using a level doubling network (LDN). The LDN takes the form of
a half-bridge inverter to almost double the number of output volt-
age levels. The concept (of the proposed LDN) has the capability
of self-balancing during positive and negative cycles without any
closed-loop control/algorithm, and it does not consume or supply
any power. The topology uses a symmetric cascaded H-bridge MLI
but offers an equivalent performance of an asymmetric topology
in terms of the number of levels. Also, it maintains the merit of
uniform loading of the individual cell for a symmetric MLI. The
topology is implemented by connecting only a three-arm H-bridge
(only two switches per phase) with the entire three-phase inverter
to double the number of levels. Thus, it significantly improves the
power quality, reduces the switching frequency, and reduces the
cost and size of the power filter. Operation of the circuit is verified
by simulation result and experiments from a laboratory prototype.
Index TermsAC drives, converter topology, level doubling
network (LDN), multilevel inverter (MLI), power quality.
I. I NTRODUCTION
N ONAVAILABILITY of power electronic switches capa-
ble to withstand high voltage is the main motivation
for the promotion of multilevel inverters (MLIs). Over the
years, this technology is extensively investigated and has now
reached a level of maturity. MLIs are now very popular and
globally recognized topology for many industrial applications,
like medium-voltage ac drives, renewable energy, HVDC and
FACTS, traction and propulsion systems, electric vehicles, etc.
In high-voltage and high-current applications, high switching
frequency is prohibited mainly due to switching losses and high
dV /dt. Efforts are put to achieve acceptable voltage waveform
and power quality through reduced switching frequency. The
number of voltage level that can be generated using a minimum
number of switching devices remains very crucial for such
topologies. A number of approaches are proposed to increase
the number of levels of MLI. References [1][3] cover most of
the important modulation, control, and topological reviews.
Cascaded H-bridge (CHB) MLI allows one to achieve high-
quality output voltages and input currents and also high reli-
ability due to their intrinsic component redundancy [2]. One
Manuscript received April 19, 2013; revised September 19, 2013; accepted
October 22, 2013. Date of publication November 13, 2013; date of current
version March 21, 2014. The laboratory prototype of this work was developed
with partial financial support from the Department of Science and Technology,
Government of India, through project Grant (No.SR/RC-UK/Solar-2(C)/2010).
The authors are with the Department of Electrical Engineering, In-
dian Institute of Technology Kharagpur, Kharagpur 721302, India (e-mail:
sumitkc1981@gmail.com; chakraborty@ieee.org).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2013.2290751
of the techniques to increase the number of levels is by intro-
ducing asymmetry in voltage ratio of the inverter cells. The
asymmetric structure of the MLI is introduced in [4] and [5]
and is capable to produce a very high number of levels with
a given switch count [2]. For a given topology, the number
of levels depends on the configuration of the dc voltage ratio
(leading to binary, trinary, and other configurations). Note that,
in asymmetric structure, powers delivered by the various levels
are quite different [2]. While most of the power is delivered by
the highest voltage cell [6], the lower voltage cells deal with
only a fraction of the same. This is a serious limitation of such
configurations for applications in ac drives.
A scheme for floating source binary MLI is presented in
[7]. In this topology, special attention is required to take care
of the voltage balancing problem demanding complex control
algorithms. This is also not very suitable for high-power appli-
cations. In [8], higher voltage and higher number of levels are
achieved using low-voltage switch-based power converters and
summing transformer. In this topology, high-voltage switches
are avoided at the cost of summing transformers. Neutral point
clamped (NPC)-CHB hybrid and asymmetric topology are
introduced in [9]. A CHB with a dc bus voltage lower than
NPC is connected in between the NPC terminal and the load
terminals to obtain finer and more numbers of voltage steps.
This topology also requires special attention to take care of the
voltage balancing problem.
As already discussed, an asymmetrical configuration has un-
equal power sharing. This does not allow the bridges to be eas-
ily replaced (as the high side and low side bridges most likely
to be made by different power devices) and hence loses the
advantage of modularity. This makes the asymmetric topology
not very attractive for medium-voltage (MV) drives and many
other applications. Recently, many hybrid multilevel topologies
are proposed [10][17]. However, the symmetric CHB structure
has definite merits in high-power applications due to fault
tolerance/reliability and modularity. The recent trend is to use a
symmetric MLI fed by a multipulse rectifier [18][24] for high-
and medium-power applications in industry. Many topologies
were proposed with floating capacitors [example: flying ca-
pacitor (FC)-MLI] or capacitor-based voltage dividers (exam-
ple: NPC MLI) [10][17], [25][28], and (example: modular
MLI) [29]. Synchronous optimal pulsewidth modulation [30]
is utilized for neutral point balancing in [31]. All of these
works overcome the voltage balancing problem of the floating
capacitor with considerable effort, necessitating either some
algorithm [11][17], [26], [27], [29], [31] or external voltage
balancing network [28]. The proposed work has definite edge
over the existing ones as this does not require any attention to

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CHATTOPADHYAY AND CHAKRABORTY: NEW MULTILEVEL INVERTER TOPOLOGY WITH SELF-BALANCING LDN
Fig. 1. Circuit diagram of the proposed topology (single-phase version).
balance its floating capacitor. The capacitors here maintain the
voltage by virtue of the self-balancing property of the topology,
detailed at a later stage in this work.
This paper proposes a new topology to almost double the
number of levels in an MLI, by adding only two switches per
phase. This paper is organized as follows. Section I puts for-
ward the motivation of the work with a literature review of the
existing techniques to boost up the number of levels. Section II
explains the operating principle of the configuration proposed.
Section III explains the inherent self-balancing capacity of
the level doubling network (LDN). Section IV describes the
approach for sizing of the LDN capacitor. Sections V and
VI report the results from simulation and experimentation,
respectively. A laboratory prototype is made for this purpose.
Section VII concludes the work.
II. P ROPOSED T OPOLOGY
The single-phase version of the proposed topology is shown
in Fig. 1. The topology is realized by adding an extra half-
bridge connected to a capacitor that maintains half the volt-
age of other bridges by a self-balancing mechanism. For a
three-phase system, three half-bridges (i.e., one half-bridge per
phase) in parallel are required. Thus, effectively, a three-phase
full-bridge needs to be connected as shown in Fig. 2. Note
that the dc buses of these half-bridges do not consume any
power. If this delivers a given amount of power in the first half
cycle, it will absorb the same amount of power in the next half
cycle.
For the configuration considered in Fig. 1, if it is assumed
that there are N number of H-bridges (each with a dc bus
voltage of V ) that are cascaded, then the MLI circuit can
generate 2N + 1 levels of output voltage without the LDN (i.e.,
N V to N V in steps of V ). When the half-bridge comes in
4623
Fig. 2. Circuit diagram of the proposed topology for three-phase output.
operation, we get N additional levels in the positive half cycle
with the output voltage: V /2, 3V /2, 5V /2, . . . , (2N 1)V /2
(by adding voltage V /2 with 0, V , 2V, . . . , (N 1)V , respec-
tively, in the positive half cycle). Similarly, on the other half
cycle, N additional levels are obtained (i.e., V /2, 3V /2,
5V /2, . . . , (2N 1)V /2). However, the difference with
the first half cycle is that the levels are obtained by alge-
braically summing the half-bridge voltage V /2 with V , 2V ,
4V, . . . , N V , respectively. Therefore, in the second half
cycle, the dc bus of the half-bridge will be equally charged.
Finally, at the end of one complete cycle, the dc bus voltage of
the half-bridge will ideally remain unchanged. This will remain
valid for any power factor (as the power distribution ratio of
MLI is independent of power factor [32]).
Each phase of the inverter may operate in one of the four
different modes as illustrated in Fig. 3. When the inverter
produces an even voltage level with either positive or negative
polarity, the LDN will be bypassed, as shown in Fig. 3(b) and
(d). When an odd voltage level is generated, LDN will always
be in the circuit as shown in Fig. 3(a) and (c). For the positive-
side half cycle, LDN voltage will be added with the rest of
the converter voltage. Fig. 3(a) can be referred to understand
the equivalent circuit in this condition. When it is required to
generate an odd voltage at negative half cycle, the positive LDN
voltage will be algebraically summed with the negative voltage
of the rest of the converter as shown in Fig. 3(c). A switching
table is thus formed for the proposed inverter with three CHBs
per phase (as shown in Table I). Cells 1, 2, and 3 are of equal
voltage. Cell 4 is at a voltage half of other cells and having
only two switches (due to half-bridge configuration). Cell 4
acts as a level doubling block for the entire inverter circuit.
For a polyphase system, these LDNs of all phases may be
4624 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 9, SEPTEMBER 2014

Fig. 4. Energy-balance-determining waveforms for the LDN.

levels in both positive and negative sides to be 2N , resulting in

Fig. 3. Operating modes of the proposed inverter along with LDN. (a) Positive
odd voltage level generated by adding the LDN voltage. (b) Positive even
voltage level generated by bypassing the LDN. (c) Negative odd voltage level
generated by algebraically summing the positive LDN voltage with negative
voltage wrt ground. (d) Negative even voltage level generated by bypassing
the LDN.
TABLE I
S WITCHING TABLE OF O NE P HASE
a total of 4N + 1 levels (by including the LDN).
Therefore, if the LDN is added to a 2N + 1 level MLI, the
topology will effectively behave like an MLI of 4N + 1 levels,
where N is an integer. Note that the LDN will always apply a
positive voltage with respect to ground when it will be required
to produce an odd voltage level, as shown in Fig. 4.
Now, we assume that the inverter is driving a load with a
power factor of cos . There will be 2N discrete intervals per
half cycle when the LDN will apply a positive voltage at its
terminal. For the rest of the intervals, its terminal voltage will
be zero.
The energy delivered/absorbed (by the LDN) at any nth
interval is

2n

Wn = V Im sin d (1)
2n1

where Im is the peak magnitude of the sinusoidal load current,

is the phase difference between the load current and the
reference voltage, and V is the dc bus voltage. The energy
delivered or absorbed by this network will depend on the sign
of the integration.
Therefore, the total energy values delivered in the first half
cycle (W1st ) and second half cycles (W2nd ), respectively, are


2N 
2n

W1st = V Im sin d (2)

n=1
2n1
connected to a common dc bus and will also help in reducing
the dc bus current ripple (with corresponding reduction in dc 
4N 
2n

bus capacitance). It is important to note that, for N number W2nd = V Im sin d. (3)
of voltage cells, the symmetry restricts the maximum voltage n=2N +1
2n1
CHATTOPADHYAY AND CHAKRABORTY: NEW MULTILEVEL INVERTER TOPOLOGY WITH SELF-BALANCING LDN 4625

Equation (3) may be rewritten as

+2N
4N

2N
W2nd = V Im sin d. (4)
n=1
4N +2N 1

From the voltage waveform shown in Fig. 4, it may be

noted that

4N +1 = + 1 , . . . , 8N = + 4N . (5)

Therefore, the right-hand-side integrals of (4) may be rewrit-

ten as
+2n
4N 2n
+

V Im sin d = V Im sin d. (6)

4N +2n1 +2n1

From (2), (4), and (6), the following relation may be

achieved:

W1st = W2nd . (7)

Hence, the energy delivered/absorbed in first half cycle will

be equal to the energy absorbed/delivered by LDN in the next
half cycle.
Fig. 5. Generalized equivalent circuit of the converter at any nth level with
LDN (a) at the negative half cycle and (b) at the positive half cycle after time
III. I NHERENT S ELF -BALANCING C APABILITY U NDER period .
T RANSIENTS AND D ISTURBANCES

Due to various possible transients and disturbances, the dc (n1)V
+ V vc e
bus voltage of the LDN may become higher or lower than Q= 2
z
the desired voltage for short duration. This section illustrates
the self-balancing capability of the LDN without any closed- (n1)V

+ v c e
loop control. The basic assumptions for this explanation are the + 2 T
following. z
 
1) The output voltage and current waveforms will have half- 2vc V
wave symmetry. = T. (10)
z
2) There will be a negligible dc component in the output
current waveform under steady state. If 2vc > V , then the capacitor will be discharging and will
3) A load with back EMF will also have half-wave symme- reduce its voltage. Moreover, if 2vc < V , the charge delivered
try in back EMF. by the capacitor is negative (i.e., the capacitor will be getting
Fig. 5(a) shows the inverter circuit intending to generate an charged and raising its voltage). At steady state, the output
output voltage of nV /2 with respect to ground (where n is an current will have half-wave symmetry. Therefore, considering
odd integer). The average current flowing through the capacitor Q = 0 in (10), it may be concluded that vc = v/2 in steady
in Fig. 5(a) is expressed in (8). Fig. 5(b) shows an equivalent state. Therefore, the desired voltage of the dc bus capacitor
circuit of the inverter intending to generate a voltage of +nV /2 of LDN will be reached without any dc bus voltage balancing
with respect to ground. Therefore, the expression of the average mechanism and/or closed-loop control.
current flowing through the capacitor during this interval will be
given in (9).
Assuming that both levels exist for a period of T , the expres- IV. LDN C APACITOR S IZING
sion of the net charge delivered/absorbed by the capacitor in
those two intervals is expressed in (10): Sizing of the capacitance used in the LDN is highly applica-
tion dependent. The worst case of discharging/charging of this
(n1)V
+ V vc e capacitor is influenced by following factors.
ic  = 2
(8)
z 1) The maximum output current drawn at a given frequency:
(n1)V
+ vc e the higher the output current, the higher is the LDN
ic+  = 2
(9) capacitor requirement.
z
4626 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 9, SEPTEMBER 2014

find the capacitor requirement at any given modulation index.

Therefore, the LDN capacitance is found for all modulation in-
dex individually, by finding the maxima/minima of the integral
of (22). From Fig. 6, it may be noted that, in a given modulation
index, for a particular value of n, n may have two solutions. In
such cases, the higher value of n will be recorded as 2N +1 ,
else 2N +1 = /2.
The phase currents of the inverter are given as

IR (t) = Im Sin(ma t) (13)

IY (t) = Im Sin(ma t 2/3) (14)
IB (t) = Im Sin(ma t + 2/3) (15)

where is the frequency of the current waveform correspond-

ing to ma = 1. Therefore, the currents through the LDN for the
three phases are
R R
ILDN = IR (t)fLDN (t) (16)
Y Y
ILDN = IY (t)fLDN (t) (17)
Fig. 6. (a) Output phase voltage versus time for different modulation indexes. B B
ILDN = IB (t)fLDN (t) (18)
(b) Conduction interval of LDN for different modulation indexes.
R
where fLDN is a function for the R phase, expressed as
2) The worst case capacitor ripple occurs at unity power 2N +1
factor. Therefore, the power factor is assumed as unity   


n
in this calculation.
R
fLDN (t) = 1 (n+1)
u t +k
n=1
ma
3) Increasing the number of phases can drastically reduce k=0



the LDN capacitor requirement. n
t 1 +k (19)
4) The modulation strategy has an influence on capacitor ma
sizing.
where u(t ) is the unit step function with a time delay
In this paper, the analysis of capacitor sizing is kept limited
of as 1 2 , 3 4 , 5 6 , . . . , (2 2 ) (2
to three-phase MLI as shown in Fig. 2, with constant V /f ratio
1 ), . . . are the instants when the LDN for the R phase conducts
(as it is used to be in drive application) and nearest level control. Y B
(vide Figs. 4 and 6). Similarly, fLDN (t) and fLDN (t) will
The level doubling concept works equally with or without third
be the corresponding functions for the Y phase and B phase,
harmonic injection in the phase voltage. However, in this paper,
respectively
typical results with third harmonic injection are shown, which


reduced the capacitor requirement of LDN and increased the Y R 4
line-to-line voltage by approximately 15%. fLDN (t) = fLDN t + (20)
3ma
The following nature of the third-harmonic-injected wave-

B R 2
form is considered: fLDN (t) = fLDN t+ . (21)
3ma
Vph = N V ma (1.15 sin + .19 sin 3) (11) Since the LDNs of all of the phases are sharing a common
dc bus (as shown in Fig. 2), the current through the capacitor
where ma is the modulation index. Therefore, the switching
across the LDN (i.e., the LDN capacitor) may be expressed as
instants n can be found from the following equation:
R Y B
2n1 ILDN = ILDN + ILDN + ILDN . (22)
ma (1.72 sin n .76 sin3 n ) = (12)
4N
The nature of the current through the LDN is highly non-
where n = 1, 2, 3, . . . , 2N as shown in Fig. 4 and n /2. If linear due to multiple discontinuities as shown in Fig. 6.
(12) does not have any solution for a given n , in a particular Overlapping of these discontinuous current segments (due to
modulation index, then n = /2. N = 3 for this paper (as sharing of the common dc bus) for all phases finally forms
shown in Fig. 2). The 3-D plot in Fig. 6(a) shows how the the resultant current. The requirement of maximum value of
third-harmonic-injected voltage waveform changes with the the capacitor (corresponding to the worst case situation) may
modulation index for the output voltage considered in this work be found by plotting the LDN capacitor required at various
(the voltage is presented in p.u., and waveforms are drawn modulation indexes within the operating range and with rated
for the quarter cycle only). The top view of this 3-D-plot in current at each modulation index. Fig. 7 shows the plot. The
Fig. 6(b) helps in understanding the reason of nonlinearity. The dc bus voltage ripple across the capacitor is kept within 1%.
shaded areas, for which the LDN is supposed to carry the phase This figure also indicates that less capacitance is required with
current, are indicated. This figure provides an excellent tool to third harmonic injection. Considering the effect of ESR, a
CHATTOPADHYAY AND CHAKRABORTY: NEW MULTILEVEL INVERTER TOPOLOGY WITH SELF-BALANCING LDN 4627

Fig. 7. Requirement of LDN capacitance wrt the modulation index, with and
without third harmonic injection for the same load.

TABLE II
S IMULATION PARAMETERS

capacitance of 66 000 F is chosen (even if a requirement of

nearly 34 000 F is observed in Fig. 7). The higher value of the Fig. 8. Output line voltage and corresponding phase voltage waveforms
LDN capacitor increases the start-up transient but makes the with fundamental frequency switching, nearest voltage level control, and third
harmonic injection in phases. (a) Without LDN. (b) With LDN.
system less sensitive to load disturbance. A precharge circuit of
the LDN may be provided to avoid this transient if the LDN
capacitor is high enough to cause a long start-up transient.

V. S IMULATION R ESULTS
The performance of the topology is evaluated by simulat-
ing the circuit in MATLAB/Simulink. A Simulink model is
developed for the three-phase version of the proposed topol-
ogy. The output voltage and current waveforms and their total
harmonic distortion (THD) are analyzed in detail. Also, the
performance of the LDN and its energy consumption are inves-
tigated. Table II shows the parameters used for simulation. The
corresponding phase and line voltages without and with LDN
are shown in Fig. 8(a) and (b), respectively. While Fig. 8(a) Fig. 9. Comparison of energy delivered by one of the H-bridges and the LDN.
shows 7 levels per phase and 13 levels line-to-line, Fig. 8(b)
confirms 13 levels per phase and 25 levels line-to-line. The
energy delivered by one of the H-bridges and the LDN is
compared in Fig. 9. The instantaneous product of the source
voltages and corresponding source currents is integrated to find
the energy delivered over a period of time. One of the H-bridges
has delivered nearly 8.7 kJ of energy in 0.5 s, while the LDN
has not delivered/absorbed any energy in the same interval (as
shown in Fig. 9). The energy-time waveform of the LDN is
zoomed in Fig. 10. As the LDN for the three-phase system
shares a common dc bus (as shown in Fig. 2), there are three Fig. 10. Zoomed waveform of the energy charge-discharge cycle of the LDN.
charging and discharging cycles over a complete cycle of
the output voltage waveform. The time period of the output As derived in Section III, the dc bus voltage of the LDN
voltage is 0.02 s (50 Hz). Therefore, there are 15 charging and should reach 47 V (vc = v/2 at steady state and V = 94 V as
discharging cycles in 0.1 s of time as shown in Fig. 10. indicated in Table II) from any initial condition. This is verified
4628 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 9, SEPTEMBER 2014
Fig. 11. LDN dc bus voltage transient while reaching the desired steady-state
voltage in open loop. (a) Initial voltage is higher than the desired voltage (200%
of desired). (b) Initial voltage is lower than the desired voltage (0% of desired).
Fig. 12. Output line voltage and corresponding third-harmonic-injected phase
voltage waveforms of the proposed topology with multicarrier PWM (carrier
frequency of 5 kHz).
by simulation. Fig. 11(a) indicates that the simulation was
started with an initial voltage double than the desired voltage,
and Fig. 11(b) indicates that the simulation was started with
zero initial voltage; finally, in both cases, the LDN voltage is
settling to the desired voltage. The self-regulating characteristic
of the LDN is thus proved by simulation.
For a lower modulation index, the inverter output will have
a lower number of levels. Fundamental frequency switching
with a lower number of levels will result in higher THD of
the current output. In order to obtain better power quality at
a lower modulation index, a multicarrier PWM with a moderate
switching frequency of 5 kHz is utilized. The line voltage wave-
form and corresponding third-harmonic-injected phase voltage
waveforms with multicarrier PWM are shown in Fig. 12. The
three line voltages of three phases are shown together in Fig. 13.
The energy-time waveform in Fig. 10 is observed with 5-kHz
PWM carrier frequency (without three-phase symmetry). It
may be noted that any three successive charge-discharge cycles
are unequal and repetitive in the time period of the output
voltage.
Fig. 13. Output line voltage of three phases together.
TABLE III
H ARDWARE S ETUP D ETAILS
VI. E XPERIMENTAL R ESULTS
A symmetrical CHB-MLI prototype available (three
H-bridges cascaded per phase) in the laboratory is reconfigured
to operate as the proposed (i.e., 13 level per phase and
25 level line-to-line by means of third harmonic injection)
inverter by connecting a three-arm H-bridge inverter externally
to the CHB-MLI as shown in Fig. 2. The major parameters of
the hardware setup are given in Table III. The performance of
the LDN is first verified by operating the prototype to drive
an RL (details are shown in Table III) load. The line voltage
and corresponding third-harmonic-injected phase voltages are
captured in Fig. 14. Here, 13 levels at the phase voltages and
25 levels at the line voltage can be observed. The peak line
voltage observed is double the peak of the phase voltage.
The line voltage and corresponding line current are shown in
Fig. 15. The THD of the line current was within 1.6%.
An induction motor (Brown Boveri make) with 400-V line-
to-line voltage rating is next driven by this setup. The dc bus
of three H-bridges was kept at 94 V so that about 400 V will
be the maximum line-to-line voltage possible by adapting third
harmonic injection.
To validate the concept at all operating conditions, the motor
was driven from a frequency of 55 Hz (overmodulated condi-
tion) to 25 Hz approximately, at the steps of 5 Hz as shown in
CHATTOPADHYAY AND CHAKRABORTY: NEW MULTILEVEL INVERTER TOPOLOGY WITH SELF-BALANCING LDN 4629

Fig. 14. Line voltage and corresponding third-harmonic-injected phase volt-

ages applied to the RL load.

Fig. 15. Line voltage (channel 1) and line current (channel 2) of the RL load.

Fig. 16. Fig. 16 also highlights that the LDN dc bus voltage
was observed to swing within the range of 46.2-48.6 V in
the entire operating range. Discussions in Section III may be
referred to conclude that the LDN dc bus voltage should reach
47 V without any closed-loop control (under ideal condition).
The deviation is due to the nonidealities in the network, and it
will reduce further (in terms of percentage) with higher dc bus
voltage. To verify the self-balancing capability of the system
under harmonic load, the harmonic current is drawn from the
inverter output.
The harmonic current waveform and the LDN dc bus voltage
are provided in Fig. 17. Half-wave symmetry is maintained in
the harmonic current, and the LDN dc bus voltage was observed
to be within 1 V of the desired value. Self-balancing happens
through charging and discharging the capacitor when with load.
The self-balancing capability of the LDN dc bus voltage
under transient condition is experimented and illustrated in
Fig. 18. An initial voltage of 75 V is applied to the LDN capac-
itor as observed in Fig. 18(a), and it reaches the desired voltage
without any closed-loop control. Similarly, in Fig. 18(b), the
LDN voltage starts rising from an initial voltage much lower
Fig. 16. LDN voltage is stable under different modulation indexes and
than the desired voltage and finally gets settled at the desired frequencies.
value.
both symmetric and asymmetric topologies. However, when
applied with a symmetric topology, this has not only increased
VII. C ONCLUSION
the levels but also maintained uniform power loading of the
This paper has presented a new concept to increase the individual cell of the cascaded configuration. The dc bus of
number of levels in a cascaded MLI. A three-phase bridge the H-bridge block ideally remains in self-balancing condition.
network is used to almost double the number of levels of the The operating principle of the circuit is explained. A detailed
three-phase cascaded MLI. The concept may be applied for simulation is presented using MATLAB/Simulink. A laboratory
4630 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 9, SEPTEMBER 2014
Fig. 17. LDN dc bus voltage is stable under harmonic load current with half-
wave symmetry.
Fig. 18. Transient of the LDN dc bus. (a) Higher voltage to the desired
voltage. (b) Lower voltage to the desired voltage.
prototype is produced using dSPACE1104 controller. The sim-
ulation results match well with the corresponding experimen-
tal counterpart, confirming the effectiveness of the proposed
topology. Such configurations are expected to be very useful
in medium-voltage drives and other applications.
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Sumit K. Chattopadhyay (S11) received the B.E.
degree in electrical engineering from Burdwan Uni-
versity, Bardhaman, India, in 2004 and the M.Tech.
degree in industrial electrical systems from the Na-
tional Institute of Technology Durgapur, Durgapur,
India, in 2006. He has been working toward the
Ph.D. degree in the Department of Electrical Engi-
neering, Indian Institute of Technology Kharagpur,
Kharagpur, India, since January 2010.
From September 2006 to January 2010, he was a
Design Engineer of power electronic system design
with Larsen & Toubro Ltd., Navi Mumbai, India, where he was responsible for
power electronic system design of multiple industrial and mission-critical naval
projects executed for the first time in India with foreign collaboration. His area
of research is power electronic converter for grid-connected photovoltaic sys-
tems. His research interests also include converter topologies, machine drives,
field-programmable gate array-based embedded system design, economic uti-
lization of upcoming power electronic devices, and power electronic converters.
4631
Chandan Chakraborty (SM01) received the B.E.
and M.E. degrees in electrical engineering from
Jadavpur University, Kolkata, India, in 1987 and
1989, respectively, and the Ph.D. degrees from
the Indian Institute of Technology Kharagpur,
Kharagpur, India, and Mie University, Tsu, Japan, in
1997 and 2000, respectively.
He is currently a Professor with the Department
of Electrical Engineering, Indian Institute of Tech-
nology Kharagpur. His research interest includes
power converters, motor drives, electric vehicles, and
renewable energy.
Dr. Chakraborty is a fellow of the Indian National Academy of Engineering.
He is currently the Chair of the Power Electronics Technical Committee of the
IEEE Industrial Electronics Society (IES). He is an ADCOM member of the
IEEE-IES. He is one of the Technical Program Chairs of IECON2014 to be held
in Dallas, TX, USA. He was the Technical Program Chair/Cochair of ICIT2006,
ICIT2008, ICIT2010, and IECON2012, held in Mumbai, Melbourne, Chile,
and Montreal, respectively. He has been regularly associated with IECONs and
ISIEs as a track chair in the areas of power electronics and electrical machines.
He is one of the Associate Editors of the IEEE T RANSACTIONS ON I NDUS -
TRIAL E LECTRONICS and IEEE I NDUSTRIAL E LECTRONICS M AGAZINE ,
and an Editor of the IEEE T RANSACTIONS ON S USTAINABLE E NERGY. He
is the Founding Editor-in-Chief of IE Technology News, a web-only publication
of IEEE-IES. He was awarded the JSPS Fellowship to work at the University
of Tokyo (at Hongo Campus) in 2000-2002. He received the Bimal Bose award
in power electronics from the IETE, India, in 2006.