CIRCUITS AND

6.002x ELECTRONICS

Energy,
CMOS

Reading Section 11.4, 11.5 of A&L 1

Review Hypothetical example circuit
R1
S1 S2
VS +
C R2 P = CVS f
2

T
T1 T2

S1 closed S1 open 1
S 2 open S 2 closed
T = T1 + T2 =
f
t

2
Review Inverter RL
Eqvt. ckt On for T/2
VS Off for T/2
RL
VS +
C
RON
vO
vIN RON C

2
vIN VS
P= + CVS f
2

2 RL
T T
2 2
P STATIC P DYNAMIC
T t
1
T=
f 3
Review Inverter numbers
2
V
One gate: P = S + CVS 2 f
2 RL
C =1f F
P STATIC P DYNAMIC
RL = 10 k
25 15 9
P = 5 10
6
+ 10 25 3 10 f = 3 109
2 10
4
VS = 5 V

= 5 10 [1.25 milliwatts + 75 microwatts]

6 # gates = 5 106

6.25KW! 375W
bad
disaster !

How do we get rid of static power?

4
How to get rid of static power
Intuition:

1
How to get rid of static power when input is high
VS VS
Intuition:
vI high vI low RL
i RL vO high
vI high vO low vI low
MOSFET
RON off
Problem case No problem

2
New Device PFET
N-channel MOSFET (NFET) P-channel MOSFET (PFET)

1
Consider this circuit

2
Behavior of the circuit VS

vI = 5V (input high) vI = 0V (input low) S

G D
vI vO
+ D
G S

3
Key: no path from VS to GND! no static power!
Lets compute P DYNAMIC
VS

vO
vI

vI
T

t
1
f =
T
1
Using numbers from our previous example for CMOS
2
P = CVS f
C =1f F
RL = 10 k
f = 3 109
VS = 5 V
# gates = 5 106

2
 2
Scaling up Increase frequency and number of gates, P = CVS f
but if everything else stayed the same C =1f F

Gates f
RL = 10 k
P
100 ~2.5 f = 3 109
106 MHz watts VS = 5 V
300 ~15
2x106 MHz watts
600 ~30
2x106 MHz watts
~375
5x106 3 GHz watts
~1875
25x106 3 GHz watts

3
How to reduce power 2
P = CVS f
C =1f F
RL = 10 k
f = 3 109
VS = 5 V

13
 2
Real numbers P = CVS f
Transistors f P
Intel Pentium
2.5x106 66 MHz 15W 700nm, 1993

Intel PII
7.5x106 400 MHz 35W 350nm, 1997

Intel PIII
44x106 1 GHz 15W 180nm, 1999

MIT Raw processor 16-core

120x106 0.43 GHz 18W 180nm, 2002

Intel PIV
120x106 3 GHz 75W 130nm, 2001

Tilera Tile64Pro 64-core http://groups.csail.mit.edu/cag/raw

615x106 0.7 GHz 20W 90nm, 2007

Intel Nehalem 8-core

2300x106 3.6 GHz 75W 45nm, 2011

2
Scaling up leakage arises, causes static power dissipation

3
CMOS Logic
S on S
G D G D

1
In general, if we want to implement F

2
If we want to implement F
e.g. F = A B
VS
VS
short
when F
is true, A B
else open
A
Z Z
B short A
when F
is true, B
else open