Design Metrics For RTL Level Estimation Of Delay
Variability Due To Intradie (Random) Variations
Michael Merrett, Yangang Wang, Mark Zwolinski, Koushik Maharatna
School of Electronics and Computer Science
University of Southampton
Email: mam06r@ecs.soton.ac.uk , yw2@ecs.soton.ac.uk
mz@ecs.soton.ac.uk , km3@ecs.soton.ac.uk
AbstractA simple metric is presented for the accurate pre-
diction of path delay variability during the automated synthesis
of digital VLSI circuits. This allows circuit variability to be
assessed at early stages within the design process with minimal
computational effort, as extensive Monte Carlo or SSTA runs are
not required. This paper introduces the metric and investigates
its effectiveness. The final predictions of path delay variability
are found to be within 10% of measured path delay variability,
with an average error of 3%, for a series of test paths synthesised
from randomised models of a 130nm technology library. These
randomised models are generated from a 3D atomistic simula-
tor and provide more accuracy than traditional Monte Carlo
simulation runs.
I. I NTRODUCTION
The accuracy of timing validation tools and methods is
being challenged by the scaling of fabrication process dimen-
sions down to the nanometre level. Designers must be able to
alter their designs to accommodate random physical intradie
variations, but this relies on the ability to predict their effects
within design tools, something which is not yet fully available.
There has been much work within the literature to im-
prove statistical methods for the modelling of random intradie
variations; including correlations between delays [1]; adding
signal transition time and power supply variations [2] [3];
incorporating non-Gaussian distributions [4] and a metric of
sensitivity [5]. These incarnations of SSTA have increased
computational complexity over STA algorithms and have not
yet been adopted by the industry.
This paper presents the derivation and evaluation of a
simple but effective metric for the prediction of path delay
variability in CMOS logic circuits. This metric allows for
a rapid comparison of path variability, without the need for
extensive SSTA or Monte Carlo simulations. The variability
of a given path is defined as path
path
where path and path are
the mean and standard deviation of the path delay respectively.
The proposed metric permits the evaluation of the path
delay variability in any synthesis methodology (i.e., based on
wire load models or physically based), and strongly simplifies
the path timing analysis process for modelling the effects of
intradie variations on delays. The information required for
predicting path delay variability is minimal, as it depends on
very basic parameters of the cell involved in the synthesis,
which are known directly from the knowledge of the adopted
978-1-4244-5309-2/10/$26.00 2010 IEEE 2498
Massimo Alioto
Dipartimento di Ingegneria
dellInformazione (DII)
Universita di Siena
Email: malioto@dii.unisi.it
cell library (i.e. the number of stacked transistors and cell
strength).
Interestingly, the proposed metric permits statistical eval-
uation of the path delay by simply resorting to standard
(deterministic) CAD tools. In other words, no statistical timing
analyser is needed. This also permits a dramatic reduction of
the computational effort involved in SSTA in the early digital
design phases, and in the preliminary design space exploration
and comparison of different design options. Using the pro-
posed approach, SSTA can be performed only to validate the
final design version (sign-off) with a greater accuracy (and
computational effort).
The paper is structured as follows. Section II introduces the
metric, describing the assumptions made during the derivation.
Section III contains an assessment of the effectiveness and
limitations of the metric. A summary and conclusions is
provided in section IV.
II. D ESCRIPTION OF THE PROPOSED METRIC
Delay variations due to process variability of a given logic
gate depend on
1) Gate topology (i.e., logic function - number of stacked
transistors)
2) Transistor size
3) Input rise/fall time
4) Output parasitic capacitance of the gate
5) Load capacitance (interconnect + input capacitance of
the subsequent gate)
The following observations can be made about these vari-
ability sources in order to simplify the process of modelling the
intradie variability (i.e. variations that have a different impact
on different transistors within the same die [6]):
1) Topology affects the current Igate delivered by the gate
to the output capacitance. In [6], it was demonstrated
that the variations in the on current delivered by a
generic logic gate Igate (and hence the resulting delay
variations) are proportional to the reciprocal of the
square root of the number of stacked transistors nstack :
delay 1
(1)
delay nstack
 2) For a given topology, in [6] it was demonstrated that the
variability of Igate is proportional to the reciprocal of
the square root of the transistor size, i.e. the cell strength
[6]
delay 1 delays along the path are comparable, (4) can be simplified
(2)
delay strength
3) It can be shown that the effect of the input rise/fall time
on the delay variability tends to be negligible, compared
to the above discussed effects [6]
4) It can be shown that the effect of the output parasitic
capacitance on the delay variability is also negligible,
compared with the variation of the on current (see point
1) [6]
5) Effect of load capacitance (due to input capacitance
of subsequent gates and the in-between wires). The
input capacitance is rather insensitive to intradie process
variations [6]. Wire capacitance is well-known to be
rather insensitive to random intradie variations (highly
correlated) [7]
From observations 1, 4-5 and equations (1)-(2), the delay
variability of a logic gate due to random intradie variations
can be simply estimated as:
delay k
= (3)
delay nstack strength
where k is a technology-dependent constant that is easily
evaluated from very few preliminary simulations. From (3),
the delay variability of a logic gate for a given input transition
is characterised very easily from the knowledge of its topology
and strength (i.e., the cell version adopted - 1X, 4X, ...), which
are obviously known from the library that is adopted for the
synthesis.
It should be observed that the above considerations hold
for intradie process variations, but do not hold for interdie
variations. Nevertheless, interdie variations are well known to
be easier to model and compensate for with feedback adaptive
schemes [6] [7].
A. Early estimation of path delay variability
Under random intradie variations, the delays of all gates
belonging to a given path are uncorrelated random variables
with variability ii given by (3) (i = 1...N , where N = no.
of gates belonging to the considered path) [7]. The resulting
path delay variability results to (Gaussian pdf is assumed)
v of 2 when the input is falling and rising respectively. 10,000
u N  2 
path uX i i
2
=t
path i path
i=1
v
uN 2
uX

1 i
= kt (4)
nstack,i strengthi path
i=1
which is very easy to evaluate with standard CAD tools
(without SSTA) . Indeed, k is extracted once for a given tech-
nology, nstack and strength are defined by the structure of
i
the cells within the path, whereas the weight path represents
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the fraction of the path delay spent in the i-th gate and can
be deterministically evaluated by standard timing analysers.
The metric in (4) can be further simplified by introducing
some approximations. In particular, assuming that the gate
to
path k
= p (5)
path N nstack strength
where nstack is the average number of stacked transistors
along the path, strength is the average cell strength along the
path and N represents the path logic depth. Many other metrics
can be easily derived by considering that the gate delays are
not equal (the only difference is that the above parameters will
be evaluated as a weighted average).
III. E VALUATING THE D ESIGN M ETRICS
Previous work has been carried out by members of the
EPSRC funded nanoCMOS project [8] to produce a 3D atom-
istic simulator for characterizing stochastic process variations
within nanoscale transistors, [9], and on simulating the effects
of line edge roughness (LER) [10]. The Device Modelling
Group at the University of Glasgow (DMG), responsible
for a 3D atomistic simulator, have developed a tool named
randomspice, which can be used to replace every transistor
instance within a SPICE netlist with a randomly selected
BSIM model generated from this 3D simulator. This tool
allows the accurate modelling of random physical variations
within transistors, without approximations to Gaussian dis-
tributions, as opposed to usual analyses that simplistically
assume a Gaussian probability distribution for a couple of
device parameters (e.g., threshold voltage, transconductance
factor). Accordingly, randomspice simulation results provide
a more accurate reference, compared to usual analyses.
An investigation has been carried out to test the metric
described within (5), using randomspice models for a small
subset of a 130nm technology library, the method and results
of which are presented here.
A. Simulation Framework
Gates such as inverters, NANDs and NORs provide simple
test cases, as each gate has either a pull-up or pull-down
network consisting of transistors solely connected in series.
An inverter has an nstack value of 1 irrespective of the input
transition, while NOR and NAND gates have nstack values
randomspice netlists were generated for each of four paths
constructed from combinations of these simple gates shown
in Figure 1. The configuration of the testbench used in each
case is given in Figure 2.
The numerical value for the technology-dependent constant
k was obtained from the path variability results of the Inverter
chain, as the inverter represents the simplest CMOS logic
structure. This was obtained by first generating a prediction
of the path delay variability using (5) with k set to 1.
Results in Figure 3 confirm that a linear relationship exists
between the predicted and measured values, adding credibility
 (a) INVERTERS
(b) NAND Gates
(c) NOR Gates
(d) NAND & NOR Gates
Fig. 1. Test Circuits
to the proposed metric (i.e., the variability is confirmed to be
proportional to the right-hand side in (6) through a constant
k). Then, the numerical value of k was found from the
slope of the plot of the measured and predicted variability
(obtained through linear regression). Figure 3 shows a plot of
logic gate with a given nstack , an equivalent number of
the measured variability ( path ) against the prediction, where
path
k was found to be 0.0567. The calculated value of k was
then used to provide predictions of the path variability for each
of the remaining test paths. Figure 4 is a plot of the measured
path variability against the predicted path variability, which lie
within 25% of each other (this accuracy will be shown to be
significantly better under appropriate improvemets).
B. Analysis of Results
The predicted values of path delay variability for a rising
input transition in test path Figure 1(c), and for a falling input
transition for Figures 1(b) and 1(d), are on average within
5% of the measured values. For these input transitions the
pull-up and pull-down networks within the cells consist of
single switching transistor (inverters), or a switching transis-
tor arranged in parallel with an inactive transistor (NAND
and NOR gates). This suggests that the addition of inactive
transistors in parallel within the switching transistor does not
greatly increase the variability of the gate, as the proposed
metric does not include inactive parallel transistors within the
value of nstack and the generated predictions remain accurate.
In contrast, predictions for the opposite transitions through
these paths are on average 20% lower than the measured
values. In these cases the pull-up and pull-down networks
within the cells consist of single switching transistors (in-
verters), or a switching transistor arranged in series with an
Fig. 2. Testbench used for SPICE simulations
2500
Fig. 3. A plot of measured path delay variability ( path ) against predicted
path
path delay variability (Equation 5) for test path Figure 1(a). k has been initially
set to 1
inactive transistor (NAND and NOR gates). The addition of
transistors in series with the switching transistor is included
within nstack , but does not reduce the variability as much as
predicted. In other words, the approximation made within (1)
is not very accurate and can be improved by a modification
in the calculation of nstack . More specifically, in a generic
series transistors nstack can be derived as the value of nstack
that makes the estimated variability (4) equal to the exact
variability (which is evaluated with a simple simulation of
a path consisting of equal cascaded logic gates). This leads to
the following expression for the equivalent number of series
transistors in (6).
!2
path k
nstack = p (6)
path N strength
Experimental values of nstack indicated that a single transis-
tor within a stack could be counted as 1 within the metric, for
both PMOS and NMOS transistors, but the equivalent nstack
of two series transistors is equal to 1.2 (instead of 2). The
corrected values were used to recalculate the predicted vari-
ability of the paths with serially stacked transistors, providing
a much improved prediction. The results from this corrected
Fig. 4. A plot of measured path delay variability ( path ) against predicted
path
path delay variability (Equation 5) for the test paths in Figure 1. k is set
to the calculated value of 0.0567

Fig. 5. A plot of measured path delay variability ( path ) against predicted
path
path delay variability (Equation 5) for the test paths in Figures 1. The values
of nstack have been changed to 1.2 for cells with two transistors in series
stage to provide greater accuracy when required.
Fig. 6. A plot of measured path delay variability ( path ) against predicted
path
path delay variability (Equation 5) for the test path in Figures 1(b), where the
number of inputs to the NAND gates are varied
value of nstack are given in Figure 5.
The accuracy of the metric increases with a greater depth
of logic, and the differences between the predicted values and
measured values have a maximum error of 10% and an average
error of 3% for N > 2. The increase in accuracy with logic
depth may be due to the assumptions within the metric of the
Gaussian nature of the delays, as the randomspice models are
not based on Gaussian distributions of transistor parameters.
The accuracy improves because the delays through the path
become increasingly Gaussian in nature as the logic depth
increases, as predicted by the Central Limit Theorem.
The corrected value of nstack was verified by repeating
the analysis of test path Figure 1(b) with three, four and five
input NAND gates replacing the previously analysed two input
NAND gates. An increase of 0.2 was applied to nstack for
each additional input, and the predicted variability was found
to remain within 8%, again with an average error of 3%. Figure
6 provides a plot of the path delay variability predictions for
multiple input NAND gates, where nstack was set to 1.2,
1.4, 1.6 and 1.8 for the two, three, four and five input gates
respectively.
At this level of accuracy the proposed metric provides a
simple and efficient method of predicting the variability of
circuits synthesised from simple CMOS logic, especially if
the circuit is constructed from simple NAND or NOR based
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logic.
IV. C ONCLUSIONS AND F UTURE W ORK
A simple metric has been developed which accurately
predicts the variability of delays through circuits comprising
of simple CMOS logic. Equation 5 allows for the variability of
different paths to be compared without the need for extensive
Monte Carlo or SSTA analysis, allowing circuit variability to
be assessed at early stages within the design process with
minimal computational effort. The predictions are based on
Gaussian distributions of gate delays, and have been used to
accurately predict the variability of paths consisting of non-
Gaussian gate delays for logic depths greater than two cells.
The randomspice based modelling of random physical vari-
ations within transistors used within this work provides a
more accurate reference than results based on typical Monte
Carlo simulations of commercial design kits (where a few
device parameters are varied randomly according to a Gaussian
probability distribution).
The proposed metric therefore provides an accurate and
rapid statistical evaluation (always within 10% and usually
within 3%) of designs at the first stages of synthesis for circuits
consisting of simple CMOS gates. This permits to avoid
performing Monte Carlo simulations during design iterations,
thereby dramatically reducing the computational effort. Hence,
Monte Carlo simulations can be performed only at the signoff
Future work will investigate the limitations of the metric
when predicting the variability of circuits containing complex
cell structures, and will verify its effectiveness for other
technology nodes.
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