EEEB161:

DIGITAL LOGIC DESIGN LAB

LAB REPORT 4 & 5:

COMBITIONAL LOGIC CIRCUIT
(DESIGN, SIMULATION AND CIRCUIT CONSTRUCTION)

SECTION: 03
DATE OF LABORATORY SESSION: 5th OF JULY 2017
DATE OF REPORT SUBMISSION: 31st OF JULY 2017
NAME OF LECTURER: MADAM SHARIFAH AZWA BTE SHAAYA

GROUP MEMBERS:

1. ZAIRIL ASHRIQ BIN MOHD ZAILANI EP0101216

2. AMMAR BIN IZAM EP0101232
TABLE OF CONTENTS

Introduction

Equipment

Procedure

Design/Implementation

Results

Discussions

Conclusion
Introduction
Equipment

1. IDL800 digital experimenter

2. 74 series ICs
3. Wire connector

Procedures

1. The experiment was done by identifying the problem as states in lab manual.
2. Based on the problem statement, a truth table consisting of input (X,Y,Z)
and the output signal (G,R,B) was produced.
3. A method named K-map was used to minimize the output to construct a
Boolean expression.
4. A rough sketch of the circuit was drawn indicating an early result.
5. The circuit was then simulated using schematic diagram in ModelSim Altera
and Quartus II
6. The result shown by the simulation was recorded and changes were made.
7. The Boolean expression was then altered due to a few errors in simulation.
8. The circuit was simulated again and the desired result produced in the timing
diagram has been recorded.
9. The expression was again proved by using VHDL in ModelSim Altera and
Quartus II.
10.The result obtained by the VHDL was compared with the result obtained
from schematic.
11.The desire results were obtained and recorded.
Design/Implementation

1. K-map:
G
xy z 0 1
00 1 1
01 1 0
11 0 0
10 0 0

Table 1: K-map for Green (G)

R
xy z 0 1
00 0 0
01 1 1
11 1 0
10 1 1

Table 2: K-map for Red (R)

B
xy z 0 1
00 0 0
01 0 0
11 1 1
10 0 1

Table 3: K-map for Blue (B)

2. Boolean expression
= +
= +

= + +
= +

= +
= ( + )

3. Truth table:
INPUT OUTPUT
X Y Z G R B
0 0 0 1 0 0
0 0 1 1 0 0
0 1 0 1 1 0
0 1 1 0 1 0
1 0 0 0 1 0
1 0 1 0 1 1
1 1 0 0 1 1
1 1 1 0 0 1

Table 4: Truth Table

4. Rough sketches of the circuit

Diagram 1: Rough sketching of the circuit

5. Schematic diagram of the circuit

Diagram 2: Schematic diagram of the circuit

6. VHDL code

Diagram 3: VHDL code

RESULTS
DISCUSSION

From this experiment, we designed a logic circuit to solve the problem given to us by
using two different methods which are using VHDL coding and schematic entry. Both methods
gave us the same output based the data presented earlier. Well, actually both methods have their
own pros and cons. For VHDL coding, it is easier for us to troubleshoot the problems and also it
is easier for us to do VHDL is our problem require us to have a lot of logic gates. But, practical
wise schematic entry is way better because once the schematic is done, we can use it as a
reference when we want to assemble the practical circuit. But, personally we think that schematic
entry is more user friendly than VHDL.

When constructing our logic circuit, we used multiple kind of chips to solve the problem
and to produce the desired output. So, we have three outputs which are Red (R), Green (G), and
Blue (B). To produce the output for G, we used AND and NOR gate. The outputs for AND were
z and y. The NOR gate then got its inputs from x and the output of AND gate. The output of
NOR then produced output G.

To produce output R, we used four gates, NOT gate, AND gate, XOR gate and an OR
gate. The inputs that went through XOR gate are x and y, while input z would go through NOT
gate. The output from the NOT gate then became the input for AND along with input y. Then the
output for R, would come from the outputs of XOR gate and an AND gate that went through OR
gate. In producing output B, only two gates were used, OR gate and an AND gate. The OR gate
took y and z as the inputs and the output of it became the inputs for AND gate along with x to
produce output B. We got to learn a lot of new things when conducting this experiment and it
also boosted our interest in digital logic.

CONCLUSION