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Student should come with thorough preparation for the experiment to be

conducted.
Student should take prior permission from the concerned faculty before
availing the leave.
Student should come with proper dress code and to be present on time
in the laboratory.
Student will not be permitted to attend the laboratory unless they bring
the practical record fully completed in all respects pertaining to the
experiment conducted in the previous class.
Student will not be permitted to attend the laboratory unless they bring
the observation book fully completed in all respects pertaining to the
experiment to be conducted in present class.
Experiment should be started conducting only after the staff-in-charge

has checked the circuit diagram.
All the calculations should be made in the observation book. Specimen

calculations for one set of readings have to be shown in the practical
record.
Wherever graphs to be drawn, A-4 size graphs only should be used and
the same should be firmly attached in the practical record.
Practical record and observation book should be neatly maintained.
Student should obtain the signature of the staff-in-charge in the

observation book after completing each experiment.
Theory related to each experiment should be written in the practical

record before procedure in your own words with appropriate references.

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Viva questions 60
Appendix

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D3 D2 D1 D0
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D3 D2 D1 D0
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Ton T 1 1
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;+ 79 0 79

C = 0.01 F
Ton 0.435 X 10 3
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0.693 X C 0.693 X 0.01 X 10 6
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UUUUU %!'K!' !*!U
U UUU U

Product Sample & Technical Tools & Support &
Folder Buy Documents Software Community
uA741
SLOS094E NOVEMBER 1970 REVISED JANUARY 2015
A741 General-Purpose Operational Amplifiers

1 Features 3 Description
1 Short-Circuit Protection The A741 device is a general-purpose operational

amplifier featuring offset-voltage null capability.
Offset-Voltage Null Capability
Large Common-Mode and Differential Voltage The high common-mode input voltage range and the
Ranges absence of latch-up make the amplifier ideal for
voltage-follower applications. The device is short-
No Frequency Compensation Required circuit protected and the internal frequency
No Latch-Up compensation ensures stability without external
components. A low value potentiometer may be
2 Applications connected between the offset null inputs to null out
the offset voltage as shown in Figure 11.
DVD Recorders and Players
Pro Audio Mixers The A741C device is characterized for operation
from 0C to 70C. The A741M device (obsolete) is
characterized for operation over the full military
temperature range of 55C to 125C.
Device Information(1)
PART NUMBER PACKAGE (PIN) BODY SIZE (NOM)
SOIC (8) 4.90 mm 3.91 mm
A741x PDIP (8) 9.81 mm 6.35 mm
SO (8) 6.20 mm 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
OFFSET N1
IN + +
OUT
IN
OFFSET N2
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
uA741
SLOS094E NOVEMBER 1970 REVISED JANUARY 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ......................................... 9
2 Applications ........................................................... 1 8.3 Feature Description................................................. 10
3 Description ............................................................. 1 8.4 Device Functional Modes........................................ 10
8.5 A741Y Chip Information........................................ 10
4 Simplified Schematic............................................. 1
5 Revision History..................................................... 2 9 Application and Implementation ........................ 11
9.1 Application Information............................................ 11
6 Pin Configurations and Functions ....................... 3
9.2 Typical Application .................................................. 11
7 Specifications......................................................... 4
10 Power Supply Recommendations ..................... 13
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Recommended Operating Conditions....................... 4 11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
7.3 Electrical Characteristics A741C, A741M ............. 5
7.4 Electrical Characteristics A741Y............................. 6 11.2 Layout Example .................................................... 13
7.5 Switching Characteristics A741C, A741M ............ 6 12 Device and Documentation Support ................. 15
7.6 Switching Characteristics A741Y ............................ 6 12.1 Trademarks ........................................................... 15
7.7 Typical Characteristics .............................................. 7 12.2 Electrostatic Discharge Caution............................ 15
12.3 Glossary ................................................................ 15
8 Detailed Description .............................................. 9
8.1 Overview ................................................................... 9 13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
5 Revision History
Changes from Revision D (February 2014) to Revision E Page
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. ..................................................................................................................... 1
Moved Typical Characteristics into Specifications section. ................................................................................................... 7
Changes from Revision C (January 2014) to Revision D Page
Fixed Typical Characteristics graphs to remove extra lines. ................................................................................................. 7
Changes from Revision B (September 2000) to Revision C Page
Updated document to new TI data sheet format - no specification changes. ........................................................................ 1

Deleted Ordering Information table. ....................................................................................................................................... 1
2 Submit Documentation Feedback Copyright 19702015, Texas Instruments Incorporated
Product Folder Links: uA741

uA741
www.ti.com SLOS094E NOVEMBER 1970 REVISED JANUARY 2015
6 Pin Configurations and Functions

A741M . . . J PACKAGE A741M . . . JG PACKAGE
(TOP VIEW) A741C, A741I . . . D, P, OR PW PACKAGE
(TOP VIEW)
NC 1 14 NC
NC 2 13 NC OFFSET N1 1 8 NC
OFFSET N1 3 12 NC IN 2 7 VCC+
IN 4 11 VCC + IN + 3 6 OUT
IN + 5 10 OUT VCC 4 5 OFFSET N2
VCC 6 9 OFFSET N2
NC 7 8 NC
A741M . . . U PACKAGE A741M . . . FK PACKAGE

(TOP VIEW) (TOP VIEW)
OFFSET N1
NC 1 10 NC
OFFSET N1 2 9 NC
IN 3 8 VCC +
NC
NC
NC
NC
IN + 4 7 OUT
VCC 5 6 OFFSET N2
3 2 1 20 19
NC 4 18 NC
IN 5 17 VCC +
NC 6 16 NC
IN + 7 15 OUT
NC 8 14 NC
9 10 11 12 13
VCC
NC
NC
OFFSET N2
NC
NC No internal connection
Pin Functions
PIN
NAME JG, D, P, or TYPE DESCRIPTION
J U FK
PW
IN+ 5 3 4 7 I Noninverting input
IN 4 2 3 5 I Inverting input
1, 2, 8,
1,3,4,6,8,9,11,13,1
NC 12, 13, 8 1, 9, 10 Do not connect
4,16,18,19,20
14
OFFSET
3 1 2 2 I External input offset voltage adjustment
N1
OFFSET
9 5 6 12 I External input offset voltage adjustment
N2
OUT 10 6 7 15 O Output
VCC+ 11 7 8 17 Positive supply
VCC 6 4 5 10 Negative supply
Copyright 19702015, Texas Instruments Incorporated Submit Documentation Feedback 3

uA741
7 Specifications
7.1 Absolute Maximum Ratings
over virtual junction temperature range (unless otherwise noted) (1)
A741C A741M
UNIT
MIN MAX MIN MAX
VCC Supply voltage (2) 18 18 22 22 C
VID Differential input voltage (3) 15 15 30 30 V
VI Input voltage, any input (2) (4) 15 15 15 15 V
Voltage between offset null (either OFFSET N1 or OFFSET N2) and VCC 15 15 0.5 0.5 V
Duration of output short circuit (5) Unlimited
Continuous total power dissipation See Table 1
TA Operating free-air temperature range 0 70 55 125 C
Case temperature for 60 seconds FK package N/A N/A 260 C
Lead temperature 1.6 mm (1/16 inch) from case for
J, JG, or U package N/A N/A 300 C
60 seconds
Lead temperature 1.6 mm (1/16 inch) from case for
D, P, or PS package 260 N/A N/A C
10 seconds
Tstg Storage temperature range 65 150 65 150 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC.
(3) Differential voltages are at IN+ with respect to IN .
(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
(5) The output may be shorted to ground or either power supply. For the A741M only, the unlimited duration of the short circuit applies at
(or below) 125C case temperature or 75C free-air temperature.
7.2 Recommended Operating Conditions

MIN MAX UNIT
VCC+ 5 15
Supply voltage V
VCC 5 15
A741C 0 70
TA Operating free-air temperature C
A741M 55 125
Table 1. Dissipation Ratings Table

TA 25C TA = 70C
DERATING DERATE TA = 85C TA = 125C
PACKAGE POWER POWER
FACTOR ABOVE TA POWER RATING POWER RATING
RATING RATING
D 500 mW 5.8 mW/C 64C 464 mW 377 mW N/A
FK 500 mW 11.0 mW/C 105C 500 mW 500 mW 275 mW
J 500 mW 11.0 mW/C 105C 500 mW 500 mW 275 mW
JG 500 mW 8.4 mW/C 90C 500 mW 500 mW 210 mW
P 500 mW N/A N/A 500 mW 500 mW N/A
PS 525 mW 4.2 mW/C 25C 336 mW N/A N/A
U 500 mW 5.4 mW/C 57C 432 mW 351 mW 135 mW

uA741
7.3 Electrical Characteristics !A741C, !A741M

at specified virtual junction temperature, VCC = 15 V (unless otherwise noted)
!A741C !A741M
PARAMETER TEST CONDITIONS TA (1) UNIT
MIN TYP MAX MIN TYP MAX
25C 1 6 1 5
VIO Input offset voltage VO = 0 mV
Full range 7.5 15 6
!VIO(adj) Offset voltage adjust range VO = 0 25C 15 20 200 mV
25C 20 200 500
IIO Input offset current VO = 0 nA
Full range 300 500
25C 80 500 80 500
IIB Input bias current VO = 0 nA
Full range 800 1500
25C 12 13 12 13
VICR Common-mode input voltage range V
Full range 12 12
RL = 10 k" 25C 12 14 12 14
RL # 10 k" Full range 12 12
VOM Maximum peak output voltage swing V
RL = 2 k" 25C 10 10 13
RL # 2k" Full range 10 10
Large-signal differential voltage RL # 2k" 25C 20 200 50 200

AVD V/mV
amplification VO = 10 V Full range 15 25
ri Input resistance 25C 0.3 2 0.3 2 M"
ro Output resistance VO = 0, See (2) 25C 75 75 "
Ci Input capacitance 25C 1.4 1.4 pF
25C 70 90 70 90
CMRR Common-mode rejection ratio VIC = VICRmin dB
Full range 70 70
25C 30 150 30 150
kSVS Supply voltage sensitivity (!VIO/!VCC) VCC = 9 V to 15 V V/V
Full range 150 150
IOS Short-circuit output current 25C 25 40 25 40 mA
25C 1.7 2.8 1.7 2.8
ICC Supply current VO = 0, No load mA
Full range 3.3 3.3
25C 50 85 50 85
PD Total power dissipation VO = 0, No load mW
Full range 100 100
(1) All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full
range for the A741C is 0C to 70C and the A741M is 55C to 125C.
(2) This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback.

uA741
7.4 Electrical Characteristics !A741Y

at specified virtual junction temperature, VCC = 15 V, TA = 25C (unless otherwise noted) (1)
!A741Y
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
VIO Input offset voltage VO = 0 1 5 mV
!VIO(adj) Offset voltage adjust range VO = 0 15 mV
IIO Input offset current VO = 0 20 200 nA
IIB Input bias current VO = 0 80 500 nA
VICR Common-mode input voltage range 12 13 V
RL = 10 k" 12 14
VOM Maximum peak output voltage swing V
RL = 2 k" 10 13
AVD Large-signal differential voltage amplification RL # 2k" 20 200 V/mV
ri Input resistance 0.3 2 M"
(1)
ro Output resistance VO = 0, See 75 "
Ci Input capacitance 1.4 pF
CMRR Common-mode rejection ratio VIC = VICRmin 70 90 dB
kSVS Supply voltage sensitivity (!VIO/!VCC) VCC = 9 V to 15 V 30 150 V/V
IOS Short-circuit output current 25 40 mA
ICC Supply current VO = 0, No load 1.7 2.8 mA
PD Total power dissipation VO = 0, No load 50 85 mW
(1) This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback.
7.5 Switching Characteristics !A741C, !A741M

over operating free-air temperature range, VCC = 15 V, TA = 25C (unless otherwise noted)
A741C A741M
MIN TYP MAX MIN TYP MAX
tr Rise time VI = 20 mV, RL = 2 k", 0.3 0.3 s
Overshoot factor CL = 100 pF, See Figure 1 5% 5%
VI = 10 V, RL = 2 k",
SR Slew rate at unity gain 0.5 0.5 V/s
CL = 100 pF, See Figure 1
7.6 Switching Characteristics !A741Y

over operating free-air temperature range, VCC = 15 V, TA = 25C (unless otherwise noted)
A741Y
MIN TYP MAX
tr Rise time VI = 20 mV, RL = 2 k", 0.3 s
Overshoot factor CL = 100 pF, See Figure 1 5%
VI = 10 V, RL = 2 k",
SR Slew rate at unity gain 0.5 V/s
CL = 100 pF, See Figure 1

uA741
7.7 Typical Characteristics

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
VI
OUT
IN
+
0V
INPUT VOLTAGE
WAVEFDORM
CL = 100 pF RL = 2 k
TEST CIRCUIT
Figure 1. Rise Time, Overshoot, and Slew Rate
100 400
VCC+ = 15 V
90 VCC+ = 15 V
VCC = 15 V
350 VCC = 15 V
I IO Input Offset Current nA
I IB Input Bias Current nA

80
300
70
60 250
50 200
40
150
30
100
20
10 50
0 0
60 40 20 0 20 40 60 80 100 120 140 60 40 20 0 20 40 60 80 100 120 140
TA Free-Air Temperature C TA Free-Air Temperature C
Figure 2. Input Offset Current vs Free-Air Temperature Figure 3. Input Bias Current vs Free-Air Temperature
14 20
VCC+ = 15 V VCC+ = 15 V
VOM Maximum Peak Output Voltage V
VOM Maximum Peak Output Voltage V
13 VCC = 15 V 18 VCC = 15 V
TA = 25C RL = 10 k
12 16 TA = 25C
11 14
10 12
9 10
8 8
7 6
6 4
5 2
4 0
0.1 0.2 0.4 0.7 1 2 4 7 10 100 1k 10k 100k 1M
RL Load Resistance k
f Frequency Hz
Figure 4. Maximum Output Voltage vs Load Resistance Figure 5. Maximum Peak Output Voltage vs Frequency

uA741
Typical Characteristics (continued)

Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various
devices.
400 110
VO = 10 V
RL = 2 k 100 VCC+ = 15 V
TA = 25C VCC = 15 V
AVD Open-Loop Signal Differential
AVD Open-Loop Signal Differential

200 90 VO = 10 V
Voltage Amplification V/mV
80 RL = 2 k
Voltage Amplification dB
TA = 25C
70
100
60
50
40 40
30
20
20
10
0
10 10
0 2 4 6 8 10 12 14 16 18 20 1 10 100 1k 10k 100k 1M 10M
VCC Supply Voltage V f Frequency Hz
Figure 6. Open-Loop Signal Differential Figure 7. Open-Loop Large-Signal Differential
Voltage Amplification Voltage Amplification
vs vs
Supply Voltage Frequency
100 28
CMRR Common-Mode Rejection Ratio dB
VCC+ = 15 V
90 VCC = 15 V 24
BS = 10 k
80
TA = 25C
20
VO Output Voltage mV
70
90%
16
60
50 12
40 8
30 VCC+ = 15 V
4
VCC = 15 V
20 10% RL = 2 k
0
10 CL = 100 pF
tr TA = 25C
0 4
1 100 10k 1M 100M 0 0.5 1 1.5 2 2.5
f Frequency Hz t Time - s
Figure 8. Common-Mode Rejection Ratio vs Frequency Figure 9. Output Voltage vs Elapsed Time
8
VCC+ = 15 V
6 VCC = 15 V
RL = 2 k
CL = 100 pF
Input and Output Voltage V
4
TA = 25C
VO
2
0
VI
2
8
0 10 20 30 40 50 60 70 80 90
t Time ms
Figure 10. Voltage-Follower Large-Signal Pulse Response

uA741
8 Detailed Description
8.1 Overview
The A741 device is a general-purpose operational amplifier featuring offset-voltage null capability.
The high common-mode input voltage range and the absence of latch-up make the amplifier ideal for voltage-
follower applications. The device is short-circuit protected and the internal frequency compensation ensures
stability without external components. A low value potentiometer may be connected between the offset null
inputs to null out the offset voltage as shown in Figure 11.
The A741C device is characterized for operation from 0C to 70C. The A741M device (obsolete) is
characterized for operation over the full military temperature range of 55C to 125C.
8.2 Functional Block Diagram
VCC+
IN
OUT
IN+
OFFSET N1
OFFSET N2
VCC
Component Count
Transistors 22
Resistors 11
Diode 1
Capacitor 1

uA741
8.3 Feature Description

8.3.1 Offset-Voltage Null Capability
The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the
differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-
gain betas ($), collector or emitter resistors, etc. The input offset pins allow the designer to adjust for these
mismatches by external circuitry. See the Application and Implementation section for more details on design
techniques.
8.3.2 Slew Rate

The slew rate is the rate at which an operational amplifier can change its output when there is a change on the
input. The A741 has a 0.5-V/ s slew rate. Parameters that vary significantly with operating voltages or
temperature are shown in the Typical Characteristics graphs.
8.4 Device Functional Modes

The A741 is powered on when the supply is connected. It can be operated as a single supply operational
amplifier or dual supply amplifier depending on the application.
8.5 A741Y Chip Information

This chip, when properly assembled, displays characteristics similar to the A741C. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS

VCC+
(7)
(7) (6) IN +
(3)
+ (6)
(2) OUT
IN
OFFSET N1 (1) (4)
(8)
OFFSET N2 (5) VCC
45
(5)
(1) CHIP THICKNESS: 15 TYPICAL

(4)
BONDING PADS: 4 4 MINIMUM
TJmax = 150C.
(2) (3) TOLERANCES ARE 10%.
ALL DIMENSIONS ARE IN MILS.
36

uA741
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the
differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current-
gain betas ( ), collector or emitter resistors, etc. The input offset pins allow the designer to adjust for these
mismatches by external circuitry. These input mismatches can be adjusted by putting resistors or a potentiometer
between the inputs as shown in Figure 13. A potentiometer can be used to fine tune the circuit during testing or
for applications which require precision offset control. More information about designing using the input-offset
pins, see the application note Nulling Input Offset Voltage of Operational Amplifiers, SLOA045.
IN + +
OUT
IN OFFSET N2
OFFSET N1
10 k
To VCC
Figure 11. Input Offset Voltage Null Circuit
9.2 Typical Application

The voltage follower configuration of the operational amplifier is used for applications where a weak signal is
used to drive a relatively high current load. This circuit is also called a buffer amplifier or unity gain amplifier. The
inputs of an operational amplifier have a very high resistance which puts a negligible current load on the voltage
source. The output resistance of the operational amplifier is almost negligible, so it can provide as much current
as necessary to the output load.
10 k
12 V
VOUT
+
VIN
Figure 12. Voltage Follower Schematic
9.2.1 Design Requirements

Output range of 2 V to 11.5 V
Input range of 2 V to 11.5 V

uA741
Typical Application (continued)

Resistive feedback to negative input
9.2.2 Detailed Design Procedure
9.2.2.1 Output Voltage Swing

The output voltage of an operational amplifier is limited by its internal circuitry to some level below the supply
rails. For this amplifier, the output voltage swing is within 12 V, which accommodates the input and output
voltage requirements.
9.2.2.2 Supply and Input Voltage

For correct operation of the amplifier, neither input must be higher than the recommended positive supply rail
voltage or lower than the recommended negative supply rail voltage. The chosen amplifier must be able to
operate at the supply voltage that accommodates the inputs. Because the input for this application goes up to
11.5 V, the supply voltage must be 12 V. Using a negative voltage on the lower rail rather than ground allows the
amplifier to maintain linearity for inputs below 2 V.
9.2.3 Application Curves for Output Characteristics
12 0.045
0.040
10
0.035
0.030
8
0.025
VOUT (V)
IIO (mA)
6 0.020
0.015
4
0.010
0.005
2
0.000
0 0.005
0 2 4 6 8 10 12 0 2 4 6 8 10 12
VIN (V) C001 VIN (V) C002
Figure 13. Output Voltage vs Input Voltage Figure 14. Current Drawn Input of Voltage Follower (IIO)
vs Input Voltage
0.45
0.40
0.35
0.30
ICC (mA)
0.25
0.20
0.15
0.10
0.05
0.00
0 2 4 6 8 10 12
VIN (V) C003
Figure 15. Current Drawn from Supply (ICC)

vs Input Voltage

uA741
10 Power Supply Recommendations

The !A741 is specified for operation from 5 to 15 V; many specifications apply from 0C to 70C. The Typical
Characteristics section presents parameters that can exhibit significant variance with regard to operating voltage
or temperature.
CAUTION
Supply voltages larger than 18 V can permanently damage the device (see the
Absolute Maximum Ratings).
Place 0.1-!F bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
Guidelines.
11 Layout
11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational
amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power
sources local to the analog circuitry.
Connect low-ESR, 0.1-!F ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to
Circuit Board Layout Techniques, SLOA089.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as
opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Layout Example.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Example

RIN
VIN +
VOUT
RG
RF
Figure 16. Operational Amplifier Schematic for Noninverting Configuration

uA741
Layout Example (continued)
Place components close to

device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines RF
as possible
NC NC VS+
Use low-ESR, ceramic
RG bypass capacitor
GND IN1 VCC+
VIN IN1+ OUT

RIN
VCC NC GND
Only needed for
dual-supply
operation
GND VS-
(or GND for single supply) VOUT Ground (GND) plane on another layer
Figure 17. Operational Amplifier Board Layout for Noninverting Configuration

uA741
12 Device and Documentation Support

12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
UA741CD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 UA741C

& no Sb/Br)
UA741CDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 UA741C
& no Sb/Br)
UA741CDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 UA741C
& no Sb/Br)
UA741CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 UA741C
& no Sb/Br)
UA741CJG OBSOLETE CDIP JG 8 TBD Call TI Call TI 0 to 70
UA741CJG4 OBSOLETE CDIP JG 8 TBD Call TI Call TI 0 to 70
UA741CP ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 UA741CP
(RoHS)
UA741CPE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 UA741CP
(RoHS)
UA741CPSR ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 U741
& no Sb/Br)
UA741CPSRE4 ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 U741
& no Sb/Br)
UA741MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125
UA741MJ OBSOLETE CDIP J 14 TBD Call TI Call TI -55 to 125
UA741MJB OBSOLETE CDIP J 14 TBD Call TI Call TI -55 to 125
UA741MJG OBSOLETE CDIP JG 8 TBD Call TI Call TI -55 to 125
UA741MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI -55 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Feb-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UA741CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UA741CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
Pack Materials-Page 1
www.ti.com 17-Feb-2014

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UA741CDR SOIC D 8 2500 340.5 338.1 20.6
UA741CPSR SO PS 8 2000 367.0 367.0 38.0
MECHANICAL DATA
MCER001A JANUARY 1995 REVISED JANUARY 1997
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8 5
0.280 (7,11)
0.245 (6,22)
1 4
0.065 (1,65)
0.045 (1,14)
0.063 (1,60) 0.310 (7,87)

0.020 (0,51) MIN
0.015 (0,38) 0.290 (7,37)
0.200 (5,08) MAX

Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
015
0.015 (0,38)
0.100 (2,54) 0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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Product Sample & Technical Tools & Support &
Folder Buy Documents Software Community
LM555
SNAS548D FEBRUARY 2000 REVISED JANUARY 2015
LM555 Timer
1 Features 3 Description
1 Direct Replacement for SE555/NE555 The LM555 is a highly stable device for generating
accurate time delays or oscillation. Additional
Timing from Microseconds through Hours terminals are provided for triggering or resetting if
Operates in Both Astable and Monostable Modes desired. In the time delay mode of operation, the time
Adjustable Duty Cycle is precisely controlled by one external resistor and
Output Can Source or Sink 200 mA capacitor. For a stable operation as an oscillator, the
free running frequency and duty cycle are accurately
Output and Supply TTL Compatible controlled with two external resistors and one
Temperature Stability Better than 0.005% per C capacitor. The circuit may be triggered and reset on
Normally On and Normally Off Output falling waveforms, and the output circuit can source
or sink up to 200 mA or drive TTL circuits.
Available in 8-pin VSSOP Package
Device Information(1)
2 Applications PART NUMBER PACKAGE BODY SIZE (NOM)
Precision Timing SOIC (8) 4.90 mm 3.91 mm
Pulse Generation LM555 PDIP (8) 9.81 mm 6.35 mm
Sequential Timing VSSOP (8) 3.00 mm 3.00 mm
Time Delay Generation (1) For all available packages, see the orderable addendum at
the end of the datasheet.
Pulse Width Modulation
Pulse Position Modulation
Linear Ramp Generator
Schematic Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM555
SNAS548D FEBRUARY 2000 REVISED JANUARY 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................... 8
2 Applications ........................................................... 1 7.4 Device Functional Modes.......................................... 9
3 Description ............................................................. 1 8 Application and Implementation ........................ 12
4 Revision History..................................................... 2 8.1 Application Information............................................ 12
8.2 Typical Application ................................................. 12
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations ...................... 15
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 15
6.2 ESD Ratings.............................................................. 4 10.1 Layout Guidelines ................................................. 15
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 15
6.4 Thermal Information ................................................. 4 11 Device and Documentation Support ................. 16
6.5 Electrical Characteristics .......................................... 5 11.1 Trademarks ........................................................... 16
6.6 Typical Characteristics .............................................. 6 11.2 Electrostatic Discharge Caution............................ 16
7 Detailed Description .............................................. 8 11.3 Glossary ................................................................ 16
7.1 Overview ................................................................... 8 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ......................................... 8 Information ........................................................... 16
4 Revision History
Changes from Revision C (March 2013) to Revision D Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision B (March 2013) to Revision C Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 13
Product Folder Links: LM555

LM555
www.ti.com SNAS548D FEBRUARY 2000 REVISED JANUARY 2015
5 Pin Configuration and Functions
D, P, and DGK Packages

8-Pin PDIP, SOIC, and VSSOP
Top View
1 8
GND +VCC
2 COMPAR- 7
TRIGGER R DISCHARGE
ATOR
FLIP FLOP R
3 OUTPUT COMPAR-
6
OUTPUT R THRESHOLD
STAGE ATOR
4 VREF (INT) 5 CONTROL

RESET
VOLTAGE
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
Control Controls the threshold and trigger levels. It determines the pulse width of the output
5 Voltage I waveform. An external voltage applied to this pin can also be used to modulate the output
waveform
Discharge Open collector output which discharges a capacitor between intervals (in phase with output).
7 I
It toggles the output from high to low when voltage reaches 2/3 of the supply voltage
1 GND O Ground reference voltage
3 Output O Output driven waveform
Reset Negative pulse applied to this pin to disable or reset the timer. When not used for reset
4 I
purposes, it should be connected to VCC to avoid false triggering
Threshold Compares the voltage applied to the terminal with a reference voltage of 2/3 Vcc. The
6 I
amplitude of voltage applied to this terminal is responsible for the set state of the flip-flop
Trigger Responsible for transition of the flip-flop from set to reset. The output of the timer depends
2 I
on the amplitude of the external trigger pulse applied to this pin
8 V+ I Supply voltage with respect to GND

LM555
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT
LM555CM, LM555CN (4) 1180 mW
Power Dissipation (3)
LM555CMM 613 mW
PDIP Package Soldering (10 Seconds) 260 C
Soldering
Small Outline Packages (SOIC and Vapor Phase (60 Seconds) 215 C
Information
VSSOP) Infrared (15 Seconds) 220 C
Storage temperature, Tstg 65 150 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) For operating at elevated temperatures the device must be derated above 25C based on a 150C maximum junction temperature and a
thermal resistance of 106C/W (PDIP), 170C/W (S0IC-8), and 204C/W (VSSOP) junction to ambient.
(4) Refer to RETS555X drawing of military LM555H and LM555J versions for specifications.
6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 500 (2) V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) The ESD information listed is for the SOIC package.
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply Voltage 18 V
Temperature, TA 0 70 C
Operating junction temperature, TJ 70 C
6.4 Thermal Information

LM555
THERMAL METRIC (1) PDIP SOIC VSSOP UNIT
8 PINS
R JA Junction-to-ambient thermal resistance 106 170 204 C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

LM555
6.5 Electrical Characteristics

(TA = 25C, VCC = 5 V to 15 V, unless otherwise specified) (1) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply Voltage 4.5 16 V
Supply Current VCC = 5 V, RL = ! 3 6
VCC = 15 V, RL = ! 10 15 mA
(Low State) (3)
Timing Error, Monostable
Initial Accuracy 1%
Drift with Temperature RA = 1 k to 100 k", 50 ppm/C
(4)
C = 0.1 #F,
Accuracy over Temperature 1.5 %
Drift with Supply 0.1 % V
Timing Error, Astable
Initial Accuracy 2.25
Drift with Temperature RA, RB =1 k to 100 k", 150 ppm/C
(4)
C = 0.1 #F,
Accuracy over Temperature 3.0%
Drift with Supply 0.30 % /V
Threshold Voltage 0.667 x VCC
Trigger Voltage VCC = 15 V 5 V
VCC = 5 V 1.67 V
Trigger Current 0.5 0.9 #A
Reset Voltage 0.4 0.5 1 V
Reset Current 0.1 0.4 mA
(5)
Threshold Current 0.1 0.25 #A
Control Voltage Level VCC = 15 V 9 10 11
V
VCC = 5 V 2.6 3.33 4
Pin 7 Leakage Output High 1 100 nA
(6)
Pin 7 Sat
Output Low VCC = 15 V, I7 = 15 mA 180 mV
Output Low VCC = 4.5 V, I7 = 4.5 mA 80 200 mV
Output Voltage Drop (Low) VCC = 15 V
ISINK = 10 mA 0.1 0.25 V
ISINK = 50 mA 0.4 0.75 V
ISINK = 100 mA 2 2.5 V
ISINK = 200 mA 2.5 V
VCC = 5 V
ISINK = 8 mA V
ISINK = 5 mA 0.25 0.35 V
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate
conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC
electrical specifications under particular test conditions which ensures specific performance limits. This assumes that the device is within
the Recommended Operating Conditions. Specifications are not ensured for parameters where no limit is given, however, the typical
value is a good indication of device performance.
(3) Supply current when output high typically 1 mA less at VCC = 5 V.
(4) Tested at VCC = 5 V and VCC = 15 V.
(5) This will determine the maximum value of RA + RB for 15 V operation. The maximum total (RA + RB) is 20 M".
(6) No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded.

LM555
Electrical Characteristics (continued)

(TA = 25C, VCC = 5 V to 15 V, unless otherwise specified)(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output Voltage Drop (High) ISOURCE = 200 mA, VCC = 15 V 12.5 V
ISOURCE = 100 mA, VCC = 15 V 12.75 13.3 V
VCC = 5 V 2.75 3.3 V
Rise Time of Output 100 ns
Fall Time of Output 100 ns
6.6 Typical Characteristics
Figure 1. Minimum Pulse Width Required For Triggering Figure 2. Supply Current vs. Supply Voltage
Figure 3. High Output Voltage vs. Output Source Current Figure 4. Low Output Voltage vs. Output Sink Current

LM555
Typical Characteristics (continued)
Figure 5. Low Output Voltage vs. Output Sink Current Figure 6. Low Output Voltage vs. Output Sink Current
Figure 7. Output Propagation Delay vs. Voltage Level of Figure 8. Output Propagation Delay vs. Voltage Level of
Trigger Pulse Trigger Pulse
Figure 9. Discharge Transistor (Pin 7) Voltage vs. Sink Figure 10. Discharge Transistor (Pin 7) Voltage vs. Sink
Current Current

LM555
7 Detailed Description
7.1 Overview
The LM555 is a highly stable device for generating accurate time delays or oscillation. Additional terminals are
provided for triggering or resetting if desired. In the time delay mode of operation, the time is precisely controlled
by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and duty
cycle are accurately controlled with two external resistors and one capacitor. The circuit may be triggered and
reset on falling waveforms, and the output circuit can source or sink up to 200mA or driver TTL circuits. The
LM555 are available in 8-pin PDIP, SOIC, and VSSOP packages and is a direct replacement for SE555/NE555.
7.2 Functional Block Diagram
CONTROL
THRESHOLD VOLTAGE +Vcc
COMPARATOR
RESET
Vref (int)
TRIGGER
FLIP FLOP COMPARATOR
DISCHARGE
OUTPUT
OUTPUT
STAGE
7.3 Feature Description

7.3.1 Direct Replacement for SE555/NE555
The LM555 timer is a direct replacement for SE555 and NE555. It is pin-to-pin compatible so that no schematic
or layout changes are necessary. The LM555 come in an 8-pin PDIP, SOIC, and VSSOP package.
7.3.2 Timing From Microseconds Through Hours

The LM555 has the ability to have timing parameters from the microseconds range to hours. The time delay of
the system can be determined by the time constant of the R and C value used for either the monostable or
astable configuration. A nomograph is available for easy determination of R and C values for various time delays.
7.3.3 Operates in Both Astable and Monostable Mode

The LM555 can operate in both astable and monostable mode depending on the application requirements.
Monostable mode: The LM555 timer acts as a one-shot pulse generator. The pulse beings when the LM555
timer receives a signal at the trigger input that falls below a 1/3 of the voltage supply. The width of the output
pulse is determined by the time constant of an RC network. The output pulse ends when the voltage on the

LM555
Feature Description (continued)

capacitor equals 2/3 of the supply voltage. The output pulse width can be extended or shortened depending
on the application by adjusting the R and C values.
Astable (free-running) mode: The LM555 timer can operate as an oscillator and puts out a continuous stream
of rectangular pulses having a specified frequency. The frequency of the pulse stream depends on the values
of RA, RB, and C.
7.4 Device Functional Modes

7.4.1 Monostable Operation
In this mode of operation, the timer functions as a one-shot (Figure 11). The external capacitor is initially held
discharged by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 VCC to
pin 2, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high.
Figure 11. Monostable
The voltage across the capacitor then increases exponentially for a period of t = 1.1 RA C, at the end of which
time the voltage equals 2/3 VCC. The comparator then resets the flip-flop which in turn discharges the capacitor
and drives the output to its low state. Figure 12 shows the waveforms generated in this mode of operation. Since
the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing
interval is independent of supply.
VCC = 5 V Top Trace: Input 5V/Div.

TIME = 0.1 ms/DIV. Middle Trace: Output 5V/Div.
RA = 9.1 k" Bottom Trace: Capacitor Voltage 2V/Div.
C = 0.01 #F
Figure 12. Monostable Waveforms
During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit
so long as the trigger input is returned high at least 10 #s before the end of the timing interval. However the
circuit can be reset during this time by the application of a negative pulse to the reset terminal (pin 4). The output
will then remain in the low state until a trigger pulse is again applied.
When the reset function is not in use, TI recommends connecting the Reset pin to VCC to avoid any possibility of
false triggering.

LM555
Device Functional Modes (continued)

Figure 13 is a nomograph for easy determination of R, C values for various time delays.
Figure 13. Time Delay
7.4.2 Astable Operation

If the circuit is connected as shown in Figure 14 (pins 2 and 6 connected) it will trigger itself and free run as a
multivibrator. The external capacitor charges through RA + RB and discharges through RB. Thus the duty cycle
may be precisely set by the ratio of these two resistors.
Figure 14. Astable
In this mode of operation, the capacitor charges and discharges between 1/3 VCC and 2/3 VCC. As in the
triggered mode, the charge and discharge times, and therefore the frequency are independent of the supply
voltage.
Figure 15 shows the waveforms generated in this mode of operation.

LM555
Device Functional Modes (continued)
VCC = 5 V Top Trace: Output 5V/Div.

TIME = 20#s/DIV. Bottom Trace: Capacitor Voltage 1V/Div.
RA = 3.9 k"
RB = 3 k"
C = 0.01 #F
Figure 15. Astable Waveforms
The charge time (output high) is given by:

t1 = 0.693 (RA + RB) C (1)
And the discharge time (output low) by:
t2 = 0.693 (RB) C (2)
Thus the total period is:
T = t1 + t2 = 0.693 (RA +2RB) C (3)
The frequency of oscillation is:
(4)
Figure 16 may be used for quick determination of these RC values.
The duty cycle is:
(5)
Figure 16. Free Running Frequency

LM555
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information

The LM555 timer can be used a various configurations, but the most commonly used configuration is in
monostable mode. A typical application for the LM555 timer in monostable mode is to turn on an LED for a
specific time duration. A pushbutton is used as the trigger to output a high pulse when trigger pin is pulsed low.
This simple application can be modified to fit any application requirement.
8.2 Typical Application

Figure 17 shows the schematic of the LM555 that flashes an LED in monostable mode.
Figure 17. Schematic of Monostable Mode to Flash an LED
8.2.1 Design Requirements

The main design requirement for this application requires calculating the duration of time for which the output
stays high. The duration of time is dependent on the R and C values (as shown in Figure 17) and can be
calculated by:
t = 1.1 R C seconds (6)
8.2.2 Detailed Design Procedure

To allow the LED to flash on for a noticeable amount of time, a 5 second time delay was chosen for this
application. By using Equation 6, RC equals 4.545. If R is selected as 100 k", C = 45.4 F. The values of R =
100 k" and C = 47 F was selected based on standard values of resistors and capacitors. A momentary push
button switch connected to ground is connected to the trigger input with a 10-K current limiting resistor pullup to
the supply voltage. When the push button is pressed, the trigger pin goes to GND. An LED is connected to the
output pin with a current limiting resistor in series from the output of the LM555 to GND. The reset pin is not used
and was connected to the supply voltage.
8.2.2.1 Frequency Divider

The monostable circuit of Figure 11 can be used as a frequency divider by adjusting the length of the timing
cycle. Figure 18 shows the waveforms generated in a divide by three circuit.

LM555
VCC = 5 V Top Trace: Input 4 V/Div.

TIME = 20 #s/DIV. Middle Trace: Output 2V/Div.
RA = 9.1 k" Bottom Trace: Capa citor 2V/Div.
C = 0.01 #F
Figure 18. Frequency Divider
8.2.2.2 Additional Information

Lower comparator storage time can be as long as 10 #s when pin 2 is driven fully to ground for triggering. This
limits the monostable pulse width to 10 #s minimum.
Delay time reset to output is 0.47 #s typical. Minimum reset pulse width must be 0.3 #s, typical.
Pin 7 current switches within 30 ns of the output (pin 3) voltage.
8.2.3 Application Curves

The data shown below was collected with the circuit used in the typical applications section. The LM555 was
configured in the monostable mode with a time delay of 5.17 s. The waveforms correspond to:
Top Waveform (Yellow) Capacitor voltage
Middle Waveform (Green) Trigger
Bottom Waveform (Purple) Output
As the trigger pin pulses low, the capacitor voltage starts charging and the output goes high. The output goes low
as soon as the capacitor voltage reaches 2/3 of the supply voltage, which is the time delay set by the R and C
value. For this example, the time delay is 5.17 s.

LM555
Figure 19. Trigger, Capacitor Voltage, and Output Waveforms in Monostable Mode

LM555
9 Power Supply Recommendations

The LM555 requires a voltage supply within 4.5 V to 16 V. Adequate power supply bypassing is necessary to
protect associated circuitry. The minimum recommended capacitor value is 0.1 #F in parallel with a 1-#F
electrolytic capacitor. Place the bypass capacitors as close as possible to the LM555 and minimize the trace
length.
10 Layout
10.1 Layout Guidelines

Standard PCB rules apply to routing the LM555. The 0.1-F capacitor in parallel with a 1-F electrolytic capacitor
should be as close as possible to the LM555. The capacitor used for the time delay should also be placed as
close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity and
signal integrity.
Figure 20 is the basic layout for various applications.
C1 based on time delay calculations
C2 0.01-F bypass capacitor for control voltage pin
C3 0.1-F bypass ceramic capacitor
C4 1-F electrolytic bypass capacitor
R1 based on time delay calculations
U1 LMC555
10.2 Layout Example
Figure 20. Layout Example

LM555
11 Device and Documentation Support

11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
11.3 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 27-Jul-2016
(1) Drawing Qty (2) (6) (3) (4/5)
LM555-MWC ACTIVE WAFERSALE YS 0 1 Green (RoHS Call TI Level-1-NA-UNLIM -40 to 85

& no Sb/Br)
LM555CM NRND SOIC D 8 95 TBD Call TI Call TI 0 to 70 LM
555CM
LM555CM/NOPB ACTIVE SOIC D 8 95 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 LM
& no Sb/Br) 555CM
LM555CMM NRND VSSOP DGK 8 1000 TBD Call TI Call TI 0 to 70 Z55
LM555CMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 Z55
& no Sb/Br)
LM555CMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 Z55
& no Sb/Br)
LM555CMX NRND SOIC D 8 2500 TBD Call TI Call TI 0 to 70 LM
555CM
LM555CMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS CU SN Level-1-260C-UNLIM 0 to 70 LM
& no Sb/Br) 555CM
LM555CN/NOPB ACTIVE PDIP P 8 40 Green (RoHS CU SN Level-1-NA-UNLIM 0 to 70 LM
& no Sb/Br) 555CN
MC1455P1 OBSOLETE PDIP P 8 TBD Call TI Call TI 0 to 70 LM
555CN
NE555V OBSOLETE PDIP P 8 TBD Call TI Call TI 0 to 70 LM
555CN
(1)
(2)
Addendum-Page 1
www.ti.com 27-Jul-2016
(3)
(4)
(5)
(6)
Addendum-Page 2
www.ti.com 21-Oct-2014

(mm) W1 (mm)
LM555CMM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM555CMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM555CMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM555CMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM555CMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
www.ti.com 21-Oct-2014

LM555CMM VSSOP DGK 8 1000 210.0 185.0 35.0
LM555CMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LM555CMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LM555CMX SOIC D 8 2500 367.0 367.0 35.0
LM555CMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
IMPORTANT NOTICE
performed.
OBSOLETE
LM565, LM565C
www.ti.com SNOSBU1B MAY 1999 REVISED APRIL 2013
LM565/LM565C Phase Locked Loop

Check for Samples: LM565, LM565C
1 FEATURES DESCRIPTION
2 200 ppm/C Frequency Stability of the VCO The LM565 and LM565C are general purpose phase
locked loops containing a stable, highly linear voltage
Power Supply Range of 5 to 12 Volts with controlled oscillator for low distortion FM
100 ppm/% Typical demodulation, and a double balanced phase detector
0.2% Linearity of Demodulated Output with good carrier suppression. The VCO frequency is
Linear Triangle Wave with in Phase Zero set with an external resistor and capacitor, and a
Crossings Available tuning range of 10:1 can be obtained with the same
capacitor. The characteristics of the closed loop
TTL and DTL Compatible Phase Detector Input systembandwidth, response speed, capture and
and Square Wave Output pull in rangemay be adjusted over a wide range
Adjustable Hold in Range from 1% to > 60% with an external resistor and capacitor. The loop may
be broken between the VCO and the phase detector
APPLICATIONS for insertion of a digital frequency divider to obtain
frequency multiplication.
Data and Tape Zynchronization
The LM565H is specified for operation over the
Modems
55C to +125C military temperature range. The
FSK Demodulation LM565CN is specified for operation over the 0C to
FM Demodulation +70C temperature range.
Frequency Synthesizer
Tone Decoding
Frequency Multiplication and Division
SCA Demodulators
Telemetry Receivers
Signal Regeneration
Coherent Demodulators
Connection Diagram
TO-100 Package
See Package Number LME
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright 19992013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
OBSOLETE
LM565, LM565C
SNOSBU1B MAY 1999 REVISED APRIL 2013 www.ti.com
Dual-in-Line Package
PDIP
See Package Number NFF
Product Folder Links: LM565 LM565C

OBSOLETE
LM565, LM565C
Absolute Maximum Ratings (1) (2)

Supply Voltage 12V
Power Dissipation (3) 1400 mW
Differential Input Voltage 1V
Operating Temperature Range LM565H 55C to +125C
LM565CN 0C to +70C
Storage Temperature Range 65C to +150C
Lead Temperature (Soldering, 10 sec.) 260C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The maximum junction temperature of the LM565 and LM565C is +150C. For operation at elevated temperatures, devices in the TO-5
package must be derated based on a thermal resistance of +150C/W junction to ambient or +45C/W junction to case. Thermal
resistance of the dual-in-line package is +85C/W.
Electrical Characteristics
AC Test Circuit, TA = 25C, VCC = 6V
LM565 LM565C
Parameter Conditions Units
Min Typ Max Min Typ Max
Power Supply Current 8.0 12.5 8.0 12.5 mA
Input Impedance (Pins 2, 3) 4V < V2, V3 < 0V 7 10 5 k!
VCO Maximum Operating Frequency Co = 2.7 pF 300 500 250 500 kHz
VCO Free-Running Frequency Co = 1.5 nF
Ro = 20 k! 10 0 +10 30 0 +30 %
fo = 10 kHz
Operating Frequency
100 200 ppm/C
Temperature Coefficient
Frequency Drift with
0.1 1.0 0.2 1.5 %/V
Supply Voltage
Triangle Wave Output Voltage 2 2.4 3 2 2.4 3 Vp-p
Triangle Wave Output Linearity 0.2 0.5 %
Square Wave Output Level 4.7 5.4 4.7 5.4 Vp-p
Output Impedance (Pin 4) 5 5 k!
Square Wave Duty Cycle 45 50 55 40 50 60 %
Square Wave Rise Time 20 20 ns
Square Wave Fall Time 50 50 ns
Output Current Sink (Pin 4) 0.6 1 0.6 1 mA
VCO Sensitivity fo = 10 kHz 6600 6600 Hz/V
Demodulated Output Voltage (Pin 7) 10% Frequency Deviation 250 300 400 200 300 450 mVp-p
Total Harmonic Distortion 10% Frequency Deviation 0.2 0.75 0.2 1.5 %
Output Impedance (Pin 7) 3.5 3.5 k!
DC Level (Pin 7) 4.25 4.5 4.75 4.0 4.5 5.0 V
Output Offset Voltage
30 100 50 200 mV
|V7 V6|
Temperature Drift of |V7 V6| 500 500 "V/C
AM Rejection 30 40 40 dB
Phase Detector Sensitivity KD 0.68 0.68 V/radian

OBSOLETE
LM565, LM565C
Typical Performance Characteristics

Power Supply Current as a Lock Range as a Function
Function of Supply Voltage of Input Voltage
Figure 1. Figure 2.
Oscillator Output
VCO Frequency Waveforms
Figure 3. Figure 4.
Phase Shift
vs VCO Frequency as a
Frequency Function of Temperature
Figure 5. Figure 6.

OBSOLETE
LM565, LM565C
Typical Performance Characteristics (continued)

Loop Gain
vs
Load Hold in Range as a
Resistance Function of R67
Figure 7. Figure 8.

OBSOLETE
LM565, LM565C
Schematic Diagram
Figure 9. Schematic Diagram

OBSOLETE
LM565, LM565C
AC Test Circuit
Note: S1 open for output offset voltage (V7 V6) measurement.
Figure 10. AC Test Circuit

OBSOLETE
LM565, LM565C
Typical Applications
Figure 11. 2400 Hz Synchronous AM Demodulator

OBSOLETE
LM565, LM565C
Figure 12. FSK Demodulator (20252225 cps)
Figure 13. FSK Demodulator with DC Restoration

OBSOLETE
LM565, LM565C
Figure 14. Frequency Multiplier (10)
Figure 15. IRIG Channel 13 Demodulator

OBSOLETE
LM565, LM565C
APPLICATIONS INFORMATION
In designing with phase locked loops such as the LM565, the important parameters of interest are:
FREE RUNNING FREQUENCY
(1)
LOOP GAIN: relates the amount of phase change between the input signal and the VCO signal for a shift in input
signal frequency (assuming the loop remains in lock). In servo theory, this is called the velocity error coefficient.
(2)
The loop gain of the LM565 is dependent on supply voltage, and may be found from:
(3)
fo = VCO frequency in Hz
Vc = total supply voltage to circuit
Loop gain may be reduced by connecting a resistor between pins 6 and 7; this reduces the load impedance on
the output amplifier and hence the loop gain.
HOLD IN RANGE: the range of frequencies that the loop will remain in lock after initially being locked.
where
fo= free running frequency of VCO
Vc= total supply voltage to the circuit (4)
THE LOOP FILTER

In almost all applications, it will be desirable to filter the signal at the output of the phase detector (pin 7); this
filter may take one of two forms:
Figure 16. Simple Lead Filter
Figure 17. Lag-Lead Filter

OBSOLETE
LM565, LM565C
A simple lag filter may be used for wide closed loop bandwidth applications such as modulation following where
the frequency deviation of the carrier is fairly high (greater than 10%), or where wideband modulating signals
must be followed.
The natural bandwidth of the closed loop response may be found from:
(5)
Associated with this is a damping factor:
(6)
For narrow band applications where a narrow noise bandwidth is desired, such as applications involving tracking
a slowly varying carrier, a lead lag filter should be used. In general, if 1/R1C1 < Ko KD, the damping factor for the
loop becomes quite small resulting in large overshoot and possible instability in the transient response of the
loop. In this case, the natural frequency of the loop may be found from
(7)
R2 is selected to produce a desired damping factor #, usually between 0.5 and 1.0. The damping factor is found
from the approximation:
# $ %2fn (8)
These two equations are plotted for convenience.
Figure 18. Filter Time Constant vs Natural Frequency
Figure 19. Damping Time Constant vs Natural Frequency
Capacitor C2 should be much smaller than C1 since its function is to provide filtering of carrier. In general C2 &
0.1 C1.

OBSOLETE
LM565, LM565C
REVISION HISTORY
Changes from Revision A (April 2013) to Revision B Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 12

IMPORTANT NOTICE
performed.
MC1496, MC1496B
Balanced Modulators/
Demodulators
These devices were designed for use where the output voltage is a
product of an input voltage (signal) and a switching function (carrier).
Typical applications include suppressed carrier and amplitude
modulation, synchronous detection, FM detection, phase detection, http://onsemi.com
and chopper applications. See ON Semiconductor Application Note
AN531 for additional design information. SOIC 14
14 D SUFFIX
Features CASE 751A
1
! Excellent Carrier Suppression 65 dB typ @ 0.5 MHz
50 dB typ @ 10 MHz
! Adjustable Gain and Signal Handling PDIP 14
! Balanced Inputs and Outputs P SUFFIX
CASE 646
! High Common Mode Rejection 85 dB Typical 14
! This Device Contains 8 Active Transistors 1

! Pb Free Package is Available*
PIN CONNECTIONS
Signal Input 1 14 VEE
Gain Adjust 2 13 N/C
Gain Adjust 3 12 Output

Signal Input 4 11 N/C
Bias 5 10 Carrier Input
Output 6 9 N/C
N/C 7 8 Input Carrier
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
DEVICE MARKING INFORMATION

See general marking information in the device marking
section on page 12 of this data sheet.
Semiconductor Components Industries, LLC, 2006 1 Publication Order Number:

October, 2006 Rev. 10 MC1496/D
MC1496, MC1496B
IC = 500 kHz
IS = 1.0 kHz
Log Scale Id
20
40
IC = 500 kHz, IS = 1.0 kHz
60
499 kHz 500 kHz 501 kHz
Figure 1. Suppressed Carrier Output Figure 2. Suppressed Carrier Spectrum

Waveform
10
IC = 500 kHz
8.0 IS = 1.0 kHz
Linear Scale
6.0
4.0
2.0
IC = 500 kHz 0
IS = 1.0 kHz 499 kHz 500 kHz 501 kHz
Figure 3. Amplitude Modulation Figure 4. Amplitude Modulation Spectrum

Output Waveform
MAXIMUM RATINGS (TA = 25"C, unless otherwise noted.)

Rating Symbol Value Unit
Applied Voltage DV 30 Vdc
(V6 V8, V10 V1, V12 V8, V12 V10, V8 V4, V8 V1, V10 V4, V6 V10, V2 V5, V3 V5)
Differential Input Signal V8 V10 +5.0 Vdc
V4 V1 #(5 + I5Re)
Maximum Bias Current I5 10 mA
Thermal Resistance, Junction to Air RqJA 100 "C/W
Plastic Dual In Line Package
Operating Ambient Temperature Range MC1496 TA 0 to +70 "C
MC1496B 40 to +125
Storage Temperature Range Tstg 65 to +150 "C
Electrostatic Discharge Sensitivity (ESD) ESD V
Human Body Model (HBM) 2000
Machine Model (MM) 400
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
http://onsemi.com
2
MC1496, MC1496B
ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, VEE = 8.0 Vdc, I5 = 1.0 mAdc, RL = 3.9 kW, Re = 1.0 kW, TA = Tlow to Thigh,
all input and output characteristics are single ended, unless otherwise noted.) (Note 1)
Characteristic Fig. Note Symbol Min Typ Max Unit
Carrier Feedthrough 5 1 VCFT mVrms
VC = 60 mVrms sine wave and fC = 1.0 kHz 40
offset adjusted to zero fC = 10 MHz 140
VC = 300 mVpp square wave: mVrms
offset adjusted to zero fC = 1.0 kHz 0.04 0.4
offset not adjusted fC = 1.0 kHz 20 200
Carrier Suppression 5 2 VCS dB
fS = 10 kHz, 300 mVrms
fC = 500 kHz, 60 mVrms sine wave 40 65
fC = 10 MHz, 60 mVrms sine wave 50 k
Transadmittance Bandwidth (Magnitude) (RL = 50 W) 8 8 BW3dB MHz
Carrier Input Port, VC = 60 mVrms sine wave 300
fS = 1.0 kHz, 300 mVrms sine wave
Signal Input Port, VS = 300 mVrms sine wave 80
|VC| = 0.5 Vdc
Signal Gain (VS = 100 mVrms, f = 1.0 kHz; | VC|= 0.5 Vdc) 10 3 AVS 2.5 3.5 V/V
Single Ended Input Impedance, Signal Port, f = 5.0 MHz 6
Parallel Input Resistance rip 200 kW
Parallel Input Capacitance cip 2.0 pF
Single Ended Output Impedance, f = 10 MHz 6
Parallel Output Resistance rop 40 kW
Parallel Output Capacitance coo 5.0 pF
Input Bias Current 7 mA
IbS 12 30
I + I1 ) I4 ; I + I8 ) I10 IbC 12 30
bS 2 bC 2
Input Offset Current 7 $ IioS$ 0.7 7.0 mA
IioS = I1 I4; IioC = I8 I10 IioC$ 0.7 7.0
Average Temperature Coefficient of Input Offset Current 7 $ TCIio$ 2.0 nA/"C
(TA = 55"C to +125"C)
Output Offset Current (I6 I9) 7 $ Ioo$ 14 80 mA
Average Temperature Coefficient of Output Offset Current 7 $ TCIoo$ 90 nA/"C
(TA = 55"C to +125"C)
Common Mode Input Swing, Signal Port, fS = 1.0 kHz 9 4 CMV 5.0 Vpp
Common Mode Gain, Signal Port, fS = 1.0 kHz, |VC|= 0.5 Vdc 9 ACM 85 dB
Common Mode Quiescent Output Voltage (Pin 6 or Pin 9) 10 Vout 8.0 Vpp
Differential Output Voltage Swing Capability 10 Vout 8.0 Vpp
Power Supply Current I6 +I12 7 6 ICC 2.0 4.0 mAdc
Power Supply Current I14 IEE 3.0 5.0
DC Power Dissipation 7 5 PD 33 mW
1. Tlow = 0"C for MC1496 Thigh = +70"C for MC1496
= 40"C for MC1496B = +125"C for MC1496B
http://onsemi.com
3
MC1496, MC1496B
GENERAL OPERATING INFORMATION
Carrier Feedthrough Note that in the test circuit of Figure 10, VS corresponds to
Carrier feedthrough is defined as the output voltage at a maximum value of 1.0 V peak.
carrier frequency with only the carrier applied
(signal voltage = 0). Common Mode Swing
Carrier null is achieved by balancing the currents in the The common mode swing is the voltage which may be
differential amplifier by means of a bias trim potentiometer applied to both bases of the signal differential amplifier,
(R1 of Figure 5). without saturating the current sources or without saturating
the differential amplifier itself by swinging it into the upper
Carrier Suppression switching devices. This swing is variable depending on the
Carrier suppression is defined as the ratio of each particular circuit and biasing conditions chosen.
sideband output to carrier output for the carrier and signal
voltage levels specified. Power Dissipation
Carrier suppression is very dependent on carrier input Power dissipation, PD, within the integrated circuit
level, as shown in Figure 22. A low value of the carrier does package should be calculated as the summation of the
not fully switch the upper switching devices, and results in voltage current products at each port, i.e. assuming
lower signal gain, hence lower carrier suppression. A higher V12 = V6, I5 = I6 = I12 and ignoring base current,
than optimum carrier level results in unnecessary device and PD = 2 I5 (V6 V14) + I5)V5 V14 where subscripts refer
circuit carrier feedthrough, which again degenerates the to pin numbers.
suppression figure. The MC1496 has been characterized
Design Equations
with a 60 mVrms sinewave carrier input signal. This level The following is a partial list of design equations needed
provides optimum carrier suppression at carrier frequencies
to operate the circuit with other supply voltages and input
in the vicinity of 500 kHz, and is generally recommended for conditions.
balanced modulator applications.
Carrier feedthrough is independent of signal level, VS. A. Operating Current
Thus carrier suppression can be maximized by operating The internal bias currents are set by the conditions at Pin 5.
with large signal levels. However, a linear operating mode Assume:
must be maintained in the signal input transistor pair % or I5 = I6 = I12,
harmonics of the modulating signal will be generated and IBtt IC for all transistors
appear in the device output as spurious sidebands of the then :
suppressed carrier. This requirement places an upper limit
on input signal amplitude (see Figure 20). Note also that an V * *f where: R5 is the resistor between
R5+ *500 W where: Pin 5 and ground
optimum carrier level is recommended in Figure 22 for good I5
carrier suppression and minimum spurious sideband where: f = 0.75 at TA = +25"C
generation. The MC1496 has been characterized for the condition
At higher frequencies circuit layout is very important in I5 = 1.0 mA and is the generally recommended value.
order to minimize carrier feedthrough. Shielding may be B. Common Mode Quiescent Output Voltage
necessary in order to prevent capacitive coupling between V6 = V12 = V+ I5 RL
the carrier input leads and the output leads.
Biasing
Signal Gain and Maximum Input Level The MC1496 requires three dc bias voltage levels which
Signal gain (single ended) at low frequencies is defined must be set externally. Guidelines for setting up these three
as the voltage gain, levels include maintaining at least 2.0 V collector base bias
Vo R on all transistors while not exceeding the voltages given in
A + + L where r e + 26 mV the absolute maximum rating table;
VS V R e)2r e I5(mA)
S
30 Vdc w [(V6, V12) (V8, V10)] w% 2 Vdc
A constant dc potential is applied to the carrier input 30 Vdc w [(V8, V10) (V1, V4)] w% 2.7 Vdc
terminals to fully switch two of the upper transistors on 30 Vdc w [(V1, V4) (V5)] w% 2.7 Vdc
and two transistors off (VC = 0.5 Vdc). This in effect The foregoing conditions are based on the following
forms a cascode differential amplifier. approximations:
Linear operation requires that the signal input be below a
V6 = V12, V8 = V10, V1 = V4
critical value determined by RE and the bias current I5.
VS p I5 RE (Volts peak)
http://onsemi.com
4
MC1496, MC1496B
Bias currents flowing into Pins 1, 4, 8 and 10 are transistor Negative Supply
base currents and can normally be neglected if external bias VEE should be dc only. The insertion of an RF choke in
dividers are designed to carry 1.0 mA or more. series with VEE can enhance the stability of the internal
current sources.
Transadmittance Bandwidth
Carrier transadmittance bandwidth is the 3.0 dB bandwidth Signal Port Stability
of the device forward transadmittance as defined by: Under certain values of driving source impedance,
oscillation may occur. In this event, an RC suppression
i o (each sideband)
g21C+ v s (signal) $ Vo + 0 network should be connected directly to each input using
short leads. This will reduce the Q of the source tuned
Signal transadmittance bandwidth is the 3.0 dB bandwidth circuits that cause the oscillation.
of the device forward transadmittance as defined by:
Signal Input
i o (signal)
g21S+ v (signal)
s
$ Vc + 0.5 Vdc, Vo + 0 (Pins 1 and 4)
510
10 pF
Coupling and Bypass Capacitors
Capacitors C1 and C2 (Figure 5) should be selected for a
reactance of less than 5.0 W at the carrier frequency.
An alternate method for low frequency applications is to
Output Signal insert a 1.0 kW resistor in series with the input (Pins 1, 4). In
The output signal is taken from Pins 6 and 12 either this case input current drift may cause serious degradation
balanced or single ended. Figure 11 shows the output levels of carrier suppression.
of each of the two output sidebands resulting from variations
in both the carrier and modulating signal inputs with a
single ended output connection.
TEST CIRCUITS
VCC
12 Vdc Re = 1.0 k
1.0 k 1.0 k
Re 2 3
RL RL 0.5 V 8
51 C1
1.0 k 3.9 k 3.9 k + 10 +V o
C2 0.1 mF 2 3
Carrier 8 1 MC1496 6 Zout
Input 0.1 mF 10 I9 I6 Zin 4 V o
VC +V o 12
1 MC1496 6
VS V o 14 5
Modulating 4 12
Signal Input 14 5 6.8 k
10 k 10 k 51 51
50 k I5 6.8 k
I10 8.0 Vdc
R1 V
Carrier Null
8.0 Vdc NOTE: Shielding of input and output leads may be needed
VEE to properly perform these tests.
Figure 5. Carrier Rejection and Suppression Figure 6. Input Output Impedance

VCC VCC
12 Vdc 1.0 k 1.0 k 12 Vdc
Re = 1.0 k Re 2.0 k
1.0 k 51 0.1 mF 1.0 k 0.01
2 3 Carrier 2 3 mF
I7 2.0 k 8 50 50
8 I6 Input 0.1 mF
I8 10 VC 10 +V o
1.0 k 6 1 MC1496 6
I1 1 MC1496 I9 VS
4 V o
I4 4 Modulating 12
12
Signal Input 5
14 5 10 k 10 k 51 51 14
I10 50 k 6.8 k
6.8 k
V
Carrier Null
8.0 Vdc 8.0 Vdc
VEE VEE
Figure 7. Bias and Offset Currents Figure 8. Transconductance Bandwidth
http://onsemi.com
5
MC1496, MC1496B
VCC VCC
12 Vdc 12 Vdc
Re = 1.0 k Re = 1.0 k
1.0 k 1.0 k
3.9 k 3.9 k 3.9 k 3.9 k
0.5 V 8 2 3 0.5 V 2 3
1.0 k 8
+ 10 + 10
1.0 k +V o +V o
1 MC1496 6 1 MC1496 6
VS 4 V o VS V o
12 4 12
14 5 14 5
50
6.8 k I5 =
50 6.8 k
1.0 mA
$ V $
A + 20 log o
8.0 Vdc CM V
S 8.0 Vdc
VEE
VEE
Figure 9. Common Mode Gain Figure 10. Signal Gain and Output Swing
TYPICAL CHARACTERISTICS
Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave),
VO , OUTPUT AMPLITUDE OF EACH SIDEBAND (Vrms)
VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25"C, unless otherwise noted.
2.0 1.0 M
r ip, PARALLEL INPUT RESISTANCE (k&)
500
1.6 +rip
rip
Signal Input = 600 mV 100
1.2
50
400 mV
0.8
300 mV 10
200 mV 5.0
0.4
100 mV
0 1.0
0 50 100 150 200 1.0 5.0 10 50 100
VC, CARRIER LEVEL (mVrms) f, FREQUENCY (MHz)
Figure 11. Sideband Output versus Figure 12. Signal Port Parallel Equivalent
Carrier Levels Input Resistance versus Frequency
cop, PARALLEL OUTPUT CAPACITANCE (pF)

cip , PARALLEL INPUT CAPACITANCE (pF)
5.0 140 14
rop, PARALLEL OUTPUT RESISTANCE (k&)
120 12
4.0
100 10
3.0 rop
80 8.0
2.0 60 cop 6.0
40 4.0
1.0
20 2.0
0 0 0
1.0 2.0 5.0 10 20 50 100 0 1.0 10 100
f, FREQUENCY (MHz) f, FREQUENCY (MHz)
Figure 13. Signal Port Parallel Equivalent Figure 14. Single Ended Output Impedance
Input Capacitance versus Frequency versus Frequency
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6
MC1496, MC1496B
TYPICAL CHARACTERISTICS (continued)

Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave),
VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25"C, unless otherwise noted.
1.0 0
' 21, TRANSADMITTANCE (mmho)
0.9 Signal Port
VCS , CARRIER SUPPRESION (dB)

10
0.8
0.7 20
0.6 Side Band MC1496
30
0.5 Sideband Transadmittance (70"C)
$
I out(EachSideband) 40
0.4 g21 + V out + 0
V (Signal)
0.3 in
50
0.2 Signal Port Transadmittance
I
0.1
0
V
in
$
g21 + out V out + 0|V | + 0.5Vdc
C
60
70
0.1 1.0 10 100 1000 75 50 25 0 25 50 75 100 125 150 175
fC, CARRIER FREQUENCY (MHz) TA, AMBIENT TEMPERATURE ("C)
Figure 15. Sideband and Signal Port Figure 16. Carrier Suppression
Transadmittances versus Frequency versus Temperature
SUPPRESSION BELOW EACH FUNDAMENTAL

20 0
A VS, SINGLE-ENDED VOLTAGE GAIN (dB)
RL = 3.9 k
Re = 500 W 10
10
CARRIER SIDEBAND (dB)
20
RL = 3.9 k (Standard
0 Re = 1.0 k Test Circuit) RL = 3.9 k 30 2fC
Re = 2.0 k
10 40
RL = 500 W
|VC| = 0.5 Vdc Re = 1.0 k 50
20 fC
RL 60 3fC
A +
V R e ) 2r e
30 70
0.01 0.1 1.0 10 100 0.05 0.1 0.5 1.0 5.0 10 50
f, FREQUENCY (MHz) fC, CARRIER FREQUENCY (MHz)
Figure 17. Signal Port Frequency Response Figure 18. Carrier Suppression
versus Frequency
VCFT , CARRIER OUTPUT VOLTAGE (mVrms)
10 0
10
20
1.0
30
40
fC #% 3fS
50
0.1
60 fC #% 2fS
70
0.01 80
0.05 0.1 0.5 1.0 5.0 10 50 0 200 400 600 800
fC, CARRIER FREQUENCY (MHz) VS, INPUT SIGNAL AMPLITUDE (mVrms)
Figure 19. Carrier Feedthrough Figure 20. Sideband Harmonic Suppression

versus Frequency versus Input Signal Level
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7
MC1496, MC1496B
0 0
V CS , CARRIER SUPPRESSION (dB)

10 10
3fC #% fS
20 20
30 30 fC = 10 MHz
2fC #% fS
40 40
50 2fC #% 2fS fC = 500 kHz

50
60 60
70 70
0.05 0.1 0.5 1.0 5.0 10 50 0 100 200 300 400 500
fC, CARRIER FREQUENCY (MHz) VC, CARRIER INPUT LEVEL (mVrms)
Figure 21. Suppression of Carrier Harmonic Figure 22. Carrier Suppression versus
Sidebands versus Carrier Frequency Carrier Input Level
OPERATIONS INFORMATION
The MC1496, a monolithic balanced modulator circuit, is components and have an amplitude which is a function of the
shown in Figure 23. product of the input signal amplitudes.
This circuit consists of an upper quad differential amplifier For high level operation at the carrier input port and
driven by a standard differential amplifier with dual current linear operation at the modulating signal port, the output
sources. The output collectors are cross coupled so that signal will contain sum and difference frequency
full wave balanced multiplication of the two input voltages components of the modulating signal frequency and the
occurs. That is, the output signal is a constant times the fundamental and odd harmonics of the carrier frequency.
product of the two input signals. The output amplitude will be a constant times the
Mathematical analysis of linear ac signal multiplication modulating signal amplitude. Any amplitude variations in
indicates that the output spectrum will consist of only the sum the carrier signal will not appear in the output.
and difference of the two input frequencies. Thus, the device The linear signal handling capabilities of a differential
may be used as a balanced modulator, doubly balanced mixer, amplifier are well defined. With no emitter degeneration, the
product detector, frequency doubler, and other applications maximum input voltage for linear operation is
requiring these particular output signal characteristics. approximately 25 mV peak. Since the upper differential
The lower differential amplifier has its emitters connected amplifier has its emitters internally connected, this voltage
to the package pins so that an external emitter resistance may applies to the carrier input port for all conditions.
be used. Also, external load resistors are employed at the Since the lower differential amplifier has provisions for an
device output. external emitter resistance, its linear signal handling range
may be adjusted by the user. The maximum input voltage for
Signal Levels linear operation may be approximated from the following
The upper quad differential amplifier may be operated expression:
either in a linear or a saturated mode. The lower differential
V = (I5) (RE) volts peak.
amplifier is operated in a linear mode for most applications.
For low level operation at both input ports, the output This expression may be used to compute the minimum
signal will contain sum and difference frequency value of RE for a given input voltage amplitude.
() 12
Vo, 1.0 k 1.0 k 12 Vdc
Output 0.1 mF
(+) 6 RL RL
2 Re 1.0 k 3
51 3.9 k 3.9 k
10 () 8
Carrier V
Input C V 0.1 mF 10
+Vo
8 (+) Carrier C 6
Input 1 MC1496
4 () VS 4
Signal V 2 Modulating Vo
S Gain 12
Input 1 (+) Signal 10 k 51 51
Adjust 10 k
3 Input 14 5
Bias 5 50 k
I5 6.8 k
(Pin numbers
500 500 500 per G package) Carrier Null 8.0 Vdc
VEE 14 VEE
Figure 23. Circuit Schematic Figure 24. Typical Modulator Circuit
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8
MC1496, MC1496B
Table 1. Voltage Gain and Output Frequencies

Carrier Input Signal (VC) Approximate Voltage Gain Output Signal Frequency(s)
RL V
C
Low level dc fM
2(R E ) 2r e) KT
q

RL
High level dc fM
R ) 2r e
E
R L V (rms)
C
Low level ac fC #% fM
2 2 KT

q (RE ) 2r e)
0.637 R L
High level ac fC #% fM, 3fC #% fM, 5fC #% fM, . . .
R ) 2r e
E
2. Low level Modulating Signal, VM, assumed in all cases. VC is Carrier Input Voltage.
3. When the output signal contains multiple frequencies, the gain expression given is for the output amplitude ofeach of the two desired outputs,
fC + fM and fC fM.
4. All gain expressions are for a single ended output. For a differential output connection, multiply each expression by two.
5. RL = Load resistance.
6. RE = Emitter resistance between Pins 2 and 3.
7. re = Transistor dynamic emitter resistance, at 25"C; 26 mV
re [
I5 (mA)
8. K = Boltzmann(s Constant, T = temperature in degrees Kelvin, q = the charge on an electron.
The gain from the modulating signal input port to the All that is required to shift from suppressed carrier to AM
output is the MC1496 gain parameter which is most often of operation is to adjust the carrier null potentiometer for the
interest to the designer. This gain has significance only when proper amount of carrier insertion in the output signal.
the lower differential amplifier is operated in a linear mode, However, the suppressed carrier null circuitry as shown in
but this includes most applications of the device. Figure 26 does not have sufficient adjustment range.
As previously mentioned, the upper quad differential Therefore, the modulator may be modified for AM
amplifier may be operated either in a linear or a saturated operation by changing two resistor values in the null circuit
mode. Approximate gain expressions have been developed as shown in Figure 27.
for the MC1496 for a low level modulating signal input and
the following carrier input conditions: Product Detector
1) Low level dc The MC1496 makes an excellent SSB product detector
2) High level dc (see Figure 28).
3) Low level ac This product detector has a sensitivity of 3.0 mV and a
4) High level ac dynamic range of 90 dB when operating at an intermediate
frequency of 9.0 MHz.
These gains are summarized in Table 1, along with the The detector is broadband for the entire high frequency
frequency components contained in the output signal. range. For operation at very low intermediate frequencies
down to 50 kHz the 0.1 mF capacitors on Pins 8 and 10 should
APPLICATIONS INFORMATION be increased to 1.0 mF. Also, the output filter at Pin 12 can
Double sideband suppressed carrier modulation is the be tailored to a specific intermediate frequency and audio
basic application of the MC1496. The suggested circuit for amplifier input impedance.
this application is shown on the front page of this data sheet. As in all applications of the MC1496, the emitter
In some applications, it may be necessary to operate the resistance between Pins 2 and 3 may be increased or
MC1496 with a single dc supply voltage instead of dual decreased to adjust circuit gain, sensitivity, and dynamic
supplies. Figure 25 shows a balanced modulator designed range.
for operation with a single 12 Vdc supply. Performance of This circuit may also be used as an AM detector by
this circuit is similar to that of the dual supply modulator. introducing carrier signal at the carrier input and an AM
signal at the SSB input.
AM Modulator
The carrier signal may be derived from the intermediate
The circuit shown in Figure 26 may be used as an
frequency signal or generated locally. The carrier signal may
amplitude modulator with a minor modification.
http://onsemi.com
9
MC1496, MC1496B
be introduced with or without modulation, provided its level Figures 30 and 31 show a broadband frequency doubler
is sufficiently high to saturate the upper quad differential and a tuned output very high frequency (VHF) doubler,
amplifier. If the carrier signal is modulated, a 300 mVrms respectively.
input level is recommended.
Phase Detection and FM Detection
Doubly Balanced Mixer The MC1496 will function as a phase detector. High level
The MC1496 may be used as a doubly balanced mixer input signals are introduced at both inputs. When both inputs
with either broadband or tuned narrow band input and output are at the same frequency the MC1496 will deliver an output
networks. which is a function of the phase difference between the two
The local oscillator signal is introduced at the carrier input input signals.
port with a recommended amplitude of 100 mVrms. An FM detector may be constructed by using the phase
Figure 29 shows a mixer with a broadband input and a detector principle. A tuned circuit is added at one of the
tuned output. inputs to cause the two input signals to vary in phase as a
function of frequency. The MC1496 will then provide an
Frequency Doubler output which is a function of the input signal frequency.
The MC1496 will operate as a frequency doubler by
introducing the same frequency at both input ports.
TYPICAL APPLICATIONS
VCC
1.0 k 820 1.3 k 12 Vdc
0.1 mF 1.0 k 1.0 k VCC

+ 1.0 k 3.0 k 3.0 k 12 Vd
25 mF 2 3
51 8 DSB RL
15 V 0.1 mF 0.1 mF 2 Re 1.0 k 3 3.9 k RL
Carrier Input 10 6 51 3.9
0.1 mF Output 8
60 mVrms MC1496 VC 0.1 mF +
1 10 6
Carrier
Modulating 4 1 MC1496
+ Input
12 VS 4
Signal Input 10 mF 25 mF 14 5
Modulating 12

300 mVrms 15 V 15 V 10 k Signal 10 k 10 k 51 51 14 5
+
Carrier Input 50 k
Null 50 k 10 k 10 k 100 100 I5 6.8 k
R1
VEE
Carrier Null 8.0 Vdc
Figure 25. Balanced Modulator Figure 26. Balanced Modulator Demodulator

(12 Vdc Single Supply)
VCC
VCC 820 1.3 k
1.0 k 1.0 k 12 Vdc
12 Vdc
RL 0.1 mF
0.1 mF 2 Re 1.0 k 3 3.9 k RL 1.0 k 100
51 2 3.0 k 3.0 k
3.9 k 3
8 51 8
VC 0.1 mF 10 6 0.1 mF
Carrier +Vo Carrier Input 10 6 0.005
1 MC1496 300 mVrms mF
Input V 1 MC1496 AF
4
1.0 k 1.0 mFOutp
S
Modulating 12 SSB Input 0.1 mF 1.0 k 4
Vo
Signal 750 750 51 51 14 5 12 RLq 10
1.0 k 14 5
Input 50 k 0.1
mF 0.005 0.005
15 6.8 k 10 k
mF mF
VEE
Carrier Adjust 8.0 Vdc
Figure 27. AM Modulator Circuit Figure 28. Product Detector

(12 Vdc Single Supply)
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10
MC1496, MC1496B
VCC
12 Vdc
VCC
1.0 k 1.0 k +8.0 Vdc + 100 mF
0.01 1.0 k 25 Vdc
0.001 mF 1.0 k
mF RFC 2 3 3.9 k
Local 2 3 8 3.9 k
Oscillator 100 mH 1.0 k C2
51 8 100 10 6
Input 6
10
100 mVrms 0.001 mF 1 Input 100 mF C2+ Outp
MC1496 0.001 mF MC1496
9.0 MHz 15 mVrms 15 Vdc Max 100 mF 15 Vdc 1
RF Input 4 9.5 mF
10 k Output 12
12 L1 4
51 14 5 5.080 RL = 50W
10 k 51
pF 90480 pF 14 5
50 k 10 k 10 k 100 100
6.8 k
Null Adjust VEE 50 k
8.0 Vdc 6.8 k
I5
L1 = 44 Turns AWG No. 28 Enameled Wire, Wound
Balance VEE
on Micrometals Type 44 6 Toroid Core. 8.0 Vdc
Figure 29. Doubly Balanced Mixer Figure 30. Low Frequency Doubler
(Broadband Inputs, 9.0 MHz Tuned Output)
VCC
1.0 k 1.0 k V+ +8.0 Vdc
0.001
18 pF
mF
0.001 RFC L1
100 mF 0.68 mH 18 nH
2 3 1.010 pF 300 MHz
8 6
Output
0.001 mF 10 RL = 50W
150 MHz 1 MC1496 1.010 pF
Input
4
10 k 12
100
10 k 100 14 5
50 k
6.8 k
L1 = 1 Turn AWG
No. 18 Wire, 7/32) ID
Balance VEE
8.0 Vdc
Figure 31. 150 to 300 MHz Doubler

(fC f S )
(fC + f S )
AMPLITUDE
(2fC + 2f S )
(2fC 2f S )
(3fC + f S)
(3fC fS )
(2fC 2f S )
(2f C + 2f S )
(3fC + 2f S )
(3fC 2f S )
(fC 2f S )
(f + 2f )
S
(2fC )
(3fC )
(fC )
Frequency Balanced Modulator Spectrum

DEFINITIONS
fC Carrier Fundamental fC #% nfS Fundamental Carrier Sideband Harmonics
fS Modulating Signal nfC Carrier Harmonics
fC #% fS Fundamental Carrier Sidebands nfC #% nfS Carrier Harmonic Sidebands
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11
MC1496, MC1496B
ORDERING INFORMATION
Device Package Shipping
MC1496D SOIC 14
MC1496DG SOIC 14 55 Units/Rail
(Pb Free)
MC1496DR2 SOIC 14
MC1496DR2G SOIC 14 2500 Tape & Reel
(Pb Free)
MC1496P PDIP 14
MC1496PG PDIP 14
(Pb Free)
25 Units/Rail
MC1496P1 PDIP 14
MC1496P1G PDIP 14
(Pb Free)
MC1496BD SOIC 14
MC1496BDG SOIC 14 55 Units/Rail
(Pb Free)
MC1496BDR2 SOIC 14
MC1496BDR2G SOIC 14 2500 Tape & Reel
(Pb Free)
MC1496BP PDIP 14
MC1496BPG PDIP 14 25 Units/Rail
(Pb Free)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
SOIC 14 PDIP 14
D SUFFIX P SUFFIX
CASE 751A CASE 646
14 14 14 14
MC1496DG MC1496BDG MC1496P MC1496BP

AWLYWW AWLYWW AWLYYWWG AWLYYWWG
1 1 1 1
A = Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
G = Pb Free Package
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12
MC1496, MC1496B
PACKAGE DIMENSIONS
SOIC 14
CASE 751A 03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
A ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
14 8 3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
B 5. DIMENSION D DOES NOT INCLUDE
P 7 PL DAMBAR PROTRUSION. ALLOWABLE
0.25 (0.010) M B M DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
1 7 CONDITION.
G MILLIMETERS INCHES
R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
T F 0.40 1.25 0.016 0.049
K M J
SEATING D 14 PL G 1.27 BSC 0.050 BSC
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04 14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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13
MC1496, MC1496B
PDIP 14
CASE 646 06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 7 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
F L C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
N C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
T J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
SEATING L 0.290 0.310 7.37 7.87
PLANE
K J M 10 _ 10 _
H G D 14 PL N 0.015 0.039 0.38 1.01
M
0.13 (0.005) M
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: N. American Technical Support: 800 282 9855 Toll Free ON Semiconductor Website: http://onsemi.com
Literature Distribution Center for ON Semiconductor USA/Canada
P.O. Box 5163, Denver, Colorado 80217 USA Order Literature: http://www.onsemi.com/litorder
Phone: 303 675 2175 or 800 344 3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
Fax: 303 675 2176 or 800 344 3867 Toll Free USA/Canada 2 9 1 Kamimeguro, Meguro ku, Tokyo, Japan 153 0051 For additional information, please contact your
Email: orderlit@onsemi.com Phone: 81 3 5773 3850 local Sales Representative.
http://onsemi.com MC1496/D
14
Data sheet acquired from Harris Semiconductor
SCHS026C Revised September 2003
The CD4016 B Series types are supplied in

14-lead hermetic dual-in-line ceramic packages
(F3A suffix), 14-lead dual-in-line plastic
packages (E suffix), 14-lead small-outline
packages (M, MT, M96, and NSR suffixes), and
14-lead thin shrink small-outline packages (PW
and PWR suffixes).

(1) Drawing Qty (2) (6) (3) (4/5)
5962-9064001CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9064001CA
CD4016BF3A
CD4016BE ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD4016BE
(RoHS)
CD4016BEE4 ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD4016BE
(RoHS)
CD4016BF ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4016BF
CD4016BF3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9064001CA
CD4016BF3A
CD4016BM ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4016BM
& no Sb/Br)
CD4016BM96 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4016BM
& no Sb/Br)
CD4016BM96G4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4016BM
& no Sb/Br)
CD4016BMG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4016BM
& no Sb/Br)
CD4016BMT ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4016BM
& no Sb/Br)
CD4016BNSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4016B
& no Sb/Br)
CD4016BPW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM016B
& no Sb/Br)
CD4016BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM016B
& no Sb/Br)
CD4016BPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM016B
& no Sb/Br)
(1)
Addendum-Page 1
(2)
(3)
(4)
(5)
(6)
OTHER QUALIFIED VERSIONS OF CD4016B, CD4016B-MIL :
Catalog: CD4016B
Military: CD4016B-MIL
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Addendum-Page 2
Military - QML certified for Military and Defense Applications
Addendum-Page 3
www.ti.com 22-Jan-2015

(mm) W1 (mm)
CD4016BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4016BMT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4016BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4016BPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
www.ti.com 22-Jan-2015

CD4016BM96 SOIC D 14 2500 367.0 367.0 38.0
CD4016BMT SOIC D 14 250 367.0 367.0 38.0
CD4016BNSR SO NS 14 2000 367.0 367.0 38.0
CD4016BPWR TSSOP PW 14 2000 367.0 367.0 35.0
IMPORTANT NOTICE
performed.
Decade and Binary Counters
DM5490/DM7490A, DM7493A
July 1992
DM5490/DM7490A, DM7493A
General Description
Each of these monolithic counters contains four master- described in the appropriate truth table. A symmetrical di-
slave flip-flops and additional gating to provide a divide-by- vide-by-ten count can be obtained from the 90A counters by
two counter and a three-stage binary counter for which the connecting the QD output to the A input and applying the
count cycle length is divide-by-five for the 90A and divide- input count to the B input which gives a divide-by-ten square
by-eight for the 93A. wave at output QA.
All of these counters have a gated zero reset and the 90A
also has gated set-to-nine inputs for use in BCD nines com- Features
plement applications. Y Typical power dissipation
To use their maximum count length (decade or four-bit bina- 90A 145 mW
ry), the B input is connected to the QA output. The input 93A 130 mW
count pulses are applied to input A and the outputs are as Y Count frequency 42 MHz
Connection Diagrams
Dual-In-Line Package
TL/F/6533 1
Order Number DM5490J, DM5490W or DM7490AN
See NS Package Number J14A, N14A or W14B
Dual-In-Line Package
TL/F/6533 2
Order Number DM7493AN
See NS Package Number N14A
C1995 National Semiconductor Corporation TL/F/6533 RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required, Note: The Absolute Maximum Ratings are those values
please contact the National Semiconductor Sales beyond which the safety of the device cannot be guaran-
Office/Distributors for availability and specifications. teed. The device should not be operated at these limits. The
Supply Voltage 7V parametric values defined in the Electrical Characteristics
table are not guaranteed at the absolute maximum ratings.
Input Voltage 5.5V
The Recommended Operating Conditions table will define
Operating Free Air Temperature Range the conditions for actual device operation.
DM54 b 55 C to a 125 C
DM74 0 C to a 70 C
Storage Temperature Range b 65 C to a 150 C
Recommended Operating Conditions

DM5490 DM7490A
Symbol Parameter Units
Min Nom Max Min Nom Max
VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
VIH High Level Input Voltage 2 2 V
VIL Low Level Input Voltage 0.8 0.8 V
IOH High Level Output Current b 0.8 b 0.8 mA
IOL Low Level Output Current 16 16 mA
fCLK Clock Frequency A 0 32 0 32
MHz
(Note 5)
B 0 16 0 16
tW Pulse Width A 15 15
(Note 5)
B 30 30 ns
Reset 15 15
tREL Reset Release Time (Note 5) 25 25 ns
TA Free Air Operating Temperature b 55 125 0 70 C
90A Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 1)
VI Input Clamp Voltage VCC e Min, II e b12 mA b 1.5 V
VOH High Level Output VCC e Min, IOH e Max
2.4 3.4 V
Voltage VIL e Max, VIH e Min
VOL Low Level Output VCC e Min, IOL e Max
0.2 0.4 V
Voltage VIH e Min, VIL e Max (Note 4)
II Input Current @ Max VCC e Max, VI e 5.5V
1 mA
Input Voltage
IIH High Level Input VCC e Max A 80
Current VI e 2.7V
Reset 40 mA
B 120
IIL Low Level Input VCC e Max A b 3.2
Current VI e 0.4V
Reset b 1.6 mA
B b 4.8
IOS Short Circuit VCC e Max DM54 b 20 b 57
mA
Output Current (Note 2)
DM74 b 18 b 57
ICC Supply Current VCC e Max (Note 3) 29 42 mA
Note 1: All typicals are at VCC e 5V, TA e 25 C.
Note 2: Not more than one output should be shorted at a time.
Note 3: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V, and all other inputs grounded.
Note 4: QA outputs are tested at IOL e Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.
Note 5: TA e 25 C and VCC e 5V.
2
90A Switching Characteristics
at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)
RL e 400X
From (Input)
Symbol Parameter CL e 15 pF Units
To (Output)
Min Max
fMAX Maximum Clock A to QA 32
MHz
Frequency
B to QB 16
tPLH Propagation Delay Time
A to QA 16 ns
Low to High Level Output
tPHL Propagation Delay Time
A to QA 18 ns
High to Low Level Output
A to QD 48 ns
A to QD 50 ns
B to QB 16 ns
B to QB 21 ns
B to QC 32 ns
B to QC 35 ns
B to QD 32 ns
B to QD 35 ns
tPLH Propagation Delay Time SET-9 to
30 ns
Low to High Level Output QA, QD
tPHL Propagation Delay Time SET-9 to
40 ns
High to Low Level Output QB, QC
tPHL Propagation Delay Time SET-0
40 ns
High to Low Level Output Any Q
3
Recommended Operating Conditions
DM7493A
Symbol Parameter Units
Min Nom Max
VCC Supply Voltage 4.75 5 5.25 V
VIH High Level Input Voltage 2 V
VIL Low Level Input Voltage 0.8 V
IOH High Level Output Current b 0.8 mA
IOL Low Level Output Current 16 mA
fCLK Clock Frequency A 0 32
MHz
(Note 5)
B 0 16
tW Pulse Width A 15
(Note 5)
B 30 ns
Reset 15
tREL Reset Release Time (Note 5) 25 ns
TA Free Air Operating Temperature 0 70 C
93A Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions Min Max Units
(Note 1)
VI Input Clamp Voltage VCC e Min, II e b12 mA b 1.5 V
VOH High Level Output VCC e Min, IOH e Max
2.4 3.4 V
Voltage VIL e Max, VIH e Min
VOL Low Level Output VCC e Min, IOL e Max
0.2 0.4 V
Voltage VIH e Min, VIL e Max (Note 4)
II Input Current @ Max VCC e Max, VI e 5.5V
1 mA
Input Voltage
IIH High Level Input VCC e Max Reset 40
Current VI e 2.4V
A 80 mA
B 80
IIL Low Level Input VCC e Max Reset b 1.6
Current VI e 0.4V
A b 3.2 mA
B b 3.2
IOS Short Circuit VCC e Max b 18 b 57 mA
Output Current (Note 2)
ICC Supply Current VCC e Max (Note 3) 26 39 mA
Note 1: All typicals are at VCC e 5V, TA e 25 C.
Note 2: Not more than one output should be shorted at a time.
Note 3: ICC is measured with all outputs open, both R0 inputs grounded following momentary connection to 4.5V and all other inputs grounded.
Note 4: QA outputs are tested at IOL e Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.
Note 5: TA e 25 C and VCC e 5V.
4
93A Switching Characteristics
at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load)
RL e 400X
From (Input)
Symbol Parameter CL e 15 pF Units
To (Output)
Min Max
fMAX Maximum Clock A to QA 32 MHz
Frequency B to QB 16
tPLH Propagation Delay Time A to
16 ns
Low to High Level Output QA
tPHL Propagation Delay Time A to
18 ns
High to Low Level Output QA
tPLH Propagation Delay Time A to
70 ns
Low to High Level Output QD
tPHL Propagation Delay Time A to
70 ns
High to Low Level Output QD
tPLH Propagation Delay Time B to
16 ns
Low to High Level Output QB
tPHL Propagation Delay Time B to
21 ns
High to Low Level Output QB
32 ns
Low to High Level Output QC
35 ns
High to Low Level Output QC
51 ns
Low to High Level Output QD
51 ns
High to Low Level Output QD
tPHL Propagation Delay Time SET-0
High to Low Level Output to 40 ns
Any Q
5
Function Tables (Note D)
90A 90A 93A
BCD Count Sequence BCD Bi-Quinary (5-2) Count Sequence
(See Note A) (See Note B) (See Note C)
Outputs Outputs Outputs
Count Count Count
QD QC QB QA QA QD QC QB QD QC QB QA
0 L L L L 0 L L L L 0 L L L L
1 L L L H 1 L L L H 1 L L L H
2 L L H L 2 L L H L 2 L L H L
3 L L H H 3 L L H H 3 L L H H
4 L H L L 4 L H L L 4 L H L L
5 L H L H 5 H L L L 5 L H L H
6 L H H L 6 H L L H 6 L H H L
7 L H H H 7 H L H L 7 L H H H
8 H L L L 8 H L H H 8 H L L L
9 H L L H 9 H H L L 9 H L L H
10 H L H L
11 H L H H
12 H H L L
13 H H L H
14 H H H L
15 H H H H
90A 93A
Reset/Count Function Table Reset/Count Function Table
Reset Inputs Outputs Reset Inputs Outputs
R0(1) R0(2) R9(1) R9(2) QD QC QB QA R0(1) R0(2) QD QC QB QA
H H L X L L L L H H L L L L
H H X L L L L L L X COUNT
X X H H H L L H X L COUNT
X L X L COUNT
Note A: Output QA is connected to input B for BCD count.
L X L X COUNT
Note B: Output QD is connected to input A for bi-quinary count.
L X X L COUNT
Note C: Output QA is connected to input B.
X L L X COUNT
Note D: H e High Level, L e Low Level, X e Dont Care.
6
Logic Diagrams
90A 93A
TL/F/6533 4
TL/F/6533 3
The J and K inputs shown without connection are for reference only and are functionally at a high level.
7
8
Physical Dimensions inches (millimeters)
14-Lead Ceramic Dual-In-Line Package (J)

Order Number DM5490J
NS Package Number J14A
14-Lead Molded Dual-In-Line Package (N)

Order Number DM7490AN or DM7493AN
NS Package Number N14A
9
DM5490/DM7490A, DM7493A
Physical Dimensions inches (millimeters) (Continued)
14-Lead Ceramic Flat Package (W)

Order Number DM5490W
NS Package Number W14B
LIFE SUPPORT POLICY
NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor

Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309
Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, Kowloon
Fax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong
Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600
Italiano Tel: (a49) 0-180-534 16 80 Fax: (852) 2736-9960
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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A741 General-Purpose Operational Amplifiers

1 Short-Circuit Protection The A741 device is a general-purpose operational

Changes from Revision C (January 2014) to Revision D Page

Fixed Typical Characteristics graphs to remove extra lines. ................................................................................................. 7

Changes from Revision B (September 2000) to Revision C Page

Updated document to new TI data sheet format - no specification changes. ........................................................................ 1

2 Submit Documentation Feedback Copyright 19702015, Texas Instruments Incorporated

Product Folder Links: uA741

6 Pin Configurations and Functions

A741M . . . U PACKAGE A741M . . . FK PACKAGE

Copyright 19702015, Texas Instruments Incorporated Submit Documentation Feedback 3

7.2 Recommended Operating Conditions

Table 1. Dissipation Ratings Table

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