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A Voltage-Controlled DSTATCOM
for Power-Quality Improvement
Chandan Kumar, Student Member, IEEE, and Mahesh K. Mishra, Senior Member, IEEE
AbstractThis paper proposes a new algorithm to generate ref- In CCM operation, the DSTATCOM cannot compensate for
erence voltage for a distribution static compensator (DSTATCOM) voltage disturbances. Hence, CCM operation of DSTATCOM is
operating in voltage-control mode. The proposed scheme exhibits not useful under voltage disturbances, which is a major disad-
several advantages compared to traditional voltage-controlled
DSTATCOM where the reference voltage is arbitrarily taken as vantage of this mode of operation [13]. Traditionally, in VCM
1.0 p.u. The proposed scheme ensures that unity power factor operation, the DSTATCOM regulates the PCC voltage at 1.0 p.u.
(UPF) is achieved at the load terminal during nominal operation, [2], [8][11]. However, a load works satisfactorily for a permis-
which is not possible in the traditional method. Also, the compen- sible voltage range [14]. Hence, it is not necessary to regulate
sator injects lower currents and, therefore, reduces losses in the the PCC voltage at 1.0 p.u. While maintaining 1.0-p.u. voltage,
feeder and voltage-source inverter. Further, a saving in the rating
of DSTATCOM is achieved which increases its capacity to mitigate DSTATCOM compensates for the voltage drop in feeder. For
voltage sag. Nearly UPF is maintained, while regulating voltage this, the compensator has to supply additional reactive currents
at the load terminal, during load change. The state-space model which increases the source currents. This increases losses in the
of DSTATCOM is incorporated with the deadbeat predictive voltage-source inverter (VSI) and feeder. Another important as-
controller for fast load voltage regulation during voltage distur- pect is the rating of the VSI. Due to increased current injection,
bances. With these features, this scheme allows DSTATCOM to
tackle power-quality issues by providing power factor correction, the VSI is de-rated in steady-state condition. Consequently, its
harmonic elimination, load balancing, and voltage regulation capability to mitigate deep voltage sag decreases. Also, UPF
based on the load requirement. Simulation and experimental cannot be achieved when the PCC voltage is 1 p.u. In the litera-
results are presented to demonstrate the efficacy of the proposed ture, so far, the operation of DSTATCOM is not reported where
algorithm. the advantages of both modes are achieved based on load re-
Index TermsCurrent control mode, power quality (PQ), quirements while overcoming their demerits.
voltage-control mode, voltage-source inverter. This paper considers the operation of DSTATCOM in VCM
and proposes a control algorithm to obtain the reference load
terminal voltage. This algorithm provides the combined advan-
I. INTRODUCTION
tages of CCM and VCM. The UPF operation at the PCC is
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1500 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 29, NO. 3, JUNE 2014
(3)
In (3), and represent the th sample and sampling period,
respectively. During the consecutive sampling period, the value
of is held constant, and can be taken as . After simpli-
fication and changing the integration variable, (3) is written as
[18]
Fig. 1. Circuit diagram of the DSTATCOM-compensated distribution system.
(4)
(5)
(6)
on instantaneous symmetrical component theory and complex
Fourier transform, a reference voltage magnitude generation
scheme is proposed that provides the advantages of CCM at
nominal load. The overall controller block diagram is shown in
Fig. 3. These steps are explained as follows.
(7)
A. System Modeling and Generation of the Voltage-Control From (6) and (7), ,
Law , , ,
, and . Hence, the capacitor voltage using
The state-space equations for the circuit shown in Fig. 2 are
(5) is given as
given by
(1)
(8)
where As seen from (8), the terminal voltage can be maintained at a ref-
erence value depending upon the VSI parameters , , ,
, and sampling time . Therefore, VSI parameters must be
chosen carefully. Let be the reference load terminal voltage.
A cost function is chosen as follows [8]:
(9)
(10)
The general time-domain solution of (1) to compute the state The deadbeat voltage-control law, from (8) and (10), is given as
vector with known initial value , is given as follows:
(2)
(11)
KUMAR AND MISHRA: VOLTAGE-CONTROLLED DSTATCOM FOR PQ IMPROVEMENT 1501
Fig. 3. Overall block diagram of the controller to control DSTATCOM in a distribution system.
In (11), is the future reference voltage which is un- where and are the reference dc bus voltage and max-
known. One-step-ahead prediction of this voltage is done using imum-allowed voltage during transients, respectively. Hence
a second-order Lagrange extrapolation formula as follows:
(14)
(12)
The term is valid for a wide frequency range [17] and Here, 10 kVA, 650 V, 1, and
when substituted in (11), yields to a one-step-ahead deadbeat or . Using (14), capacitor values are found to be 2630
voltage-control law. Finally, is converted into the ON/OFF and 2152 . The capacitor value 2600 is chosen to achieve
switching command to the corresponding VSI switches using a satisfactory performance during all operating conditions.
deadbeat hysteresis controller [17]. 3) Filter Inductance : Filter inductance should pro-
vide reasonably high switching frequency and a sufficient rate
B. Design of VSI Parameters of change of current such that VSI currents follow desired cur-
rents. The following equation represents inductor dynamics:
DSTATCOM regulates terminal voltage satisfactorily, de-
pending upon the properly chosen VSI parameters. The design
(15)
procedure of these parameters is presented as follows.
1) Voltage Across DC Bus ( ): The dc bus voltage is taken
twice the peak of the phase voltage of the source for satisfactory The inductance is designed to provide good tracking per-
performance [19]. Therefore, for a line voltage of 400 V, the dc formance at a maximum switching frequency ( ) which is
bus voltage is maintained at 650 V. achieved at the zero of the source voltage in the hysteresis con-
2) DC Capacitance : Values of dc capacitors are troller. Neglecting , is given by
chosen based on a period of sag/swell and change in dc bus
voltage during transients. Let the total load rating be kVA. (16)
In the worst case, the load power may vary from minimum to
maximum that is, from 0 to kVA. The compensator needs where is the ripple in the current. With 10 kHz and
to exchange real power during transient to maintain the load 0.75 A (5% of rated current), the value of using (16) is
power demand. This transfer of real power during the tran- found to be 21.8 mH, and 22 mH is used in realizing the filter.
sient will result in the deviation of capacitor voltage from its 4) Shunt Capacitor : The shunt capacitor should not
reference value. The voltage continues to decrease until the resonate with feeder inductance at the fundamental frequency
capacitor voltage controller comes into action. Consider that ( ). Capacitance, at which resonance will occur, is given as
the voltage controller takes cycles, that is, seconds to act,
where is the system time period. Hence, maximum energy (17)
exchange by the compensator during transient will be .
This energy will be equal to the change in the capacitor stored For proper operation, must be chosen very small compared
energy. Therefore to . Here, a value of 5 F is chosen which provides an
impedance of 637 at . This does not allow the capacitor
(13) to draw significant fundamental reactive current.
1502 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 29, NO. 3, JUNE 2014
C. Controller for DC Bus Capacitor Voltage The fundamental positive-sequence component of load cur-
Average real power balance at the PCC will be rent , calculated by finding the complex Fourier coefficient,
is expressed as follows:
(18)
(22)
where , , and are the average PCC power, load
power, and losses in the VSI, respectively. The power available is a complex quantity, contains magnitude and phase angle
at the PCC, which is taken from the source, depends upon the information, and can be expressed in phasor form as follows:
angle between source and PCC voltages, that is, load angle .
Hence, must be maintained constant to keep constant. (23)
The voltage of the dc bus of DSTATCOM can be maintained
at its reference value by taking inverter losses from the Hence, the instantaneous fundamental positive-sequence com-
source. If the capacitor voltage is regulated to a constant refer- ponent of load current in phase- , , is expressed as
ence value, is a constant value. Consequently, is also a
constant value. Thus, it is evident that dc-link voltage can be (24)
regulated by generating a suitable value of . This includes The fundamental positive-sequence component of load currents
the effect of losses in the VSI and, therefore, it takes care of must be supplied by the source at nominal load. Hence, it will
the term in its action. To calculate load angle , the aver- be treated as reference source currents. For UPF at nominal op-
aged dc-link voltage ( ) is compared with a reference eration, the nominal load angle is used. By knowing ,
voltage, and error is passed through a PI controller. The output fundamental positive-sequence currents in phases and can be
of the PI controller, which is load angle , is given as follows: easily computed by providing a phase displacement of
and , respectively, and are given as
(19)
(20)
(27)
where represent three phases, is the harmonic Substituting (27) into (26), the phasor equation will be
number, and is the maximum harmonic order. repre-
sents the phase angle of the th harmonic with respect to ref- (28)
erence in phase- and is similar to other phases. Using instan-
taneous symmetrical component theory, instantaneous zero-se- Simplifying the above equation
quence , positive-sequence , and negative-sequence
(29)
current components are calculated as follows:
Equating real and imaginary parts of both sides of (29), the
(21) following equation is obtained:
TABLE I
SIMULATION PARAMETERS
(31)
(32)
Finally, using from (32), the load angle from (19), and the
phase- source voltage as reference, three-phase reference ter-
minal voltages are given as
Fig. 5. Terminal voltages and source currents using the traditional method.
(33) (a) Phase- . (b) Phase- . (c) Phase- .
Fig. 9. Phase- source rms currents. (a) Traditional method. (b) Proposed
method.
Fig. 7. Terminal voltages and source currents using the proposed method.
(a) Phase- . (b) Phase- . (c) Phase- . Fig. 10. Phase- compensator rms currents. (a) Traditional method. (b) Pro-
posed method.
(34)
(35)
Using (34) and (35), VSI losses are reduced by 61.68% and only
Fig. 8. Load reactive power ( ), compensator reactive power ( ), and
61.9% VSI rating is utilized in the proposed method.
reactive power at PCC ( ). (a) Traditional method. (b) Proposed method. In the traditional method, DSTATCOM maintains a load
terminal voltage at 1.0 p.u. For this, it needs to compensate
for the entire feeder drop. Hence, at the steady state, the com-
pensator supplies reactive power to the source to overcome
methods are given in Fig. 8(a) and (b), respectively. In the this drop. However, in the proposed scheme, the compensator
traditional method, the compensator needs to overcome voltage does not compensate for the feeder drop in the steady-state
drop across the feeder by supplying reactive power into the condition. Hence, a lesser rating of VSI is utilized in the steady
source. As shown in Fig. 8(a), reactive power that is supplied state. This savings in rating is utilized to mitigate deep sag, and
by the compensator and has a value of 4.7 kVAr is significantly DSTATCOM capacity to mitigate deep sag increases.
more than the load reactive power demand of 2.8 kVAr. This
additional reactive power of 1.9 kVAr goes into the source.
B. Operation During Sag
This confirms that significant reactive current flows along the
feeder in the traditional method. However, in the proposed To create sag, source voltage is lowered by 20% from its nom-
method, UPF is achieved at the PCC by maintaining suitable inal value at 0.6 s as shown in Fig. 11(a). Sag is removed
voltage magnitude. Thus, the reactive power supplied by the at 1.0 s as shown in Fig. 11(b). Since voltage regulation
compensator is the same as that of the load reactive power de- capability does not depend upon reference voltage, it is not
mand. Consequently, reactive power exchanged by the source shown separately for the traditional method. Fig. 11(c) and (d)
at the PCC is zero. These waveforms are given in Fig. 8(b). shows terminal voltages regulated at their reference value.
Fig. 9(a) and (b) shows the source rms currents in phase- The controller provides a fast voltage regulation at the load
for the traditional and proposed methods, respectively. The terminal. Fig. 11(e) and (f) shows the total dc bus voltage
source current has decreased from 11.35 to 10.5 A in the and the load angle, respectively. During the transient period,
proposed method. Consequently, it reduces the ohmic losses capacitors supply real power to maintain load power which
in the feeder. Fig. 10(a) and (b) shows the compensator rms results in discharging of capacitors. Consequently, increases
currents in phase- for the traditional and proposed methods, to draw more power from the source compared to normal
respectively. The current has decreased from 8.4 to 5.2 A in operation. After some time, the dc bus voltage again reaches
KUMAR AND MISHRA: VOLTAGE-CONTROLLED DSTATCOM FOR PQ IMPROVEMENT 1505
Fig. 12. (a) Source voltages. (b) Terminal voltages. (c) Voltage at the dc bus.
(d) Compensator rms current in the proposed method.
Fig. 11. (a) Source voltages during normal to sag. (b) Source voltages during
sag to normal. (c) Terminal voltages during normal to sag. (d) Terminal voltages
during sag to normal. (e) Voltage at the dc bus. (f) Load angle. (g) Compensator
rms current in the traditional method. (h) Compensator rms current in the pro- Fig. 13. Terminal voltage and source current in phase- during load change.
posed method. (a) Traditional method. (b) Proposed method.
the reference voltage whereas the load angle settles down at The terminal voltages, maintained at the reference value, are
17.4 . However, the load angle again settles down at nominal shown in Fig. 12(b). The voltage across the dc bus is shown
value once the sag gets cleared. Compensator rms currents in Fig. 12(c). During transients, this voltage deviates from its
in the traditional and proposed method in phase- are shown reference voltage. However, it is brought back to the reference
in Fig. 11(g) and (h), respectively. In the proposed method, value once steady state is reached. Fig. 12(d) shows the phase-
compensator rms current has decreased to 21.3 from 24.8 A. rms compensator current which is large, nearly 47 A, during
Loss reduction and percentage loss reduction in the VSI are the sag period. These waveforms confirm that the DSTATCOM
given as has the capability to mitigate deep sag independent of duration.
However, it requires a high current rating of the VSI.
achieved during voltage disturbances; and 4) losses in the VSI [14] M. Moradlou and H. Karshenas, Design strategy for optimum rating
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that the proposed scheme provides DSTATCOM, a capability to IEEE Trans. Ind. Electron., vol. 54, no. 1, pp. 495503, Feb. 2007.
[16] J. Barros and J. Silva, Multilevel optimal predictive dynamic voltage
improve several PQ problems (related to voltage and current). restorer, IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 27472760,
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vol. 21, no. 2, pp. 726735, Apr. 2006. College of Technology, Pantnagar, India, in 1991, the
[10] R. Gupta, A. Ghosh, and A. Joshi, Switching characterization of cas- M.E. degree in electrical engineering from the Uni-
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[11] P. Mitra and G. Venayagamoorthy, An adaptive control strategy for dian Institute of Technology, Kanpur, India, in 2002.
DSTATCOM applications in an electric ship power system, IEEE He has teaching and research experience of about
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[12] A. Yazdani, M. Crow, and J. Guo, An improved nonlinear STATCOM Electrical Engineering Department, Visvesvaraya
control for electric arc furnace voltage flicker mitigation, IEEE Trans. National Institute of Technology, Nagpur, India.
Power Del., vol. 24, no. 4, pp. 22842290, Oct. 2009. Currently, he is a Professor in the Electrical Engineering Department, Indian
[13] S.-H. Ko, S. Lee, H. Dehbonei, and C. Nayar, Application of voltage- Institute of Technology Madras, Chennai. His interests are in the areas of power
and current-controlled voltage source inverters for distributed gen- distribution systems, power electronics, microgrids, and renewable energy
eration systems, IEEE Trans. Energy Convers., vol. 21, no. 3, pp. systems.
782792, Sep. 2006. Dr. Mahesh is a life member of the Indian Society of Technical Education.