School of Electronics Engineering

Winter Semester 2015

ECE103 Digital Logic Design Lab
List of Experiments:
HARDWARE

1) Verification of logic gates, HA and HS

2) Design and Verification of Multiplexer and De-
multiplexer.
3) Design and Verification of Encoder and Decoder.
4) Design of Parity Generator and code converter
(Binary to gray, gray to binary)

SOFTWARE ( Model sim, Altera DE board)

1) Modeling of HA, FA, HS, FS, MUX ,De-MUX,

Encoder, Decoder (Data flow, gatelevel and behaviour level)
2) FF and shift registers( SISO,PISO) ( any modeling
style)
3) Demo on downloading in DE-2 board and Counter
Design ( up and down counter, Johnson) ( any modeling style)
4) Sequence Detector
 1. VERIFICATION OF LOGIC GATES

AIM:
To study and verify the truth table of logic gates.

APPARATUS\ COMPONENTS REQUIRED:

THEORY:
The logic gates belonging to the TTL family perform the following functions:

OR GATE
The OR gate does the OR logic operation. If A and B are the inputs then the output Y is
given by
Y=A+B, + denotes OR operation.
AND GATE
The AND gate does the AND logic operation. If A and B are the inputs then the output
Y is given by
Y=A.B, . denotes AND operation.
NOT GATE
The NOT gate does the NOT logic operation. If A is the input then the output Y is
given by
Y=A, where denotes NOT operation.
The logic gates OR, AND, NOT are called universal gates

NOR GATE
The NOR gate does the NOR logic operation. It is NOT operation of the OR logic. If
A and B are the inputs then the output Y is given by
Y= (A+B), where + denotes OR operation.

NAND GATE
The NAND gate does the NAND logic operation. It is NOT operation of the AND
logic. If A and B are the inputs then the output Y is given by

Y= (A.B), . denotes AND operation.

EXOR GATE
The EXOR gate does the EXOR logic operation. If A and B are the inputs then the
output Y is given by
Y=A.B+A.B
AND gate

IC 7408

OR gate

IC 7432

NOT gate

IC 7404

NAND gate

IC 7400
NOR gate

IC 7402

EXOR gate

IC 7486

EXNOR gate

IC4077

RESULT:

Thus the operations of logic gates were verified with its truth table.
 1a. DESIGN HALF ADDER & HALF SUBTRACTOR USING LOGIC GATES

THEORY
Half Adder
This is a logic circuit, which accepts two binary bits on its input and produces two binary
bits at the output called the sum and the carry bits. From the operation of the half adder circuit,
the expression for sum and carry outputs are given as a function of the inputs
SUM = A B. CARRY = AB.
Half Subtractor
This is a logical circuit which subtracts one input from the other and generates the
difference bit and the borrow bit. The logical expression for the difference and borrow output is
a function of inputs.
D =A B B0 = B

Half Adder Circuit Diagram

1
3
A 2 1
3
7400 2

7400

1
B 3 1 1 R1
2 3 3 SUM
2 2
330
7400
7400 7400

1 1 R2
3 3 CARRY
2 2
330
7400 7400
Truth Table
Half Adder

A
B S C0
0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Half Subtractor Circuit Diagram

1
3
A 2 1
3
7400 2

7400

1
B 3 1 1 R1
2 3 3 DIFFERENCE
2 2
330
7400
7400 7400

R2
1 BORROW
3
330
2
1 1
7400 3 3
2 2

7400 7400
Truth Table

A B D B0

0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Inference and Result:

Thus the functionality of half adder, full adder, half subtractor and full subtractor are verified.

Facultys Evaluation:
 2. DESIGN AND VERIFICATION OF MULTIPLEXER AND
DE-MULTIPLEXER.

AIM
To study the 4:1 multiplexer and 1:4 De-multiplexer using gates.

APPARATUS REQUIRED

THEORY
Multiplexer is a combinational circuit which can select any one of the input and route it to the
out put. A multiplexer has data input lines, data select lines and output. The logical symbol of a 4
line to 1 line multiplexer is shown in figure. According to the two bit binary code on the data
select input, corresponding data input line will be selected and routed to the output. For example
if S1S0 is 00 , D0 will be selected, if S1S0 01, D1 will be selected and so on. from the truth table it
can be seen that output

Y=D0S1S0+D1S1S0+D2S1S0+D3S1S0

Logic Symbol /Truth Table

S0
S1
S1 S0 Y

MUX Y 0 0 D0
D0
D1 0 1 D1
D2 1 0 D2
D3 1 1 D3
Circuit Diagram

THEORY
Demultiplexer does the reverse operation of multiplexer. The data on a line is distributed any
one of the output line according to the binary code on data select lines. The logic symbol of a 1
line to 4 line demultiplixer is shown in figure. When the input on data select inputs S1 S0 is 00 ,
data on the data line will be available on D0 output, if the input on data select inputs S0 S1 is 01 ,
data on the data line will be available on D1 output and so on
 Logic Symbol/ Truth Table

Data select

S0 S0 S1 D0 D1 D2 D3
D0
S1 D1 0 0 D 0 0 0

DEMUX 1
D2 0 1 0 D 0 0

1D3
1 0 0 0 D 0
Data input
1

1 1 0 0 0 D

Circuit Diagram
 Data select

S0

S1

D0
D

Data input

D1

D2

D3
Inference and Result
The functionality of the 1 to 4 DEMUX was verified with truth table.

Facultys Evaluation
 3. DESIGN AND VERIFICATION OF ENCODER AND DECODER.

AIM:
To design and investigate the decoder and encoder.

APPARATUS REQUIRED:

THEORY:
DECODER:
A decoder is a combinational circuit that converts binary information from n input lines
to a maximum 2n unique output (n) lines.
If the n-bit decoded information has an unused dont care combinations. The decoder
output will be fewer than 2n outputs.
2 to 4 DECODER:
Since it has two input lines and four output lines, it is called 2 to 4 line decoder. Only one
output will be activated for the given input.
CIRCUIT OPERATIONS:
i) If both the inputs are zero i.e., A=0 and B=0.The first AND gate D0 =A1 B1 is selected
and the remaining AND gates are active low.
ii) If the inputs A=0 and B=1, then the first, third and fourth AND gates outputs are
active low. The output of second AND gate is active high.
iii) If both the inputs A=1 and B=1, then the first, second and third AND gates outputs
are active low and the fourth one is active high.
DECODER:

BLOCK DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT
A B D0 D1 D2 D3
0
0 1 0 0 0
0
1 0 1 0 0
1
0 0 0 1 0
1
1 0 0 0 1
Circuit Diagram
THEORY:
ENCODER:
An encoder is a digital circuit that performs the reverse operation of the decoder. The
encoder has 2n input lines and n output lines. The output lines generate the binary code
corresponding to the input values. The process of translating decimal number to binary is
encoding.
4 to 2 ENCODER:
It accepts four inputs and produces two bit output code corresponding to that input. It is
assumed that only one input has a value 1 at any given time.
CIRCUIT OPERATIONS:
i) When D2 = 1 and D3 = 1 (active high) the output A is active high. So A=D2+D3.
ii) When D1= 1 and D3 = 1 (active high) the output B is active high. So B=D1+D3.
ENCODER:

BLOCK DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT
D0 D1 D2 D3 X Y
0 0 0 0 0
1
0 1 0 0 0 1

0 0 1 0 1 0

0 0 0 1 1 1
Circuit Diagram

Inference and Result

Thus the 4 : 2 encoder and 2 : 4 Decoder circuit was designed, constructed using logic gates and verified
with truth table.

Facultys Evaluation
 4. DESIGN OF PARITY GENERATOR AND CODE CONVERTER (BINARY TO
GRAY, GRAY TO BINARY)

AIM

To design the parity generator and code converter to convert binary to gray and vice versa.

APPARATUS REQUIRED:

THEORY

To indicate any occurrence of error, an extra bit is included with the message according to the
total number of 1s in a set of data, which is called parity.

If the extra bit is considered 0 if the total number of 1s is even and 1 for odd quantities of 1s in a
set of data, then it is called even parity.

Pe D0 D1 D2 D3

On the other hand, if the extra bit is 1 for even quantities of 1s and 0 for an odd number of 1s,
then it is called odd parity.

Po D0 D1 D2 D3
Circuit Diagram

ODD PARITY

EVEN PARITY
Truth Table

D0 D1 D2 D3 Pe PO
0 0 0 0 0 0

0 0 0 1 1 0

0 0 1 0 0 1

0 0 1 1 1 0

0 1 0 0 0 1

0 1 0 1 1 0

0 1 1 0 0 1

0 1 1 1 1 0

1 0 0 0 0 1

1 0 0 1 1 0

1 0 1 0 0 1

1 0 1 1 1 0

1 1 0 0 0 1

1 1 0 1 1 0

1 1 1 0 0 1

1 1 1 1 1 0
BINARY TO GRAY CODE

An interesting application for the exclusive-OR gate is a logic gate to change a binary number to
its equivalent in Gray Code. The logic circuit can be used to convert a 4-bit binary number
ABCD into its Gray- code equivalent, G1, G2, G3 and G4. As an example, the binary number
0011 will be converted into its Gray-Code equivalent of 0010 by the circuit.

Circuit Diagram
Truth Table
GRAY TO BINARY CONVERTER

A Gray code is an encoding of numbers so that adjacent numbers have a single digit differing by
1. The term Gray code is often used to refer to a "reflected" code, or more specifically still, the
binary reflected Gray code.

To convert a binary reflected Gray code to a binary number, start again with the
th digit, and compute

If is 1, replace by ; otherwise, leave it the unchanged. Next compute

and so on. The resulting number is the binary number corresponding to the initial
binary reflected Gray code.

Circuit Diagram
Truth Table

Inference and Result

Facultys Evaluation
Exp.No.1 Design and Implementation of Combinational Circuits

Aim:

To design and implement the following combinational circuit using Dataflow, Structural,
Behavioral Modeling.

a. Half-Adder and Full-Adder.

b. Half-Subtractor and Full-Subtractor.
c. Decoder and Encoder.
d. Multiplexer and De-multiplexer.

Software Details:
For design Fuctional Simulation Result: ModelSim
For designSynthesis: Quartus II
For design Implementation: Quartus II

a. Half-Adder and Full-Adder Using Dataflow, Structural, Behavioral

Modeling

RTL Code for Half adder :

Behavioral Modeling:
modulehalf_adder(a,b,s,co);
inputa,b;
outputs,co;
always@(a or b)
begin
if(a==0 && b==0) begin s=0;co=0; end
if(a==0 && b==1) begin s=1;co=0; end
if(a==1 && b==0) begin s=1;co=0; end
if(a==1 && b==1) begin s=0;co=1; end
endmodule

Data Flow Modeling

modulehalf_adder(a,b,s,co);
inputa,b;
outputs,co;
assign s=(a^b),co=(a&b);
endmodule
Structural Modeling:

modulehalf_adder(a,b,s,co);
inputa,b;
outputs,co;
xor(s,a,b);
and (co,a,b);
endmodule

Test Bench for Half adder :

modulehalfadder_test();
rega,b;
wires,co;
half_addera1(a,b,s,co);
initial
begin
a=1'b0;b=1'b0;#10; a=1'b0;b=1'b1;#10;
a=1'b1;b=1'b0;#10; a=1'b1;b=1'b1;#100;
$stop;
end
endmodule

Functional Simulation Result of Half adder:

RTL Schematic of Half adder

Inference:

RTL Code for Full adder:

Behavioral Modeling:

modulefull_adder(a,b,c,s,co);
inputa,b;
outputs,co;
always@(a or b or c)
begin
if(a==0 && b==0&&c=0) begin s=0;co=0; end
if(a==0 && b==0&& c=1) begin s=1;co=0; end
if(a==0 && b==0&&c=0) begin s=1;co=0; end
if(a==0 && b==1&&c=1) begin s=0;co=1; end
if(a==1 && b==0&&c=0) begin s=1;co=0; end
if(a==1 && b==0&& c=1) begin s=0;co=1; end
if(a==1 && b==1&&c=0) begin s=0;co=1; end
if(a==1 && b==1&&c=1) begin s=1;co=1; end
endmodule
Data Flow Modeling

modulefull_adder(a,b,c,s,co);
inputa,b,c;
outputs,co;
assign s=(a^b)^c,co=(a&b)|(b&c)|(c&a);
endmodule

Structural Modeling:

moduleFA_mod(a,b,c,s,co);
inputa,b,c;
outputs,co;
wire w1,w2,w3;
half_adderh1(.a(a),.b(b),.s(w2),.co(w1));
half_adderh2(.a(w2),.b(c),.s(s),.co(w3));
or r1(co,w1,w3);
endmodule

Test Bench for Full adder

modulefulladder_test();
rega,b,c;
wires,co;
full_addera1(a,b,c,s,co);
initial
begin
a=1'b0;b=1'b0;c=1'b0;#10;
a=1'b0;b=1'b0;c=1'b1;#10;
a=1'b0;b=1'b1;c=1'b0;#10;
a=1'b0;b=1'b1;c=1'b1;#10;
a=1'b1;b=1'b0;c=1'b0;#10;
a=1'b1;b=1'b0;c=1'b1;#10;
a=1'b1;b=1'b1;c=1'b0;#10;
a=1'b1;b=1'b1;c=1'b1;#100;
$stop; end endmodule

Functional Simulation Result of Full addergate:

RTL Schematic of Full adder

Inference:
 b. Half-Subtractor and Full-Subtractor Using Dataflow, Structural,
Behavioral Modeling

RTL Code for Half subtractor:

Data Flow Modeling

modulehalf_sub(a,b,s,co);
inputa,b;
outputs,co;
assign s=(a^b),co=(~a&b);
endmodule

Structural Modeling:

module half_sub12(a,b,s,co);
inputa,b;
outputs,co; wire d;
not n1(d,a);
xor(s,a,b);
and (co,b,b);
endmodule

Test Bench forHalfsubtractor

modulehalfsub_test();
rega,b;
wires,co;
half_suba1(a,b,s,co);
initial
begin
a=1'b0;b=1'b0;#10; a=1'b0;b=1'b1;#10;
a=1'b1;b=1'b0;#10; a=1'b1;b=1'b1;#100;
$stop;
end endmodule

Functional Simulation Result of Half subtractor:

RTL Schematic of Half subtractor

Inference:
RTL Code for Full Subtractor:

Data Flow Modeling

modulefull_sub(a,b,c,s,co);
inputa,b,c;
outputs,co;
assign s=(a^b)^c,co=(~a&b)|(b&c)|(c&~a);
endmodule

Structural Modeling:

module full_sub12(a,b,c,s,co);
inputa,b,c;
outputs,co;wire d;
not n1(d,a); or r1(co,g,f,e);
xor(s,a,b,c);
and (e,d,b); and (f,b,c);and (g,c,d);
endmodule
Test Bench for Full subtractor

modulefullsub_test();
rega,b,c;
wires,co;
full_suba1(a,b,c,s,co);
initial
begin
a=1'b0;b=1'b0;c=1'b0;#10; a=1'b0;b=1'b0;c=1'b1;#10;
a=1'b0;b=1'b1;c=1'b0;#10; a=1'b0;b=1'b1;c=1'b1;#10;
a=1'b1;b=1'b0;c=1'b0;#10; a=1'b1;b=1'b0;c=1'b1;#10;
a=1'b1;b=1'b1;c=1'b0;#10; a=1'b1;b=1'b1;c=1'b1;#100;
$stop;endendmodule

Functional Simulation Result of Full subtractor:

RTL Schematic of Full subtractor

Inference:
 c. Decoder and Encoder Using Dataflow, Structural, Behavioral Modeling

RTL Code forDecoder:

Behavioral Modeling using case statement:
module decoder2_4 ( din ,dout );
output [3:0] dout ;
reg [3:0] dout ;
input [1:0] din ;
wire [1:0] din ;
always @ (din) begin
case (din)
0 : dout = 8;
1 : dout = 4;
2 : dout = 2;
default : dout = 1;
endcase
end endmodule

Data Flow Modeling

module de2to4(a,b,d0,d1,d2,d3);
output d0,d1,d2,d3;
inputa,b;
wire d0=~a&~b,d1=~a&b,d2=a&~b,d3=a&b;
endmodule

Structural Modeling:

module de2to4(a,b,d0,d1,d2,d3);
output d0,d1,d2,d3;
inputa,b;
wirec,d;
not n1(c,a); not n2(d,b);
and a1 (d0,c,d); and a2(d1,c,b);
and a3 (d2,a,d); and a4(d3,a,b);
endmodule

Test Bench for Decoder

module de2to4_test();
rega,b;
wire d0,d1,d2,d3;
de2to412 d5(a,b,d0,d1,d2,d3);
initial
begin
a=1'b0;b=1'b0;#10; a=1'b0;b=1'b1;#10;
a=1'b1;b=1'b0;#10; a=1'b1;b=1'b1;#100;
$stop;
end
endmodule

Functional Simulation Result of Decoder:

RTL Schematic of Decoder:

Inference:

RTL Code for Encoder:

Behavioral Modelingusing case statement:

module encoder4_2 ( din ,dout
output [1:0] dout ;
reg [1:0] dout ;
input [3:0] din ;
wire [3:0] din ;
always @ (din) begin
case (din)
8 : dout = 0;
4 : dout = 1;
2 : dout = 2;
1 : dout = 3;
default : dout = 1'bZ;
endcase
end endmodule

Data Flow Modeling

module encoder4to2(a,b,d0,d1,d2,d3);
input d0,d1,d2,d3;
outputa,b;
wire a=d3|d2,b=d1|d3;
endmodule

Structural Modeling:
module encoder4to2(a,b,d0,d1,d2,d3);
input d0,d1,d2,d3;
outputa,b;
wirea,b;
or r1(a,d2,d3);or r12(b,d1,d3);
endmodule
Test Bench for Encoder

module de2to4_test();
rega,b;
wire d0,d1,d2,d3;
de2to412 d5(a,b,d0,d1,d2,d3);
initial
begin
a=1'b0;b=1'b0;#10; a=1'b0;b=1'b1;#10;
a=1'b1;b=1'b0;#10; a=1'b1;b=1'b1;#100;
$stop;
end
endmodule

Functional Simulation Result of Encoder:

RTL Schematic of Encoder:

Inference:
 d. Mux and De-Mux Using Dataflow, Structural, Behavioral Modeling

RTL Code for 4:1 Multiplexer using nested if-else construct:

Behavioral Modeling
modulemuxbeh(s0,s1,a,y);
input s0,s1 ;
input [3:0]a;
output y ;
reg y;
wire [3:0]a;
wire s0,s1;
always @ (s0,s1,a)
begin
if(s0==0 && s1==0)
y=a[0];
else if(s0==1 && s1==0)
y=a[1];
else if(s0==0 && s1==1)
y=a[2];
else
y=a[3];
end
endmodule

Data Flow Modeling

module mux4to1(a,b,i0,i1,i2,i3,s);
input a,b,i0,i1,i2,i3;
output s;
wire s=a?(b?i3:i2):(b?i1:i0);
endmodule

Structural Modeling:

module mux4to111(a,b,i0,i1,i2,i3,s);
input a,b,i0,i1,i2,i3;
output s; wire c,d,w1,w2,w3,w4;
not n1(c,a);
not n2(d,b);
and a1(w1,c,d,i0);
and a12(w2,c,b,i1);
and a13(w3,a,d,i2);
and a14(w4,a,b,i3);
or r1(s,w1,w2,w3,w4); endmodule
Test Bench for4:1 Multiplexer
module mux4to1_test();
reg a,b,i0,i1,i2,i3;
wire s;
mux4to1 m1(a,b,i0,i1,i2,i3,s);
initial
begin
i0=1'b0;i1=1'b1;i2=1'b0;i3=1'b1;
a=1'b0;b=1'b0;#10; a=1'b0;b=1'b1;#10;
a=1'b1;b=1'b0;#10; a=1'b1;b=1'b1;#10;
$stop;
end
endmodule
Functional Simulation Result of 4:1Multiplexer:

RTL Schematic of 4:1Multiplexer:

Inference:

RTL Code for 1:4Demultiplexerusing nested if-else construct:

Behavioral Modeling
moduledemuxbeh(s0,s1,a,y);
input s0,s1 ;
input a;
output [3:0]y ;
reg [3:0]y;
always @ (s0,s1,a)
begin
if(s0==0 && s1==0)
begin
y[0]=a;y[1]=0;y[2]=0;y[3]=0;
end
else if(s0==1 && s1==0)
begin
y[0]=0;y[1]=a;y[2]=0;y[3]=0;
end
else if(s0==0 && s1==1)
begin
y[0]=0;y[1]=0;y[2]=a;y[3]=0;
end
else
begin
y[0]=0;y[1]=0;y[2]=0;y[3]=a;
end
end
endmodule

Data Flow Modeling

module demux2to4(a,b,d,d0,d1,d2,d3);
output d0,d1,d2,d3;
inputa,b,d;
wire d0=~a&~b&d,d1=~a&b&d,d2=a&~b&d,d3=a&b&d;
endmodule

Structural Modeling:

module demux2to411(a,b,d,d0,d1,d2,d3);
output d0,d1,d2,d3;
inputa,b,d;
wirex,y;
not n1(x,a); not n2(y,b);
and a1 (d0,x,y,d); and a2(d1,x,d,b);
and a3 (d2,a,y,d); and a4(d3,d,a,b);
endmodule

Test Bench for 1:4Demultiplexer:

module demux2to4_test();
rega,b,d;
wire d0,d1,d2,d3;
demux2to4 d5(a,b,d,d0,d1,d2,d3);
initial
begin
d=1'b1;
a=1'b0;b=1'b0;#10;
a=1'b0;b=1'b1;#10;
a=1'b1;b=1'b0;#10;
a=1'b1;b=1'b1;#100;
$stop;
endendmodule

Fuctional Simulation Result of 1:4 De-Multiplexer:

RTL Schematic of 1:4 De-multiplexer:

Inference:
Exp.No.2 Design and Implementation of Sequential Circuits

Aim:

To design and implement the following combinational circuit using Behavioral modeling,
dataflow modelling.

a. Flip-Flop.
b. Serial in serial out shift register.
c. Parallel in Serial out shift register.

Software Details:
For design Fuctional Simulation Result: ModelSim
For designSynthesis: Quartus II
For design Implementation: Quartus II

a. Flip-Flops Using Behavioral Modeling,dataflow modeling

RTL Code for D-Flip-flop :

Behavioral Modeling:
moduled_ff (d,clk,rst,do);
inputd,clk,rst;
output do;
reg do;
always@(negedgeclk)
begin
if (rst)
do=1'b0;
else do=d; end
endmodule

Test Bench for D-Flip flop :

moduledff_test();
regd,rst,clk;
wire do;
d_ffd12(d,clk,rst,do);
initial
begin
clk=1'b0;
rst=1'b1;
d=1'b0;
end
always
#10 clk=~clk;
initial
begin
#20 rst=1'b0;
#30 d=1'b0;
#20 d=1'b1;
#20 rst=1'b1;
end
initial
#300 $stop;
initial
$monitor($time,"do=%b,d=%b,rst=%b",do,d,rst);
endmodule

Functional Simulation Result of D flip flop:

RTL Schematic of D-flip flop

Inference:

RTL Code for SR-Flip-flop :

Dataflow Modeling:

modulers_ff (r,s,clk,rst,q);
inputs,r,clk,rst;
output q;
reg q;
always@(negedgeclk)
begin
if (rst)
q=1'b0;
else if (r==1'b0 && s==1'b0) q=q;
else if (r==1'b1 && s==1'b0) q=1'b1;
else if (r==1'b0 && s==1'b1) q=1'b0;
else if (r==1'b1 && s==1'b1) q=1'bz;
end
endmodule

Test Bench for SR-Flip flop :

modulesrff_test();
regs,r,clk,rst;
wire q;
rs_ff j1(s,r,clk,rst,q);
initial
begin
clk=1'b0;
rst=1'b1;
s=1'b0;r=1'b1;
end
always
#10 clk=~clk;
initial
begin
#20 rst=1'b0;
#20 s=1'b0;r=1'b1;
#20 s=1'b1;r=1'b1;
#20 s=1'b0;r=1'b0;
#20 s=1'b1;r=1'b0;
#20 rst=1'b1;
end
initial
#300 $stop;
initial
$monitor($time,"s=%b,r=%b,q=%b,rst=%b",s,r,q,rst);
endmodule

Functional Simulation Result of SR flip flop:

RTL Schematic of SR-flip flop

Inference:
 b. 4 bit Serial in Serial out shift registerUsing Behavioral Modeling
RTL Code for SISO register :

Behavioral Modeling:

module siso12(d,clk,rst,do);
inputd,clk,rst;
output do;
wire do,q1,q2;
d_ffd1(d,clk,rst,q1);
d_ffd2(q1,clk,rst,q2);
d_ffd3(q2,clk,rst,do);
endmodule

Test Bench for SISO :

module siso12_test();
regd,rst,clk;
wire do;
siso12 d12(d,clk,rst,do);
initial
begin
clk=1'b0;
rst=1'b1; d=1'b1;
end
always
#10 clk=~clk;
initial
begin
#20 rst=1'b0; #30 d=1'b0;
#30 d=1'b1; #20 d=1'b0; #30 rst=1'b1;
end
initial
#300 $stop;
initial
$monitor($time,"d=%b,do=%b,rst=%b",d,do,rst);
endmodule
Functional Simulation Result of SISO:

RTL Schematic of SISO:

Inference:
 c. 4 bit Parallel in Serial out shift register Using Behavioral Modeling
RTL Code for PISO register :

Behavioral Modeling:

module piso123(clk,rst,load,din,qout);
inputclk,rst,load;
input [0:3]din;
outputqout;
regqout;
reg [0:3]temp;
always@(posedgeclk)
begin
if(rst)
begin
temp=4'b0000;
qout=0;
end
else
begin
if(load)
begin
temp=din;
end
else
begin
qout=temp[3];
temp={1'b0,temp[0:2]};
end
end
end
endmodule

Test Bench for PISO :

module piso123_test();
reg [0:3]din;
regclk,rst,load;
wireqout;
piso123 a1(.clk(clk),.load(load),.rst(rst),.din(din),.qout(qout));
initial
begin
rst=1;
clk=0;
din=4'b0000;
load=1;
end
always
#10 clk=~clk;
always
#50load=~load;
initial
begin
#20 rst=0;din=4'b1010;
#50 din=4'b1101;end
initial
#200 $stop;
initial
begin
$monitor($time,"rst=%b,load=%b,din=%b,qout=%b",rst,load,din,qout);
end
endmodule

Functional Simulation Result of PISO:

RTL Schematic of PISO:

Inference:
Exp.No.3 Design and Implementation of Counter design

Aim:

To design and implement the following combinational circuit using Behavioral Modeling.

a. UP down counter

b. Johnson counter

Software Details:
a. For design Fuctional Simulation Result: ModelSim
b. For designSynthesis: Quartus II
c. For design Implementation: Quartus II

Hardware Details:
a. DE-2 board
b. USB cable

a. 4 bit up down counterUsing Behavioral Modeling

RTL Code for up down counter:

Behavioral Modeling:

module counter (clk,rst,a);

inputclk,rst;
outputreg [3:0]a;
always @(posedgeclk)
begin if (rst)
a=4'b0000;
else if(c=1) a<=a+1;
else a<=a-1;
endendmodule

Test Bench :

modulecounter_tst();
regclk,rst;
wire [3:0]a;
always #5 clk=~clk;
counter c1 (clk,rst,c,a);
initial
begin
clk=1;
rst=1;c=1
#24 c=0;
#50 $stop;
end
endmodule

Functional Simulation Result:

RTL Schematic:

Verification using DE-2 board:

b. 4 Johnson down counterUsing Behavioral Modeling

RTL Code for Johnson counter:

Behavioral Modeling:

modulejohnson_beh(clk,rst,q);
inputclk,rst;
output [0:2]q;
reg [0:2]q;
always @(negedgeclk)
begin
if(rst)
q=3'b010;
else begin q[1]<=q[0];
q[2]<=q[1];
q[0]<=~q[2];
endendendmodule

Test Bench:

modulejohnson_test();
regclk,rst;
wire [0:2]q;
johnson_behr1(clk,rst,q);
initial
begin
clk=1'b0;
rst=1'b1;
end
always #10 clk=~clk;
initial
begin
#20 rst=1'b0;
#100 rst=1'b1;
end
initial
#200 $stop;
initial
$monitor($time,"q=%b,rst=%b",q,rst);
endmodule

Functional Simulation Result:

RTL Schematic:

Verification using DE-2 board:

Exp.No.4 Design of Sequence detector

Aim:

To design sequence detector using FSM.

Software Details:
a. For design Fuctional Simulation Result: ModelSim
b. For designSynthesis: Quartus II

Sequence detector Using FSM

RTL Code for sequence detector:

Behavioral Modeling:
modulefsm(clk,rst,x,z);
inputclk,rst,x;
output z;
reg z;
parameter s0=2'b00;parameter s1=2'b01;
parameter s2=2'b10;parameter s3=2'b11;
reg [1:0]ps,ns;
always @(posedgeclk)
begin
if(rst)
ps<=s0;
elseps<=ns;
end
always@(ps or x)
begin
case(ps)
s0:begin
ns=x?s1:s0;
z=x?0:0;
end
s1:begin
ns=x?s2:s0;
z=x?0:0;
end
s2:begin
ns=x?s2:s3;
z=x?0:0;
end
 s3:begin
ns=x?s1:s0;
z=x?0:1;
end
default:begin
ns=s0;
z=0;
end
endcase
end
endmodule

Test Bench:

modulefsm_test();
regclk,rst,x;
wire z;
fsm f1(clk,rst,x,z);
initial
begin
rst=1'b1;
clk=1'b1;
x=1'b0;
end
always
#5 clk=~clk;
initial
begin
rst=1'b0;
#10 x=1'b1; #10 x=1'b1; #10 x=1'b1; #10 x=1'b0; #10 x=1'b0; #10 x=1'b1;
#10 x=1'b1;#10 x=1'b1;#10 x=1'b0; #10 x=1'b0; #10 x=1'b1; #10 x=1'b0;
end
initial begin
$dumpfile("sequence.vcd");$dumpvars;
end
initial #150 $stop;
initial $monitor($time,"x=%b,z=%b,clk=%b",x,z,clk);
endmodule

Functional Simulation Result:

Inference: