DRV

101
DRV101
DRV
10 1

www.ti.com SBVS008B JANUARY 1998 REVISED MAY 2009

PWM SOLENOID/VALVE DRIVER

FEATURES DESCRIPTION
HIGH OUTPUT DRIVE: 2.3A The DRV101 is a low-side power switch employing a
WIDE SUPPLY RANGE: +9V to +60V pulse-width modulated (PWM) output. Its rugged design
is optimized for driving electromechanical devices such
COMPLETE FUNCTION
PWM Output as valves, solenoids, relays, actuators, and positioners.
Internal 24kHz Oscillator The DRV101 is also ideal for driving thermal devices
Digital Control Input such as heaters and lamps. PWM operation conserves
Adjustable Delay and Duty Cycle power and reduces heat rise, resulting in higher
Over/Under Current Indicator reliability. In addition, adjustable PWM allows fine
control of the power delivered to the load. Time from
FULLY PROTECTED
Thermal Shutdown with Indicator dc output to PWM output is externally adjustable.
Internal Current Limit The DRV101 can be set to provide a strong initial
PACKAGES: 7-Lead TO-220 and 7-Lead closure, automatically switching to a soft hold mode for
Surface-Mount DDPAK power savings. Duty cycle can be controlled by a
resistor, analog voltage, or digital-to-analog converter
for versatility. A flag output indicates thermal shutdown
APPLICATIONS and over/under current limit. A wide supply range
ELECTROMECHANICAL DRIVERS: allows use with a variety of actuators.
Solenoids Positioners The DRV101 is available in a 7-lead staggered
Actuators High Power Relays/Contactors TO-220 package and a 7-lead surface-mount DDPAK
Valves Clutch/Brake plastic power package. It is specified over the extended
FLUID AND GAS FLOW SYSTEMS industrial temperature range of 40C to +85C.
INDUSTRIAL CONTROL
FACTORY AUTOMATION
PART HANDLERS Flag VS (+9V to +60V)
PHOTOGRAPHIC PROCESSING
7 5
ELECTRICAL HEATERS
Load
MOTOR SPEED CONTROL Thermal Shutdown
Over/Under Current
SOLENOID/COIL PROTECTORS 6

MEDICAL ANALYZERS 24kHz Out

Oscillator

Input 1
PWM
On (TTL-Compatible)
Gnd (electrically
Delay connected to
Off 4
tab)
2 3

Delay
Duty Cycle Adjust
Adjust

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright 1998-2009, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

www.ti.com
SPECIFICATIONS
At TC = +25C, VS = +24V, Load = 100 || 1000pF, and 4.99k Flag pullup to +5V, unless otherwise noted.

DRV101T, F

PARAMETER COMMENTS MIN TYP MAX UNITS

OUTPUT
Output Saturation Voltage, Sink IO = 1A +0.8 +1 V
IO = 0.1A +0.2 +0.3 V
Current Limit 1.9 2.3 3 A
Under-Scale Current(1) 23 mA
Leakage Current Output Transistor Off, VS = VO = +60V 0.01 1 mA
DIGITAL CONTROL INPUT(2)
VCTR Low (output disabled) 0 +1.2 V
VCTR High (output enabled) +2.2 +5.5 V
ICTR Low (output disabled) VCTR = 0V 80 A
ICTR High (output enabled) VCTR = +5V 20 A
Propagation Delay On-to-Off and Off-to-On 2 s
DELAY TO PWM(3) dc to PWM Mode
Delay Equation(4) Delay to PWM CD 106 (CD in F) s
Delay Time CD = 0.1F 80 95 110 ms
Minimum Delay Time(5) CD = 0 15 s
DUTY CYCLE ADJUST
Duty Cycle Range 10 to 90 %
Duty Cycle Accuracy 50% Duty Cycle, RPWM = 28.7k 2 5 %
vs Supply Voltage 50% Duty Cycle, VS = VO = +9V to +60V 1 5 %
Nonlinearity(6) 10% to 80% Duty Cycle 2 % FSR
DYNAMIC RESPONSE
Output Voltage Rise Time VO = 10% to 90% of VS 1 2.5 s
Output Voltage Fall Time VO = 90% to 10% of VS 0.1 2.5 s
Oscillator Frequency 19 24 29 kHz
FLAG
Normal Operation 20k Pull-Up to +5V, IO < 1.5A +4 +4.9 V
Fault(7) Sinking 1mA +0.2 +0.8 V
Sink Current VFLAG = 0.4V 2 mA
Under-Current Flag: Set 4 s
Reset 2 s
Over-Current Flag: Set 2 s
Reset 2 s
THERMAL SHUTDOWN
Junction Temperature
Shutdown +165 C
Reset from Shutdown +150 C
POWER SUPPLY
Specified Operating Voltage +24 V
Operating Voltage Range +9 +60 V
Quiescent Current IO = 0 3.5 5 mA
TEMPERATURE RANGE
Specified Range 40 +85 C
Operating Range 55 +125 C
Storage Range 65 +150 C
Thermal Resistance, JC
7-Lead DDPAK, 7-Lead TO-220 3 C/W
Thermal Resistance, JA
7-Lead DDPAK, 7-Lead TO-220 No Heat Sink 65 C/W

NOTES:(1) Under-scale current for TC < 100Csee Under-Scale Current vs Temperature typical performance curve. (2) Logic High enables output (normal
operation). (3) Constant dc output to PWM (pulse-width modulated) time. (4) Maximum delay is determined by an external capacitor. Pulling the Delay Adjust Pin
low corresponds to an infinite (continuous) delay. (5) Connecting the Delay Adjust pin to +5V reduces delay time to 3s. (6) VIN at pin 3 to percent of duty cycle
at pin 6. (7) A fault results from over-temperature, over-current, or under-current conditions.

2
DRV101
www.ti.com SBVS008B
CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage, VS .............................................................................. 60V
Top Front View TO-220, DDPAK
Input Voltage .......................................................................... 0.2V to VS
PWM Adjust Input .................................................................. 0.2V to VS
Delay Adjust Input ................................................ 0.2V to VS (24V max)
7-Lead Operating Temperature Range ...................................... 40C to +125C
Stagger-Formed Storage Temperature Range ......................................... 65C to +150C
TO-220 Junction Temperature .................................................................... +150C
7-Lead
Lead Temperature (soldering, 10s)(2) ........................................... +300C
DDPAK
Surface-Mount NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may de-
grade device reliability. (2) Vapor-phase or IR reflow techniques are recom-
mended for soldering the DRV101F surface-mount package. Wave soldering
is not recommended due to excessive thermal shock and shadowing of
nearby devices.

1 2 3 4 5 6 7 1 2 3 4 5 6 7 ELECTROSTATIC
DISCHARGE SENSITIVITY
In PWM
This integrated circuit can be damaged by ESD. Texas Instruments
VS Flag
recommends that all integrated circuits be handled with appropriate
Delay Gnd Out
In VS
precautions. Failure to observe proper handling and installation
PWM Flag
procedures can cause damage.
Delay Gnd Out
ESD damage can range from subtle performance degradation to
NOTE: Tabs are electrically connected to ground (pin 4). complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Ordering Addendum at the end of this data sheet.

DRV101 3
SBVS008B www.ti.com
PIN DESCRIPTIONS
PIN # NAME DESCRIPTION

Pin 1 Input The input is compatible with standard TTL levels. The device output becomes enabled when the input voltage is driven above
the typical switching threshold, 1.7V. Below this level, the output is disabled. With no connection to the pin, the input level rises
to 3.4V. Input current is 20A when driven high and 80A with the input low. The input may be momentarily driven to the power
supply (VS) without damage.

Pin 2 Delay Adjust This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results
in a delay of approximately 15s, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less
than 3s by tying the pin to 5V. This pin connects internally to a 3A current source from VS and to a 3V threshold comparator.
When the pin voltage is below 3V, the output device is 100% on. The PWM oscillator is not synchronized to the Input (pin 1),
so the first pulse may be extended by any portion of the programmed duty cycle.

Pin 3 Duty Cycle Adjust Internally, this pin connects to the input of a comparator and a 19k resistor to ground. It is driven by a 200A current source
(PWM) from VS. The voltage at this node linearly sets the duty cycle. Duty cycle can be programmed with a resistor, analog voltage,
or output of a D/A converter. The active voltage range is from 0.75V to 3.7V to facilitate the use of single-supply control
electronics. At 0.75V (or RPWM = 3.5k), duty cycle is near 90%. Swing to ground should be limited to no lower than 0.1V. PWM
frequency is a constant 24kHz.

Pin 4 Ground This pin is electrically connected to the package tab. It must be connected to system ground for the DRV101 to function. It
carries the 3.5mA quiescent current plus the load current when the device is on.

Pin 5 VS This is the power supply pin. Operating range is +9V to +60V.

Pin 6 Out The output is the collector of a power npn with the emitter connected to ground. Low power dissipation in the DRV101 is attained
by the low saturation voltage and the fast switching transitions. Fall time is less than 75ns, rise time depends on load
impedance. Base drive to the power device is limited with light loads to control turn-off delay. The response of this circuit causes
the brief dip in saturation voltage after turn on. A flyback diode is needed with inductive loads to conduct the load current during
the off cycle. The external diode should be selected for low forward voltage. The internal clamp diode provides protection but
shouuld not be used to conduct load currents greater than 0.5A.

Pin 7 Flag Normally high (active low), the Flag signals either an over-temperature, over-current, or under-current fault. The over/under-
current flags are true only when the output is on (constant dc output or the on portion of PWM mode). A thermal fault (thermal
shutdown) occurs when the die surface reaches approximately 165C and latches until the die cools to 150C. Its output
requires a pull-up resistor. It can typically sink two milliamps, sufficient to drive a low-current LED.

LOGIC BLOCK DIAGRAM

Flag VS (+9V to +60V)

7 5

Load
Over/Under Current
6

Thermal Out Schottky Power

Shutdown Rectifier

1 PWM
Input
On 4

Delay Gnd
Off

2 3

CD RPWM

4
DRV101
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TYPICAL PERFORMANCE CURVES
At TC = +25C and VS = +24V, unless otherwise noted.

DUTY CYCLE and DUTY CYCLE ERROR vs VOLTAGE DUTY CYCLE vs TEMPERATURE
90 8 100
Load = 1A RPWM = 6.04k
80 6
Duty Cycle 80
70 4

Duty Cycle Error (%)

Duty Cycle (%)

Duty Cycle (%)

60 Error 2 60 RPWM = 30.1k
50 0

40 2 40 RPWM = 100k

RPWM = 301k
30 4
20
20 6 RPWM = 750k

10 8 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 75 50 25 0 25 50 75 100 125
VPWM (V) Temperature (C)

OUTPUT SATURATION VOLTAGE vs TEMPERATURE CURRENT LIMIT vs TEMPERATURE

2.5 2.6
VS = +9V to +60V

2.0 IO = 2A 2.4
Saturation Voltage (V)

Effect of
Current Limit (mA)

Current-Limit
1.5 2.2
IO = 1.5A

1.0 IO = 1A 2.0

IO = 0.5A 1.8
0.5
IO = 0.1A
0 1.6
75 50 25 0 25 50 75 100 125 75 50 25 0 25 50 75 100 125
Temperature (C) Temperature (C)

QUIESCENT CURRENT vs TEMPERATURE UNDER-SCALE CURRENT vs TEMPERATURE

3.9 30
VS = +9V
VS = +60V
25
Under-Scale Current (mA)
Quiescent Current (mA)

3.7 VS = +24V
VS = +24V
20

3.5 15
VS = +9V
Lines represent maximum current
10
before under-current Flag occurs.
3.3 Under-current Flag may not
VS = +60V
5 occur for case temperature
above 100C.
3.1 0
75 50 25 0 25 50 75 100 125 75 50 25 0 25 50 75 100 125
Temperature (C) Temperature (C)

DRV101 5
SBVS008B www.ti.com
TYPICAL PERFORMANCE CURVES (CONT)
At TC = +25C and VS = +24V, unless otherwise noted.

FLAG OPERATION FLAG OPERATION

OVER-CURRENT LIMIT UNDER-CURRENT
(VS = +60V, CD = 110pF, RPWM = 750k) (VS = +24V, CD = 110pF, RPWM = 6.04k)

60V 4V
VOUT

Onset of No Load

VIN
40V 2V
current limit
20V 0
Flag only on during constant output
0 or ON portion of PWM mode
Flag only set
4V during constant 4V
output mode or

VFLAG
VFLAG

2V ON portion of 2V
PWM mode
0 0
Constant Output PWM Mode

25s/div 50s/div

DC TO PWM MODE
DRIVING INDUCTIVE LOAD DUTY CYCLE UNDERSHOOT
(VS = +60V, CD = 110pF, RPWM = 301k) Load = 1A
30V

60V 20V
VOUT
VOUT

40V 10V
Non-optimized Layout
20V 0

0V 30V
See Duty Cycle Undershoot
2A curve for detail 20V
VOUT

1A 10V Clean Layout

IGND

0 0
Inductive load ramp current

1s/div
50s/div

TYPICAL SOLENOID CURRENT WAVEFORM

(VS = +24V) OSCILLATOR FREQUENCY vs TEMPERATURE
24.2
Oscillator Frequency (kHz)

24.0
Solenoid
VS = +9V
1A Motion
Period
{

23.8

0.5A

PWM Mode 23.6

0 VS = +60V
Solenoid Closure
23.4
25ms/div 75 55 35 15 5 25 45 65 85 105 125
Temperature (C)

6
DRV101
www.ti.com SBVS008B
TYPICAL PERFORMANCE CURVES (CONT)
At TC = +25C and VS = +24V, unless otherwise noted.

MINIMUM DELAY TO PWM vs TEMPERATURE NOMINAL DELAY TIME TO PWM vs TEMPERATURE

22 104
No connection to CD = 0.1F
21 Delay Adjust pin 102
(CD = 0)
20 VS = +9V 100 V
VSS == +24V
+24V

19 98
Delay (s)

Delay (ms)
18 96 VS = +60V

17 94
VS = +60V
16 VS = +24V 92

15 90 VS = +9V

14 88
75 50 25 0 25 50 75 100 125 75 50 25 0 25 50 75 100 125
Temperature (C) Temperature (C)

DRV101 7
SBVS008B www.ti.com
BASIC OPERATION
The DRV101 is a low-side, bipolar power switch employing
a pulse-width modulated (PWM) output for driving electro-
mechanical and thermal devices. Its design is optimized for
two types of applications; a two-state driver (open/close) for
loads such as solenoids and actuators, and a linear driver for
valves, positioners, heaters, and lamps. Its wide supply
range, adjustable delay to PWM mode, and adjustable duty
cycle make it suitable for a wide range of applications.
Figure 1 shows the basic circuit connections to operate the
DRV101. A 0.1F bypass capacitor is shown connected to
the power supply pin.
The Input (pin 1) is compatible with standard TTL levels.
Input voltages between +2.2V and +5.5V turn the device
output on, while pulling the pin low (0V to +1.2V), shuts the
DRV101 output off. Input current is typically 80A.
Delay Adjust (pin 2) and Duty Cycle Adjust (pin 3) allow
external adjustment of the PWM output signal. The Delay
Adjust pin can be left floating for minimum delay to PWM
mode (typically 15s) or a capacitor can be used to set the
delay time. Duty cycle of the PWM output can be controlled
by a resistor, analog voltage, or D/A converter. Figure 1b
provides an example timing diagram with the Delay Adjust
pin connected to 0.1F and duty cycle set for 25%. See the
Delay Adjust and Duty Cycle Adjust text for equations
and further explanation.
Ground (pin 4) is electrically connected to the package tab.
This pin must be connected to system ground for the
DRV101 to function. This serves as the load current path to
ground, as well as the DRV101 reference ground.
The load (solenoid, valve, etc.) is connected between the
supply (pin 5) and output (pin 6). For an inductive load, an
external diode across the output is required as shown in
Figure 1a. The diode serves to maintain the hold force during
PWM operation. For remotely located loads, the external
diode should be placed close to the DRV101 (Figure 1a). The
internal clamp diode between the output and ground should
not be used to carry load current.
The Flag (pin 7) provides fault status for under-current,
over-current, and thermal shutdown conditions. This pin is
active low with pin voltage typically +0.3V during a fault
condition. A small value capacitor may be needed between
Flag and ground for noisy applications.

Basic Circuit Connections

VS

0.1F

Flag

7 5
(1)

Load
Thermal Shutdown
Over/Under Current 6

24kHz Out
(a) Oscillator

Input 1
PWM
(TTL-Compatible)
Gnd (electrically
Delay
connected to
On 4
tab)
Off 2 3

CD Delay Duty Cycle Adjust

RPWM
Adjust

NOTE: (1) External flyback diode required for inductive loads to conduct load current during the off cycle.
For remotely located loads, diode should be placed close to the DRV101.
Motorola MSRS1100T3 (1A, 100V), MBRS360T3 (3A, 60V)

Simplified Timing Diagram

CD = 0.1F (95ms constant dc output before PWM)
RPWM = 130k

+2.2V to +5.5V
INPUT
0V to +1.2V
(b)
VS CD = 0.1F
OUTPUT 95ms
0 RPWM = 130k
tON
tON 10.4s

tP tP 41.6s (1/24kHz)
t
Duty Cycle = ON = 25%
tP
Initial dc Output PWM Mode
(set by value (resistor or voltage
of CD) controlled)

FIGURE 1. Basic Circuit Connections and Timing Diagram.

8
DRV101
www.ti.com SBVS008B
APPLICATIONS INFORMATION ADJUSTABLE DUTY CYCLE
The DRV101s externally adjustable duty cycle provides an
POWER SUPPLY accurate means of controlling power delivered to the load.
The DRV101 operates from a single +9V to +60V supply Duty cycle can be set from 10% to 100% with an external
with excellent performance. Most behavior remains un- resistor, analog voltage, or the output of a D/A converter.
changed throughout the full operating voltage range. Param- Reduced duty cycle results in reduced power dissipation.
eters which vary significantly with operating voltage are This keeps the DRV101 and load cooler, resulting in in-
shown in the Typical Performance Curves. creased reliability for both devices. PWM frequency is a
constant 24kHz.
ADJUSTABLE INITIAL 100% DUTY CYCLE Resistor Controlled Duty Cycle
A unique feature of the DRV101 is its ability to provide an Duty cycle is easily programmed with a resistor (RPWM)
initial constant dc output (100% duty cycle) and then switch connected between the Duty Cycle Adjust pin and ground.
to PWM mode to save power. This function is particularly Increased resistor values correspond to decreased duty cycles.
Table II provides resistor values for typical duty cycles.
useful when driving solenoids which have a much higher
Resistor values for additional duty cycles can be obtained
pull-in current requirement than hold requirement.
from Figure 3. For reference purposes, the equation for
The duration of this constant dc output (before PWM output calculating RPWM is included in Figure 3.
begins) can be externally controlled with a capacitor con-
nected from Delay Adjust (pin 2) to ground according to the
RESISTOR(1) VOLTAGE(2)
following equation: DUTY CYCLE RPWM (k) VPWM (V)
Delay Time CD 106 10 976 3.7
20 205 3.4
(time in seconds, CD in Farads) 30 84.5 3.0
40 46.4 2.6
Leaving the Delay Adjust pin open results in a constant 50 28.7 2.2
output time of approximately 15s. The duration of this 60 18.2 1.75
70 11.8 1.35
initial output can be reduced to less than 3s by connecting 80 7.50 1.00
the pin to 5V. Table I provides examples of desired delay 90 4.87 0.75
times (constant output before PWM mode) and the appropri- NOTES: (1) Resistor values listed are nearest 1% standard values. (2) Do not
ate capacitor values or pin connection. drive pin below 0.1V. For additional values, see Duty Cycle vs Voltage typical
performance curve.

CONSTANT OUTPUT DURATION CD TABLE II. Duty Cycle Adjust. TA= +25C, VS = +24V.
3s Pin connected to 5V
15s Pin open
100s 100pF 1000
1ms 1nF
100ms 0.1F

TABLE I. Delay Adjust Pin Connections.

100
RPWM (k)

The internal Delay Adjust circuitry is composed of a 3A

current source and a 3V comparator as shown in Figure 2.
Thus, when the pin voltage is less than 3V, the output device 10
is 100% on (dc output mode).

1
10 20 40 60 80 100
Duty Cycle (%)
DRV101

VS 3V Reference
RPWM = [ a + b (DC) + c (DC)2 + d (DC)3 + e (DC)4]1

Comparator where: a = 2.4711 x 106 d = 7.6427 x 1010

3A b = 5.2095 x 107 e = 6.8039 x 1012
c = 4.4576 x 108
DC = duty cycle in %

2 For 50% duty cycle:

RPWM = [2.4711 x 106 + (5.2095 x 107) (50) + (4.4576 x 108) (50)2
Delay Adjust CD + (7.6427 x 1010) (50)3 + (6.8039 x 1012) (50)4]1
= 28.7k

FIGURE 2. Simplified Circuit Model of the Delay Adjust Pin. FIGURE 3. RPWM vs Duty Cycle.

DRV101 9
SBVS008B www.ti.com
Voltage Controlled Duty Cycle
Duty cycle can also be programmed with an analog voltage,
VPWM. With VPWM 0.75V, duty cycle is near 90%. Increas-
ing this voltage results in decreased duty cycles. Table II
provides VPWM values for typical duty cycles. See the Duty
Cycle vs Voltage Typical Performance Curve for addi-
tional duty cycles.
The Duty Cycle Adjust pin should not be driven below 0.1V.
If the voltage source used can go between 0.1V and ground,
a series resistor between the voltage source and the Duty
Cycle Adjust pin (Figure 4) is required to limit swing. If the
pin is driven below 0.1V, the output will be unpredictable.
VS
STATUS FLAG
Flag (pin 7) provides fault indication for under-current,
over-current, and thermal shutdown conditions. During a
fault condition, Flag output is driven low (pin voltage
typically drops to 0.3V). A pull-up resistor, as shown in
Figure 6, is required to interface with standard logic. A small
value capacitor may be needed between Flag and ground in
noisy applications.
Figure 6 gives an example of a non-latching fault monitoring
circuit, while Figure 7 provides a latching version. The Flag
pin can sink several milliamps, sufficent to drive external
logic circuitry or an LED (Figure 8) to indicate when a fault
has occurred. In addition, the Flag pin can be used to turn off
other DRV101s in a system for chain fault protection.

5
DRV101
6 +5V
Out

5k
TTL or HCT
Pull-Up
PWM 4

VPWM 3 Flag 7
D/A
Converter
(or analog Thermal Shutdown
1k(1) voltage) Over/Under Current 6
Out
NOTE: (1) Required if voltage source can go below 0.1V.

FIGURE 4. Using a Voltage to Program Duty Cycle. 4

DRV101

The DRV101s internal 24kHz oscillator sets the PWM

period. This frequency is not externally adjustable. Duty
FIGURE 6. Non-Latching Fault Monitoring Circuit.
Cycle Adjust (pin 3) is internally driven by a 200A current
source and connects to the input of a comparator and a 19k
resistor as shown in Figure 5. The DRV101s PWM control
design is inherently monotonic. That is, a decreased voltage +5V

(or resistor value) always produces an increased duty cycle.

74XX76A
VS
Flag Q J 20k
3.8V
Flag Q
f = 24kHz
Flag Reset CLR CLK
(1)
0.7V
GND K
VS

Comparator
200A
Flag 7

19k Thermal Shutdown

6
Over/Under Current Out
DRV101
3
4
Resistor or DRV101
Duty Cycle Voltage Source(1)
Adjust
NOTE: (1) Small capacitor (10pF) may be required in noisy environments.
NOTE: (1) Do not drive pin below 0.1V.

FIGURE 5. Simplified Circuit Model of the Duty Cycle FIGURE 7. Latching Fault Monitoring Circuit.
Adjust Pin.

10
DRV101
www.ti.com SBVS008B
 An under-current fault occurs when the output current is
below the under-scale current threshold (typically 23mA).
+5V For example, this function indicates when the load is discon-
nected. Again, the flag output is not latched, so an under-
current condition during PWM mode will produce a flag
5k
output that is modulated by the PWM waveform. An initial,
(LED)
HLMP-Q156 brief under-current flag normally appears driving inductive
loads and may be avoided by adding a parallel resistor
Flag 7 sufficient to move the initial current above the under-current
threshold. An under-current flag may not appear for case
Thermal Shutdown
6
temperatures above 100C. Avoid adding capacitance to pin
Over/Under Current Out 6 (Out) as it may cause momentary current limiting.

4 Over-Temperature Fault
DRV101
FIGURE 8. LED to Indicate Fault Condition.
Over/Under Current Fault
An over-current fault occurs when the output current is
greater than approximately 2.3A. The status flag is not
latched. Since current during PWM mode is switched on and
off, the flag output will be modulated with PWM timing (see
flag waveforms in the Typical Performance Curves).
A thermal fault occurs when the die reaches approximately
165C, producing a similar effect as pulling the input low.
Internal shutdown circuitry disables the output and resets the
Delay Adjust pin. The Flag is latched in the low state (fault
condition) until the die has cooled to approximately 150C.
A thermal fault can occur in any mode of operation. Recov-
ery from thermal fault will start in delay mode (constant dc
output).
PACKAGE MOUNTING
Figure 9 provides recommended PCB layouts for both the
TO-220 and DDPAK power packages. The tab of both
packages is electrically connected to ground (pin 4). It may
be desirable to isolate the tab of TO-220 package from its
mounting surface with a mica (or other film) insulator (see

7-Lead TO-220 7-Lead DDPAK(1)

KVT Package(2) KTW Package(2)
0.51
0.45
0.335

0.15

0.085

0.04
0.05
0.2

0.035
0.05
0.105

Mean dimensions in inches. Refer to end of data sheet NOTES: (1) For improved thermal performance increase footprint area.
for tolerances and detailed package drawings. See Figure 11, Thermal Resistance vs Circuit Board Copper Area.
(2) Refer to the mechanical drawings at the end of this document.

FIGURE 9. TO-220 and DDPAK Solder Footprints.

DRV101 11
SBVS008B www.ti.com
 THERMAL RESISTANCE
vs ALUMINUM PLATE AREA
18 Aluminum Plate Area
Vertically Mounted
Flat, Rectangular

Thermal Resistance JA (C/W)

in Free Air
16 Aluminum Plate

14
0.030in Al

12

0.050in Al
10
Aluminum
Plate Thickness 0.062in Al
8 Optional mica or film insulator
0 1 2 3 4 5 6 7 8 for electrical isolation. Adds DRV101
Aluminum Plate Area (inches2) approximately 1C/W. TO-220 Package

FIGURE 10. TO-220 Thermal Resistance vs Aluminum Plate Area.

THERMAL RESISTANCE vs
CIRCUIT BOARD COPPER AREA
50
DRV101 Circuit Board Copper Area
Thermal Resistance, JA (C/W)

DDPAK
40
Surface-Mount Package
1oz. copper
30

20

10

0 DRV101
0 1 2 3 4 5 DDPAK
Copper Area (inches2) Surface-Mount Package

FIGURE 11. DDPAK Thermal Resistance vs Circuit Board Copper Area.

Figure 10). For lowest overall thermal resistance, it is best to protection circuitry disables the output when the junction
isolate the entire heat sink/DRV101 structure from the temperature reaches approximately +165C, allowing the
mounting surface rather than to use an insulator between the device to cool. When the junction temperature cools to
semiconductor and heat sink. approximately +150C, the output circuitry is again enabled.
For best thermal performance, the tab of the DDPAK sur- Depending on load and signal conditions, the thermal protec-
face-mount version should be soldered directly to a circuit tion circuit may cycle on and off. This limits the dissipation
board copper area. Increasing the copper area improves heat of the amplifier but may have an undesirable effect on the
dissipation. Figure 11 shows typical thermal resistance from load.
junction-to-ambient as a function of the copper area. Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an inadequate heat
POWER DISSIPATION sink. For reliable operation, junction temperature should be
limited to +125C, maximum. To estimate the margin of
Power dissipation depends on power supply, signal, and load safety in a complete design (including heat sink), increase
conditions. Power dissipation is equal to the product of the ambient temperature until the thermal protection is
output current times the voltage across the conducting out- triggered. Use worst-case load and signal conditions. For
put transistor times the duty cycle. Power dissipation can be good reliability, thermal protection should trigger more than
minimized by using the lowest possible duty cycle necessary 40C above the maximum expected ambient condition of
to assure the required hold force. your application. This produces a junction temperature of
Application Bulletin AB-039 explains how to calculate or 125C at the maximum expected ambient condition.
measure power dissipation with unusual signals and loads.
The internal protection circuitry of the DRV101 was de-
signed to protect against overload conditions. It was not
THERMAL PROTECTION intended to replace proper heat sinking. Continuously run-
Power dissipated in the DRV101 will cause the junction ning the DRV101 into thermal shutdown will degrade reli-
temperature to rise. The DRV101 has thermal shutdown ability.
circuitry that protects the device from damage. The thermal

12
DRV101
www.ti.com SBVS008B
HEAT SINKING Heat Sink Selection Example
Most applications will not require a heat sink to assure that A TO-220 package is dissipating 5 Watts. The maximum
the maximum operating junction temperature (125C) is not expected ambient temperature is 35C. Find the proper heat
exceeded. However, junction temperature should be kept as sink to keep the junction temperature below 125C.
low as possible for increased reliability. Junction tempera- Combining Equations 1 and 2 gives:
ture can be determined according to the equation:
TJ = TA + PD(JC + CH + HA) (3)
TJ = TA + PDJA (1)
TJ, TA, and PD are given. JC is provided in the specification
where, JA = JC + CH + HA (2) table, 3C/W. CH can be obtained from the heat sink
TJ = Junction Temperature (C) manufacturer. Its value depends on heat sink size, area, and
TA = Ambient Temperature (C) material used. Semiconductor package type, mounting screw
PD = Power Dissipated (W) torque, insulating material used (if any), and thermal
joint compound used (if any) also affect CH. A typical CH
JC = Junction-to-Case Thermal Resistance (C/W)
for a TO-220 mounted package is 1C/W. Now we can solve
CH = Case-to-Heat Sink Thermal Resistance (C/W) for HA:
HA = Heat Sink-to-Ambient Thermal Resistance (C/W)
JA = Junction-to-Air Thermal Resistance (C/W) HA =
TJ TA
( JC + CH ) (4)
Figure 12 shows maximum power dissipation versus ambi- PD
125 C 35 C
ent temperature with and without the use of a heat sink. HA = (3 C/ W + 1 C/ W ) = 14 C/ W
Using a heat sink significantly increases the maximum 5W
power dissipation at a given ambient temperature as shown.
To maintain junction temperature below 125C, the heat
sink selected must have a HA less than 14C/W. In other
words, the heat sink temperature rise above ambient must be
MAXIMUM POWER DISSIPATION less than 70C (14C/W x 5W). For example, at 5 Watts
vs AMBIENT TEMPERATURE
10 Thermalloy model number 6030B has a heat sink
TO-220 with Thermalloy
PD = (TJ (max) TA) / JA temperature rise of 66C above ambient (HA = 66C/5W =
6030B Heat Sink TJ (max) = 125C
8 JA = 16.7C/W
13.2C/W), which is below the 70C required in this ex-
Power Dissipation (Watts)

With infinite heat sink

ample. Figure 12 shows power dissipation versus ambient
6
( JA = 3C/W), temperature for a TO-220 package with a 6030B heat sink.
max PD = 33W
DDPAK at TA = 25C Another variable to consider is natural convection versus
JA = 26C/W
4 (3 in2 one oz
forced convection air flow. Forced-air cooling by a small fan
copper mounting pad) can lower CA (CH + HA) dramatically. Heat sink manufac-
2 turers provide thermal data for both of these cases. For
DDPAK or TO-220 additional information on determining heat sink require-
JA = 65C/W (no heat sink) ments, consult Application Bulletin AB-038.
0
0 25 50 75 100 125 As mentioned earlier, once a heat sink has been selected, the
Ambient Temperature (C) complete design should be tested under worst-case load and
signal conditions to ensure proper thermal protection.

FIGURE 12. Maximum Power Dissipation vs Ambient

Temperature.

The difficulty in selecting the heat sink required lies in

determining the power dissipated by the DRV101. For dc
output into a purely resistive load, power dissipation is simply
the load current times the voltage developed across the
conducting output transistor times the duty cycle. Other loads
are not as simple. Consult Application Bulletin AB-039 for
further insight on calculating power dissipation. Once power
dissipation for an application is known, the proper heat sink
can be selected.

DRV101 13
SBVS008B www.ti.com
APPLICATION CIRCUITS

+5V Pinch Valve

Flexible Tube
5k
Flag VS (+9V to +60V)

Plunger
7 5

Thermal Shutdown
Over/Under Current Solenoid Coil
6
Out
24kHz
Oscillator
Microprocessor Can drive most types
TTL Control Input 1
PWM of solenoid-actuated
Gnd valves and actuators
On Delay 4
Off DRV101
2 3

Delay Duty Cycle Adjust(1)

CD RPWM NOTE: (1) Duty cycle can be programmed by
Adjust (10% to 100%)
a resistor, analog voltage, or D/A converter.
Do not drive below 0.1V.

FIGURE 13. Fluid Flow Control System.

VS

VS

Brighter light results in

5
increased duty cycle (1)
Coil
5 DRV101
Lamp 6
DRV101
6 Input 1
(On/Off)
On/Off 4
4
3

100
Aimed at Cadmium Sulfide
ambient Optical Detector
(Clairex CL70SHL
Duty Cycle Adjust
light
or CLSP5M) 4-20mA 187

10k

NOTE: (1) Rectifier diode required for inductive

loads to conduct load current during the off cycle.

FIGURE 14. Instrument Light Dimmer Circuit. FIGURE 15. 4-20mA Input to PWM Output.

14
DRV101
www.ti.com SBVS008B
 Higher temperature results in lower duty cycle

(a) VS
Heating Element

5 Thermistor

DRV101

6
1
On/Off R1

4
R2

Duty Cycle 3
Adjust

10F
(b) VS
0.1F
REF200
7, 8

5 Heating 100A 100A

Element
DRV101
6

1 1 2
On/Off
4

2 3
2F Film
NC

0.1F VS

7 10M
2
1k
Duty Cycle 6
OPA134
Adjust 3

4 Temperature
10k Control
4.7V

or
Thermistor IN4148(1)
5k at +25C

Integrator improves accuracy

NOTE: (1) Or any common silicon diode suited

20k
to the mechanical mounting requirements.

FIGURE 16. Temperature Controller.

DRV101 15
SBVS008B www.ti.com
 +12V

dc Tachometer Coupled to Motor

5
DRV101
M T
6

Input 1
(On/Off)
4

3 Duty Cycle

Speed Control(1)
R1 R2

NOTE: (1) Select R1/R2 ratio based on tachometer output voltage.

FIGURE 17. Constant Speed Motor Control.

+40V

5 DC
M Motor
6
Open circuit will
provide 3.4V DRV101
on signal 1
4

2 3 Duty Cycle
Speed Control Input 40k Adjust
Delay Adjust
0V to +10V
+15V

0.5F
1k
+15V
22k 470k

1nF 100k Frequency In

One-Shot VOUT
47k
2N2222 10k

AC
Tachometer
T
VFC32
Coupled to Motor
5nF
15V NP0

FIGURE 18. DC Motor Speed Control Using AC Tachometer.

16
DRV101
www.ti.com SBVS008B
 Only one DRV101 is turned
on at sequence time
Phase 2
Stepper DRV101
Logic In

+VS
M

Phase 1
Stepper DRV101
Logic In Phase 3
DRV101 Stepper
Logic In

FIGURE 19. Three-Phase Stepper Motor Driver Provides High-Stepping Torque.

VS

5
Lamp
DRV101
VS = +9V to +60V
6
R1
1

R2 4

3
Select R1 and R2 to divide R3 C1
down VS to 5.5V max. 4.87k 20F
For example: with VS = 60V Duty Cycle Adjust
R1 = 11k, R2 = 1k +
after soft start
1k 4.3V R4
VIN = 60V = 5V
1k + 11k Sets start-up DIN5229 4.87k
duty cycle

FIGURE 20. Soft-Start Circuit for Incandescent Lamps and Other Sensitive Loads.

DRV101 17
SBVS008B www.ti.com
 +12V

5 20
DRV101 (10W)
P-Channel
6
MOSFET
IRF4905

12V
Load
4 70A

FIGURE 21. High Power, High-Side Driver.

+12V

12 12V
1.4k Load 50A
5 (20W)
1 DRV101
N-Channel
6
MOSFET
1k Out IRFZ48N

2 3

CD(1) RPWM(2)

NOTES: (1) CD controls OFF time (turn-on delay). (2) Duty cycle is inverted.

FIGURE 22. High Power, Time Delay, Low-Side Driver.

+12V VS

480V
Load
27A
120
750
(2W) 2N3725A
5 N-Channel
IGBT
DRV101 IRGPC50F
6 MPSA56
2N3725A

NOTE: Duty cycle is inverted. For example, to achieve 25% duty cycle, program 75%.

FIGURE 23. Very High Power, Low-Side Driver.

18
DRV101
www.ti.com SBVS008B
 +170V

0.1F
2.7k 200
5
2N3725A
DRV101 P-Channel
6
1 6 MOSFET
+5V IRF9640
+ MPSA56
1
DCP010512 12V 0.1F
Control
2k
4
Load
2 5 In

2 3
4N32
Optocoupler
CD RPWM

FIGURE 24. Isolated High-Side Driver.

DRV101 19
SBVS008B www.ti.com
 Revision History

DATE REVISION PAGE SECTION DESCRIPTION

1 Front Page Updated front page appearance.
5/09 B
11 Package Mounting Changed Figure 9 to show TI package designator.

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

20
DRV101
www.ti.com SBVS008B
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Mar-2017

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

DRV101F/500 ACTIVE DDPAK/ KTW 7 500 Green (RoHS CU SN Level-2-260C-1 YEAR DRV101F
TO-263 & no Sb/Br)
DRV101FKTWT ACTIVE DDPAK/ KTW 7 250 Green (RoHS CU SN Level-3-245C-168 HR DRV101F
TO-263 & no Sb/Br)
DRV101FKTWTG3 ACTIVE DDPAK/ KTW 7 250 Green (RoHS CU SN Level-3-245C-168 HR DRV101F
TO-263 & no Sb/Br)
DRV101T ACTIVE TO-220 KVT 7 50 Green (RoHS CU SN N / A for Pkg Type DRV101T
& no Sb/Br)
DRV101TG3 ACTIVE TO-220 KVT 7 50 Green (RoHS CU SN N / A for Pkg Type DRV101T
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Mar-2017

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Nov-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV101F/500 DDPAK/ KTW 7 500 330.0 24.4 10.95 16.5 5.15 16.0 24.0 Q2
TO-263
DRV101FKTWT DDPAK/ KTW 7 250 330.0 24.4 10.6 15.6 4.9 16.0 24.0 Q2
TO-263

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Nov-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV101F/500 DDPAK/TO-263 KTW 7 500 346.0 346.0 41.0
DRV101FKTWT DDPAK/TO-263 KTW 7 250 367.0 367.0 45.0

Pack Materials-Page 2
 MECHANICAL DATA

MPSF015 AUGUST 2001

KTW (R-PSFM-G7) PLASTIC FLANGE-MOUNT

0.410 (10,41) 0.304 (7,72)

A
0.385 (9,78) 0.006 0.296 (7,52)
B
0.303 (7,70) 0.300 (7,62)
0.0625 (1,587) H 0.297 (7,54) 0.055 (1,40) 0.252 (6,40)
0.064 (1,63)
0.0585 (1,485) 0.045 (1,14)
0.056 (1,42)

0.370 (9,40) 0.187 (4,75)

0.330 (8,38) 0.179 (4,55)
H A
0.605 (15,37)
0.595 (15,11)
0.012 (0,305)
C 0.000 (0,00)
0.104 (2,64)
0.019 (0,48) 0.096 (2,44) H
0.017 (0,43)

0.050 (1,27) 0.026 (0,66)

C
0.034 (0,86) 0.014 (0,36)
0~3
C F 0.022 (0,57)
0.010 (0,25) M B AM C M

0.183 (4,65)
0.170 (4,32)

4201284/A 08/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Lead width and height dimensions apply to the
plated lead.
D. Leads are not allowed above the Datum B.
E. Standoff height is measured from lead tip
with reference to Datum B.
F. Lead width dimension does not include dambar
protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum
dimension by more than 0.003.
G. Crosshatch indicates exposed metal surface.
H. Falls within JEDEC MO169 with the exception
of the dimensions indicated.

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