Lecture #23

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OUTLINE
MOSFET ID vs. VGS characteristic
Circuit models for the MOSFET
resistive switch model
small-signal model

Reference Reading
Rabaey et al.: Chapter 3.3.2
Howe & Sodini: Chapter 4.5

EECS40, Fall 2003 Lecture 23, Slide 1 Prof. King

MOSFET ID vs. VGS Characteristic

Typically, VDS is fixed when ID is plotted as a function of VGS
Long-channel MOSFET Short-channel MOSFET
VDS = 2.5 V > VDSAT VDS = 2.5 V > VDSAT

EECS40, Fall 2003 Lecture 23, Slide 2 Prof. King

1
 MOSFET VT Measurement
VT can be determined by plotting ID vs. VGS,
using a low value of VDS :

W VDS
I D = k n V
GS V VDS
2
ID (A) T
L

VGS (V)
0 VT

EECS40, Fall 2003 Lecture 23, Slide 3 Prof. King

Subthreshold Conduction (Leakage Current)

The transition from the ON state to the OFF state
is gradual. This can be seen more clearly when
ID is plotted on a logarithmic scale:

VDS > 0
In the subthreshold
(VGS < VT) region,

qV
I D exp GS
nkT
This is essentially the channel-
source pn junction current.
(Some electrons diffuse from the
source into the channel, if this
pn junction is forward biased.)
EECS40, Fall 2003 Lecture 23, Slide 4 Prof. King

2
Qualitative Explanation for Subthreshold Leakage
The channel Vc (at the Si surface) is capacitively
coupled to the gate voltage VG:
DEVICE CIRCUIT MODEL Using the capacitive
voltage divider formula
VG VG (Lecture 12, Slide 7):
VD Cox
n+ poly-Si Vc = VG
Cox Cox + Cdep
n+ n+ +
Cdep The forward bias on
depletion Wdep the channel-source pn
region p-type Si Vc
junction increases with
VG scaled by the factor
Cox / (Cox+Cdep)
Si 1 Cox + Cdep Cdep
C dep = n= = 1+
W dep NA Cox Cox
EECS40, Fall 2003 Lecture 23, Slide 5 Prof. King

Slope Factor (or Subthreshold Swing) S

S is defined to be the inverse slope of the log (ID)
vs. VGS characteristic in the subthreshold region:

VDS > 0 kT
S n ln(10)
q
Units: Volts per decade
1/S is the slope
Note that S 60 mV/dec
at room temperature:
kT
ln(10) = 60 mV
q
EECS40, Fall 2003 Lecture 23, Slide 6 Prof. King

3
 VT Design Trade-Off
(Important consideration for digital-circuit applications)
Low VT is desirable for high ON current
IDSAT (VDD - VT) 1<<2
where VDD is the power-supply voltage

but high VT is needed for low OFF current

log IDS
Low VT

High VT
IOFF,low VT

IOFF,high VT
0 VGS
EECS40, Fall 2003 Lecture 23, Slide 7 Prof. King

The MOSFET as a Resistive Switch

For digital circuit applications, the MOSFET is
either OFF (VGS < VT) or ON (VGS = VDD). Thus,
we only need to consider two ID vs. VDS curves:
1. the curve for VGS < VT
2. the curve for VGS = VDD

ID
VGS = VDD (closed switch)
Req

VDS
VGS < VT (open switch)

EECS40, Fall 2003 Lecture 23, Slide 8 Prof. King

4
 Equivalent Resistance Req
In a digital circuit, an n-channel MOSFET in the
ON state is typically used to discharge a
capacitor connected to its drain terminal:
gate voltage VG = VDD
source voltage VS = 0 V
drain voltage VD initially at VDD, discharging toward 0 V
The value of Req should be
set to the value which gives
the correct propagation
Cload
delay (time required for
output to fall to VDD):
3 VDD 5
k n W Req 1 nVDD
I DSATn = (VDD VTn )2 4 I DSATn 6
2 L
EECS40, Fall 2003 Lecture 23, Slide 9 Prof. King

Typical MOSFET Parameter Values

For a given MOSFET fabrication process
technology, the following parameters are known:
VT (~0.5 V)
Cox and k (<0.001 A/V2)
VDSAT ( 1 V)
( 0.1 V-1)

Example Req values for 0.25 m technology (W = L):

How can Req be decreased?

EECS40, Fall 2003 Lecture 23, Slide 10 Prof. King

5
 MOSFET Model for Analog Circuits
For analog circuit applications, the MOSFET is
biased in the saturation region, and the circuit is
designed to process incremental signals.
A DC operating point is established by the bias
voltages VBIAS and VDD, such that VDS > VGS VT
Incremental voltages vs and vds that are much smaller
in magnitude perturb the operating point
The MOSFET small-signal model is a circuit which
models the change in the drain current (id) in
response to these perturbations
vs ID + id RD
+
G D
+
VBIAS + MOSFET VDS + vds
+ VDD

S S
EECS40, Fall 2003 Lecture 23, Slide 11 Prof. King

NMOSFET Small-Signal Model

G D
+ id +

vgs gmvgs ro vds

S S
iD i
id = v gs + D vds = g m v gs + g o vds
vGS vDS
iD W
gm k (VGS VT ) transconductance
vGS L
iD
go I D output conductance
vDS
EECS40, Fall 2003 Lecture 23, Slide 12 Prof. King