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Enrique Maset (l), Enrique Dede Guichao Hua (2)1 Fred C. Lee (21
Abstract: The power factor correction has power factor (0.5-0.6) and high total harmonic
been becoming an important topic in power distortion (THD).
electronics field in the recent years. The
classical boost single-phase Power Factor The high power factor preregulator
Correction (PFC) scheme have a serious described in this paper are interposed between
problem, while running under CCM operation, the input rectifier bridge and the bulk filter
the diode reverse recovery problem causing capacitor. Switching at a frequency much
significant losses when the output voltage is higher than the line, the preregulator is
quite high. This not only decreases the total programmed to draw a half-sinusoid input
efficiency, but also create thermal and noise current, in phase with the line voltage,
problems. To solve this problem, the zero- therefore the improvements are:
voltage transition (ZVT) technique has been
developed recently, which allow the use of d High input Power Factor: 0.95 .... 0.99.
IGBT, reducing the switching loss and achieve
low conduction loss. A prototype circuit has d Reduced THD.
been built and tested to verify this new
technique. d The bulk capacitor of the PFC is located
at high voltage (380 Vdc). Smaller size and
cost.
AC-DC converter has a nonisolated PFC front voltage and current stress. Soft-switching
end followed by a DC-DC converter with operation that can be easily maintained for
. isolation transformer as show in figure 1. wide line range and load range. In the
following section the Boost ZVT-PWM is used
as preregulator PFC and the use of MOSFET
and IGBT's are compared.
li
For this propositi we can use a boost PWM
DC-DC conver'ter. But the serious problem of Yo
this boost PFC while running under CCM
operation mode is the boost diode reverse
recovery problem. Since the output voltage is
high, every time when the active switch is
". S
103
- High efficiency.
- Low EM1 noise.
104
between (96.5% ... 97.3%) at low line and excessive device current stress and intolerable
(98.2%...98.4%) at full line (360 Vac European capacitive turn-on loss. Now ZVT technique
line voltage) with a considerable reduction of use the energy stored in the external capacitor
the cost. to achieve the zero-voltage turn-on [3],
reducing the turn-on losses.
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FIGURE 6: EFFICIENCY :RSWITCH.
105
Table 1 summarizes the power factor and the 1V.-SUMMARY
efficiency for different line and load conditions,
measured with an ac power analyzer ( Voltech In this paper, a novel ZVT technique is
PM1000) : applied to solve high device stress and high
switching losses problems of boost PWM
Vline (Vrms) PF. U Io (A) converter as front-end PFC converter of two
182 0.996 97.1 3.4 stage scheme in distributed power systems. So,
222 0.997 97.4 5.2 at low line where the current is high, the ZVT
250 0.996 98.1 5.4 technique shows significant improvement of
the efficiency, which will increase the power
The oscillograph of the waveforms is shown density.
in Fig.8. It can seen that the line current has
been well controlled to follow the line voltage. IGBT devices are recommended for their
low conduction loss and reduced price,
compared to MOSFETs at the same voltage
rating. The worst power stage efficiency is
above 96% at low line (180 Vac European line
range).
V.- REFERENCES
106