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Solutions to Problems
from Essentials of Electronic Testing
c
?
M. L. Bushnell and V. D. Agrawal, 2002
February 10, 2006
Please Read This
This manual contains solutions to all problems that appear at the end of the
chaptersin the book. At the end of the manual we have included the solutions to
problemswe used for the examinations in the Spring 2002 course at Rutgers
University, andSpring 2004 and Spring 2005 courses at Auburn University.In spite of
all the care taken to ensure accuracy, we caution the user that someanswers may
contain errors as it is the ?rst release of this manual. We will appreciateif any
errors or comments are forwarded to us by email:
vagrawal@eng.auburn.edu
or
bushnell@caip.rutgers.edu
.This manual has been created as teaching material that accompanies the book.To
preserve its e?ectiveness, it should not be distributed. If necessary, only a
verysmall set of solutions can be copied for distribution in the class. Please do
not passyour copy on to others and ask any one requesting it to contact the
authors.Teachers can also use the presentation slides for 31 lectures (or an
alternativesequence of 23-lectures), based on the book and available at the
following websites:
http://www.eng.auburn.edu/
~
vagrawal/COURSE/lectures.html http://www.caip.rutgers.edu/
~
bushnell/rutgers.html
We hope the readers of our book, both teachers and students, will bene?t fromthis
work. We acknowledge the help from colleagues and students in completingthis
solution manual and the assistance of the University of Wisconsin-Madison inits
initial distribution.
Solution Manual V1.4
c
?
M. L. Bushnell and V. D. Agrawal
For Teachers only
Page 1
Chapter 1: Introduction
1.1 Chip testing
The events of Example 1.1 are rede?ned as follows:PQ: chip is good P: chip passes
the testFQ: chip is bad F: chip fails the testA 70% yield means,
Prob
(
PQ
) = 0
.
7 and
Prob
(
FQ
) = 0
.
3. Following the analysisof Example 1.1,
Prob
(
P
) = 0
.
68. Then,Defect level = Bad chips that pass testsAll chips that pass tests=
Prob
(
FQ
|
P
)=
Prob
(
P
|
FQ
)
Prob
(
FQ
)
Prob
(
P
)= 0
.
05
0
.
30
.
68 = 0
.
022
The defect level is 22
,
000 ppm (parts per million).
1.2 Chip testing
Let
x
denote the escape probability,
Prob
(
P
|
FQ
). Referring to the formula derivedin Problem 1.1, a defect level of 500
ppm
means,
Prob
(
P
|
FQ
)
Prob
(
FQ
)
Prob
(
P
) =
x
0
.
30
.
95
0
.
7 +
x
0
.
3 = 0
.
0005This gives,
x
= 0
.
00033250
.
29985Next, we obtain,Defect coverage =
Prob
(
F
|
FQ
) = 1
-
Prob
(
P
|
FQ
)= 1
-
x
= 0
.
99889
The required defect coverage is 99.889%.
This represents the capability of thetest in detecting the actual defects that
occur and should not be confused withthe fault coverage, which is de?ned for the
single stuck-at fault model.
1.3 Test cost
Assuming that one vector is applied per clock cycle during the digital test, the
rateof test application is 200 million vectors per second. Therefore,Digital test
time = 1000
10
6
200
10
6
= 5
s
c
?
For Teachers only
Page 2
Adding the analog test time, we getTotal test time = 1

.
5 + 5
.
0 = 6
.
5
s
The testing cost for a 500
MHz
, 1,024 pin tester was obtained as 4
.
56
cents
inExample 1.2 (see page 11 of the book.) Thus,Cost of testing a chip = 6
.
5
4
.
56 = 29
.
64
cents
The cost of testing bad chips should also be recovered from the price of good
chips.Since the yield of good chips is 70%, we obtainTest cost in the price of a
chip = 29
.
640
.
7

42
cents
41.8 cents should be included as the cost of testing while ?guring out theprice of
chips
.
1.4 Test cost and self-test
Following Example 1.2 of the book (pp. 10-11), we obtainATE purchase price = $1
.
2
M
+ 256
$3
,
000 = $1
.
968
M
Assuming a 20% per year linear rate of depreciation, a maintenance cost of 2% of
the price, and an annual operating cost of $0
.
5
M
,Running cost = $1
.
968
M

0
.
2 + $1
.
968
M

0
.
02 + $0
.
5
M
= $932
,
960
/year
Testing cost = $932
,
960365
24
3600 = 2
.
96
cents/second
Testing cost of the self-test design is 2.96 cents per second, down from4.56 cents
per second calculated in Example 1.2
1.5 Test complexity
Consider a cube of side
d
. The number of transistors (
N
t
) is proportional to thevolume
d
3
, and the number of pins (
N
p
) is proportional to the surface area 6
d
2
.Thus, the Rents rule for the cube can be expressed as,
N
p
=
K

N
t
2
/
3
where
K
is a constant, which depends on such technology parameters as the mini-mum feature
spacing. For simplicity, we will assume that this constant is the samefor the ?at
and cubic chips. Following Example 1.3 (pp. 12-13 of book), we de?nethe test
complexity,
TC
, as transistors per pin, or
TC
=
N
t
/N
p
. For the cube,
TC
cube
=
N
t
N
p
=
N
t
KN
t
2
/
3
= 1
K N
t
1
/
3
c
?
For Teachers only
Page 3
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UT Dallas Syllabus for ce3320.002.10s taught by Mehrdad Nourani (nourani)

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